WO2023087510A1 - 一种基于数字tdr技术的模拟测量装置和测量方法 - Google Patents

一种基于数字tdr技术的模拟测量装置和测量方法 Download PDF

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WO2023087510A1
WO2023087510A1 PCT/CN2021/143606 CN2021143606W WO2023087510A1 WO 2023087510 A1 WO2023087510 A1 WO 2023087510A1 CN 2021143606 W CN2021143606 W CN 2021143606W WO 2023087510 A1 WO2023087510 A1 WO 2023087510A1
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signal
tdr
measurement
channel
analog
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French (fr)
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乔世栋
程绪
金君钢
高登
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上海御渡半导体科技有限公司
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

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  • the present invention relates to the field of semiconductor automatic test equipment (Automatic Test Equipment, referred to as ATE), in particular to an analog measurement device and measurement method based on the digital full name Time Domain Reflectometry (TDR).
  • ATE Automatic Test Equipment
  • TDR Time Domain Reflectometry
  • the frequency of the system clock increases, allowing the error on the time parameter to continuously decrease.
  • the vector period is often 50ns or 100ns, and the test signal of the test channel has sufficient time to reach a steady state, so the process of signal transmission inside the channel and the transient process of signal establishment can basically be ignored.
  • the system clock often reaches more than 100MHz, and the arrival time of the signal needs to be considered.
  • the problem of pin time synchronization accuracy that is, the time synchronization problem of the test vectors loaded on each pin (pin) on the chip under test (Device Under Test, DUT) needs to be paid attention to.
  • the two test signals that should arrive at them at the same time have a difference of 10ns in arrival time.
  • For a system with a vector period of 100ns there is a high probability that there is no problem, but for a vector period of 10ns
  • the system is likely to have problems, and it is likely to cause the DUT to have a wrong logic output, resulting in a DUT test failure. This is the problem caused by insufficient pin time synchronization accuracy.
  • the higher the speed of the system the higher the requirements for pin time synchronization accuracy.
  • the root cause of the asynchronous pin time is that the transmission paths of the test signals are different.
  • an electrical signal is also a type of electromagnetic wave, which propagates at a specific speed in a medium.
  • the theoretical transfer rate is described by the following formula:
  • c 0 the speed of light in vacuum
  • ⁇ r the relative permittivity
  • ⁇ r the relative magnetic permeability
  • This formula shows that the propagation speed of electrical signals in the medium is lower than the propagation speed of light in vacuum. For example, electrical signals travel at about 2/3 the speed of light in some 50 ⁇ coaxial cables. Therefore, it takes a corresponding time for the electrical signal to propagate in the medium. Moreover, similar to sound waves, impedance changes will also cause reflections during transmission, which leads to different transmission paths and different transmission times.
  • the purpose of the present invention is to provide a low-cost digital TDR technology using analog measurement to solve the problem of insufficient pin time synchronization accuracy of the digital integrated circuit test system.
  • An analog measurement device based on digital TDR technology, used for measuring and calculating delay information (delay parameters) of N channels, and performing delay correction on measurement data during formal measurement; it includes FPGA module 1, N A pin driver PE2, an RC filter circuit 3 and an analog-to-digital converter ADC4 corresponding to the N channels; wherein,
  • the FPGA module 1 is used to realize the transmission, reception and data path selection of the N-way channel test signal; it includes an N-way PWM generator 1-1, an N-way transmission signal selector 1-2, and an N-way data transmission path 1 -3. N data receiving paths 1-4 and a data path selector 1-5;
  • the PWM generator 1-1 is used to generate the TDR test pattern of each channel; the transmission signal selector 1-2 of each channel selects to transmit a normal test pattern or a TDR test pattern through an enable signal TDR_EN;
  • the data transmission path 1-3 of each channel includes a first programmable delay unit and a transmission logic resource unit, and the first programmable delay unit is used to delay the normal test pattern of this channel during normal testing Synchronously, the sending logic resource unit is used to send the TDR test pattern or the normal test pattern to the pin driver PE2; wherein, the initialization value of the first programmable delay unit is 0;
  • Each pin driver PE2 is used to perform port level conversion on the TDR test pattern of the corresponding channel, and configure different level thresholds according to the level threshold judgment rule; the pin driver PE2 includes receiving channel end cmpl, sending Channel end data and test bidirectional channel end;
  • the data receiving path 1-4 of each channel includes a receiving logic resource unit and a second programmable delay unit, the logic resource unit is used to receive the measurement signal of the corresponding channel input through the pin driver PE2, and the second programmable delay unit
  • the programming delay unit is used to delay and synchronize the measurement signal of the corresponding channel; the second programmable delay is used to delay and synchronize the normally received test data of this channel during normal testing;
  • the data channel selector 1-5 selects one of the N channels through the selection signal TDR_DC_SEL, and transmits the measured TDR signal to the external measurement unit;
  • the RC filter circuit 3 performs low-pass filtering on the TDR signal after being determined and selected, and converts the duty cycle signal into an analog signal of a DC voltage;
  • the analog-to-digital converter ADC4 performs analog-to-digital conversion on the analog signal of the DC voltage filtered by the RC filter circuit 3 to obtain a digitized voltage value, and produces different values for the TDR reflection signal of the TDR test pattern.
  • the determination result of the empty ratio is combined with the time/voltage coefficient to obtain the measurement signal of the corresponding channel.
  • the FPGA module 1 also includes a parameter configuration unit, the parameter configuration unit PWM configures the continuous step signal period parameters of the PWM generator 1-1, and confirms the period and duty cycle of the TDR test pattern, And setting the threshold level of the pin driver PE2.
  • a measurement method using the above-mentioned analog measurement device based on digital TDR technology which includes a measurement signal generation step for measuring and calculating delay information of N channels and a step of delay correction for measurement data during formal measurement Test step, described extension information generation step comprises:
  • Step S1 Configure the internal module parameters of FPGA1, including setting the parameters of PWM generator 1-1, confirming the period and duty cycle of the TDR test pattern; setting the transmit signal selector 1-2, and setting the TDR_EN of the test channel to 1, Gate the TDR test pattern; set the data channel selector 1-5, and select the required test channel through TDR_DC_SEL;
  • Step S2 Set the threshold level of the pin driver PE2, judge the received TDR signal, and transmit the result of the TDR signal fed back from the connector to the FPGA module 1 through the pin of the pin driver PE2
  • Step S3 the signal is converted to a DC level through the RC filter circuit 3, and the digital signal conversion is completed at the analog-to-digital converter ADC4; the digital voltage corresponding to the TDR signal is obtained;
  • Step S4 Repeat step S2, set different threshold levels, and obtain digital voltages corresponding to multiple sets of TDR signals of the current channel;
  • Step S5 Obtain the measurement signal of the current channel according to the corresponding TDR signal measurement method
  • Step S6 Repeat steps S1-S5 to measure the measurement signals of all channels;
  • Step S7 Take the measurement signal greater than or equal to all channels as the measurement signal for synchronization, and input the measurement signal for synchronization to the first programmable delay unit and the second programmable delay unit for subsequent It is used for delay correction of measurement data during normal measurement.
  • step S2 specifically includes:
  • Step S21 The PWM generator 1-1 continuously sends a square wave signal S0 with a period of T0, wherein the high level width of the square wave signal S0 is Th;
  • Step S23 The signal S1 forms a signal S2 after the multi-threshold determination process is executed by the pin driver PE2, and the signal S2 generates a time difference Tv between two thresholds according to different comparison thresholds; wherein, Tv includes two parts of time, one is Channel delay Tdly, one is the voltage rise time;
  • Step S24 Using multiple threshold position determination methods to eliminate the influence of voltage rise time and obtain accurate channel time delay Tdly.
  • the procedure of the multi-threshold determination specifically includes:
  • Step S241 The pin driver PE2 uses 1/6 and 5/6 level thresholds respectively, the comparison threshold a is 1/6, and the comparison threshold b is 5/6; according to the method of step S23, the threshold time difference Tv2 is obtained;
  • Step S242 The pin driver PE2 uses 2/6 and 4/6 level thresholds respectively, the comparison threshold a is 2/6, and the comparison threshold b is 4/6; according to the method of step S23, the threshold time difference Tv1 is obtained;
  • Step S243 In the above steps, set the voltage rise time set by using 1/6--5/6 level thresholds and 2/6--4/6 level thresholds to be the same, and use 3/6--4
  • the /6 level threshold is the same as the voltage rise time set by using the 4/6--5/6 level threshold; Tdly can be calculated using the following method:
  • step S25 is further included after step S24: performing time/voltage coefficient verification on each of the N channels in sequence.
  • step S25 specifically includes:
  • Step S251 set a period of the verification pattern as T0, and set the decision threshold as one of 1/6, 2/6, 3/6, 4/6, and 5/6 level thresholds;
  • Step S252 set the high level time as Th, and the voltage value measured by the analog-to-digital converter ADC4 is V1;
  • Step S253 reset the high-level time to Th+ ⁇ T, and the voltage value measured by the analog-to-digital converter ADC4 is V2;
  • the present invention has the following beneficial effects:
  • the implementation method is simple and effective, and the workload is small; batch automated testing can be performed, and when the testing environment changes, the measurement signal can be re-calibrated conveniently and compensation corrections can be made.
  • FIG. 1 shows a schematic diagram of the TDR signal model
  • Fig. 2 shows the functional module schematic diagram of the analog measurement device based on digital TDR technology in the embodiment of the present invention
  • Figure 3 is a schematic diagram of an analog measurement method based on digital TDR technology in an embodiment of the present invention
  • Fig. 4 is a schematic diagram of the TDR signal measurement method (using the principle of multi-threshold judgment) in the embodiment of the present invention
  • Figure 5 is a schematic diagram of the time/voltage coefficient calibration principle in the embodiment of the present invention.
  • TDR Time Domain Reflectometry
  • TDR time-domain reflectometry is the main tool for measuring the characteristic impedance of transmission lines, and it works similarly to radar location technology.
  • Figure 1 shows a schematic diagram of a TDR signal model. Assuming that the impedance of the path under test is R, for a step signal, as shown in Figure 1, there are three ideal models for TDR technology:
  • FIG. 2 is a schematic diagram of the functional modules of the TDR measurement circuit in the implementation of the present invention.
  • the analog measurement device based on digital TDR technology is used to measure and calculate delay information of N channels before testing, and to perform delay correction on measurement data during formal measurement.
  • the analog measurement device based on digital TDR technology includes a programmable logic gate array FPGA1 , corresponding pin drivers PE2 with N channels, an RC filter circuit 3 and an analog-to-digital converter ADC4 .
  • the FPGA module 1 (Programmable Logic Gate Array) is used to realize the sending and receiving of test signals and the selection of data paths.
  • FPGA1 module mainly can comprise the selection that is used to realize the transmission of described N road test signal, receive and data path; It comprises N road PWM generator 1-1, N road sending signal selector 1-2, N road data sending paths 1-3, N data receiving paths 1-4 and a data path selector 1-5.
  • the PWM generator 1-1 is used to generate the TDR test pattern of each channel, that is, a continuous step signal, and the signal period can be programmed for different measurement environments or self-adaptive adjustment of accuracy.
  • the data transmission path 1-3 of each channel includes a first programmable delay unit and a transmission logic resource unit, and the first programmable delay unit is used to delay the normal test pattern of this channel during normal testing Synchronously, the sending logic resource unit is used to send the TDR test pattern or the normal test pattern to the pin driver PE2; wherein, the initialization value of the first programmable delay unit is 0.
  • the data receiving path 1-4 of each channel includes a receiving logic resource unit and a second programmable delay unit, the logic resource unit is used to receive the peripheral sampling signal input through the pin driver PE2, and the second programmable The delay unit is used to synchronize the delay of the peripheral sampling signal; wherein, the initialization value of the second programmable delay unit is 0; in the measurement signal generation step for measuring and calculating the delay information of N channels When completed, the value of the second programmable delay unit is a synchronous measurement signal, which is used to delay and synchronize the normally received test data of this channel during normal testing;
  • the data path selector 1-5 selects one of the N channels through a selection signal TDR_DC_SEL, and transmits the measured TDR signal to an external measurement unit.
  • Each pin driver PE 2 is used to perform port level conversion on the TDR test pattern of the corresponding channel, configure different level thresholds according to the level threshold judgment rule, and perform electrical switching on the TDR reflection signal of the TDR test pattern. Ping judgment, generate digital logic signal, return to FPGA1 unit for post-stage processing.
  • the pin driver PE 2 is used to perform port level conversion on the TDR test pattern of the corresponding channel, configure different level thresholds, receive signal level threshold judgment and other functions according to the level threshold judgment rules; the pin driver PE 2 It includes receiving channel end cmpl, sending channel end data, and test bidirectional channel end; port level conversion can be performed as required, and functions such as tri-state output of the TDR test pattern can be completed.
  • the pin driver PE 2 completes the conversion of digital level signals to analog level signals and the control of three-state output by configuring different level thresholds. After completion, the pin (CMPL) of the pin driver PE 2 is output to the N-way send signal selector 1-2 inside the FPGA module 1.
  • RC filter circuit 3 resistance-capacitance filter circuit
  • its main function is to perform low-pass filtering on the TDR signal after the judgment and selection, and convert the duty ratio signal into a DC voltage for the subsequent stage circuit to collect analog quantities.
  • ADC 4 Analog-to-Digital Converter
  • ADC 4 performs low-pass filtering on the TDR signal after the judgment and selection, and converts the duty ratio signal into an analog signal of DC voltage, that is, the DC signal after RC filtering, performs analog-digital Convert to get the digitized voltage value, enter the post-processing module, cooperate with the time/voltage coefficient, and convert it into a delay result.
  • Step S1 Configure the internal module parameters of FPGA 1, including setting the parameters of PWM generator 1-1, confirming the period and duty cycle of the TDR test pattern; setting the sending signal selector 1-2, setting TDR_EN of the test channel to 1, Gate the TDR test pattern; set the data channel selector 1-5, and select the required test channel through TDR_DC_SEL.
  • the internal module parameters may include setting the parameters of the PWM generator 1-1 to confirm the period and duty cycle of the TDR test pattern; setting the transmission signal selector 1-2 to select and send the normal test pattern through the enable signal TDR_EN Or TDR test pattern, for example, by setting the enable signal TDR_EN of the test channel to 1, the gate sends the TDR test pattern, or by setting the enable signal TDR_EN of the test channel to 0, the gate sends the normal test pattern.
  • Step S2 Set the threshold level of the pin driver PE 2, judge the received TDR signal, and transmit the result of the TDR signal fed back from the connector to the FPGA module through the pin of the pin driver PE 2 1's data receiving path 1-4; then through the data path selector 1-5, the strobe is output to the external measurement unit; wherein, the external measurement unit may include an RC filter circuit 3 and an analog-to-digital converter ADC 4.
  • Step S3 The signal is converted to a DC level through the RC filter circuit 3, and the digital signal conversion is completed at the analog-to-digital converter ADC4; a digital voltage corresponding to the TDR signal is obtained.
  • Step S4 Repeat step S2, set different threshold levels, and obtain digital voltages corresponding to multiple sets of TDR signals of the current channel.
  • Step S5 Obtain the measurement signal of the current channel according to the corresponding TDR signal measurement method
  • Step S6 Repeat steps S1-S5 to measure the measurement signals of all channels;
  • Step S7 Take the measurement signal greater than or equal to all channels as the measurement signal for synchronization, and input the measurement signal for synchronization to the first programmable delay unit and the second programmable delay unit for subsequent normal It is used for delay correction of measurement data during measurement.
  • the key point of the technical solution is the TDR signal measurement method, which is now specifically described as follows:
  • FIG. 3 is a schematic diagram of an analog measurement method based on digital TDR technology in an embodiment of the present invention. As shown in FIG. 3 , it describes the required threshold position, the schematic diagram of signal judgment, and the time domain relationship of the judgment signal in the process of TDR signal measurement.
  • TDR signal measurement method The specific implementation of the TDR signal measurement method is as follows:
  • Step S21 The PWM generator 1-1 continuously sends a square wave signal S0 with a period T0, wherein the high level width of the square wave signal S0 is Th.
  • Step S23 The signal S1 forms a signal S2 after passing through the comparison unit CMP of the pin driver PE2, and the signal S2 will generate different judgment results according to different comparison thresholds.
  • the signal generated by the comparison threshold a judgment is recorded as S2a, and the high level time is Ta, and the signal generated by the comparison threshold b judgment is recorded as S2b, and the high level time is Tb.
  • the time difference between two thresholds is defined as Tv:
  • Tv includes two parts of time, one is the channel delay Tdly, and the other is the voltage rise time.
  • Step S24 Using multiple threshold position determination methods to eliminate the influence of voltage rise time and obtain accurate channel time delay Tdly.
  • FIG. 4 is a schematic diagram of an implementation flow of multi-threshold determination in an embodiment of the present invention. As shown in Figure 4, the flow of the multi-threshold determination includes:
  • Step S241 The pin driver PE 2 uses 1/6 and 5/6 level thresholds respectively, the comparison threshold a is 1/6, and the comparison threshold b is 5/6; according to the method of step S23, the threshold time difference Tv2 is obtained;
  • Step S242 The pin driver PE 2 uses 2/6 and 4/6 level thresholds respectively, the comparison threshold a is 2/6, and the comparison threshold b is 4/6; according to the method of step S23, the threshold time difference Tv1 is obtained.
  • Step S243 Assume that the voltage rise time is the same when using 1/6--5/6 level thresholds and 2/6--4/6 level thresholds, and using 3/6--4/6 level thresholds It is the same as the voltage rise time set by using the 4/6--5/6 level threshold; Tdly can be calculated using the following method:
  • Tdly should be twice the actual path delay because the TDR signal is superimposed by reflected signals.
  • step S23 after the signal S2 passes through an external RC filter circuit (low-pass filter), the actual measurement obtained by the analog-to-digital converter ADC4 is a voltage value, while non-time value. Therefore, it is necessary to pass the time/voltage conversion verification to obtain the time/voltage coefficient of each channel, which is defined as k and the unit is (ps/mv).
  • FIG. 5 is a schematic diagram of the principle of time/voltage coefficient calibration in the embodiment of the present invention.
  • the implementation method of the time/voltage coefficient verification is described as follows by using one of the N channels:
  • Step S251 set a period of the verification pattern as T0, and set the judgment threshold as the 5/6 level threshold;
  • Step S252 set the high level time as Th, and the voltage value measured by the analog-to-digital converter ADC4 is V1;
  • Step S253 reset the high-level time to Th+ ⁇ T, and the voltage value measured by the analog-to-digital converter ADC4 is V2;
  • time/voltage coefficient calibration needs to be based on a premise: increasing ⁇ T will only change the ratio of high and low levels, and will not affect the rising and falling edges. Therefore, it is necessary to ensure that the rising and falling processes before and after the increase are complete, that is, reserve enough rising fall time. Also, it should be noted that the time/voltage coefficient calibration coefficients are only applicable to the current T0.
  • the voltage quantity measured by the analog-to-digital converter ADC4 can be converted into a time quantity.
  • the measurement signals Tdly of the N channels can be respectively obtained according to the method used in step S4.
  • the large range rough side As shown in Figure 2, assuming that there are N channels (32 channels in the figure, 0-31), in the process of measuring and calculating the delay information of N channels, for each channel, the measurement channel TDR_EN is set to 1. Strobe the TDR test pattern. For example, setting TDR_DC_SEL to 0 is to enable channel 0 for testing.
  • Tdly 2*Tv1-Tv2.
  • Tdly/2 is the required channel measurement signal.
  • each channel is calibrated synchronously, which can effectively improve the pin time synchronization accuracy and ensure the accuracy of the subsequent test process.

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Abstract

一种基于数字TDR技术的模拟测量装置和测量方法，用于测量和计算N路通道的延时信息，以及在正式测量时，对测量数据进行延时校正；该装置包括FPGA模块(1)、与多路通道相应的引脚驱动器PE(2)、RC滤波电路(3)和模拟数字转换器ADC(4)。该基于数字TDR技术的模拟测量装置用模拟测量的低成本数字TDR技术，解决了数字集成电路测试系统引脚时间同步精度不足的问题，可进行批量自动化测试；在测试环境变化时，可便捷地重新校对测量信号，进行补偿修正，且可自动化精度调整，可针对任意路径模型进行测量，通用性能好。

Description

一种基于数字TDR技术的模拟测量装置和测量方法
交叉引用
本申请要求2021年11月19日提交的申请号为202111373933.1的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及半导体自动测试设备(Automatic Test Equipment，简称ATE)领域，尤其涉及一种基于数字全称时域反射技术(Time Domain Reflectometry，TDR)的模拟测量装置和测量方法。
技术背景
随着科学技术的巨大进步和在社会生活的广泛应用，集成电路产业的发展可谓日新月异。所用芯片无论是晶体规模，还是运行速率，都有了巨大的提升，从而对集成电路的生产和测试带来了越来越大的挑战。
尤其是测试领域，随着芯片的运行速率加快，系统时钟频率随之提高，允许时间参数上的误差不断减小。而在低速测试系统中，向量周期往往在50ns或者100ns，测试通道的测试信号达到稳态时间充足，基本可以忽略通道内部信号传输的过程和信号建立的暂态过程。然而，在高速系统中，系统时钟经常达到100MHz以上，需考虑信号的到达时间问题。
也就是说，引脚时间同步精度的问题，即加载到待测芯片(Device Under Test，DUT)上的每个pin(引脚)的测试向量的时间同步问题需要重点关注。假设，有2个pin的时间同步性很差，本应同时到达它们的2个测试信号，到达时间却相差了10ns，对于向量周期100ns的系统，大概率是没有问题的，但是对于向量周期10ns的系统，很可能是会出现问题的，很可能使DUT出现错误的逻辑输出，导致DUT测试失败。这就是引脚时间同步精度不够带来的问题，越是高速的系统，对于引脚时间同步精度要求越高。
造成引脚时间不同步的根源，是测试信号的传输路径不同。众所周知， 电信号也是电磁波的一种，在介质中传播具有特定的速度。理论传输速率如下公式所述：
Figure PCTCN2021143606-appb-000001
其中，c 0真空中光速，ε r相对介电常数，μ r相对导磁率
该式表明电信号在介质中的传播速度低于光在真空中的传播速度。例如，在一些50Ω同轴电缆中电信号传播速度约为2/3倍的光速。因此，电信号在介质中传播也需要相应的时间。并且，类似于声波，其传输过程中遇到阻抗变化也会产生反射，这就导致了不同的传输路径，会有不同的传输时间。
数字集成电路测试系统中，由于测试板走线、连接器和夹具等不尽相同，各个测试通道必然存在路径差异，从而导致通道时延各不相同。
考虑到这些传输时延不可避免，一些生产商往往把大量的信号产生、信号测量和数据处理等电路都集中在离DUT最近的测试头中，所测的DUT的数据也是在测试头中第一时间处理。尽管如此，仍不能根本消除测试通道的传输时延以及时延差异。
还有一些厂商，使用外部校准法。利用外部辅助测量设备直接在器件接口板(Device Board，DIB)上测量所有引脚pin的脉冲信号的真实到达时间差异，将差异一次性修正到测试通道信号发送端。但是，这种测量方式耗时多，工作量大，所以这些修正值一旦写入系统后一般不会更改。如果使用者根据测试需求更换DUT夹具或者DIB，将会导致各通道之间的传输时延引入新的差异，局限性明显。
因此，高端测试系统生产商迫切需要解决引脚时间同步精度问题。
发明概要
本发明的目的在于提供一种采用模拟测量的低成本数字TDR技术，解决数字集成电路测试系统引脚时间同步精度不足的问题。
为实现上述目的，本发明的技术方案如下：
一种基于数字TDR技术的模拟测量装置，用于测量和计算N路通道的延时信息(延时参数)，以及在正式测量时，对测量数据进行延时校正；其 包括FPGA模块1、N个与所述N路通道相应的引脚驱动器PE2、RC滤波电路3和模拟数字转换器ADC4；其中，
FPGA模块1用于实现所述N路通道测试信号的发送、接收和数据通路的选择；其包括N路PWM生成器1-1、N路发送信号选择器1-2、N路数据发送通路1-3、N路数据接收通路1-4和一个数据通路选择器1-5；
所述PWM生成器1-1用于生成每个通道的TDR测试图样；每个通道的所述发送信号选择器1-2通过使能信号TDR_EN，选择发送正常测试图样或TDR测试图样；
每个通道的数据发送通路1-3包括第一可编程延时单元和发送逻辑资源单元，所述第一可编程延时单元用于在正常测试时，将本通道的正常测试图样进行延时同步，所述发送逻辑资源单元用于将所述TDR测试图样或正常测试图样发送到引脚驱动器PE2；其中，所述第一可编程延时单元的初始化值为0；
每个所述引脚驱动器PE2用于对相应通道的TDR测试图样进行端口电平转换，根据电平阈值判定规则，配置不同的电平阈值；所述引脚驱动器PE2包括接收通道端cmpl、发送通道端data和与测试双向通道端；
每个通道的数据接收通路1-4包含接收逻辑资源单元和第二可编程延时单元，所述逻辑资源单元用于接收通过引脚驱动器PE2输入的相应通道的测量信号，所述第二可编程延时单元用于将相应通道的测量信号进行延时同步；所述第二可编程延时用于在正常测试时，将本通道的正常接收的测试数据进行延时同步；
所述数据通路选择器1-5，通过选择信号TDR_DC_SEL，选通所述N路通道之一，将测量到的TDR信号传送到外部测量单元；
所述RC滤波电路3对经过判定选择之后的TDR信号，进行低通滤波，并将占空比信号转化为直流电压的模拟量信号；
所述模拟数字转换器ADC4，将所述RC滤波电路3滤波以后的直流电压的模拟量信号，进行模拟-数字转换，得到数字化的电压值，对所述TDR测试图样的TDR反射信号产生不同占空比的判定结果，配合时间/电压系数，从而得到相应通道的测量信号。
进一步地，所述FPGA模块1还包括参数配置单元，所述参数配置单元 PWM配置所述PWM生成器1-1连续的阶跃信号周期参数，确认所述TDR测试图样的周期和占空比，以及设定所述引脚驱动器PE2的阈值电平。
为实现上述目的，本发明又一技术方案如下：
一种采用上述的基于数字TDR技术的模拟测量装置的测量方法，其包括用于测量和计算N路通道的延时信息的测量信号生成步骤和在正式测量时，对测量数据进行延时校正的测试步骤，所述延信息生成步骤包括：
步骤S1：配置FPGA1内部模块参数，包括设定PWM生成器1-1参数，确认TDR测试图样的周期和占空比；设定发送信号选择器1-2，将测试通道的TDR_EN设置为1，选通TDR测试图样；设定数据通路选择器1-5，通过TDR_DC_SEL选择所需测试通道；
步骤S2：设定引脚驱动器PE2的阈值电平，对接收到的TDR信号进行判定，对连接器反馈回来的所述TDR信号结果通过引脚驱动器PE2的引脚传输到所述FPGA模块1的数据接收通路1-4；然后经过数据通路选择器1-5，选通输出到外部测量单元；其中，外部测量单元可以包括RC滤波电路3和模拟数字转换器ADC4；
步骤S3：信号经过RC滤波电路3转换为直流电平，在模拟数字转换器ADC4处完成数字信号转换；得到TDR信号对应的数字电压；
步骤S4：重复步骤S2，设置不同的阈值电平，获取当前一路通道多组TDR信号对应的数字电压；
步骤S5：根据对应的TDR信号测量方法，得出当前通道的测量信号；
步骤S6：重复步骤S1-S5，测量所有通道的测量信号；
步骤S7：取大于等于所有通道的测量信号作为用于同步的测量信号，并将该用于同步的测量信号输入到和第一可编程延时单元和第二可编程延时单元，以备后续正常测量时对测量数据进行延时校正用。
进一步地，所述步骤S2具体包括：
步骤S21：PWM生成器1-1持续发送一个周期为T0的方波信号S0，其中，该方波信号S0高电平宽度为Th；
步骤S22：该方波信号S0经过引脚驱动器PE2发送并经选定的测试通道，到达DUT引脚端，由于所述DUT引脚端悬空，R＝∞，形成TDR反射信号，源信号与TDR反射信号叠加，形成信号S1；
步骤S23：该信号S1经过引脚驱动器PE2执行多门限判定的流程后形成信号S2，信号S2根据不同的比较门限，生成两个门限之间的时间差Tv；其中，Tv包含两部分时间，一个是通道时延Tdly，一个是电压上升时间；
步骤S24：采用多个门限位置判定的方法，消除电压上升时间的影响，获得准确的通道时延Tdly。
进一步地，所述多门限判定的流程具体包括：
步骤S241：所述引脚驱动器PE2分别使用1/6和5/6电平阈值，比较门限a为1/6，比较门限b为5/6；依照步骤S23的方法，获得门限时间差Tv2；
步骤S242：所述引脚驱动器PE2分别使用2/6和4/6电平阈值，比较门限a为2/6，比较门限b为4/6；依照步骤S23的方法，获得门限时间差Tv1；
步骤S243：设定上述步骤中，使用1/6--5/6电平阈值和使用2/6--4/6电平阈值为置的电压上升时间相同，且使用3/6--4/6电平阈值和使用4/6--5/6电平阈值为置的电压上升时间相同；Tdly可使用如下方法计算：
Tdly＝Tv1-(Tv2-Tv1)＝2*Tv1-Tv2。
进一步地，所述步骤S24后还包括步骤S25：依次对N路通道中的每一通道进行时间/电压系数校验。
进一步地，所述步骤S25具体包括：
步骤S251：设置校验图样一个周期为T0，设定判决门限为1/6、2/6、3/6、4/6、5/6电平阈值之一；
步骤S252：设置高电平时间为Th，模拟数字转换器ADC4测得电压值为V1；
步骤S253：重新设置高电平时间为Th+ΔT，模拟数字转换器ADC4测得电压值为V2；
步骤S254：分析可得出ΔT对应ΔV＝(V2-V1)，故ΔT/ΔV，得到系数k(ps/mv)，即是时间/电压系数。
从上述技术方案可以看出，本发明具有如下有益效果：
①、不依托外部测量环境，实现方法简单有效，工作量小；可进行批量自动化测试，在测试环境变化时，可便捷的重新校对测量信号，进行补偿修 正。
②、无需有源探头，避免引入不必要的干扰因素，有利于进一步提高测量精度。
③、无量程限制，可自动化精度调整，可针对任意路径模型进行测量，通用性能好。
④、成本低，效果好，且精度与测试系统的时钟相关，与模拟量采集的绝对精度无关，可方便的通过时钟频率升级提高测量精度，以满足不断变化的测试需求。
附图说明
图1所示为TDR信号模型的示意图
图2所示为本发明实施例中基于数字TDR技术的模拟测量装置的功能模块示意图
图3所示为本发明实施例中基于数字TDR技术的模拟测量方法的示意图
图4所示为本发明实施例中TDR信号测量方法(采用多门限判定原理)的示意图
图5所示为本发明实施例中的时间/电压系数校验原理示意图
发明内容
下面结合附图1-5，对本发明的具体实施方式作进一步的详细说明。
需要说明的是，本发明所采用模拟测量的低成本数字TDR技术，其全称为时域反射技术(Time Domain Reflectometry)。TDR是一门在时间域上通过对发射信号和反射信号的评估而确定被测系统的状态的一种技术。TDR时域反射技术是测量传输线特性阻抗的主要工具，其工作方式类似于 雷达定位技术。
请参阅图1，图1所示为TDR信号模型示意图。假设被测路径的阻抗为R，对于阶跃信号，如图1所示，TDR技术有三种理想模型：
当R＝∞时(开路)，末端测量点能量全部反射回去，与原有信号叠加为上升台阶信号；
当R＝R0时(阻抗匹配)，传输过来的能量刚好被末端的阻抗R吸收完，没有能量反射回去，信号无变化；
当R＝0时(短路)，末端测量点会产生一个负能量的反射，与原有信号叠加为下降台阶信号。
本发明所述采用模拟测量的低成本数字TDR技术，正是基于R＝∞时，测量Tdly位置的时间参数，从而获取测量路径的测量信号。
请参阅图2，图2所示为本发明实施中TDR测量电路的功能模块示意图。该基于数字TDR技术的模拟测量装置用于在测试前，测量和计算N路通道的延时信息，以及在正式测量时，对测量数据进行延时校正。
如图2所示，该基于数字TDR技术的模拟测量装置包括可编程逻辑门阵列FPGA1、以N路通道相应的引脚驱动器PE2、RC滤波电路3和模拟数字转换器ADC4。
在本发明的实施例中，FPGA模块1(可编程逻辑门阵列)用于实现测试信号的发送和接收，以及数据通路的选择。FPGA1模块主要可以包含用于实现所述N路通道测试信号的发送、接收和数据通路的选择；其包括N路PWM生成器1-1、N路发送信号选择器1-2、N路数据发送通路1-3、N路数据接收通路1-4和一个数据通路选择器1-5。
PWM生成器1-1，用于生成每个通道的TDR测试图样，即连续的阶跃信号，该信号周期可编程，以针对不同的测量环境或进行精度自适应调整。发送信号选择器1-2，通过TDR_EN，选择发送正常测试图样，还是TDR测试图样，每个通道可以单独使能PWM信号到测试信号输出端。
每个通道的数据发送通路1-3包括第一可编程延时单元和发送逻辑资源单元，所述第一可编程延时单元用于在正常测试时，将本通道的正常测试图样进行延时同步，所述发送逻辑资源单元用于将所述TDR测试图样或正常测试图样发送到引脚驱动器PE2；其中，所述第一可编程延时单元的初始化 值为0。
每个通道的数据接收通路1-4包含接收逻辑资源单元和第二可编程延时单元，所述逻辑资源单元用于接收通过引脚驱动器PE2输入的外设采样信号，所述第二可编程延时单元用于将外设采样信号进行延时同步；其中，所述第二可编程延时单元的初始化值为0；在用于测量和计算N路通道的延时信息的测量信号生成步骤完成时，所述第二可编程延时单元的值为同步的测量信号，用于在正常测试时，将本通道的正常接收的测试数据进行延时同步；
所述数据通路选择器1-5，通过选择信号TDR_DC_SEL，选通所述N路通道之一，将测量到的TDR信号传送到外部测量单元。
每个所述引脚驱动器PE 2用于对相应通道的TDR测试图样进行端口电平转换，根据电平阈值判定规则，配置不同的电平阈值，对所述TDR测试图样的TDR反射信号进行电平判决，生成数字逻辑信号，返回到FPGA1单元，进行后级处理。
引脚驱动器PE 2用于对相应通道的TDR测试图样进行端口电平转换，根据电平阈值判定规则，配置不同的电平阈值，接收信号电平阈值判定等功能；所述引脚驱动器PE 2包括接收通道端cmpl、发送通道端data和与测试双向通道端；可以根据需要进行端口电平转换，完成对所述TDR测试图样三态输出等功能。
具体的，引脚驱动器PE 2通过对不同的电平阈值配置，完成数字电平信号到模拟电平信号的转换，以及三态输出的控制。完成后，通过引脚驱动器PE 2的引脚(CMPL)输出到FPGA模块 1内部的N路发送信号选择器1-2。
后级ADC4测量到电压以后，才能进行结果计算的以及对所述TDR反射信号产生不同占空比的判定结果，从而得到通道的测量信号。
RC滤波电路3(阻容滤波电路)，其主要作用是，对经过判定选择之后的TDR信号，进行低通滤波，并将占空比信号转化为直流电压，供后级电路进行模拟量采集。
ADC 4(模拟数字转换器)，对经过判定选择之后的TDR信号，进行低通滤波，并将占空比信号转化为直流电压的模拟量信号，即RC滤波以后的直流信号，进行模拟-数字转换，得到数字化的电压值，进入后级处理模 块，配合时间/电压系数，转换为时延结果。
本发明实施例中基于数字TDR技术的模拟测量方法包括如下步骤：
步骤S1：配置FPGA 1内部模块参数，包括设定PWM生成器1-1参数，确认TDR测试图样的周期和占空比；设定发送信号选择器1-2，测试通道的TDR_EN设置为1，选通TDR测试图样；设定数据通路选择器1-5，通过TDR_DC_SEL选择所需测试通道。
具体地，该内部模块参数可以包括设定PWM生成器1-1参数，确认TDR测试图样的周期和占空比；设定发送信号选择器1-2通过使能信号TDR_EN，选择发送正常测试图样或TDR测试图样，例如，通过将所述测试通道的使能信号TDR_EN设置为1，选通发送TDR测试图样，或者过将所述测试通道的使能信号TDR_EN设置为0，选通发送正常测试图样。
设定数据通路选择器1-5，通过选择信号TDR_DC_SEL选择所需测试通道，即通过选择信号TDR_DC_SEL，选通所述N路通道之一，将测量到的TDR信号传送到外部测量单元。
步骤S2：设定引脚驱动器PE 2的阈值电平，对接收到的TDR信号进行判定，对连接器反馈回来的所述TDR信号结果通过引脚驱动器PE 2的引脚传输到所述FPGA模块1的数据接收通路1-4；然后经过数据通路选择器1-5，选通输出到外部测量单元；其中，外部测量单元可以包括RC滤波电路3和模拟数字转换器ADC 4。
步骤S3：信号经过RC滤波电路3转换为直流电平，在模拟数字转换器ADC4处完成数字信号转换；得到TDR信号对应的数字电压。
步骤S4：重复步骤S2，设置不同的阈值电平，获取当前一路通道多组TDR信号对应的数字电压。
步骤S5：根据对应的TDR信号测量方法，得出当前通道的测量信号；
步骤S6：重复步骤S1-S5，测量所有通道的测量信号；
步骤S7：取大于等于所有通道的测量信号作为用于同步的测量信号，并将该用于同步的测量信号输入到第一可编程延时单元和第二可编程延时单元，以备后续正常测量时对测量数据进行延时校正用。
实施例1
在本发明实施例中，其技术方案的关键点在于TDR信号测量方法，现在具体说明如下：
请参阅图3，图3所示为本发明实施例中基于数字TDR技术的模拟测量方法的示意图。如图3所示，其描述了TDR信号测量的过程中，所需门限位置，信号判定示意图，以及判定信号的时域关系。
该TDR信号测量方法具体实施如下：
步骤S21：PWM生成器1-1持续发送一个周期为T0的方波信号S0，其中，该方波信号S0高电平宽度为Th。
步骤S22：该方波信号S0经过引脚驱动器PE 2发送并经选定的测试通道，到达连接器的DUT引脚端，由于所述DUT引脚端悬空，R＝∞，形成TDR反射信号，源信号与TDR反射信号叠加，形成信号S1；
步骤S23：该信号S1经过引脚驱动器PE 2的比较单元CMP后形成信号S2，信号S2根据不同的比较门限，会生成不同的判定结果。
如图3所示，比较门限a判决生成的信号记录为S2a，高电平时间为Ta，比较门限b判决生成的信号记录为S2b，高电平时间为Tb。两个门限之间的时间差定义为Tv：
Tv＝(Ta-Tb)/2
其中，Tv包含两部分时间，一个是通道时延Tdly，一个是电压上升时间。
步骤S24：采用多个门限位置判定的方法，消除电压上升时间的影响，获得准确的通道时延Tdly。
请参阅4，图4所示为本发明实施例中多门限判定的实施流程示意图。如图4所示，该多门限判定的流程包括：
步骤S241：引脚驱动器PE 2分别使用1/6和5/6电平阈值，比较门限a为1/6，比较门限b为5/6；依照步骤S23的方法，获得门限时间差Tv2；
步骤S242：引脚驱动器PE 2分别使用2/6和4/6电平阈值，比较门限a为2/6，比较门限b为4/6；依照步骤S23的方法，获得门限时间差Tv1。
如图4所示，通过理论分析，可得到：
步骤S243：假设使用1/6--5/6电平阈值和使用2/6--4/6电平阈值为置的电压上升时间相同，而且使用3/6--4/6电平阈值和使用4/6--5/6电平阈值 为置的电压上升时间相同；Tdly可使用如下方法计算：
Tdly＝Tv1-(Tv2-Tv1)＝2*Tv1-Tv2。
由此，可以获得精确的通道测量信号。请注意，由于TDR信号是经过反射信号叠加，Tdly应该是实际路径时延的2倍。
需要说明的是，以上测试流程均基于时间参数计算，而步骤S23中，信号S2经过外部的RC滤波电路(低通滤波器)后，由模拟数字转换器ADC4测量实际得到的是电压值，而非时间值。因此，需要通过时间/电压的转换校验，获得各个通道的时间/电压系数，定义为k，单位是(ps/mv)。
本领域技术人员清楚，在模拟数字转换器ADC4的测量过程中，电压值始终是存在误差的。尤其是FPGA1模块普通引脚送出的信号，在这个测试过程中，本发明的技术方案实际不需要对信号的高电平幅值进行校准，只需要得到精确的电压时间关系即可。
请参阅图5，图5所示为本发明实施例中的时间/电压系数校验原理示意图。以N路通道中的某一通道来说明该时间/电压系数校验的实现方法如下：
步骤S251：设置校验图样一个周期为T0，设定判决门限为5/6电平阈值；
步骤S252：设置高电平时间为Th，模拟数字转换器ADC4测得电压值为V1；
步骤S253：重新设置高电平时间为Th+ΔT，模拟数字转换器ADC4测得电压值为V2；
步骤S254：分析可得出ΔT对应ΔV＝(V2-V1)，故ΔT/ΔV，得到系数k(ps/mv)，即是时间/电压系数。
需要说明的是，上述时间/电压系数校准需要基于一个前提：增加ΔT只会改变高低电平占比，不会影响上升下降边沿，因此，需要确保增加前后上升下降过程完整，即预留足够上升下降时间。而且，需要注意的是，时间/电压系数校准系数仅适用于当前T0。
接下来，在获得时间/电压系数k后，可以将模拟数字转换器ADC4测量的电压量，转换为时间量。可根据步骤S4中所用方法，分别获得N路通道的测量信号Tdly。
实际应用的过程中，为确保获得最佳的精度，一般会先进行大量程的粗 测，然后根据预估测量结果进行精确测量。
实施例1
下面以一个优选的实施例，说明本发明的采用模拟测量的低成本数字TDR技术具体实施方法，该描述是以一路通道进行的，其它的不再赘述。另外，在实际应用的过程中，为确保获得最佳的精度，一般会先进行大量程的粗测，然后根据预估测量结果进行精确测量。
具体的，基于数字TDR技术的模拟测量方法具体实施步骤如下：
首先，大量程粗侧。如图2所示，假设该有N条通道(图示中为32路，0-31)，在测量和计算N路通道的延时信息过程中，对于每一条通道，将测量通道TDR_EN设置为1，选通TDR测试图样。例如，将TDR_DC_SEL设置为0，就是选通通道0进行测试。
如图3所示，配置N路PWM生成器1-1，设定T0＝100ns，Th＝50ns；配置引脚驱动器PE 2，设定门限a判决电平为1/6*3.3V(假定PE输出信号高电平为3.3V)，假定ADC测量电压为1.848V(FPGA的引脚输出高电平也为3.3V)，计算信号的占空比为1.848/3.3＝0.56。
也就是说，高电平的时间为100*0.56＝56ns，信号S2a的高电平时间可粗略认为，是50ns+2*Tdly，故而粗略计算Tdly＝3ns，可使用T0＝20ns的精确测量模型。
第二，将使能信号TDR_EN设置为0，关闭TDR测试图样的发送。修改PWM生成器配置，T0＝20ns，Th＝10ns；将使能信号TDR_EN重新设置为1，继续后续测量。
第三，进行系数校验，如图5所示，测量T0＝20ns，Th＝10ns，ADC测得电压V1。重复步骤2，设置T0＝20ns，Th＝15ns，模拟数字转换器ADC4测得电压V2。计算可得到时间/电压系数：
k＝5*1000/(V2-V1)*1000＝5/(V2-V1)，单位是ps/mv。
第四，重复上述第二步骤，设置T0＝20ns，Th＝10ns，开始精确测量。
第五，如图3所示，配置引脚驱动器PE，设定判定门限a判决电平为1/6*3.3V，模拟数字转换器ADC测量电压为Va。再重新配置引脚驱动器PE，设定门限b判决电平为5/6*3.3V，模拟数字转换器ADC的测量电压为 Vb，计算两个门限信号之间的测量电压差为Vab2＝(Va-Vb)/2。
第六，重复上述第五步骤，设定判定门限a判决电平为2/6*3.3V，设定判定门限b判决电平为4/6*3.3V，计算两个设定判定门限信号之间的测量电压差为Vab1。
第七，如图3所示，Tdly＝2*Tv1-Tv2。结合系数k，可计算出Tdly＝(2*Vab1-Vab2)*1000*k，单位为ps。从而得到通道0的两倍测量信号，即Tdly/2就是所需的通道测量信号。
第八，如图2所示，将TDR_DC_SEL设置为1～31，选通其它测试通道，重复上述第一步骤至第七步骤，就可以获得N个通道的测量信号。
上述各个通道测量信号测试完成后，结合通道时延补偿技术，对各个通道进行同步校准，可有效提高引脚时间同步精度，保证后续测试过程的准确性。
以上所述的仅为本发明的优选实施例，所述实施例并非用以限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。

Claims (7)

  1. 一种基于数字TDR技术的模拟测量装置，用于测量和计算N路通道的延时信息，以及在正式测量时，对测量数据进行延时校正；其特征在于，包括FPGA模块(1)、N个与所述N路通道相应的引脚驱动器PE(2)、RC滤波电路(3)和模拟数字转换器ADC(4)；其中，
    FPGA模块(1)用于实现所述N路通道测试信号的发送、接收和数据通路的选择；其包括N路PWM生成器(1-1)、N路发送信号选择器(1-2)、N路数据发送通路(1-3)、N路数据接收通路(1-4)和一个数据通路选择器(1-5)；
    所述PWM生成器(1-1)用于生成每个通道的TDR测试图样；每个通道的所述发送信号选择器(1-2)通过使能信号TDR_EN，选择发送正常测试图样或TDR测试图样；
    每个通道的数据发送通路(1-3)包括第一可编程延时单元和发送逻辑资源单元，所述第一可编程延时单元用于在正常测试时，将本通道的正常测试图样进行延时同步，所述发送逻辑资源单元用于将所述TDR测试图样或正常测试图样发送到引脚驱动器PE(2)；其中，所述第一可编程延时单元的初始化值为0；
    每个所述引脚驱动器PE(2)用于对相应通道的TDR测试图样进行端口电平转换，根据电平阈值判定规则，配置不同的电平阈值；所述引脚驱动器PE(2)包括接收通道端cmpl、发送通道端data和与测试双向通道端；
    每个通道的数据接收通路(1-4)包含接收逻辑资源单元和第二可编程延时单元，所述逻辑资源单元用于接收通过引脚驱动器PE(2)输入的相应通道的测量信号，所述第二可编程延时单元用于将相应通道的测量信号进行延时同步；所述第二可编程延时用于在正常测试时，将本通道的正常接收的测试数据进行延时同步；
    所述数据通路选择器(1-5)，通过选择信号TDR_DC_SEL，选通所述N路通道之一，将测量到的TDR信号传送到外部测量单元；
    所述RC滤波电路(3)对经过判定选择之后的TDR信号，进行低通滤波，并将占空比信号转化为直流电压的模拟量信号；
    所述模拟数字转换器ADC(4)，将所述RC滤波电路(3)滤波以后 的直流电压的模拟量信号，进行模拟-数字转换，得到数字化的电压值，对所述TDR测试图样的TDR反射信号产生不同占空比的判定结果，配合时间/电压系数，从而得到相应通道的测量信号。
  2. 根据权利要求1所述的基于数字TDR技术的模拟测量装置，其特征在于，所述FPGA模块(1)还包括参数配置单元，所述参数配置单元PWM配置所述PWM生成器(1-1)连续的阶跃信号周期参数，确认所述TDR测试图样的周期和占空比，以及设定所述引脚驱动器PE(2)的阈值电平。
  3. 一种采用权利要求1所述的基于数字TDR技术的模拟测量装置的测量方法，其特征在于，包括用于测量和计算N路通道的延时信息的测量信号生成步骤和在正式测量时，对测量数据进行延时校正的测试步骤，所述延信息生成步骤包括：
    步骤S1：配置FPGA1内部模块参数，包括设定PWM生成器(1-1)参数，确认TDR测试图样的周期和占空比；设定发送信号选择器(1-2)，将测试通道的TDR_EN设置为1，选通TDR测试图样；设定数据通路选择器(1-5)，通过TDR_DC_SEL选择所需测试通道；
    步骤S2：设定引脚驱动器PE(2)的阈值电平，对接收到的TDR信号进行判定，对连接器反馈回来的所述TDR信号结果通过引脚驱动器PE(2)的引脚传输到所述FPGA模块(1)的数据接收通路(1-4)；然后经过数据通路选择器(1-5)，选通输出到外部测量单元；其中，外部测量单元可以包括RC滤波电路(3)和模拟数字转换器ADC(4)；
    步骤S3：信号经过RC滤波电路3转换为直流电平，在模拟数字转换器ADC(4)处完成数字信号转换；得到TDR信号对应的数字电压；
    步骤S4：重复步骤S2，设置不同的阈值电平，获取当前一路通道多组TDR信号对应的数字电压；
    步骤S5：根据对应的TDR信号测量方法，得出当前通道的测量信号；
    步骤S6：重复步骤S1-S5，测量所有通道的测量信号；
    步骤S7：取大于等于所有通道的测量信号作为用于同步的测量信号，并将该用于同步的测量信号输入到和第一可编程延时单元和第二可编程延时单元，以备后续正常测量时对测量数据进行延时校正用。
  4. 根据权利要求3所述的基于数字TDR技术的模拟测量方法，其特征 在于，所述步骤S2具体包括：
    步骤S21：PWM生成器(1-1)持续发送一个周期为T0的方波信号S0，其中，该方波信号S0高电平宽度为Th；
    步骤S22：该方波信号S0经过引脚驱动器PE(2)发送并经选定的测试通道，到达DUT引脚端，由于所述DUT引脚端悬空，R＝∞，形成TDR反射信号，源信号与TDR反射信号叠加，形成信号S1；
    步骤S23：该信号S1经过引脚驱动器PE(2)执行多门限判定的流程后形成信号S2，信号S2根据不同的比较门限，生成两个门限之间的时间差Tv；其中，Tv包含两部分时间，一个是通道时延Tdly，一个是电压上升时间；
    步骤S24：采用多个门限位置判定的方法，消除电压上升时间的影响，获得准确的通道时延Tdly。
  5. 根据权利要求4所述的基于数字TDR技术的模拟测量方法，其特征在于，所述多门限判定的流程具体包括：
    步骤S241：所述引脚驱动器PE(2)分别使用1/6和5/6电平阈值，比较门限a为1/6，比较门限b为5/6；依照步骤S23的方法，获得门限时间差Tv2；
    步骤S242：所述引脚驱动器PE(2)分别使用2/6和4/6电平阈值，比较门限a为2/6，比较门限b为4/6；依照步骤S23的方法，获得门限时间差Tv1；
    步骤S243：设定上述步骤中，使用1/6--5/6电平阈值和使用2/6--4/6电平阈值为置的电压上升时间相同，且使用3/6--4/6电平阈值和使用4/6--5/6电平阈值为置的电压上升时间相同；Tdly可使用如下方法计算：
    Tdly＝Tv1-(Tv2-Tv1)＝2*Tv1-Tv2。
  6. 根据权利要求4所述的基于数字TDR技术的模拟测量方法，其特征在于，所述步骤S24后还包括步骤S25：依次对N路通道中的每一通道进行时间/电压系数校验。
  7. 根据权利要求6所述的基于数字TDR技术的模拟测量方法，其特征在于，所述步骤S25具体包括：
    步骤S251：设置校验图样一个周期为T0，设定判决门限为1/6、2/6、 3/6、4/6、5/6电平阈值之一；
    步骤S252：设置高电平时间为Th，模拟数字转换器ADC(4)测得电压值为V1；
    步骤S253：重新设置高电平时间为Th+ΔT，模拟数字转换器ADC(4)测得电压值为V2；
    步骤S254：分析可得出ΔT对应ΔV＝(V2-V1)，故ΔT/ΔV，得到系数k(ps/mv)，即是时间/电压系数。
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