WO2023147732A1 - 一种时序校准方法和系统 - Google Patents

一种时序校准方法和系统 Download PDF

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WO2023147732A1
WO2023147732A1 PCT/CN2022/127520 CN2022127520W WO2023147732A1 WO 2023147732 A1 WO2023147732 A1 WO 2023147732A1 CN 2022127520 W CN2022127520 W CN 2022127520W WO 2023147732 A1 WO2023147732 A1 WO 2023147732A1
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channel
test
output
clock
timing calibration
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PCT/CN2022/127520
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English (en)
French (fr)
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董亚明
韩洁
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苏州华兴源创科技股份有限公司
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Publication of WO2023147732A1 publication Critical patent/WO2023147732A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits

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  • the present invention relates to the field of chip testing, and more particularly, to a timing calibration method and system.
  • Digital chip testing machines usually support pattern (test vector) testing, which is used for digital chips to judge whether the function of the chip is normal by testing the pattern, so as to realize rapid testing of digital chips during mass production.
  • pattern test vector
  • Digital chip testing machines generally support hundreds of test channels, and the digital signals output by each test channel need to be output to the pins of the digital chip under test at the same time, that is, the digital signals need to be edge-aligned to ensure that they are output to the pins of the digital chip under test. Timing between signals at pins is correct. To ensure that the edges of digital signals output by all test channels of all digital chip testers are aligned, it is necessary to calibrate the timing of digital signals.
  • An object of the present invention is to provide a timing calibration method and system to solve at least one of the problems in the prior art.
  • the present invention adopts the following technical solutions:
  • the first aspect of the present invention provides a timing calibration method for timing calibration of test signals in several test channels of a digital testing machine, the method comprising:
  • a window comparator is used to compare the test signals output by the two gated test channels, and output the comparison result to the FPGA;
  • test signal output by one of the two gated test channels is transmitted to the FPGA through the clock buffer as the sampling clock;
  • FPGA collects the output result of the window comparator according to the sampling clock, and sends the result information to the control terminal;
  • the control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output structure of the FPGA, so as to complete the timing calibration of the test channel.
  • the method further includes: using the test channel where the sampling clock is located as a calibration reference channel, sequentially selecting one of the other multiple test channels to communicate with the window comparator as the channel to be calibrated for timing calibration.
  • multiple excitation signal test channels of the digital testing machine are connected to the input terminals of the relay network, the first output terminal of the relay network is connected to the first input terminal of the window comparator, and the first output terminal of the relay network is connected to the first input terminal of the window comparator.
  • Two output ends connect the second input end of described window comparator and the input end of described clock buffer, the output end of described window comparator connects the first input end of described FPGA, the output end of described clock buffer
  • the second input end of the FPGA is connected, and the output end of the FPGA is connected to the control terminal.
  • control terminal controls the relays in the relay network to open or close, so that the two gated excitation signal test channels are respectively output to the first output terminal and the second output terminal of the relay network.
  • the control system controls the excitation signal test channel of the digital testing machine to adjust the phase of the clock output by the channel to be calibrated until it is calibrated
  • the clock phase of the channel is edge-aligned with the clock signal generated by the reference channel.
  • a binary search method is used to adjust the phase of the clock output by the channel to be calibrated.
  • the output delay of the calibrated channel is N nS.
  • the output delay of the calibrated channel is adjusted to N/ 2nS, at this time, if the phase of the calibrated channel is measured to be lagging behind the reference channel, the phase of the calibrated channel is ahead of the reference channel in the range of 0 ⁇ N/2nS; if the measured phase of the calibrated channel is ahead of the reference channel, the phase of the calibrated channel The phase lead of the reference channel is in the range of N/2 ⁇ N nS, where N>0.
  • the second aspect of the present invention provides a timing calibration system for executing the above timing calibration method, the system includes: a digital tester, a control terminal and a timing calibration board;
  • the timing calibration board includes: a relay network, a window comparator, a clock buffer and an FPGA;
  • the digital test machine contains multiple excitation signal test channels
  • the relay network is used to gate any two excitation signal test channels of multiple excitation signal test channels of the digital test machine and output them to the window comparator respectively;
  • the window comparator is used to compare the clock signals output by the two excitation signal test channels after gating, judge whether the edges of the two clock signals are aligned, and output the judgment result to the FPGA;
  • Clock buffer is used for outputting to FPGA as sampling clock after the clock signal buffering of one of the excitation signal test channels output of selected pass;
  • the FPGA is used to collect the comparison result of the window comparator according to the sampling clock, and send the result to the control terminal;
  • the control terminal is used to control the excitation signal test channel to generate a clock signal, judge whether the clock signals generated by the two excitation signal test channels are edge-aligned, and perform timing calibration.
  • the relay network and the window comparator support an operating frequency of 100-800 MHz.
  • control terminal controls one of the relay network gating test channels to communicate with the clock buffer input end and the second input end of the high-speed window comparator as a calibration reference channel, and sequentially gating other multiple One of the excitation signal test channels is connected to the first input terminal of the window comparator as the channel to be calibrated for timing calibration.
  • the technical scheme of the present invention provides a timing calibration method and system, the system can realize timing calibration without an external oscilloscope and other instruments, and is easy to use.
  • the timing calibration method of the present invention can quickly realize the timing calibration of the test channel of the digital testing machine by using the high-speed relay network and the high-speed window comparator in the timing calibration board, which improves the timing calibration efficiency, and the calibration accuracy of all test channels can reach Within 50ps, meeting the calibration accuracy requirements.
  • FIG. 1 shows a schematic diagram of a timing calibration system provided by an embodiment of the present invention.
  • FIG. 2 shows a flowchart of a timing calibration method provided by an embodiment of the present invention.
  • an embodiment of the present invention provides a timing calibration system, including a digital testing machine 1 , a control terminal 2 and a timing calibration board 3 .
  • the digital tester 1 includes several test channels, and each test channel transmits a corresponding test pattern (Pattern), and the test pattern is sent to the pins of the product under test by the digital tester as a test signal.
  • a common digital tester 1 includes 512, 768, 1024 test channels. That is, 512 test vectors are correspondingly transmitted in 512 test channels.
  • the control terminal 2 can be a computer or a cloud server, and is mainly used to control the timing calibration process.
  • Timing calibration board 3 includes: high-speed relay network 31, high-speed window comparator 32, clock buffer 33 and FPGA 34.
  • the high-speed relay network 31 is used for gating any two test channels of the digital testing machine, so that the two test vectors in the two gated test channels are respectively output to the high-speed window comparator 32 .
  • the high-speed relay network 31 and the high-speed window comparator 32 support a maximum operating frequency of 800MHz.
  • the high-speed window comparator 32 is used for comparing the test vector signals output by the two test channels after gating, and judges whether the edges of the two test vector signals are aligned, and outputs the judgment result to the FPGA 34;
  • Clock buffer 33 is used for outputting to FPGA 34 as sampling clock after the test vector signal buffering that one of them test channel produces;
  • the FPGA 34 is used to collect the comparison result of the high-speed window comparator 32 according to the sampling clock, and send the result to the control terminal 2.
  • the control terminal 2 is used to control the excitation signal test channel to generate a clock signal, judge whether the clock signals generated by the two excitation signal test channels are edge-aligned, and perform timing calibration.
  • the relay network and the window comparator support an operating frequency of 100-800 MHz.
  • control terminal controls one of the relay network gating test channels to communicate with the clock buffer input terminal and the second input terminal of the window comparator as a calibration reference channel, in turn One of the other multiple excitation signal test channels is selected to communicate with the first input terminal of the high-speed window comparator as the channel to be calibrated for timing calibration.
  • another embodiment of the present invention provides a timing calibration method for timing calibration of test signals in several test channels of a digital testing machine, the method comprising:
  • a window comparator is used to compare the test signals output by the two gated test channels, and output the comparison result to the FPGA;
  • test signal output by one of the two gated test channels is transmitted to the FPGA through the clock buffer as the sampling clock;
  • FPGA collects the output result of the window comparator according to the sampling clock, and sends the result information to the control terminal;
  • the control terminal adjusts the clock phase of the test signal in the corresponding test channel according to the output structure of the FPGA, so as to complete the timing calibration of the test channel.
  • the multiple excitation signal test channels of the digital testing machine 1 are connected to the input end of the high-speed relay network 31, and the first output end of the high-speed relay network 31 is connected to the high-speed window comparator 32
  • the first input terminal of the high-speed relay network 31 is connected to the second input terminal of the high-speed window comparator 32 and the input terminal of the clock BUFFE33, and the output terminal of the high-speed window comparator 32 is connected to the The first input end of FPGA 34, the output end of described clock buffer 33 is connected the second input end of described FPGA 34, and the output end of described FPGA 34 is connected described control terminal 2.
  • control terminal 2 controls the relays in the high-speed relay network 31 to open or close, so that the two gated excitation signal test channels are output to the high-speed relay network 31 respectively.
  • At least 512 test channels included in the digital tester 1 are connected to the input of the high-speed relay network 31, and the 512 test channels are corresponding to transmit 512 test vectors (Pattern), and the high-speed relay network 31 connects the digital tester
  • At least 512 test channels included in 1 randomly select two test channel outputs the two output terminals of the high-speed relay network 31 are connected to the input terminal of the high-speed window comparator 32, and the output terminal of one of the high-speed relay network 31 is connected to the clock at the same time
  • the input end of buffer 33, the output end of high-speed window comparator 32 is connected FPGA
  • the output end of clock buffer 33 is connected FPGA
  • FPGA utilizes the sampling clock that clock buffer 33 outputs, the comparison result of sampling high-speed window comparator 32, Then the sampling result is transmitted to the control terminal 2, for example, the control terminal 2 is a computer, and the computer judges whether the edges of the two test channels in this test are aligned, and performs timing calibration.
  • control terminal 2 controls one of the high-speed relay network 31 gating test channels to communicate with the input terminal of the clock buffer 33 and the second input terminal of the high-speed window comparator 32
  • the reference channel is called channel 2
  • one of the other multiple excitation signal test channels is sequentially selected to communicate with the first input terminal of the high-speed window comparator as the calibrated channel for timing calibration.
  • the calibrated channel is called for channel 1.
  • control terminal 2 sequentially gates other excitation signal test channels that are not gated by the high-speed window comparator 32 , and performs timing calibration on the calibrated channel 1 according to the reference channel 2 .
  • the computer controls the two gated excitation signal test channels in the digital testing machine to generate a clock signal, for example, the clock signal is a 100MHz clock signal.
  • the method further includes: using the test channel where the sampling clock is located as the calibration reference channel, sequentially selecting one of the other multiple test channels to communicate with the window comparator as the channel to be calibrated timing alignment.
  • the control system controls the digital testing machine to adjust the clock output by the channel to be calibrated by stimulating the signal test channel phase until the clock phase of the channel being calibrated is edge-aligned with the clock signal generated by the reference channel.
  • the output result of the high-speed window comparator is random 0 and 1
  • the channel to be calibrated is aligned with the edge of the clock signal generated by the reference channel;
  • the output result of the high-speed window comparator is fixed 0 or 1.
  • the edges of the clock signals generated by the channel to be calibrated and the reference channel are not aligned, so it can be judged whether the edges of the clock signals generated by the channel to be calibrated and the reference channel are aligned, thereby realizing timing calibration.
  • the control system 2 controls the digital tester 1 to adjust the clock phase output by the calibrated channel until the edge of the clock signal generated by the calibrated channel is aligned with the reference channel
  • the binary search method is used to adjust the phase of the clock output by the channel to be calibrated so that the edges of the clock signal generated by the channel to be calibrated are aligned with the reference channel.
  • the output of the calibrated channel is delayed by N nS, and if it is measured that the phase of the calibrated channel is lagging behind the reference channel, the calibrated channel The output delay is N/2nS.
  • the phase of the calibrated channel is ahead of the reference channel in the range of 0 ⁇ N/2nS. If the measured phase of the calibrated channel is ahead of the reference channel, Then the phase of the calibrated channel is ahead of the reference channel in the range of N/2 ⁇ N nS, where N>0.
  • channel 1 is a channel to be calibrated, that is, a channel that is connected to the first input end of the high-speed window comparator by one of the other multiple excitation signal test channels;
  • channel 2 is a reference channel, that is, the high-speed relay network will be One of the two excitation signal test channels of the strobe is connected with the clock buffer input terminal and the second input terminal of the high-speed window comparator.
  • the measured channel 1 ratio The phase of channel 2 is ahead, increase the output delay of channel 1 by 5nS, and then the measured phase of channel 1 is lagging behind that of channel 2, then modify the output delay of channel 1 to 2.5nS, and then if the measured phase of channel 1 is lagging behind that of channel 2, then the phase of channel 1 is lagging behind that of channel 2. 2
  • the phase lead is in the range of 0 ⁇ 2.5nS. If the phase lead of channel 1 is measured to be ahead of channel 2, then the phase lead of channel 1 is in the range of 2.5 ⁇ 5nS compared to channel 2. According to the range judgment and then binary judgment search, finally find the actual phase Difference.
  • the calibration of the test system provided by the invention does not need to be connected to the digital chip to be tested, and the digital testing machine is connected to the digital chip to be tested after the calibration is completed.
  • the calibration accuracy of the reference channel and all calibrated channels of the test system of the present invention is 50 ps, which is mainly related to the parameters of the high-speed window comparator.
  • timing calibration system provided in this embodiment are similar to the timing calibration method described above, and relevant parts can refer to the above description, which will not be repeated here.
  • the timing calibration system and method provided by the embodiments of the present invention do not need an external oscilloscope and other instruments, and use a high-speed window comparator to quickly realize the timing calibration of the pattern test channel of the digital testing machine, improve the timing calibration efficiency, and the calibration accuracy can reach 50ps Within, meet the calibration accuracy requirements.

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Abstract

本发明公开一种时序校准方法和系统，该时序校准方法，用于对数字测试机的若干测试通道中的测试信号进行时序校准，该方法包括：选通数字测试机的任意两个测试通道，以输出测试信号；采用窗口比较器对选通的两个测试通道输出的测试信号进行比较，并将比较结果输出到FPGA；被选通的两个测试通道其中之一输出的测试信号经时钟缓冲器传输到FPGA作为采样时钟；FPGA根据采样时钟采集窗口比较器的输出结果，并将结果信息发送给控制终端；控制终端根据FPGA的输出结构调整对应的测试通道中测试信号的时钟相位，以完成对测试通道的时序校准。

Description

一种时序校准方法和系统 技术领域
本发明涉及芯片测试领域，更具体地，涉及一种时序校准方法和系统。
背景技术
数字芯片测试机通常支持pattern(测试向量)测试，用于数字芯片通过测试pattern来判断芯片功能是否正常，从而实现数字芯片大规模量产时的快速测试。
数字芯片测试机一般支持几百个测试通道，每个测试通道输出的数字信号都需要同时输出到待测数字芯片的引脚处，即数字信号需要边沿对齐，以保证输出到待测数字芯片引脚处的信号间时序是正确的。要保证所有数字芯片测试机所有测试通道输出的数字信号边沿对齐，需要通过对数字信号时序校准来实现。
现有方法一般通过高速示波器来逐个判断测试通道测试边沿是否对齐，该方法需要额外的高速示波器，成本高使用不便；或者通过两个通道输出时钟后的信号相与，再将相与的信号通过电容充电后采集电压的方式测算边沿是否对齐，该方法需要通过电容充电和ADC采样导致测试时间较长。
发明内容
本发明的一个目的在于提供一种时序校准方法和系统，以解决现有技术存在的问题中的至少一个。
为达到上述目的，本发明采用下述技术方案：
本发明第一方面提供一种时序校准方法，用于对数字测试机的若干测试通道中的测试信号进行时序校准，该方法包括：
选通数字测试机的任意两个测试通道，以输出测试信号；
采用窗口比较器对选通的两个测试通道输出的测试信号进行比较，并将比较结果输出到FPGA；
被选通的两个测试通道其中之一输出的测试信号经时钟缓冲器传输到FPGA作为采样时钟；
FPGA根据采样时钟采集窗口比较器的输出结果，并将结果信息发送给控制终端；
控制终端根据FPGA的输出结构调整对应的测试通道中测试信号的时钟相位，以完成对测试通道的时序校准。
可选地，该方法进一步包括：以所述采样时钟所在的测试通道作为校准基准通道，依次选通其他多个测试通道之一与所述窗口比较器连通作为被校准通道进行时序校准。
可选地，所述数字测试机的多个激励信号测试通道连接继电器网络的输入端，所述继电器网络的第一输出端连接所述窗口比较器的第一输入端，所述继电器网络的第二输出端连接所述窗口比较器的第二输入端和所述时钟缓冲器的输入端，所述窗口比较器的输出端连接所述FPGA的第一输入端，所述时钟缓冲器的输出端连接所述FPGA的第二输入端，所述FPGA的输出端连接所述控制终端。
可选地，所述控制终端控制所述继电器网络中的继电器断开或闭合，使被选通的两个激励信号测试通道分别输出到所述继电器网络的第一输出端和第二输出端。
可选地，如果被校准通道产生的时钟信号边沿与基准通道产生的时钟信号边沿不对齐，所述控制系统控制所述数字测试机激励信号测试通道调整被校准通道输出的时钟相位，直到被校准通道的时钟相位与基准通道产生的时钟信号边沿对齐。
可选地，利用二分查找法调整被校准通道输出的时钟相位。
可选地，若测得被校准通道比基准通道相位超前，则令被校准通道输出延迟N nS，此时若测得被校准通道比基准通道相位滞后，则调整被校准通道输出延迟为N/2nS，此时若测得被校准通道比基准通道相位滞后，则被校准通道比基准通道相位超前在0～N/2nS范围，若测得被校准通道比基准通道相位超前，则被校准通道比基准通道相位超前在N/2～N nS范围，其中N＞0。
本发明第二方面提供一种执行上述时序校准方法的时序校准系统，该系统包括：数字测试机、控制终端和时序校准板卡；
所述时序校准板卡包括：继电器网络、窗口比较器、时钟缓冲器和FPGA；
其中，数字测试机包含多个激励信号测试通道；
继电器网络用于将数字测试机的多个激励信号测试通道选通任意两个激励信号测试通道分别输出到窗口比较器；
窗口比较器用于对选通后的两个激励信号测试通道输出的时钟信号进行比较，判断两个时钟信号边沿是否对齐，并将判断结果输出到FPGA；
时钟缓冲器用于将所选通的激励信号测试通道之一输出的时钟信号缓 冲后输出到FPGA作为采样时钟；
FPGA用于根据采样时钟采集窗口比较器的比较结果，并将结果发送给控制终端；
控制终端用于控制激励信号测试通道产生时钟信号，判断两个激励信号测试通道产生的时钟信号是否边沿对齐，并进行时序校准。
可选地，所述继电器网络和所述窗口比较器支持100～800MHz工作频率。
可选地，所述控制终端控制所述继电器网络选通测试通道之一与所述时钟缓冲器输入端和所述高速窗口比较器第二输入端连通用作校准基准通道，依次选通其他多个激励信号测试通道之一与所述窗口比较器第一输入端连通作为被校准通道进行时序校准。
本发明的有益效果如下：
本发明所述技术方案，提供了一种时序校准方法和系统，该系统无需外接示波器等仪器即可实现时序校准，使用方便。本发明所述时序校准方法通过利用高速继电器网络和时序校准板中的高速窗口比较器，可以快速实现数字测试机测试通道的时序校准，提高了时序校准效率，并且所有测试通道的校准精度能够达到50ps以内，满足校准精度要求。
附图说明
下面结合附图对本发明的具体实施方式作进一步详细的说明。
图1示出本发明实施例提供的一种时序校准系统的示意图。
图2示出本发明实施例提供的一种时序校准方法的流程图。
具体实施方式
为了更清楚地说明本发明，下面结合优选实施例和附图对本发明做进一步的说明。附图中相似的部件以相同的附图标记进行表示。本领域技术人员应当理解，下面所具体描述的内容是说明性的而非限制性的，不应以此限制本发明的保护范围。
如图1所示，本发明一个实施例提供了一种时序校准系统，包括数字测试机1、控制终端2和时序校准板卡3。
其中，数字测试机1包含若干测试通道，每个测试通道中对应传输一个测试向量(Pattern)，所述测试向量作为测试信号被数字测试机发送至待测产品引脚。常见的数字测试机1包含有512、768、1024个测试通道。即512 个测试通道中对应传输512个测试向量。
控制终端2可以为计算机或云端服务器，主要用于控制时序校准流程的进行。
时序校准板卡3包括：高速继电器网络31、高速窗口比较器32、时钟缓冲器33和FPGA 34。
其中，高速继电器网络31用于选通数字测试机的任意两个测试通道，使得被选通的两个测试通道中的两个测试向量分别输出到高速窗口比较器32中。在一个具体示例中，所述高速继电器网络31和所述高速窗口比较器32最大支持800MHz工作频率。
高速窗口比较器32用于对选通后的两个测试通道输出的测试向量信号进行比较，判断两个测试向量信号的边沿是否对齐，并将判断结果输出到FPGA 34；
时钟缓冲器33用于将其中一个测试通道产生的测试向量信号缓冲后输出到FPGA 34作为采样时钟；
FPGA 34用于根据采样时钟采集高速窗口比较器32的比较结果，并将结果发送给控制终端2。
控制终端2用于控制激励信号测试通道产生时钟信号，判断两个激励信号测试通道产生的时钟信号是否边沿对齐，并进行时序校准。
在一种可能的实现方式中，所述继电器网络和所述窗口比较器支持100～800MHz工作频率。
在一种可能的实现方式中，所述控制终端控制所述继电器网络选通测试通道之一与所述时钟缓冲器输入端和所述窗口比较器第二输入端连通用作校准基准通道，依次选通其他多个激励信号测试通道之一与所述高速窗口比较器第一输入端连通作为被校准通道进行时序校准。
如图2所示，本发明另一个实施例提供一种时序校准方法，用于对数字测试机的若干测试通道中的测试信号进行时序校准，该方法包括：
选通数字测试机的任意两个测试通道，以输出测试信号；
采用窗口比较器对选通的两个测试通道输出的测试信号进行比较，并将比较结果输出到FPGA；
被选通的两个测试通道其中之一输出的测试信号经时钟缓冲器传输到FPGA作为采样时钟；
FPGA根据采样时钟采集窗口比较器的输出结果，并将结果信息发送给控制终端；
控制终端根据FPGA的输出结构调整对应的测试通道中测试信号的时钟相位，以完成对测试通道的时序校准。在一种可能的实现方式中，所述数字测试机1的多个激励信号测试通道连接所述高速继电器网络31的输入端，高速继电器网络31的第一输出端连接所述高速窗口比较器32的第一输入端，高速继电器网络31的第二输出端连接所述高速窗口比较器32的第二输入端和所述时钟BUFFE33的输入端，所述高速窗口比较器32的输出端连接所述FPGA 34的第一输入端，所述时钟缓冲器33的输出端连接所述FPGA 34的第二输入端，所述FPGA 34的输出端连接所述控制终端2。
在一种可能的实现方式中，所述控制终端2控制所述高速继电器网络31中的继电器断开或闭合，使被选通的两个激励信号测试通道分别输出到所述高速继电器网络31的第一输出端和第二输出端。
在一个具体示例中，数字测试机1包含的至少512个测试通道均连接到高速继电器网络31的输入端，512个测试通道对应传输512个测试向量(Pattern)，高速继电器网络31将数字测试机1包含的至少512个测试通道任意选择两个测试通道输出，高速继电器网络31的两个输出端均连接到高速窗口比较器32的输入端，同时其中一个高速继电器网络31的输出端连接到时钟缓冲器33的输入端，高速窗口比较器32的输出端连接FPGA，时钟缓冲器33的输出端连接FPGA，FPGA利用时钟缓冲器33输出的采样时钟，来采样高速窗口比较器32的比较结果，然后将采样结果传给控制终端2，例如控制终端2为计算机，由计算机判断本次测试的两个测试通道是否边沿对齐，并进行时序校准。
在一种可能的实现方式中，所述控制终端2控制所述高速继电器网络31选通测试通道之一与所述时钟缓冲器33输入端和所述高速窗口比较器32第二输入端连通用作校准基准通道，该基准通道称为通道2，依次选通其他多个激励信号测试通道之一与所述高速窗口比较器第一输入端连通作为被校准通道进行时序校准，该被校准通道称为通道1。
在一个具体示例中，所述控制终端2将未经高速窗口比较器32选通的其他激励信号测试通道依次进行选通，并根据所述基准通道2对被校准通道1进行时序校准。
在一个具体示例中，计算机控制数字测试机中被选通的两个激励信号测试通道产生时钟信号，例如时钟信号为100MHz时钟信号。
在一种可能的实现方式中，该方法进一步包括：以所述采样时钟所在的测试通道作为校准基准通道，依次选通其他多个测试通道之一与所述窗口比 较器连通作为被校准通道进行时序校准。
在一种可能的实现方式中，如果被校准通道产生的时钟信号边沿与基准通道产生的时钟信号边沿不对齐，所述控制系统控制所述数字测试机激励信号测试通道调整被校准通道输出的时钟相位，直到被校准通道的时钟相位与基准通道产生的时钟信号边沿对齐。
在一个具体示例中，所述高速窗口比较器的输出结果为随机的0和1时，被校准通道与基准通道产生的时钟信号边沿对齐；所述高速窗口比较器的输出结果为固定的0或1时，被校准通道与基准通道产生的时钟信号边沿不对齐，由此可以判断被校准通道与基准通道产生的时钟信号是否边沿对齐，从而实现时序校准。
当被校准通道与基准通道产生的时钟信号边沿不对齐时，所述控制系统2控制所述数字测试机1调整被校准通道输出的时钟相位，直到被校准通道与基准通道产生时钟信号边沿对齐，其中利用二分查找法调整被校准通道输出的时钟相位使得被校准通道与基准通道产生的时钟信号边沿对齐。
在一种可能的实现方式中，若测得被校准通道比基准通道相位超前，则令被校准通道输出延迟N nS，此时若测得被校准通道比基准通道相位滞后，则调整被校准通道输出延迟为N/2nS，此时若测得被校准通道比基准通道相位滞后，则被校准通道比基准通道相位超前在0～N/2nS范围，若测得被校准通道比基准通道相位超前，则被校准通道比基准通道相位超前在N/2～N nS范围，其中N＞0。
在一个具体示例中，通道1为被校准通道，即其他多个激励信号测试通道之一与所述高速窗口比较器第一输入端连通的通道；通道2为基准通道，即高速继电器网络将被选通的两个激励信号测试通道之一与所述时钟缓冲器输入端和所述高速窗口比较器第二输入端连通的通道，通道1和通道2都没有输出延迟时，测得通道1比通道2相位超前，增加通道1输出延迟5nS，然后测得通道1比通道2相位滞后，则修改通道1输出延迟为2.5nS，然后如果测得通道1比通道2相位滞后，则通道1比通道2相位超前在0～2.5nS范围,如果测得通道1比通道2相位超前，则通道1比通道2相位超前在2.5～5nS范围，根据范围判断再依次二分判断查找，最终找出实际的相位差。
本发明提供的测试系统校准不需要连接待测数字芯片，校准完成后数字测试机再连接待测数字芯片。
在一个具体示例中，本发明的测试系统的基准通道和所有被校准通道的校准精度为50ps，该精度主要是和高速窗口比较器的参数有关。
需要说明的是，本实施例提供的时序校准系统的原理及工作流程与上述时序校准方法相似，相关之处可以参照上述说明，在此不再赘述。
本发明实施例提供的时序校准系统和方法，无需外接示波器等仪器，利用了高速窗口比较器，可以快速实现数字测试机pattern测试通道的时序校准，提高了时序校准效率，并且校准精度能够达到50ps以内，满足校准精度要求。
显然，本发明的上述实施例仅仅是为清楚地说明本发明所作的举例，而并非是对本发明的实施方式的限定，对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动，这里无法对所有的实施方式予以穷举，凡是属于本发明的技术方案所引伸出的显而易见的变化或变动仍处于本发明的保护范围之列。

Claims (10)

  1. 一种时序校准方法，其特征在于，用于对数字测试机的若干测试通道中的测试信号进行时序校准，该方法包括：
    选通数字测试机的任意两个测试通道，以输出测试信号；
    采用窗口比较器对选通的两个测试通道输出的测试信号进行比较，并将比较结果输出到FPGA；
    被选通的两个测试通道其中之一输出的测试信号经时钟缓冲器传输到FPGA作为采样时钟；
    FPGA根据采样时钟采集窗口比较器的输出结果，并将结果信息发送给控制终端；
    控制终端根据FPGA的输出结果调整对应的测试通道中测试信号的时钟相位，以完成对测试通道的时序校准。
  2. 根据权利要求1所述的时序校准方法，其特征在于，该方法进一步包括：以所述采样时钟所在的测试通道作为校准基准通道，依次选通其他多个测试通道之一与所述窗口比较器连通作为被校准通道进行时序校准。
  3. 根据权利要求1所述的时序校准方法，其特征在于，所述数字测试机的多个激励信号测试通道连接继电器网络的输入端，所述继电器网络的第一输出端连接所述窗口比较器的第一输入端，所述继电器网络的第二输出端连接所述窗口比较器的第二输入端和所述时钟缓冲器的输入端，所述窗口比较器的输出端连接所述FPGA的第一输入端，所述时钟缓冲器的输出端连接所述FPGA的第二输入端，所述FPGA的输出端连接所述控制终端。
  4. 根据权利要求3所述的时序校准方法，其特征在于，所述控制终端控制所述继电器网络中的继电器断开或闭合，使被选通的两个激励信号测试通道分别输出到所述继电器网络的第一输出端和第二输出端。
  5. 根据权利要求2所述的时序校准方法，其特征在于，如果被校准通道产生的时钟信号边沿与基准通道产生的时钟信号边沿不对齐，所述控制系统控制所述数字测试机激励信号测试通道调整被校准通道输出的时钟相位，直到被校准通道的时钟相位与基准通道产生的时钟信号边沿对齐。
  6. 根据权利要求5所述的时序校准方法，其特征在于，利用二分查找法调整被校准通道输出的时钟相位。
  7. 根据权利要求6所述的时序校准方法，其特征在于，若测得被校准通道比基准通道相位超前，则令被校准通道输出延迟N nS，此时若测得被校 准通道比基准通道相位滞后，则调整被校准通道输出延迟为N/2 nS，此时若测得被校准通道比基准通道相位滞后，则被校准通道比基准通道相位超前在0～N/2 nS范围，若测得被校准通道比基准通道相位超前，则被校准通道比基准通道相位超前在N/2～N nS范围，其中N＞0。
  8. 一种执行上述权利要求1-7中任一项时序校准方法的时序校准系统，其特征在于，该系统包括：数字测试机、控制终端和时序校准板卡；
    所述时序校准板卡包括：继电器网络、窗口比较器、时钟缓冲器和FPGA；
    其中，数字测试机包含多个激励信号测试通道；
    继电器网络用于将数字测试机的多个激励信号测试通道选通任意两个激励信号测试通道分别输出到窗口比较器；
    窗口比较器用于对选通后的两个激励信号测试通道输出的时钟信号进行比较，判断两个时钟信号边沿是否对齐，并将判断结果输出到FPGA；
    时钟缓冲器用于将所选通的激励信号测试通道之一输出的时钟信号缓冲后输出到FPGA作为采样时钟；
    FPGA用于根据采样时钟采集窗口比较器的比较结果，并将结果发送给控制终端；
    控制终端用于控制激励信号测试通道产生时钟信号，判断两个激励信号测试通道产生的时钟信号是否边沿对齐，并进行时序校准。
  9. 根据权利要求8所述的时序校准系统，其特征在于，所述继电器网络和所述窗口比较器支持100～800MHz工作频率。
  10. 根据权利要求8所述的时序校准系统，其特征在于，所述控制终端控制所述继电器网络选通测试通道之一与所述时钟缓冲器输入端和所述窗口比较器第二输入端连通用作校准基准通道，依次选通其他多个激励信号测试通道之一与所述窗口比较器第一输入端连通作为被校准通道进行时序校准。
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CN114646870A (zh) 2022-06-21
TW202332927A (zh) 2023-08-16
TWI826083B (zh) 2023-12-11

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