WO2023082092A1 - 半导体外延结构及其应用、半导体外延结构的制作方法 - Google Patents

半导体外延结构及其应用、半导体外延结构的制作方法 Download PDF

Info

Publication number
WO2023082092A1
WO2023082092A1 PCT/CN2021/129776 CN2021129776W WO2023082092A1 WO 2023082092 A1 WO2023082092 A1 WO 2023082092A1 CN 2021129776 W CN2021129776 W CN 2021129776W WO 2023082092 A1 WO2023082092 A1 WO 2023082092A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
barrier
type semiconductor
light
epitaxial structure
Prior art date
Application number
PCT/CN2021/129776
Other languages
English (en)
French (fr)
Inventor
孙威威
黄国栋
Original Assignee
重庆康佳光电技术研究院有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 重庆康佳光电技术研究院有限公司 filed Critical 重庆康佳光电技术研究院有限公司
Priority to PCT/CN2021/129776 priority Critical patent/WO2023082092A1/zh
Priority to US18/152,902 priority patent/US20230170437A1/en
Publication of WO2023082092A1 publication Critical patent/WO2023082092A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/305—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table characterised by the doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the application belongs to the technical field of semiconductor manufacturing, and in particular relates to a semiconductor epitaxial structure and its application, and a method for manufacturing the semiconductor epitaxial structure.
  • the quaternary material aluminum gallium indium phosphide (AlGaInP) has been widely used in the preparation of various optoelectronic devices.
  • the quaternary material is used to prepare high-brightness light-emitting diodes.
  • the light-emitting band can cover the red to blue-green bands of visible light. Therefore, the Light-emitting diodes have been widely used in many aspects such as outdoor displays, traffic lights, and car lights.
  • plant lamps made of quaternary materials aluminum gallium indium phosphide have a huge market, which can reduce cultivation costs and achieve off-season cultivation.
  • light-emitting diodes used in plant lighting are required to have high light efficiency and stable light output power during cultivation.
  • the purpose of the present application is to provide a semiconductor epitaxial structure, a manufacturing method thereof, and a light emitting diode, aiming at solving the problem of how to further improve the reliability of the light emitting diode.
  • the present application provides a semiconductor epitaxial structure, characterized in that it comprises:
  • the light-emitting layer includes potential well layers and barrier layers periodically stacked, and at least part of the barrier layer in the middle region of the light-emitting layer is doped, and the doping type is the same as that of the second type semiconductor
  • the doping type of the layers is the same.
  • the above-mentioned semiconductor epitaxial structure can provide a higher hole concentration by setting a barrier layer of the same doping type as the second-type semiconductor layer in the middle region of the light-emitting layer, which reduces the series resistance and makes the device have a higher density than the conventional structure.
  • Good thermal effect, and lower junction heat can make the carriers in the quantum well more easily trapped, thus increasing the luminous efficiency, and higher hole concentration can improve the recombination efficiency, thereby increasing the light output efficiency.
  • the total number of stacking periods of the potential well layer and the barrier layer is between 12 and 20.
  • the number of stacking cycles of the doped barrier layer and potential well layer is between 4 and 6.
  • the barrier layer in the middle region has dopant ions, and under the condition of ensuring that the light-emitting layer has a higher doping concentration, it is possible to avoid excessive ion doping in the light-emitting layer from introducing impurities, Deterioration of crystal quality, resulting in semiconductor epitaxial structure and electrical abnormalities of light-emitting diodes.
  • the barrier layer includes three barrier sublayers, and the three barrier sublayers are respectively denoted as the first barrier sublayer, the second barrier sublayer and the third barrier sublayer;
  • the first potential barrier sublayer, the second potential barrier sublayer and the third potential barrier sublayer are sequentially stacked.
  • the first barrier sublayer is doped
  • the second barrier sublayer is doped
  • the third barrier sublayer is doped.
  • the doped barrier layer is P-type doped, and the doping source is diethyl zinc.
  • the above-mentioned diethyl zinc has a diffusion effect, and the zinc in the barrier sublayer in the middle region will diffuse to both sides to increase the hole concentration in the light-emitting layer and reduce the series resistance.
  • the first type semiconductor layer includes:
  • the ohmic contact layer is formed on the etching stop layer.
  • the above-mentioned etching stop layer can prevent the substrate from being etched when the light emitting diode is formed, and the ohmic contact can form a good ohmic contact with the electrode.
  • the first type semiconductor layer further includes:
  • the first waveguide layer is formed on the first confinement layer.
  • the above-mentioned current spreading layer shape can enhance the current spreading capability
  • the first confinement layer can provide electrons to the light emitting layer, and at the same time prevent carriers from overflowing the light emitting layer
  • the first waveguide layer can prevent impurities from diffusing into the light emitting layer.
  • the second type semiconductor layer includes:
  • the window layer is set on the transition layer.
  • the above-mentioned second waveguide layer can prevent impurities from diffusing into the light-emitting region, the second confinement layer can provide holes for the light-emitting region, and at the same time prevent carriers from overflowing the light-emitting region, the transition layer is conducive to the growth of GaP crystals, and the window layer enhances current spreading capability and forms good ohmic contact with electrodes.
  • the present application also provides a method for manufacturing a semiconductor epitaxial structure, including:
  • the light-emitting layer includes potential well layers and barrier layers periodically stacked, and at least part of the middle region of the light-emitting layer is doped, and the doping type is the same as that of the second-type semiconductor layer. same.
  • the above-mentioned method for manufacturing a semiconductor epitaxial structure can form a semiconductor epitaxial structure with high light efficiency.
  • the step of forming the potential well layer includes:
  • phosphine is introduced, and hydrogen is used as a carrier gas, and a preset ratio of trimethylgallium or trimethylindium is introduced;
  • the barrier layer includes a first barrier sublayer, a second barrier sublayer and a third barrier sublayer; the step of forming the doped barrier layer includes:
  • the doping concentration of zinc ions in the second barrier sublayer ranges from 6 ⁇ 10 17 atoms/cm 2 to 1 ⁇ 10 18 atoms/cm 2 .
  • the doping concentration setting of the above-mentioned zinc ions can ensure that the light-emitting layer has a higher doping concentration, and avoid excessive ion doping in the light-emitting layer from introducing impurities, deteriorating the crystal quality, and causing semiconductor epitaxial structure and electrical properties of the light-emitting diode. abnormal.
  • the present application also provides a light emitting diode, including:
  • a semiconductor epitaxial structure, and the semiconductor epitaxial structure includes:
  • the light-emitting layer includes potential well layers and barrier layers periodically stacked, and at least part of the barrier layer in the middle region of the light-emitting layer is doped, and the doping type is the same as that of the second type semiconductor
  • the doping type of the layers is the same;
  • the second electrode is connected to the second type semiconductor layer.
  • the above-mentioned light-emitting diode can form a light-emitting diode with high light efficiency and stable light output power through the arrangement of the light-emitting layer.
  • an electronic device including:
  • the lamp board is electrically connected to the control device, and the lamp board is provided with a plurality of light-emitting diodes, and the light-emitting diodes include:
  • a semiconductor epitaxial structure, and the semiconductor epitaxial structure includes:
  • the light-emitting layer includes potential well layers and barrier layers periodically stacked, and at least part of the barrier layer in the middle region of the light-emitting layer is doped, and the doping type is the same as that of the second type semiconductor
  • the doping type of the layers is the same;
  • the second electrode is connected to the second type semiconductor layer.
  • the above-mentioned electronic equipment has high light efficiency and stable light output power through the arrangement of the light emitting diodes.
  • FIG. 1 is a schematic diagram of a semiconductor structure in the present application.
  • Fig. 2 is a schematic structural diagram of the light-emitting layer in Fig. 1 of the present application.
  • FIG. 3 is a schematic structural diagram of the first type semiconductor layer in FIG. 1 of the present application.
  • FIG. 4 is a schematic structural diagram of the second type semiconductor layer in FIG. 1 of the present application.
  • FIG. 5 is a schematic structural diagram of a light emitting diode in the present application.
  • FIG. 6 is a schematic structural diagram of a light board of an electronic device in the present application.
  • the light emitted by the aluminum gallium indium phosphide multi-quantum well covers a wide range of wavelengths, and can be widely used in electronic equipment, for example, it can be used as a light-emitting layer in light-emitting diodes and laser diodes.
  • Laser diodes made of aluminum gallium indium phosphide can be used in lasers, and light-emitting diodes made of aluminum gallium indium phosphide can be used in various display devices and various electronic equipment, such as displays, advertising Signs, lighting and display lights, etc.
  • the plant lamp 2 includes a lamp panel 20 and a control device (not shown in the figure).
  • the lamp board 20 is provided with a plurality of light-emitting diodes
  • the control device can be fixed on the lamp board 20, and the control device can also be pulled out by wires and placed in an easy-to-operate place.
  • the state of the light-emitting diode can be adjusted by adjusting the control device, including controlling the switch and light intensity of the light-emitting diode.
  • the present application provides a semiconductor epitaxial structure and a light-emitting diode with high light efficiency and stable light output power, so that light-emitting diodes and electronic devices have higher light efficiency.
  • the semiconductor epitaxial structure provided in the present application includes a first type semiconductor layer 11 , a light emitting layer 12 and a second type semiconductor layer 13 .
  • the first type semiconductor layer 11 may be disposed on the substrate 10
  • the light emitting layer 12 is disposed on the first type semiconductor layer 11
  • the second type semiconductor layer 13 is disposed on the light emitting layer 12 .
  • the light emitting diode is, for example, a red light emitting diode
  • the material of the substrate 10 is, for example, a gallium arsenide (GaAs) substrate.
  • the substrate 10 may be doped with silicon ions, for example.
  • the substrate 10 may also be a substrate made of silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), etc. , for example, can be directly grown on a sapphire substrate, and a blue or green light-emitting diode can be directly formed on the sapphire substrate.
  • the first type semiconductor layer 11 is formed on the substrate 10, and the first type semiconductor layer 11 can be an N-type semiconductor layer with more electrons, or It may be a P-type semiconductor layer with many holes.
  • the first type semiconductor layer 11 is, for example, an N-type semiconductor layer, and the first type semiconductor layer 11 is doped with donor impurities, such as silicon (Si) or tellurium (Te).
  • the first type semiconductor layer 11 includes a buffer layer 111 , an etching stop layer 112 , an ohmic contact layer 113 , a current spreading layer 114 , a first confinement layer 115 and a first waveguide layer 116 sequentially disposed on the substrate 10 .
  • the buffer layer 111 is disposed on the substrate 10 , and the material of the buffer layer 111 is, for example, N-type gallium arsenide (GaAs).
  • GaAs N-type gallium arsenide
  • the thickness range of the buffer layer 111 is, for example, 10-20 nm, specifically, for example, 12 nm, 15 nm or 18 nm.
  • the buffer layer 111 is doped with silicon ions, for example, and the ion doping concentration is 1 ⁇ 10 18 atoms/cm 2 to 2 ⁇ 10 18 atoms/cm 2 .
  • the buffer layer 111 can reduce the lattice mismatch between the substrate 10 and other first type semiconductor layers 11 on the buffer layer 111 .
  • the etch stop layer 112 is disposed on the buffer layer 111, and the material of the etch stop layer 112 is, for example, N-type gallium indium phosphide (Ga X1 In 1-X1 P), wherein X1 is, for example, 0.5, that is, the etch stop layer 112 The material is Ga 0.5 In 0.5 P.
  • the thickness of the etching stop layer 112 is, for example, 20-50 nm, specifically, for example, 30 nm, 35 nm or 40 nm.
  • the etching stop layer 112 is doped with silicon ions, for example, and the doping concentration of the ions is 1 ⁇ 10 18 atoms/cm 2 to 2 ⁇ 10 18 atoms/cm 2 .
  • the etch stop layer 112 can prevent the substrate 10 and the buffer layer 111 from being corroded when the epitaxial LED is formed by etching.
  • the ohmic contact layer 113 is disposed on the etch stop layer 112 , and the material of the etch stop layer 112 is, for example, N-type gallium arsenide (GaAs).
  • the thickness of the ohmic contact layer 113 is, for example, 10-30 nm, specifically, for example, 15 nm, 20 nm or 25 nm.
  • the ohmic contact layer 113 is doped with silicon ions, for example, and the ion doping concentration is 2 ⁇ 10 18 atoms/cm 2 to 3 ⁇ 10 18 atoms/cm 2 .
  • the doping concentration of ions in the ohmic contact layer 113 is relatively high, which can enhance the electrical connection between the ohmic contact layer 113 and the electrode.
  • the current spreading layer 114 is disposed on the ohmic contact layer 113 to increase the current spreading capability of the N-type semiconductor layer.
  • the material of the current spreading layer 114 is, for example, N-type aluminum gallium indium phosphide (Al X2 Ga 1-X2 InP), wherein X2 ranges from 0.3 to 0.6, specifically 0.4, 0.5 or 0.55.
  • the thickness of the current spreading layer 114 is, for example, 10-30 nm, specifically, for example, 15 nm, 20 nm or 25 nm.
  • the current spreading layer 114 is doped with silicon ions, for example, and the ion doping concentration is 1 ⁇ 10 18 atoms/cm 2 to 2 ⁇ 10 18 atoms/cm 2 .
  • the first confinement layer 115 is disposed on the current spreading layer 114, and the material of the first confinement layer 115 is, for example, N-type aluminum indium phosphide (Al X3 In 1-X3 P).
  • the range of X3 is, for example, 0.5, that is, the material of the first confinement layer 115 is Al 0.5 In 0.5 P.
  • the thickness of the first confinement layer 115 is, for example, 30-80 nm, specifically, for example, 50 nm, 60 nm or 70 nm.
  • the first confinement layer 115 is doped with silicon ions, for example, with a doping concentration of 7 ⁇ 10 17 atoms/cm 2 to 1 ⁇ 10 18 atoms/cm 2 , which can provide electrons for the light-emitting layer and prevent carriers from Overflow glow layer.
  • the first waveguide layer 116 is disposed on the first confinement layer 115 , and the material of the first waveguide layer 116 is, for example, N-type aluminum gallium indium phosphide (Al X4 Ga 1-X4 InP). Wherein, the range of X4 is, for example, 0.5-0.7, specifically 0.55, 0.6 or 0.65.
  • the thickness of the first waveguide layer 116 is, for example, 30-60 nm, specifically, for example, 30 nm, 40 nm, 50 nm or 60 nm.
  • the first waveguide layer 116 provided in the present application is not doped with other ions, which can prevent impurities between the first waveguide layer 116 and the substrate 10 from diffusing into the light emitting layer.
  • a buffer layer 111, an etching stop layer 112, and an ohmic contact layer can be sequentially deposited on the substrate 10 by metal organic compound chemical vapor deposition (MOCVD). 113 , a current spreading layer 114 , a first confinement layer 115 and a first waveguide layer 116 .
  • MOCVD metal organic compound chemical vapor deposition
  • the light emitting layer 12 is disposed on the first type semiconductor layer 11, the light emitting layer 12 can be a quantum well light emitting layer, or an intrinsic semiconductor layer or low doped semiconductor layer.
  • the light-emitting layer 12 is, for example, a quantum well light-emitting layer, and includes a plurality of periodically stacked gallium indium phosphide layers/aluminum gallium indium phosphide layers (Ga X11 In 1-X11 P/(Al X12 Ga 1-X12 ) 0.5 In 0.5 P).
  • the material of the light-emitting layer 12 can also be indium gallium nitride (InGaN), zinc selenide (ZnSe), indium gallium nitride/gallium nitride (InGaN/GaN), indium gallium nitride/nitride
  • InGaN/GaN gallium phosphide
  • AlGaP aluminum gallium phosphide
  • AlGaAs aluminum gallium arsenide
  • GaP gallium phosphide
  • the light-emitting layer 12 includes a plurality of potential well layers and barrier layers stacked periodically, and the total number of periods of the potential well layers and barrier layers is, for example, 12 to 20 .
  • the material of the potential well layer is, for example, gallium indium phosphide
  • the material of the barrier layer is, for example, aluminum gallium indium phosphide.
  • the potential well layer is an undoped layer
  • part of the barrier layer is an undoped layer
  • part of the barrier layer is a doped layer of the same doping type as the second type semiconductor layer 13, and doped
  • the barrier layer can be located in any region of the light emitting layer 12.
  • the doped barrier layer is located in the middle region of the light-emitting layer 12 .
  • a plurality of barrier layers disposed close to the first type semiconductor layer 11 and the second type semiconductor layer 13 for a plurality of periods are non-doped layers.
  • one or more barrier sublayers having the same doping type as the second type semiconductor layer are set, and are, for example, P-type potential barrier layers. base layer.
  • the number of periods of the doped barrier layer is close to one-third of the total number of periods, and under the condition of ensuring that the light-emitting layer has a higher doping concentration, it is possible to avoid excessively high ions in the light-emitting layer.
  • Doping introduces impurities, deteriorates the crystal quality, and causes abnormalities in the semiconductor epitaxial structure and the electrical properties of light-emitting diodes.
  • the light-emitting layer 12 includes a plurality of first potential well layers 121 and first barrier layers 122 that are stacked periodically, and a plurality of second well layers 122 that are stacked periodically.
  • the potential well layer 123 and the second potential barrier layer 124 and a plurality of third potential well layers 125 and third potential barrier layers 126 are stacked periodically.
  • a plurality of periodically stacked first potential well layers 121 and first barrier layers 122 are disposed on the first type semiconductor layer 11, and a plurality of periodically stacked second potential well layers 123 and the second barrier layer 124 are arranged on the first potential well layer 121 and the first potential barrier layer 122 which are stacked periodically, and the third potential well layer 125 and the third barrier layer 126 which are stacked periodically On the second potential well layer 123 and the second potential barrier layer 124 which are stacked periodically.
  • a plurality of periodically stacked second potential well layers 123 and second barrier layers 124 may be disposed on a side where the periodic stacked arrangement may be close to the first type semiconductor layer 11 .
  • the first period number of the first potential well layer 121 and the first potential barrier layer 122 is, for example, 4-6
  • the second period number of the second potential well layer 123 and the second potential barrier layer 124 is, for example, 4-6.
  • the number of third periods of the third potential well layer 125 and the third barrier layer 126 is, for example, 4-6.
  • the first cycle number, the second cycle number and the third cycle number may be equal or different.
  • the light-emitting layer 12 includes, for example, five periods of the first potential well layer 121 and the first potential barrier layer 122, for example, five periods of the second potential well layer 123 and the second barrier layer 124, and for example 5 periods of the third potential well layer 125 and the third potential barrier layer 126 .
  • the light-emitting layer 12 includes, for example, 6 periods of the first potential well layer 121 and the first potential barrier layer 122, such as 5 periods of the second potential well layer 123 and the second barrier layer 124, and For example, 6 periods of the third potential well layer 125 and the third potential barrier layer 126 .
  • the light-emitting layer 12 includes, for example, 5 periods of the first potential well layer 121 and the first potential barrier layer 122, such as 6 periods of the second potential well layer 123 and the second barrier layer 124, and for example 5 periods of the third potential well layer 125 and the third potential barrier layer 126 .
  • the materials of the first potential well layer 121, the second potential well layer 123 and the third potential well layer 125 are the same, such as gallium indium phosphide (Ga X11 In 1 -X11 P), and the range of X11 is 0.45-0.5, specifically for example 0.46, 0.47, 0.48 or 0.49.
  • the thickness range of the first potential well layer 121, the second potential well layer 123 and the third potential well layer 125 is 8-10 nm, and the first potential well layer 121, the second potential well layer 123 and the third potential well layer The thickness of 125 can be the same or different.
  • the thicknesses of the first potential well layer 121 , the second potential well layer 123 and the third potential well layer 125 are, for example, 9 nm. In another embodiment, the thickness of the first potential well layer 121 and the third potential well layer 125 is, for example, 9 nm, and the thickness of the second potential well layer 123 is, for example, 10 nm. In this embodiment, the first potential well layer 121 , the second potential well layer 123 and the third potential well layer 125 are non-doped layers.
  • the materials of the first barrier layer 122, the second barrier layer 124 and the third barrier layer 126 are the same, for example (Al X12 Ga 1-X12 ) 0.5 In 0.5 P, and X12 ranges from 0.5 to 0.7, and specifically, is 0.55, 0.6, or 0.65.
  • the thickness range of the first barrier layer 122, the second barrier layer 124 and the third barrier layer 126 is 18-24 nm, and the first barrier layer 122, the second barrier layer 124 and the third barrier layer
  • the thickness of 126 can be the same or different.
  • the thicknesses of the first barrier layer 122 , the second barrier layer 124 and the third barrier layer 126 are, for example, 21 nm.
  • the first barrier layer 122, the second barrier layer 124, and the third barrier layer 126 include three sublayers.
  • the first barrier layer 122 includes, for example, the second A potential barrier sublayer 1221, a second potential barrier sublayer 1222 and a third potential barrier sublayer 1223, and the second potential barrier sublayer 1222 is disposed on the first potential barrier sublayer 1221, and the third potential barrier sublayer 1223 is disposed on the second barrier sublayer 1222 .
  • the second barrier layer 124 includes, for example, a first barrier sublayer 1241, a second barrier sublayer 1242, and a third barrier sublayer 1243, and the second barrier sublayer 1242 is disposed on the first barrier sublayer 1241 , the third barrier sublayer 1243 is disposed on the second barrier sublayer 1242 .
  • the third barrier layer 126 includes, for example, a first barrier sublayer 1261, a second barrier sublayer 1262 and a third barrier sublayer 1263, and the second barrier sublayer 1262 is disposed on the first barrier sublayer 1261 , the third barrier sublayer 1263 is disposed on the second barrier sublayer 1262 .
  • the thickness of each barrier sublayer is the same, for example, 6-8 nm, specifically, for example, 7 nm.
  • the first barrier sublayer 1221/1261, the second barrier sublayer 1222/1262 and the third barrier sublayer 1223/1263 are not doped ion.
  • the first barrier sublayer 1221/1261, the second barrier sublayer 1222/1262 and the third barrier sublayer 1223/1263 can be doped with the doping of the second type semiconductor layer 13 ions of the same type. Please refer to FIG.
  • the first potential barrier sublayer 1241 and the third potential barrier sublayer 1243 in the second potential barrier layer 124 are not doped Ions
  • the second barrier sublayer 1242 is doped with ions
  • the doping type of the second barrier sublayer 1242 is the same as that of the second type semiconductor layer 13 , for example, P-type doping.
  • the dopant ions in the second barrier sublayer 1242 in the second barrier layer 124 are zinc ions, specifically, diethylzinc (DEZn), and the doping concentration of the zinc ions is 6 ⁇ 10 17 atoms/cm 2 to 1 ⁇ 10 18 atoms/cm 2 , for example, 7 ⁇ 10 17 atoms/cm 2 , 8 ⁇ 10 17 atoms/cm 2 or 9 ⁇ 10 17 atoms/cm 2 .
  • zinc ions may be doped in the first barrier sublayer and/or the third barrier sublayer, and the doping source and doping concentration may be the same as that of the second barrier sublayer.
  • the first potential barrier sub-layer or the third potential barrier sub-layer can be doped alone, and multiple or all of the first potential barrier sub-layer, the second potential barrier sub-layer and the third potential barrier sub-layer can be doped layer is doped.
  • the part of the barrier layer located in the middle region of the light-emitting layer 12 is doped with P-type doping of diethyl zinc, and the quantum well structure of this kind of doping modulation can provide a higher hole concentration and reduce
  • the series resistance makes the device have a better thermal effect than the conventional structure, and the lower junction heat can make the carriers in the quantum well easier to be trapped, thus increasing the luminous efficiency, and the higher hole concentration can improve the recombination efficiency, thereby improving light output efficiency.
  • first potential well layer 121 and the first barrier layer 122 that are stacked periodically, first, for example, at a temperature of 690°C to 710°C and a chamber pressure of 45 ⁇ 55mbar, feed phosphine (PH 3 ), a source of group V, and use hydrogen as a carrier gas, feed a certain proportion of trimethylgallium or trimethyl indium, a source of group III, and control the deposition time.
  • the growth thickness is, for example, 9nm first potential well layer 121 (Ga X11 In 1-X11 P).
  • the ratio of group V source/group III source is, for example, 100-150.
  • first potential well layer 121 is formed, trimethylaluminum is opened to enter the reaction chamber, and the proportions of group III sources trimethylgallium, trimethylaluminum and trimethylindium are adjusted, and a thickness of, for example, 7 nm is deposited sequentially.
  • the first barrier sublayer 1221 , the second barrier sublayer 1222 and the third barrier sublayer 1223 form a first barrier layer 122 (Al X12 Ga 1-X12 ) 0.5 In 0.5 P with a thickness of, for example, 21 nm.
  • steps of forming the first potential well layer 121 and the first potential barrier layer 122 are repeated, and the first potential well layer 121 and the first potential barrier layer 122 are grown for 4 to 6 periods.
  • the first potential well layer 121 after forming 4 to 6 periods of the first potential well layer 121 and the first potential barrier layer 122, the first potential well layer 121 periodically stacked The second potential well layer 123 and the second potential barrier layer 124 are formed on the first potential barrier layer 122 .
  • a group V source of phosphine (PH 3 ) can be introduced, and hydrogen can be used as a carrier gas, and a certain proportion of a group III source of trimethylgallium or trimethyl indium, and control the deposition time to grow the second potential well layer 123 (Ga X11 In 1-X11 P) with a thickness of, for example, 9 nm.
  • the ratio of group V source/group III source is, for example, 100-150.
  • trimethylaluminum can be opened to enter the reaction chamber, and the group III sources trimethylgallium, trimethylgallium, and trimethylgallium can be adjusted.
  • the proportions of methylaluminum and trimethylindium are sequentially deposited to form a first barrier sub-layer 1241 with a thickness of, for example, 7 nm.
  • the second barrier sublayer 1242, and the doping concentration of zinc ions in the second barrier sublayer 1242 is maintained at 6 ⁇ 10 17 atoms/cm 2 to 1 ⁇ 10 18 atoms/cm 2 .
  • the second potential barrier sublayer 1242 After forming the second potential barrier sublayer 1242, stop feeding the diethyl zinc dopant source, keep other growth conditions unchanged, control the deposition time, grow the third potential barrier sublayer 1243 with a thickness of 7nm, and then form the middle barrier sublayer 1243 with
  • the second barrier layer 124 is doped with ions. The steps of forming the second potential well layer 123 and the second potential barrier layer 124 are repeated, and the second potential well layer 123 and the second potential barrier layer 124 are grown for 4 to 6 periods.
  • the second potential well layer that is periodically stacked is formed 123 and the second potential barrier layer 124 and then form 4 to 6 periods of the third potential well layer 125 and the third potential barrier layer 126 .
  • the formation method of the third potential well layer 125 is the same as that of the first potential well layer 121, the first potential barrier sublayer 1261, the second potential barrier sublayer 1262 and the third potential barrier sublayer 1263 in the third potential barrier layer 126
  • the formation method is the same as that of the first barrier sublayer 1221 , the second barrier sublayer 1222 and the third barrier sublayer 1223 in the first barrier layer 122 , and will not be repeated here.
  • the second type semiconductor layer 13 is formed on the light emitting layer 12, and the second type semiconductor layer 13 can be a P-type semiconductor layer with more holes, It may also be an N-type semiconductor layer with many electrons.
  • the second-type semiconductor layer 13 is, for example, a P-type semiconductor layer, and the second-type semiconductor layer is doped with acceptor impurities, such as magnesium (Mg) or zinc (Zn).
  • the second type semiconductor layer 13 includes a second waveguide layer 131 , a second confinement layer 132 , a transition layer 133 and a window layer 134 sequentially disposed on the light emitting layer 12 .
  • the first waveguide layer 116 is directly in contact with one side of the light-emitting layer 12, and the first waveguide layer 116 is set correspondingly.
  • the second waveguide layer 131 is in direct contact with another layer of the light emitting layer 12 .
  • the second waveguide layer 131 is disposed on the light emitting layer 12 , and the material of the second waveguide layer 131 is, for example, P-type aluminum gallium indium phosphide (Al X5 Ga 1-X5 InP).
  • Al X5 Ga 1-X5 InP P-type aluminum gallium indium phosphide
  • the range of X5 is, for example, 0.5-0.7, specifically 0.55, 0.6 or 0.65.
  • the thickness of the second waveguide layer 131 is, for example, 30-60 nm, specifically, for example, 30 nm, 40 nm, 50 nm or 60 nm.
  • the second waveguide layer 131 provided in the present application is not doped with other ions, which can prevent impurities in other second-type semiconductor layers 13 from diffusing into the light-emitting layer.
  • the second confinement layer 132 is disposed on the second waveguide layer 131 , and the material of the second confinement layer 132 is, for example, P-type aluminum indium phosphide (Al X6 In 1-X6 P).
  • the range of X6 is, for example, 0.5, that is, the material of the second confinement layer 132 is Al 0.5 In 0.5 P.
  • the thickness of the second confinement layer 132 is, for example, 30-80 nm, specifically, for example, 50 nm, 60 nm or 70 nm.
  • the second confinement layer 132 is, for example, doped with magnesium ions, and the doping concentration of ions is 7 ⁇ 10 17 atoms/cm 2 to 1 ⁇ 10 18 atoms/cm 2 , which can provide holes for the light-emitting layer and prevent current carrying Sub overflow glow layer.
  • the transition layer 133 is disposed on the second confinement layer 132, and the material of the transition layer 133 is, for example, P-type aluminum gallium indium phosphide ((Al X7 Ga 1-X7 ) 0.5 In 0.5 P), wherein the range of X7 is, for example, 0.2-0.4, specifically, for example, 0.25, 0.3 or 0.35.
  • the thickness of the transition layer 133 is, for example, 30-40 nm, specifically, for example, 32 nm, 35 nm or 37 nm.
  • the transition layer 133 is doped with magnesium ions, for example, and the doping concentration of the ions is 2 ⁇ 10 18 atoms/cm 2 to 3 ⁇ 10 18 atoms/cm 2 . crystals grown on gallium.
  • the window layer 134 is disposed on the transition layer 133 and used as the current spreading layer 114 and the light output layer, and the window layer 134 can form a good ohmic contact with the electrodes.
  • the material of the window layer 134 is, for example, P-type gallium phosphide (GaP), and the thickness of the window layer 134 is, for example, 40-90 nm, specifically, for example, 50 nm, 60 nm or 70 nm.
  • the window layer 134 is doped with magnesium ions, for example, and the ion doping concentration is 1 ⁇ 10 18 atoms/cm 2 to 2 ⁇ 10 18 atoms/cm 2 .
  • the semiconductor epitaxial structure is formed. After forming a complete semiconductor epitaxial structure, epitaxial inspection is performed on the semiconductor epitaxial structure, and a qualified semiconductor epitaxial structure can be made into a light-emitting diode.
  • the light emitting diode is, for example, a light emitting diode
  • one side of the semiconductor epitaxial structure can be etched to form a recess, and the recess exposes the first type semiconductor layer Ohmic contact layer 113 in 11.
  • the first electrode 14 is deposited on the ohmic contact layer 113 in the concave portion
  • the second electrode 15 is deposited on the window layer 134
  • the first electrode 14 and the second electrode 15 can be formed by evaporation and/or sputtering techniques. Can be set as equal height electrodes.
  • the first electrode 14 is an N-type electrode, and the material of the first electrode 14 is germanium and/or copper, for example.
  • the second electrode 15 is a P-type electrode, and the material of the second electrode 15 is, for example, beryllium and/or copper.
  • a passivation layer 16 can also be deposited on the second type semiconductor layer 13, as a protective layer or package of light-emitting diodes, and the passivation layer 16 can be, for example, silicon oxide, silicon nitride or phosphorus silicon materials such as glass.
  • the present application provides a semiconductor epitaxial structure and its manufacturing method, and a light-emitting diode.
  • a light-emitting layer is formed on the first-type semiconductor layer, and a second-type semiconductor layer is formed on the light-emitting layer, thereby forming a semiconductor epitaxial structure.
  • a first electrode is deposited on the first type semiconductor layer, and a second electrode is deposited on the second type semiconductor layer to form a light emitting diode.
  • the semiconductor epitaxial structure and the light emitting diode provided in the present application have better thermal effect and can improve the output efficiency of light.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

本申请公开了一种半导体外延结构及其应用、半导体外延结构的制作方法，其中所述半导体外延结构至少包括：第一类型半导体层；发光层，设置在所述第一类型半导体层上；以及第二类型半导体层，设置在所述发光层上；其中，所述发光层包括周期性层叠设置的势阱层和势垒层，且所述发光层中间区域的至少部分所述势垒层被掺杂，且掺杂类型与所述第二类型半导体层的掺杂类型相同。

Description

半导体外延结构及其应用、半导体外延结构的制作方法 技术领域
本申请属于半导体制造技术领域，特别涉及一种半导体外延结构及其应用、半导体外延结构的制作方法。
背景技术
四元系材料磷化铝镓铟(AlGaInP)已经广泛应用于多种光电子器件的制备，使用四元系材料制备高亮度的发光二极管，发光波段可覆盖可见光的红光到蓝绿波段，因而该发光二极管已大量应用于户外显示、交通灯、汽车灯等许多方面。其中采用四元系材料磷化铝镓铟制成的植物灯拥有巨大的市场，可降低培育成本，实现反季节培植。而在培育时要求应用于植物照明的发光二极管具有高光效和稳定的光输出功率。
因此，如何将发光二极管的可靠性如何进一步提升是亟需解决的问题。
发明内容
鉴于上述现有技术的不足，本申请的目的在于提供一种半导体外延结构及其制作方法、发光二极管，旨在解决如何进一步提升发光二极管的可靠性问题。
为解决上述技术问题，本申请是通过以下技术方案实现的：
本申请提供一种半导体外延结构，其特征在于，包括：
第一类型半导体层；
发光层，设置在所述第一类型半导体层上；以及
第二类型半导体层，设置在所述发光层上；
其中，所述发光层包括周期性层叠设置的势阱层和势垒层，且所述发光层中间区域的至少部分所述势垒层被掺杂，且掺杂类型与所述第二类型半导体层的掺杂类型相同。
上述的半导体外延结构，通过在发光层中间区域设置与所述第二类型半导体层的掺杂类型相同的势垒层，可以提供更高空穴浓度，降低了串联电阻，使器件拥有比常规结构更好的热效应，且更低的结热可使得量子阱中的载流子更容易被俘获，因此增加发光效率，且更高的空穴浓度可提高复合效率，进而提高光输出效率。
可选地，所述势阱层和所述势垒层的层叠周期总数介于12～20之间。
可选地，被掺杂的所述势垒层与势阱层的层叠周期数介于4～6之间。
上述中间区域近三分之一的所述势垒层中具有掺杂离子，在保证所述发光层具有更高掺杂浓度的条件下，可避免发光层中过高的离子掺杂引入杂质，恶化晶体质量，造成半导体外延结构以及发光二极管电性异常。
可选地，所述势垒层包括三层势垒子层，三层势垒子层分别记为第一势垒子层、第二势垒子层和第三势垒子层；所述第一势垒子层、第二势垒子层和第三势垒子层依次层叠设置。
可选地，被掺杂的所述势垒层中，所述第一势垒子层被掺杂；和/或
所述第二势垒子层被掺杂；和/或
所述第三势垒子层被掺杂。
可选的，被掺杂的所述势垒层为P型掺杂，且掺杂源为二乙基锌。
上述二乙基锌具有扩散作用，所述中间区域势垒子层中的锌会向两边扩散，以增加所述发光层中的空穴浓度，以降低串联电阻。
可选的，所述第一类型半导体层包括：
腐蚀截止层；以及
欧姆接触层，形成于所述腐蚀截止层上。
上述所述腐蚀截止层可防止形成发光二极管时蚀刻衬底，所述欧姆接触可与电极形成良好的欧姆接触。
可选的，所述第一类型半导体层还包括：
电流扩展层，形成于所述欧姆接触层上；
第一限制层，形成于所述电流扩展层上；
第一波导层，形成于所述第一限制层上。
上述所述电流扩展层状可增强电流扩展能力，所述第一限制层可为发光层提供电子，同时防止载流子溢出发光层，所述第一波导层可阻止杂质扩散进发光层。
可选的，所述第二类型半导体层包括：
第二波导层，设置在所述发光层上；
第二限制层，设置在所述第二波导层上；
过渡层，设置在所述第二限制层上；以及
窗口层，设置在所述过渡层上。
上述所述第二波导层可阻止杂质扩散进发光区，所述第二限制层可为发光区提供空穴，同时防止载流子溢出发光区，所述过渡层利于GaP晶体生长，所述窗口层可增强电流扩展能力且与电极形成良好的欧姆接触。
基于同样的申请构思，本申请还提供一种半导体外延结构的制造方法，包括：
提供一衬底；
在所述衬底上形成第一类型半导体层；
在所述第一类型半导体层上形成发光层；以及
在所述发光层上形成第二类型半导体层；
其中，所述发光层包括周期性层叠设置的势阱层和势垒层，且所述发光层中间区域的至少部分被掺杂，且掺杂类型与所述第二类型半导体层的掺杂类型相同。
上述所述半导体外延结构的制造方法可形成高光效的半导体外延结构。
可选的，所述势阱层的形成步骤包括：
在预设温度和腔体压力下，通入磷烷，并以氢气为载气，通入预设比例的三甲基镓或三甲基铟；
控制沉积时间，生长预设厚度的势阱层。
可选的，所述势垒层包括第一势垒子层、第二势垒子层和第三势垒子层；被掺杂的所述势垒层的形成步骤包括：
在形成所述势阱层后，向反应室通入三甲基铝，并调整三甲基镓、三甲基铝和三甲基铟的比例，控制沉积时间，生长预设厚度的第一势垒子层；
保持形成第一势垒子层的生长条件，向反应室通入二乙基锌，控制沉积时间，生长预设厚度的第二势垒子层；
保持形成第二势垒子层的生长条件，停止向反应室通入二乙基锌，控制沉积时间，生长预设厚度的第三势垒子层。
可选的，所述第二势垒子层中锌离子的掺杂浓度范围为6×10 17atoms/cm 2～1×10 18atoms/cm 2。
上述锌离子的掺杂浓度设定，可保证所述发光层具有更高掺杂浓度，且避免发光层中过高的离子掺杂引入杂质，恶化晶体质量，造成半导体外延结构以及发光二极管电性异常。
基于同样的发明构思，本申请还提供一种发光二极管，包括：
半导体外延结构，且所述半导体外延结构包括：
第一类型半导体层；
发光层，设置在所述第一类型半导体层上；
第二类型半导体层，设置在所述发光层上；
其中，所述发光层包括周期性层叠设置的势阱层和势垒层，且所述发光层中间区域的至少部分所述势垒层被掺杂，且掺杂类型与所述第二类型半导体层的掺杂类型相同；
第一电极，与所述第一类型半导体层连接；以及
第二电极，与所述第二类型半导体层连接。
上述所述发光二极管通过发光层的设置，可形成高光效且具有稳定的光输出功率的发光二极管。
基于同样的发明构思，本申请还提供一种电子设备，包括：
控制装置；以及
灯板，电性连接于所述控制装置，且所述灯板上设置有多个发光二极管，且所述发光二极管包括：
半导体外延结构，且所述半导体外延结构包括：
第一类型半导体层；
发光层，设置在所述第一类型半导体层上；以及
第二类型半导体层，设置在所述发光层上；
其中，所述发光层包括周期性层叠设置的势阱层和势垒层，且所述发光层中间区域的至少部分所述势垒层被掺杂，且掺杂类型与所述第二类型半导体层的掺杂类型相同；
第一电极，与所述第一类型半导体层连接；
第二电极，与所述第二类型半导体层连接。
上述所述电子设备通过所述发光二极管的设置，具有具有高光效和稳定的光输出功率。
当然，实施本申请的任一产品并不一定需要同时达到以上所述的所有优点。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请中一种半导体结构示意图。
图2为本申请图1中发光层的结构示意图。
图3为本申请图1中第一类型半导体层的结构示意图。
图4为本申请图1中第二类型半导体层的结构示意图。
图5为本申请中发光二极管的结构示意图。
图6为本申请中电子设备的灯板结构示意图。
附图标记说明：
10衬底；11第一类型半导体层；111缓冲层；112腐蚀截止层；113欧姆接触层；114电流扩展层；115第一限制层；116第一波导层；12发光层；121第一势阱层；122第一势垒层；1221第一势垒子层；1222第二势垒子层；1223第三势垒子层；123第二势阱层；124第二势垒层；1241第一势垒子层；1242第二势垒子层；1243第三势垒子层；125第三势阱层；126第三势垒层；1261第 一势垒子层；1262第二势垒子层；1263第三势垒子层；13第二类型半导体层；131第二波导层；132第二限制层；133过渡层；134窗口层；14第一电极；15第二电极；16钝化层；2植物灯；20灯板。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本申请。
在本申请的描述中，需要理解的是，术语中“中心”、“上”、“下”、“前”、“后”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或组件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
使用磷化铝镓铟多量子阱发出的光波段覆盖广泛，可广泛应用在电子设备中，具体例如可以作为发光二极管和激光二极管中的发光层。使用磷化铝镓铟制成的激光二极管可用在激光器中，而使用磷化铝镓铟制成的发光二极管可应用在各种显示装置和各种电子设备中，具体例如可以用在显示器、广告牌、照明灯以及显示灯等。除此之外，请参阅图6所示，因磷化铝镓铟制成的发光二 极管发出的波长范围广，因而磷化铝镓铟制成的发光二极管还可以用在植物灯2中，实现植物的反季节培育。具体的，植物灯2包括灯板20以及控制装置(图中未显示)。其中，灯板20上设置有多个发光二极管，控制装置可固定在灯板20上，也将控制装置采用导线拉出，放置在易操作的地方。通过调节控制装置可调节发光二极管的状态，包括控制发光二极管的开关、以及光强等。为保证植物的生长质量，本申请提供一种高光效且光输出功率稳定的半导体外延结构和发光二极管，使得发光二极管及电子装置具有更高的光效。
请参阅图1所示，本申请提供的半导体外延结构包括第一类型半导体层11、发光层12和第二类型半导体层13。且第一类型半导体层11可以设置在衬底10上，发光层12设置在第一类型半导体层11上，第二类型半导体层13设置在发光层12上。通过在第一类型半导体层11和第二类型半导体层13上施加电压，使得光子与空穴复合，然后以光子的形状发出能量，进而使半导体外延结构发光。
请参阅图1所示，在本申请一实施例中，发光二极管例如为红色发光二极管，衬底10的材料例如为砷化镓(GaAs)衬底。且在本实施例中，衬底10中可例如掺杂有硅离子。在其他实施例中，当发光二极管为为蓝光二极管或绿光二极管时，衬底10也可以为硅(Si)、碳化硅(SiC)、蓝宝石(Al 2O 3)等材料制成的衬底，例如可以直接在蓝宝石衬底上生长，并在蓝宝石衬底上直接形成蓝色或绿色发光二极管。
请参阅图1和图3所示，在本申请一实施例中，第一类型半导体层11形成于衬底10上，且第一类型半导体层11可以为电子较多的N型半导体层，也可以为空穴较多的P型半导体层。在本实施例中，第一类型半导体层11例如为N型半导体层，第一类型半导体层11中掺杂的为施主杂质，例如为硅(Si)或碲(Te) 元素。且第一类型半导体层11包括依次设置在衬底10上的缓冲层111、腐蚀截止层112、欧姆接触层113、电流扩展层114、第一限制层115以及第一波导层116。
具体的，请参阅图1和图3所示，在本申请一实施例中，缓冲层111设置在衬底10上，且缓冲层111的材料例如为N型的砷化镓(GaAs)。在本实施例中，缓冲层111的厚度范围例如为10～20nm，具体例如为12nm、15nm或18nm。且缓冲层111中例如掺杂有硅离子，离子的掺杂浓度为1×10 18atoms/cm 2～2×10 18atoms/cm 2。且缓冲层111可降低衬底10和缓冲层111上其他第一类型半导体层11之间的晶格不匹配。腐蚀截止层112设置在缓冲层111上，且腐蚀截止层112的材料例如为N型的磷化镓铟(Ga X1In 1-X1P)，其中，X1例如为0.5，即腐蚀截止层112的材料为Ga 0.5In 0.5P。且在本实施例中，腐蚀截止层112的厚度例如为20～50nm，具体例如为30nm、35nm或40nm。且腐蚀截止层112中例如掺杂有硅离子，离子的掺杂浓度为1×10 18atoms/cm 2～2×10 18atoms/cm 2。腐蚀截止层112可防止在蚀刻外延形成发光二极管时，腐蚀衬底10及缓冲层111。欧姆接触层113设置在腐蚀截止层112上，且腐蚀截止层112的的材料例如为N型的砷化镓(GaAs)。在本实施例中，欧姆接触层113的厚度例如为10～30nm，具体例如为15nm、20nm或25nm。且欧姆接触层113中例如掺杂有硅离子，离子的掺杂浓度为2×10 18atoms/cm 2～3×10 18atoms/cm 2。当形成发光二极管时，其中一电极与欧姆接触层113接触，欧姆接触层113中离子的掺杂浓度较高，可增强欧姆接触层113与电极的电性连接。电流扩展层114设置在欧姆接触层113上，以增加N型半导体层的电流扩展能力。且电流扩展层114的的材料例如为N型的磷化铝镓铟(Al X2Ga 1-X2InP)，其中，X2的范围为0.3～0.6，具体为0.4、0.5或0.55。且在 本实施例中，电流扩展层114的厚度例如为10～30nm，具体例如为15nm、20nm或25nm。且电流扩展层114中例如掺杂有硅离子，离子的掺杂浓度为1×10 18atoms/cm 2～2×10 18atoms/cm 2。
请参阅图3所示，在本申请一实施例中，第一限制层115设置在电流扩展层114上，且第一限制层115的的材料例如为N型的磷化铝铟(Al X3In 1-X3P)。其中，X3的范围为例如为0.5，即第一限制层115的材料为Al 0.5In 0.5P。且在本实施例中，第一限制层115的厚度例如为30～80nm，具体例如为50nm、60nm或70nm。且第一限制层115中例如掺杂有硅离子，离子的掺杂浓度为7×10 17atoms/cm 2～1×10 18atoms/cm 2，可为发光层提供电子，同时防止载流子溢出发光层。第一波导层116设置在第一限制层115上，且第一波导层116的的材料例如为N型的磷化铝镓铟(Al X4Ga 1-X4InP)。其中，X4的范围例如为0.5～0.7，具体为0.55、0.6或0.65。且在本实施例中，第一波导层116的厚度例如为30～60nm，具体例如为30nm、40nm、50nm或60nm。本申请提供的第一波导层116中未掺杂其他离子，可防止第一波导层116和衬底10之间的杂质扩散进入发光层。
请参阅图1和图3所示，在本申请一实施例中，可采用金属有机化合物化学气相沉淀(MOCVD)的方式在衬底10上依次沉积缓冲层111、腐蚀截止层112、欧姆接触层113、电流扩展层114、第一限制层115以及第一波导层116。
请参阅图1和图2所示，在本申请一实施例中，发光层12设置在第一类型半导体层11上，发光层12可以是量子阱发光层，也可以是本征半导体层或低掺杂半导体层。在本实施例中，发光层12例如为量子阱发光层，且包括多个周期性层叠设置的磷化镓铟层/磷化铝镓铟层(Ga X11In 1-X11P/(Al X12Ga 1-X12) 0.5In 0.5P)。在其他实施例中，发光层12的材料还可以为铟氮化镓(InGaN)、硒化锌(ZnSe)、 铟氮化镓/氮化镓(InGaN/GaN)、铟氮化镓/氮化镓(InGaN/GaN)、磷化镓(GaP)、铝磷化镓(AlGaP)、铝砷化镓(AlGaAs)、磷化镓(GaP)等材料中的一种或多种。
请参阅图2所示，在本申请一实施例中，发光层12包括多个周期性层叠设置的势阱层和势垒层，且势阱层和势垒层的周期总数例如为12～20。其中，势阱层的材料例如为磷化镓铟，势垒层的材料例如为磷化铝镓铟。且在本申请中，势阱层为非掺杂层，部分势垒层为非掺杂层，部分势垒层为与第二类型半导体层13的掺杂类型相同的掺杂层，且掺杂的势垒层可位于发光层12的任意区域。在本实施例中，为保证离子在发光层中均匀扩散，掺杂的势垒层位于发光层12的中间区域。例如设置为靠近第一类型半导体层11和第二类型半导体层13的多个周期的多个势垒层为非掺杂层。而设置在发光层12中间区域的多个周期的多个势垒层中，设置一个或多个与所述第二类型半导体层的掺杂类型相同的势垒子层，且例如为P型势垒子层。且在本实施例中，掺杂的势垒层的周期数接近周期总数的三分之一，在保证所述发光层具有更高掺杂浓度的条件下，可避免发光层中过高的离子掺杂引入杂质，恶化晶体质量，造成半导体外延结构以及发光二极管电性异常。
具体的，请参阅图2所示，在本实施例中，发光层12包括多个周期性层叠设置的第一势阱层121和第一势垒层122、多个周期性层叠设置的第二势阱层123和第二势垒层124以及多个周期性层叠设置的第三势阱层125和第三势垒层126。且在本实施例中，多个周期性层叠设置的第一势阱层121和第一势垒层122设置在第一类型半导体层11上，多个周期性层叠设置的第二势阱层123和第二势垒层124设置在周期性层叠设置的第一势阱层121和第一势垒层122上，多个周期性层叠设置的第三势阱层125和第三势垒层126设置在周期性层叠设置的第二势阱层123和第二势垒层124上。在其他实施例中，多个周期性层叠设 置的第二势阱层123和第二势垒层124可设置在周期性层叠设置可靠近第一类型半导体层11的一侧。其中，第一势阱层121和第一势垒层122的第一周期数量例如为4～6个，第二势阱层123和第二势垒层124的第二周期数量例如为4～6个，第三势阱层125和第三势垒层126的第三周期数量例如为4～6个。其中，第一周期数量、第二周期数量以及第三周期数量可以相等，也可以不等。在本实施例中，发光层12包括例如5个周期的第一势阱层121和第一势垒层122，例如5个周期的第二势阱层123和第二势垒层124，以及例如5个周期的第三势阱层125和第三势垒层126。在另一些实施例中，发光层12包括例如6个周期的第一势阱层121和第一势垒层122，例如5个周期的第二势阱层123和第二势垒层124，以及例如6个周期的第三势阱层125和第三势垒层126。在其他实施例中，发光层12包括例如5个周期的第一势阱层121和第一势垒层122，例如6个周期的第二势阱层123和第二势垒层124，以及例如5个周期的第三势阱层125和第三势垒层126。
请参阅图2所示，在本申请一实施例中，第一势阱层121、第二势阱层123和第三势阱层125的材料相同，例如为磷化镓铟(Ga X11In 1-X11P)，且X11的范围为0.45～0.5，具体例如为0.46、0.47、0.48或0.49。其中，第一势阱层121、第二势阱层123和第三势阱层125的厚度范围为8～10nm，且第一势阱层121、第二势阱层123和第三势阱层125的厚度可相同，也可不同。在本实施例中，第一势阱层121、第二势阱层123和第三势阱层125的厚度例如均为9nm。在另一实施例中，第一势阱层121和第三势阱层125的厚度例如为9nm，第二势阱层123的厚度例如为10nm。在本实施例中，第一势阱层121、第二势阱层123和第三势阱层125为非掺杂层。
请参阅图2所示，在本申请一实施例中，第一势垒层122、第二势垒层124 和第三势垒层126的材料相同，例如为(Al X12Ga 1-X12) 0.5In 0.5P，且X12的范围为0.5～0.7，且具体例如为0.55、0.6或0.65等。其中，第一势垒层122、第二势垒层124和第三势垒层126的厚度范围为18～24nm，且第一势垒层122、第二势垒层124和第三势垒层126的厚度可相同，也可不同。在本实施例中，第一势垒层122、第二势垒层124和第三势垒层126的厚度例如均为21nm。
具体的，请参阅图2所示，在本实施例中，第一势垒层122、第二势垒层124和第三势垒层126包括三个子层，第一势垒层122例如包括第一势垒子层1221、第二势垒子层1222和第三势垒子层1223，且第二势垒子层1222设置在第一势垒子层1221上，第三势垒子层1223设置在第二势垒子层1222上。第二势垒层124例如包括第一势垒子层1241、第二势垒子层1242和第三势垒子层1243，且第二势垒子层1242设置在第一势垒子层1241上，第三势垒子层1243设置在第二势垒子层1242上。第三势垒层126例如包括第一势垒子层1261、第二势垒子层1262和第三势垒子层1263，且第二势垒子层1262设置在第一势垒子层1261上，第三势垒子层1263设置在第二势垒子层1262上。其中，每个势垒子层的厚度相同，例如为6～8nm，具体例如为7nm。且在第一势垒层122和第三势垒层126中，第一势垒子层1221/1261、第二势垒子层1222/1262和第三势垒子层1223/1263中未掺杂离子。在其他实施例中，可在第一势垒子层1221/1261、第二势垒子层1222/1262和第三势垒子层1223/1263中掺杂与第二类型半导体层13的掺杂类型相同的离子。请参阅图2所示，在本实施中，为进一步保证离子在发光层12中均匀扩散，第二势垒层124中的第一势垒子层1241和第三势垒子层1243未掺杂离子，第二势垒子层1242中掺杂有离子，且第二势垒子层1242的掺杂类型与第二类型半导体层13的掺杂类型相同，例如为P型掺杂。且在本实施例中，第二势垒层124中的第二势垒子层1242中的掺杂离 子为锌离子，具体例如为二乙基锌(DEZn)，且锌离子的掺杂浓度为6×10 17atoms/cm 2～1×10 18atoms/cm 2，具体例如为7×10 17atoms/cm 2、8×10 17atoms/cm 2或9×10 17atoms/cm 2等。在其他实施例中，可以在第一势垒子层和/或第三势垒子层中掺杂锌离子，且掺杂源、掺杂浓度可与第二势垒子层的掺杂相同。且可单独对第一势垒子层或第三势垒子层进行掺杂，也可以对第一势垒子层、第二势垒子层和第三势垒子多个或全部势垒子层进行掺杂。
请参阅图2所示，将位于发光层12中间区域的部分势垒层做掺二乙基锌的P型掺杂，该种掺杂调制的量子阱结构可以提供更高的空穴浓度，降低了串联电阻，使器件拥有比常规结构更好的热效应，且更低的结热可使得量子阱中的载流子更容易被俘获，因此增加发光效率，且更高的空穴浓度可提高复合效率，进而提高光输出效率。
请参阅图2所示，在本申请一实施例中，形成周期性层叠设置的第一势阱层121和第一势垒层122，首先例如可以在温度为690℃～710℃、腔体压力45～55mbar，通入Ⅴ族源磷烷(PH 3)，并以氢气为载气，通入一定比例Ⅲ族源三甲基镓或三甲基铟，并控制沉积时间，生长厚度为例如为9nm的第一势阱层121(Ga X11In 1-X11P)。其中，Ⅴ族源/Ⅲ族源的比例例如为100～150。其次在形成第一势阱层121后，打开三甲基铝通入反应室，并调整Ⅲ族源三甲基镓、三甲基铝以及三甲基铟的比例，依次沉积厚度例如为7nm的第一势垒子层1221、第二势垒子层1222以及第三势垒子层1223，以形成厚度例如为21nm的第一势垒层122(Al X12Ga 1-X12) 0.5In 0.5P。并重复形成第一势阱层121和第一势垒层122的形成步骤，生长4～6个周期的第一势阱层121和第一势垒层122。
请参阅图2所示，在本申请一实施例中，在形成4～6个周期的第一势阱层121和第一势垒层122后，在周期性层叠设置的第一势阱层121和第一势垒层 122上形成第二势阱层123和第二势垒层124。首先例如可以在温度为690℃～710℃、腔体压力45～55mbar，通入Ⅴ族源磷烷(PH 3)，并以氢气为载气，通入一定比例Ⅲ族源三甲基镓或三甲基铟，并控制沉积时间，生长厚度为例如为9nm的第二势阱层123(Ga X11In 1-X11P)。其中，Ⅴ族源/Ⅲ族源的比例例如为100～150。其次在形成第二势阱层123后，在第二势阱层123上形成第二势垒层124，具体可打开三甲基铝通入反应室，并调整Ⅲ族源三甲基镓、三甲基铝以及三甲基铟的比例，依次沉积厚度例如为7nm的第一势垒子层1241。在形成第一势垒子层1241后，保持形成第一势垒子层1241的工艺条件不变，通入一定有效量的二乙基锌掺杂源，并控制沉积时间，生长厚度为7nm的第二势垒子层1242，且第二势垒子层1242中锌离子的掺杂浓度保持在6×10 17atoms/cm 2～1×10 18atoms/cm 2。在形成第二势垒子层1242后，停止通入二乙基锌掺杂源，保持其他生长条件不变，控制沉积时间，生长厚度为7nm的第三势垒子层1243，进而形成中间具有掺杂离子的第二势垒层124。重复形成第二势阱层123和第二势垒层124的形成步骤，生长4～6个周期的第二势阱层123和第二势垒层124。
请参阅图2所示，在本申请一实施例中，在形成4～6个周期的第二势阱层123和第二势垒层124后，在形成周期性层叠设置的第二势阱层123和第二势垒层124后上形成4～6个周期的第三势阱层125和第三势垒层126。其中第三势阱层125的形成方法和第一势阱层121相同，第三势垒层126中第一势垒子层1261、第二势垒子层1262以及第三势垒子层1263的形成方法和第一势垒层122中第一势垒子层1221、第二势垒子层1222以及第三势垒子层1223的的形成方法相同，在此不多作赘述。
请参阅图1和图4所示，在本申请一实施例中，第二类型半导体层13形成 于发光层12上，且第二类型半导体层13可以为空穴较多的P型半导体层，也可以为电子较多的N型半导体层。在本实施例中，第二类型半导体层13例如为P型半导体层，第二类型半导体层中掺杂的为受主杂质，例如为镁(Mg)或锌(Zn)元素。且第二类型半导体层13包括依次设置在发光层12上的第二波导层131、第二限制层132、过渡层133以及窗口层134。
具体的，请参阅图1、图3和图4所示，在本申请一实施例中，第一波导层116直接与发光层12的一侧接触，与第一波导层116对应设置的，第二波导层131直接与发光层12的另一层接触。且第二波导层131设置在发光层12上，且第二波导层131的的材料例如为P型的磷化铝镓铟(Al X5Ga 1-X5InP)。其中，X5的范围例如为0.5～0.7，具体为0.55、0.6或0.65。且在本实施例中，第二波导层131的厚度例如为30～60nm，具体例如为30nm、40nm、50nm或60nm。本申请提供的第二波导层131中未掺杂其他离子，可防止其他第二类型半导体层13中的杂质扩散进入发光层。第二限制层132设置在第二波导层131上，且第二限制层132的的材料例如为P型的磷化铝铟(Al X6In 1-X6P)。其中，X6的范围为例如为0.5，即第二限制层132的材料为Al 0.5In 0.5P。且在本实施例中，第二限制层132的厚度例如为30～80nm，具体例如为50nm、60nm或70nm。且第二限制层132中例如掺杂有镁离子，离子的掺杂浓度为7×10 17atoms/cm 2～1×10 18atoms/cm 2，可为发光层提供空穴，同时防止载流子溢出发光层。
请参阅图1和图4所示，，在本申请一实施例中，过渡层133设置在第二限制层132上，且过渡层133的材料例如为P型的磷化铝镓铟((Al X7Ga 1-X7) 0.5In 0.5P)，其中X7的范围例如为0.2～0.4，具体例如为0.25、0.3或0.35等。且在本实施例中，过渡层133的厚度例如为30～40nm，具体例如为32nm、35nm 或37nm等。且过渡层133中例如掺杂有镁离子，且离子的掺杂浓度为2×10 18atoms/cm 2～3×10 18atoms/cm 2，较高掺杂浓度的过渡层133利于在磷化镓上生长晶体。窗口层134设置在过渡层133上，作为电流扩展层114和出光层使用，且窗口层134可与电极形成良好的欧姆接触。窗口层134的材料例如为P型的磷化镓(GaP)，且窗口层134的厚度例如为40～90nm，具体例如为50nm、60nm或70nm等。且窗口层134中例如掺杂有镁离子，且离子的掺杂浓度为1×10 18atoms/cm 2～2×10 18atoms/cm 2。
请参阅图1和图4所示，在本申请一实施例中，可采用金属有机化合物化学气相沉淀(MOCVD)的方式在发光层12上依次沉积第二波导层131、第二限制层132、过渡层133以及窗口层134。在形成第二类型半导体层13后，即形成半导体外延结构。在形成完整的半导体外延结构后，对半导体外延结构进行外延检测，合格的半导体外延结构可进行发光二极管制成。
请参阅图3、图4和图5所示，在本申请一实施例中，发光二极管例如为发光二极管，可对半导体外延结构的一侧进行蚀刻，形成凹部，且凹部暴露第一类型半导体层11中的欧姆接触层113。在形成可以通过蒸镀和/或溅射技术，分别凹部内的在欧姆接触层113上沉积第一电极14，在窗口层134上沉积第二电极15，且第一电极14和第二电极15可设置为等高电极。在本实施例中，第一电极14为N型电极，且第一电极14的材料例如为锗和/或铜。第二电极15为P型电极，且第二电极15的材料例如为铍和/或铜。在一些实施例中，还可以在第二类型半导体层13上沉积一层钝化层16，作为发光二极管的保护层或封装体，钝化层16例如可以是氧化硅、氮化硅或磷硅玻璃等材料。
综上所示，本申请提供的一种半导体外延结构及其制作方法、发光二极管，在在第一类型半导体层上形成发光层，在发光层上形成第二类型半导体层，进 而形成半导体外延结构。并在第一类型半导体层沉积第一电极，在第二类型半导体层上沉积第二电极，形成发光二极管。本申请提供的一种半导体外延结构及发光二极管，拥有较好的热效应，可提高光的输出效率。
应当理解的是，本申请的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本申请所附权利要求的保护范围。

Claims (15)

  1. 一种半导体外延结构，包括：
    第一类型半导体层；
    发光层，设置在所述第一类型半导体层上；以及
    第二类型半导体层，设置在所述发光层上；
    其中，所述发光层包括周期性层叠设置的势阱层和势垒层，且所述发光层中间区域的至少部分所述势垒层被掺杂，且掺杂类型与所述第二类型半导体层的掺杂类型相同。
  2. 如权利要求1所述的半导体外延结构，其中，所述势阱层和所述势垒层的层叠周期总数介于12～20之间。
  3. 如权利要求1所述的半导体外延结构，其中，被掺杂的所述势垒层与势阱层的层叠周期数介于4～6之间。
  4. 如权利要求1所述的半导体外延结构，其中，所述势垒层包括三层势垒子层，三层势垒子层分别记为第一势垒子层、第二势垒子层和第三势垒子层；所述第一势垒子层、第二势垒子层和第三势垒子层依次层叠设置。
  5. 如权利要求4所述的半导体外延结构，其中，被掺杂的所述势垒层中，所述第一势垒子层被掺杂；和/或
    所述第二势垒子层被掺杂；和/或
    所述第三势垒子层被掺杂。
  6. 如权利要求1-5任一项所述的半导体外延结构，其中，被掺杂的所述势垒层为P型掺杂，且掺杂源为二乙基锌。
  7. 如权利要求1所述的半导体外延结构，其中，所述第一类型半导体层包括：
    腐蚀截止层；以及
    欧姆接触层，形成于所述腐蚀截止层上。
  8. 如权利要求7所述的半导体外延结构，其中，所述第一类型半导体层还包括：
    电流扩展层，形成于所述欧姆接触层上；
    第一限制层，形成于所述电流扩展层上；以及
    第一波导层，形成于所述第一限制层上。
  9. 如权利要求1所述的半导体外延结构，其中，所述第二类型半导体层包括：
    第二波导层，设置在所述发光层上；
    第二限制层，设置在所述第二波导层上；
    过渡层，设置在所述第二限制层上；以及
    窗口层，设置在所述过渡层上。
  10. 一种半导体外延结构的制造方法，包括：
    提供一衬底；
    在所述衬底上形成第一类型半导体层；
    在所述第一类型半导体层上形成发光层；以及
    在所述发光层上形成第二类型半导体层；
    其中，所述发光层包括周期性层叠设置的势阱层和势垒层，且所述发光层中间区域的至少部分所述势垒层被掺杂，且掺杂类型与所述第二类型半导体层的掺杂类型相同。
  11. 如权利要求10所述的半导体外延结构的制造方法，其中，所述势阱层的形成步骤包括：
    在预设温度和腔体压力下，通入磷烷，并以氢气为载气，通入预设比例的 三甲基镓或三甲基铟；
    控制沉积时间，生长预设厚度的势阱层。
  12. 如权利要求11所述的半导体外延结构的制造方法，其中，所述势垒层包括第一势垒子层、第二势垒子层和第三势垒子层；被掺杂的所述势垒层的形成步骤包括：
    在形成所述势阱层后，向反应室通入三甲基铝，并调整三甲基镓、三甲基铝和三甲基铟的比例，控制沉积时间，生长预设厚度的第一势垒子层；
    保持形成第一势垒子层的生长条件，向反应室通入二乙基锌，控制沉积时间，生长预设厚度的第二势垒子层；
    保持形成第二势垒子层的生长条件，停止向反应室通入二乙基锌，控制沉积时间，生长预设厚度的第三势垒子层。
  13. 如权利要求12所述的半导体外延结构的制造方法，其中，所述第二势垒子层中锌离子的掺杂浓度范围为6×10 17atoms/cm 2～1×10 18atoms/cm 2。
  14. 一种发光二极管，包括：
    半导体外延结构，且所述半导体外延结构包括：
    第一类型半导体层；
    发光层，设置在所述第一类型半导体层上；
    第二类型半导体层，设置在所述发光层上；
    其中，所述发光层包括周期性层叠设置的势阱层和势垒层，且所述发光层中间区域的至少部分所述势垒层被掺杂，且掺杂类型与所述第二类型半导体层的掺杂类型相同；
    第一电极，与所述第一类型半导体层连接；以及
    第二电极，与所述第二类型半导体层连接。
  15. 一种电子设备，包括：
    控制装置；以及
    灯板，电性连接于所述控制装置，且所述灯板上设置有多个发光二极管，且所述发光二极管包括：
    半导体外延结构，且所述半导体外延结构包括：
    第一类型半导体层；
    发光层，设置在所述第一类型半导体层上；以及
    第二类型半导体层，设置在所述发光层上；
    其中，所述发光层包括周期性层叠设置的势阱层和势垒层，且所述发光层中间区域的至少部分所述势垒层被掺杂，且掺杂类型与所述第二类型半导体层的掺杂类型相同；
    第一电极，与所述第一类型半导体层连接；以及
    第二电极，与所述第二类型半导体层连接。
PCT/CN2021/129776 2021-11-10 2021-11-10 半导体外延结构及其应用、半导体外延结构的制作方法 WO2023082092A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2021/129776 WO2023082092A1 (zh) 2021-11-10 2021-11-10 半导体外延结构及其应用、半导体外延结构的制作方法
US18/152,902 US20230170437A1 (en) 2021-11-10 2023-01-11 Semiconductor epitaxial structure and method for manufacturing the same, and led

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/129776 WO2023082092A1 (zh) 2021-11-10 2021-11-10 半导体外延结构及其应用、半导体外延结构的制作方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/152,902 Continuation US20230170437A1 (en) 2021-11-10 2023-01-11 Semiconductor epitaxial structure and method for manufacturing the same, and led

Publications (1)

Publication Number Publication Date
WO2023082092A1 true WO2023082092A1 (zh) 2023-05-19

Family

ID=86334971

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/129776 WO2023082092A1 (zh) 2021-11-10 2021-11-10 半导体外延结构及其应用、半导体外延结构的制作方法

Country Status (2)

Country Link
US (1) US20230170437A1 (zh)
WO (1) WO2023082092A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104094A (zh) * 2009-12-21 2011-06-22 晶元光电股份有限公司 发光元件及其制造方法
CN102157647A (zh) * 2011-05-03 2011-08-17 映瑞光电科技(上海)有限公司 一种氮化物led结构及其制备方法
JP2012244163A (ja) * 2012-04-16 2012-12-10 Toshiba Corp 半導体発光素子及びウェーハ
CN105374912A (zh) * 2015-10-28 2016-03-02 厦门市三安光电科技有限公司 发光二极管及其制作方法
CN110289343A (zh) * 2018-12-03 2019-09-27 东莞理工学院 一种非极性面氮化镓衬底外延结构及其制备方法与应用
CN112366256A (zh) * 2020-09-30 2021-02-12 华灿光电（浙江）有限公司 发光二极管外延片及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102104094A (zh) * 2009-12-21 2011-06-22 晶元光电股份有限公司 发光元件及其制造方法
CN102157647A (zh) * 2011-05-03 2011-08-17 映瑞光电科技(上海)有限公司 一种氮化物led结构及其制备方法
JP2012244163A (ja) * 2012-04-16 2012-12-10 Toshiba Corp 半導体発光素子及びウェーハ
CN105374912A (zh) * 2015-10-28 2016-03-02 厦门市三安光电科技有限公司 发光二极管及其制作方法
CN110289343A (zh) * 2018-12-03 2019-09-27 东莞理工学院 一种非极性面氮化镓衬底外延结构及其制备方法与应用
CN112366256A (zh) * 2020-09-30 2021-02-12 华灿光电（浙江）有限公司 发光二极管外延片及其制造方法

Also Published As

Publication number Publication date
US20230170437A1 (en) 2023-06-01

Similar Documents

Publication Publication Date Title
US5684309A (en) Stacked quantum well aluminum indium gallium nitride light emitting diodes
KR100406200B1 (ko) 이중 헤테로구조체를 구비한 발광 질화갈륨계 화합물 반도체 장치
US7692203B2 (en) Semiconductor light emitting device
CN102117771B (zh) 一种发光二极管外延片和管芯及其制作方法
US20070284590A1 (en) Light Emitting Element And Manufacturing Method Thereof
KR101646664B1 (ko) 발광 소자, 발광 소자의 제조방법 및 발광 소자 패키지
WO2006126516A1 (ja) 窒化物半導体発光素子
JP2008282851A (ja) 半導体発光素子
WO2011079644A1 (en) Light emitting diode and method for preparing the same
JP2000068555A (ja) 照明システム
JP2003168822A (ja) 発光素子及びその製造方法
TWI786248B (zh) 發光元件
JP5906001B2 (ja) 発光ダイオード用エピタキシャルウェーハ
CN114388670A (zh) 一种不可见光发光二极管
CN108604622B (zh) 发光器件和包括发光器件的发光器件封装
JP3498140B2 (ja) 半導体発光素子
WO2023082092A1 (zh) 半导体外延结构及其应用、半导体外延结构的制作方法
US8421056B2 (en) Light-emitting device epitaxial wafer and light-emitting device
JP2003008058A (ja) ＡｌＧａＩｎＰエピタキシャルウエーハ及びそれを製造する方法並びにそれを用いた半導体発光素子
CN113224211A (zh) 紫外发光二极管外延片及其制造方法
CN114122205A (zh) 半导体外延结构及其应用、半导体外延结构的制作方法
KR20130021931A (ko) 반도체 발광소자 및 그 제조방법
KR20120116257A (ko) 발광 다이오드의 휘도 향상 방법 및 그에 의한 발광 다이오드
US8513118B2 (en) Method for producing compound semiconductor light-emitting device
JP2950316B2 (ja) 窒化ガリウム系化合物半導体発光素子及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21963548

Country of ref document: EP

Kind code of ref document: A1