WO2023077264A1 - 一种存储单元、三维存储器及其操作方法 - Google Patents

一种存储单元、三维存储器及其操作方法 Download PDF

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Publication number
WO2023077264A1
WO2023077264A1 PCT/CN2021/128164 CN2021128164W WO2023077264A1 WO 2023077264 A1 WO2023077264 A1 WO 2023077264A1 CN 2021128164 W CN2021128164 W CN 2021128164W WO 2023077264 A1 WO2023077264 A1 WO 2023077264A1
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layer
thermocouple
layers
channel
substrate
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PCT/CN2021/128164
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English (en)
French (fr)
Inventor
张刚
李春龙
霍宗亮
叶甜春
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中国科学院微电子研究所
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Priority to PCT/CN2021/128164 priority Critical patent/WO2023077264A1/zh
Publication of WO2023077264A1 publication Critical patent/WO2023077264A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements

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  • the present disclosure relates to the technical field of three-dimensional memory, and in particular to a storage unit, a three-dimensional memory and an operation method thereof.
  • Three-dimensional NAND memory technology is currently a technology that the country is focusing on developing. It can apply multi-bit storage technology, such as 4bit/cell or 5bit/cell.
  • High data density three-dimensional memory is the basis for building big data and cloud storage systems.
  • the multi-bit storage technology of the three-dimensional memory requires a clear read space (ESUM) between the data states (State). Higher channel temperature during write operation is beneficial to achieve better ESUM.
  • ESUM clear read space
  • ESUM data states
  • Higher channel temperature during write operation is beneficial to achieve better ESUM.
  • a higher temperature in the storage layer is not conducive to data storage (Data Retention), and it is easy to cause data storage failure.
  • the present disclosure provides a storage unit, a three-dimensional memory and an operation method thereof to solve the above technical problems.
  • a first aspect of the present disclosure provides a memory cell, including: a channel layer array, including: N channel layers, the N channel layers are vertically arranged on the substrate along the first direction, and the N channel layers A tunneling layer and a storage layer are arranged in sequence on the outside of the layer, and N is a positive integer; N thermally conductive cores are respectively located in N channel layers and run through the substrate; a thermocouple array includes: growing along the negative direction of the first direction The thermocouple word line layer on the substrate and the N thermocouple layers located on the thermocouple word line layer, and the N thermocouple layers are connected to the N thermal conduction cores in one-to-one correspondence; wherein, in the thermocouple word line layer and the N thermocouple layers A first potential difference is applied between some of the thermocouple layers, and the heat-conducting core connected to the part of the thermocouple layer is heated, so that the channel layer and the storage layer corresponding to the heat-conducting core are in the tunnel layer.
  • the storage unit is configured as follows: after the temperatures of part of the channel layers in the channel layer array and the corresponding storage layers are respectively maintained at the first preset temperature and the second preset temperature, the gate layer of the storage unit is applied The write voltage is used to ground the drain layer and the substrate, and the write voltage is used to drive some of the memory cells to perform a write operation.
  • the heating time of the first potential difference is negatively correlated with the heat conduction performance of the N heat conduction cores.
  • the N heat conducting cores are all made of one or more of tungsten, gold, copper and silicon carbide.
  • the storage unit further includes: a channel insulating layer disposed between the channel layer and the heat conducting core.
  • the channel insulating layer is used to isolate the channel layer and the heat conducting core, and is made of silicon oxide or aluminum oxide.
  • the tunneling layer is made of silicon oxide or silicon nitride.
  • the storage unit further includes: setting a barrier layer outside the storage layer.
  • a second aspect of the present disclosure provides a three-dimensional memory, including: the storage unit provided in the first aspect of the present disclosure.
  • a third aspect of the present disclosure provides a method for operating a three-dimensional memory based on the second aspect of the present disclosure, including: controlling the substrate, drain layer, gate layer or thermocouple of some memory cells in the three-dimensional memory
  • the voltage bias of the layer enables some memory cells in the three-dimensional memory to respectively implement data writing, reading and erasing operations.
  • the part of the storage cells in the three-dimensional memory implements the data writing operation, including: applying a first potential difference between the thermocouple word line layer and some of the thermocouple layers in the N thermocouple layers, and the part of the thermocouple layers
  • the connected heat conduction core is heated so that the channel layer and the storage layer corresponding to the heat conduction core respectively maintain the first preset temperature and the second preset temperature under the heat insulation effect of the tunnel layer;
  • the drain layer corresponding to the channel layer is grounded, and a write voltage is applied to the gate layer, and the write voltage is used to drive some memory cells in the three-dimensional memory to perform a write operation.
  • part of the memory cells in the three-dimensional memory implements the data reading operation, including: triggering the data reading program; applying a bias voltage to the drain layer of the three-dimensional memory; grounding the substrate; Apply a turn-on voltage to the electrode layer, apply a read voltage to the gate layer of the selected memory cell; sense the voltage between the drain layer of the selected memory cell and the substrate, and/or the current change to read data.
  • some memory cells in the three-dimensional memory implement data erasing operations, including: triggering a data erasing program; floating or grounding the gate layer; applying an erasing voltage to the drain layer, and the erasing voltage is sufficient to make the three-dimensional memory Tunneling effect, so that electrons stored in the three-dimensional memory are attracted to the drain layer.
  • the present disclosure at least has the following beneficial effects:
  • thermocouple is connected to the end of each heat conduction core, and the thermocouple can generate heat pulses in units of strings or strings to heat the heat conduction core to achieve The purpose of forming a temperature gradient between the channel layer, storage layer and barrier layer.
  • the storage unit can achieve good data storage while ensuring good writing.
  • thermocouple By reading the ambient temperature before the thermocouple operates, adjust the number of pulses generated by the thermocouple according to the ambient temperature to achieve a better data writing environment.
  • the writing operation time of the three-dimensional memory provided by the present disclosure does not exceed 3 ms.
  • FIG. 1 schematically shows a partial structural diagram of a section of a memory cell according to an embodiment of the present disclosure
  • Fig. 2 schematically shows a schematic diagram of the temperature gradient of the memory cell according to Fig. 1;
  • 3A to 3I schematically show the structural diagrams corresponding to each step of the method for preparing a storage unit according to an embodiment of the present disclosure
  • FIG. 4 schematically shows a flow chart of an operation method for reading data according to an operation method of a three-dimensional memory according to an embodiment of the present disclosure
  • FIG. 5 schematically shows a flow chart of an operation method for data erasing of a three-dimensional memory operation method according to an embodiment of the present disclosure
  • Fig. 6 schematically shows a flow chart of the operation method of data writing in the operation method of the three-dimensional memory according to an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a memory cell, including: a channel layer array, including: N channel layers, the N channel layers are vertically arranged on the substrate along a first direction, and the outside of the N channel layers The tunneling layer and the storage layer are arranged in sequence, and N is a positive integer; N heat-conducting cores are respectively located in the N channel layers and run through the substrate; the thermocouple array includes: growing on the substrate along the negative direction of the first direction The thermocouple word line layer on the bottom and the N thermocouple layers located on the thermocouple word line layer, and the N thermocouple layers are connected to the N thermal conduction cores in one-to-one correspondence; among them, the thermocouple word line layer and the N thermocouple layers A first potential difference is applied between some of the thermocouple layers in the double layer, and the heat-conducting core connected to the part of the thermocouple layer is heated, so that the channel layer and the storage layer corresponding to the heat-conducting core are separated by the tunnel layer.
  • a heat conduction core is arranged inside the channel, and a thermocouple is connected to each end of the heat conduction core.
  • a storage unit is provided.
  • FIG. 1 schematically shows a partial structural diagram of a section of a memory cell according to an embodiment of the present disclosure.
  • the storage unit structure of the embodiment of the present disclosure includes:
  • the stacked layer 20 is stacked on the substrate 10 along the first direction (the positive direction of the z-axis).
  • the channel layer array includes: N channel layers 30, the N channel layers 30 are vertically arranged on the substrate 10 along the first direction, and the tunnel layer 40 and the storage layer 50 are sequentially arranged outside the N channel layers 30 , where N is a positive integer.
  • N heat conducting cores 80 are respectively located in N channel layers 30 and penetrate through the substrate 10 .
  • thermocouple array including: a thermocouple word line layer 901 grown on the substrate 10 along the negative direction of the first direction (z-axis negative direction) and N thermocouple layers 902, N located on the thermocouple word line layer
  • the thermocouple layers 902 are connected to the N heat conducting cores 80 in one-to-one correspondence.
  • thermocouple word line layer 901 is applied between the thermocouple word line layer 901 and part of the thermocouple layers 902 in the N thermocouple layers, and the heat-conducting core 80 connected to the part of the thermocouple layers is subjected to heat treatment, so that the heat-conducting core 80 connected with the thermocouple layer
  • the channel layer 30 and the storage layer 50 corresponding to 80 maintain the first preset temperature and the second preset temperature respectively under the thermal insulation effect of the tunneling layer 40 .
  • the substrate 10 may be a conductive type substrate 10, including: a first conductive type substrate 101 and a second conductive type substrate 102, the first conductive type substrate 101, the second conductive type substrate
  • the material of 102 is, for example, polysilicon, but the conductivity types of the two are opposite.
  • the first conductivity type is p-type
  • the second conductivity type is n-type
  • corresponding to the first conductivity type substrate 101 is a p-type substrate
  • the second conductivity type substrate 102 is an n-type conduction layer
  • the p-type substrate The bottom is used to provide the holes needed for the erasing operation, and the holes provided by the first conductivity type substrate 101 are pumped into the channel layer 30 to realize the erasing operation
  • the n-type conduction layer provides the electrons needed for the reading operation
  • the electrons needed for the reading operation are provided by the second conductive type substrate 101.
  • the two-conductivity-type conduction layer 102 (n-type conduction layer) provides electron pumping into the channel layer 30 to implement the read operation.
  • the stacked layer 20 includes: a plurality of stacked layer pairs, each stacked layer pair includes a first stacked material 201 and a second stacked material 202, wherein the second stacked material 202 and the first stacked material Layer materials 201 are sequentially stacked on the substrate 10 .
  • the second stacked material 202 is an insulator layer, such as OX, etc.
  • the first stacked material 201 is a metal dielectric layer, which is a word line layer, wherein the stacked layer 20 closest to the substrate 10 A word line layer is the lower selection layer, and a word line layer farthest from the substrate 10 is the upper selection layer.
  • an array of channel holes is formed on the stacked layer 20 by etching.
  • the barrier layer 60, the storage layer 50, the tunneling layer 40 and the channel layer 30 are sequentially grown and formed in the channel hole array formed by etching the stacked layer 20, and part of the barrier layer 60 and the storage layer 50 are removed. 1.
  • the tunneling layer 40 exposes part of the channel layer 30 , as shown in FIG. 1 .
  • a channel insulating layer 70 is disposed between the channel layer 30 and the heat conducting core 80 .
  • the tunneling layer 40 is a heat insulating layer, used to prevent the temperature of the storage layer 50 from rising suddenly as the temperature of the heat conduction core 80 rises, and its material may be silicon oxide or silicon nitride.
  • the channel insulating layer 70 is a thin electrical insulating layer for isolating the channel layer 30 and the heat conducting core 80 , and its constituent material may be silicon oxide or aluminum oxide.
  • thermocouple word line 901 is a small-sized metal line, the line width of the thermocouple word line 901 is smaller than the width of the channel hole, and the line width of the thermocouple word line 901 is about 100 nm.
  • the thermocouple word lines 901 are in the same direction as the word line layer 201 in the y-axis direction, and each thermocouple word line 901 only covers one string in the x-axis direction.
  • the word line layer 201 is a large-sized metal line covering multiple strings in the x-axis direction, such as 9 strings, 16 strings, 19 strings, 24 strings, etc.
  • the line width of the word line layer 201 can be 1600nm or 3200nm. It should be noted that, in this embodiment, as shown in FIG. 1 , the width of the channel hole is the distance between the barrier layers 60 on both sides of each channel hole.
  • thermocouple bit lines 903 of the unit are connected in one-to-one correspondence, or are in one-to-one correspondence with the bit lines 904 (8-bit-line or 16-bit-line) in the bit line group.
  • the heat conduction core 80 is a good conductor of temperature, and its material can be metal or semiconductor, such as tungsten, gold, copper, silicon carbide, and the like.
  • the heating time of the thermally conductive core 80 connected thereto through the thermocouple layer 902 is negatively correlated with the thermal conductivity of the thermally conductive core 80, that is, the thermally conductive core
  • the heating time is 1ms to 5ms; The heating time is 6-10ms.
  • the heating time is preferably on the order of milliseconds, so that the heat-conducting core 80 can be heated quickly and then the writing operation can be performed.
  • thermocouple word line layer 901 before performing a write operation on the memory cell, by applying a first potential difference between the thermocouple word line layer 901 and part of the thermocouple layer 902 in the N thermocouple layers, the thermal The heat-conducting core 80 connected with the double layer 902 is subjected to heat treatment, so that the channel layer 30 and the storage layer 50 corresponding to the heat-conducting core maintain the first preset temperature and the second preset temperature respectively under the thermal insulation effect of the tunneling layer 40 .
  • thermocouple layers 902 in the N thermocouple layers can be selected and controlled by a logic control circuit, and the bias voltage operation can be performed on the thermocouple layers connected in the selected string or string group, so that the temperature of the thermocouples can be increased. up to less than 450°C.
  • the heat conduction core 80 conducts the temperature of the thermocouple to the selected string or string group, and raises the temperature of the channel layer and the storage layer to a preset temperature.
  • the number of thermal pulses of the bias voltage is a variable. When the ambient temperature is high, the number of thermal pulses applied is small compared to when the ambient temperature is low.
  • the first potential difference can be 8V-10V
  • the heating time is 1-10ms.
  • the temperature of the heated heat-conducting core 80 can be raised to a temperature close to the temperature of the thermocouple layer (less than 450°C ), so that the temperature of the channel layer 30 is kept at a first preset temperature t1 of 65°C to 90°C, the temperature of the storage layer 50 is kept at a second preset temperature t2 of 30°C to 40°C, and the barrier layer 60
  • the temperature is maintained at the natural ambient temperature t 3 , such as -25°C to 30°C, as shown in Figure 2.
  • the memory cell By forming a temperature gradient between the channel layer 30, the storage layer 50, and the barrier layer 60, the memory cell can achieve good data storage while ensuring good writing, effectively avoiding the problem of high temperature.
  • the temperature of the storage layer is not conducive to data storage during the write operation.
  • the selected heat conduction core is heated by a thermocouple array, and a temperature gradient is formed between the channel layer, the storage layer and the barrier layer, so that the storage unit is at a constant temperature during the write operation. carried out without interference from changes in ambient temperature.
  • a good data storage temperature can be achieved at the same time.
  • FIG. 1 is only a partial cross-sectional view of the memory cell provided by the present disclosure, which does not represent the limitation of the number of layers of the memory cell and the number of channel layer arrays provided by the present disclosure.
  • the layers of the memory cell provided by the present disclosure The number and channel layer array can be set according to actual application conditions, which are not limited in the embodiments of the present disclosure.
  • a method of manufacturing a memory cell is provided.
  • 3A to 3I schematically show the structure corresponding to each step of the method for preparing a memory unit according to an embodiment of the present disclosure, and the structure of the memory unit prepared by the steps of the method is shown in FIG. 1 .
  • the preparation method of the storage unit includes:
  • Step 301 make N channel holes in the first low-concentration conductive type extension layer 12 and the stacked layer 20 above the substrate 11, and sequentially deposit barriers inside and at the bottom of the N channel holes.
  • layer 60 storage layer 50 , tunneling layer 40 and channel layer 30 .
  • N is a positive integer.
  • the first low-concentration conductive type extension layer 12 (p-type silicon extension layer 12 ) and the stacked layer 20 are sequentially (along the positive direction of the z-axis) deposited on the substrate.
  • the first low-concentration conductive type extension layer 12 is, for example, a p-type silicon substrate.
  • the p-type silicon extension layer 12 can be stopped by wet etching with a high selectivity ratio of p-type silicon to p-type silicon. layer.
  • step 302 as shown in FIG. 3B , the substrate 11 and the first low-concentration conductive type extension layer 12 are sequentially removed, so that part of the barrier layer 60 is exposed.
  • the storage unit is a part of the three-dimensional memory, and the front of the storage unit needs to be attached to the front of the logic control unit.
  • the back side of the storage unit (substrate side) is cut off most of the thickness of the substrate 11 by chemical mechanical grinding, and the p-type silicon is used to p-type silicon (difference in doping concentration)
  • the p-type silicon is used to p-type silicon (difference in doping concentration)
  • the wet etching operation for removing the substrate in step S302 may only be performed on the substrate 11 side of the device, without placing the entire device in the etching solution.
  • the P-type silicon extension layer 12 can be removed by wet etching by utilizing the high selectivity ratio of silicon oxide to silicon, so as to expose part of the barrier layer 60 .
  • Step 303 as shown in FIG. 3C , removing part of the barrier layer 60 , the storage layer 50 , the tunneling layer 40 and the stacking layer 20 so that the channel layer 30 is partially exposed.
  • Step 304 deposit a second conductivity type covering layer on the exposed upper surface (z-axis negative direction) of the channel layer 30, and remove the second conductivity type covering layer corresponding to the protruding part of the channel layer 30, Make the second conductivity type cladding layer be at the same level and expose the protruding part of the channel layer 30 .
  • the second conductivity type cladding layer is, for example, n-type silicon, and the second conductivity type cladding layer is the corresponding second in the subsequent device structure.
  • the precursor of the conductive type substrate 102 is patterned to obtain the second conductive type substrate 102 .
  • Step 305 depositing the substrate 101 of the first conductivity type on the substrate 102 of the second conductivity type, wherein the formed substrate 101 of the first conductivity type does not cover above the protruding part of the channel layer 30 .
  • Step 306 sequentially deposit an insulator layer 202 and a thermocouple word line layer 901 on the substrate 101 of the first conductivity type, wherein the insulator layer 202 and the thermocouple word line layer 901 cover the channel layer 30 The top of the out part, and does not cover the top of the inner cavity of the channel layer 30 .
  • Step 307 sequentially deposit and form a channel insulating layer 70 and a thermally conductive core 80 inside each channel layer 30 to be at the same level as the thermal couple word line layer 901 .
  • Step 308 as shown in FIG. 3H , deposit and form a thermocouple layer 902 and a thermocouple word line 903 on the channel insulation layer 70 and the thermal conduction core 80 , and deposit an insulator layer on the thermocouple layer 902 .
  • Step 309 as shown in FIG. 3I , forming bit line leads, depositing metal, and forming bit lines 904 to complete the manufacturing of memory cells.
  • FIG. 3I The diagram shown in FIG. 3I and the structural diagram shown in FIG. 1 are upside down.
  • the process of removing part of the structure is not limited to the above-mentioned wet etching and photolithography processes, and can be A combination of the two or other dry etching or wet etching processes can be used.
  • a three-dimensional memory is provided, including any storage unit mentioned in the present disclosure.
  • the three-dimensional memory further includes: a logic control unit, the storage unit is connected to the front of the high logic control unit.
  • the three-dimensional memory may be a three-dimensional NAND memory.
  • thermocouple layer can be realized through the logic control unit, which can select one thermocouple layer or multiple thermocouple layers at the same time, and heat the corresponding heat-conducting core to make the improvement
  • the temperature of the channel layer and the storage layer reaches the preset temperature to realize a good data writing and storage process.
  • a method for operating the three-dimensional memory as described above including: controlling the substrate, drain layer, gate layer or thermocouple of some memory cells in the three-dimensional memory
  • the voltage bias of the layer enables some memory cells in the three-dimensional memory to respectively implement data writing, reading and erasing operations.
  • the operation method includes the operation method of data reading, the operation method of data erasing and the operation method of data writing, wherein, the operation method of data reading, the operation method of data erasing and the operation method of data writing There is no fixed sequence of execution.
  • the operation method of the data reading comprises the following steps:
  • Step S401 triggering a data reading program.
  • Step S402 applying a bias voltage to the drain layer; grounding the substrate; applying a turn-on voltage to the gate layer of the unselected memory unit; applying a read voltage to the gate layer of the selected memory unit.
  • Step S403 sensing the voltage and/or current change between the drain layer and the substrate of the selected memory cell to read data.
  • a bias voltage is applied to the drain layer, and the substrate is grounded, so that when the read operation is performed, the current change between the drain layer and the substrate can be sensed.
  • the bias voltage ranges from 1V to 1.4V, preferably 1.2V.
  • a turn-on voltage is applied to the gate layer, so that the channel layer is turned on, and current can flow from the drain layer to the substrate.
  • the turn-on voltage is a voltage that can be guaranteed to be greater than the VT of any memory cell, but the turn-on voltage cannot be too large, otherwise the three-dimensional memory will have a tunneling effect.
  • the range of the conduction voltage may be between 2V and 8V.
  • the gate layer applies a read voltage, and if the read voltage is greater than the VT of the memory cell, the channel layer can be turned on.
  • the gate layer By trying to apply different read voltages to the gate layer, it is possible to know the amount of charge stored in the memory cell, and thus the stored data.
  • the operation method of this data erasing comprises the following steps:
  • Step S501 triggering a data erasing program.
  • Step S502 floating or grounding the gate layer; applying an erasing voltage to the substrate; and applying an erasing voltage to the drain layer.
  • the gate layer When performing a data erasing operation on the three-dimensional memory, the gate layer is floated or grounded, an erasing voltage is applied to the semiconductor region, and an erasing voltage is applied to the drain layer. Since the drain layer is at a high potential, it can attract the electrons trapped in the charge trapping layer, and the erasing voltage is sufficient to cause the three-dimensional memory to have a tunneling effect, so that the electrons are successfully attracted by the drain, and then the electrons on the charge trapping layer are released.
  • the semiconductor region is kept at the same potential as the drain layer to prevent electrons from flowing from the drain layer to the semiconductor region.
  • the erasing voltage ranges from 14V to 20V, preferably 14V.
  • the drain layer can be used to perform data without applying a high voltage, thereby realizing top erasing and improving the efficiency of the erasing operation of the three-dimensional memory.
  • the operation method of the data writing includes the following steps:
  • Step S601 applying a first potential difference between the thermocouple word line layer and part of the thermocouple layers in the N thermocouple layers, and performing heat treatment on the thermally conductive core connected to the part of the thermocouple layer, so that the groove corresponding to the thermally conductive core
  • the channel layer and the storage layer respectively maintain the first preset temperature and the second preset temperature under the thermal insulation effect of the tunneling layer.
  • Step S602 triggering the data writing procedure.
  • Step S603 grounding the substrate and the drain layer corresponding to the channel layer, and applying a writing voltage to the gate layer.
  • thermocouple word line layer 901 before data is written into the memory, firstly by applying a first potential difference between the thermocouple word line layer 901 and a part of the thermocouple layer 902 in the N thermocouple layers, the part of the thermocouple layer 902, heat-treating the heat-conducting core 80 so that the channel layer 30 and the storage layer 50 corresponding to the heat-conducting core maintain the first preset temperature and the second preset temperature respectively under the thermal insulation effect of the tunneling layer 40 , and then trigger the data writing procedure.
  • the first potential difference may be 8V-10V, and the temperatures of the channel layer 30 and the storage layer 50 may be raised to preset temperatures in milliseconds.
  • the drain layer is grounded, the substrate is grounded, and the gate layer is applied with a writing voltage. Because the gate layer is at a high potential, it can attract electrons to approach, and the write voltage is sufficient to cause the three-dimensional memory to have a tunneling effect, so that electrons are captured by the charge trapping layer when approaching the gate layer.
  • the range of the writing voltage is not higher than 25V, and different programming voltages determine the number of electrons written into the charge trapping layer, so that different data states of three-dimensional memory storage cells can be realized by using different programming voltages. In the above-described embodiments, electrons are attracted to the gate layer, so that current flows from the gate layer to the substrate.
  • the operation method is not limited to these steps, and other steps that are omitted from description can be adjusted accordingly according to actual conditions.
  • the operation method of the three-dimensional memory provided by this embodiment can use the drain layer to clear data without applying a high voltage, and at the same time facilitate data reading and data writing, thereby better preventing damage to the device and improving the performance of the device. Lifespan of 3D memory. In the case of ensuring a good writing temperature of the storage unit, a good data storage temperature is achieved at the same time.
  • thermocouple is connected to the end of each heat conduction core, and the thermocouple can generate heat pulses in a string or a string group to heat the heat conduction core to achieve The purpose of forming a temperature gradient between the channel layer, the storage layer and the barrier layer.
  • the storage unit can achieve good data storage while ensuring good writing.
  • thermocouple By reading the ambient temperature before the thermocouple operates, adjust the number of pulses generated by the thermocouple according to the ambient temperature to achieve a better data writing environment.

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Abstract

本公开提供了一种存储单元，包括：沟道层阵列，包括：N个沟道层，N个沟道层沿着第一方向垂直设置在衬底上，N个沟道层外侧依次设置隧穿层及存储层，N为正整数；N个导热芯，分别位于N个沟道层内，且贯穿衬底；热偶阵列，包括：沿着第一方向的负方向生长在衬底上的热偶字线层及位于热偶字线层上的N个热偶层，N个热偶层与N个导热芯一一对应连接；其中，在热偶字线层及N个热偶层中的部分热偶层之间施加第一电势差，对与该部分热偶层连接的导热芯进行加热处理，使与该导热芯对应的沟道层及存储层在隧穿层的隔热作用下分别保持第一预置温度及第二预置温度。本公开还提供了一种三维存储器及其操作方法。

Description

一种存储单元、三维存储器及其操作方法 技术领域
本公开涉及三维存储器技术领域，具体涉及一种存储单元、三维存储器及其操作方法。
背景技术
三维NAND存储器技术是目前国家正在重点发展的技术，其可应用多数位存储技术，例如4bit/cell或5bit/cell，高数据密度三维存储器是建设大数据及云存储体系的基础。三维存储器的多数位存储技术要求数据态(State)之间有清晰的读取空间(ESUM)。写入操作时较高的沟道温度有利于实现更好的ESUM。但是，较高的存储层温度不利于数据存储(Data Retention)，容易造成数据存储失效。
发明内容
鉴于上述问题，本公开提供了一种存储单元、三维存储器及其操作方法，以解决上述技术问题。
本公开的第一个方面提供了一种存储单元，包括：沟道层阵列，包括：N个沟道层，N个沟道层沿着第一方向垂直设置在衬底上，N个沟道层外侧依次设置隧穿层及存储层，N为正整数；N个导热芯，分别位于N个沟道层内，且贯穿衬底；热偶阵列，包括：沿着第一方向的负方向生长在衬底上的热偶字线层及位于热偶字线层上的N个热偶层，N个热偶层与N个导热芯一一对应连接；其中，在热偶字线层及N个热偶层中的部分热偶层之间施加第一电势差，对与该部分热偶层连接的导热芯进行加热处理，使与该导热芯对应的沟道层及存储层在隧穿层的隔热作用下分别保持第一预置温度及第二预置温度。
进一步地，存储单元配置为：在沟道层阵列中的部分沟道层与其对应的存储层的温度分别保持在第一预置温度及第二预置温度之后，对存储单元的栅极层施加写入电压，将漏极层及衬底均接地，写入电压用于驱使存储单元中的部分存储单元进行写入操作。
进一步地，第一电势差的加热时间与N个导热芯的导热性能呈负相关。
进一步地，N个导热芯均由钨、金、铜及碳化硅中的一种或多种构成。
进一步地，该存储单元还包括：沟道绝缘层，设置在沟道层与导热芯之间。
进一步地，沟道绝缘层用于隔离沟道层和导热芯，其由氧化硅或氧化铝构成。
进一步地，隧穿层由氧化硅或氮化硅构成。
进一步地，该存储单元还包括：在存储层外侧设置阻挡层。
本公开的第二个方面提供了一种三维存储器，包括：本公开第一个方面提供的存储单元。
本公开的第三个方面提供了一种基于本公开第二个方面提供的三维存储器的操作方法，包括：通过控制三维存储器中部分存储单元的衬底、漏极层、栅极层或热偶层的电压偏置，使三维存储器中的部分存储单元分别实现数据写入、读取及擦除操作。
进一步地，三维存储器中的部分存储单元实现数据写入操作，包括：在热偶字线层及N个热偶层中的部分热偶层之间施加第一电势差，对与该部分热偶层连接的导热芯进行加热处理，使与该导热芯对应的沟道层及存储层在隧穿层的隔热作用下分别保持第一预置温度及第二预置温度；将衬底及与沟道层对应的漏极层接地，对栅极层施加写入电压，写入电压用于驱使三维存储器中的部分存储单元进行写入操作。
进一步地，三维存储器中的部分存储单元实现数据读取操作，包括：触发数据读取程序；对三维存储器的漏极层施加偏置电压；将衬底接地；对未被选中的存储单元的栅极层施加导通电压，对被选中的存储单元的 栅极层施加读取电压；感测选中的存储单元的漏极层与衬底之间的电压，和/或电流变化以读取数据。
进一步地，三维存储器中的部分存储单元实现数据擦除操作，包括：触发数据擦除程序；将栅极层浮置或接地；对漏极层施加擦除电压，擦除电压足以使三维存储器发生隧穿效应，以使三维存储器中存储的电子被吸引至漏极层。
本公开相比现有技术至少具备以下有益效果：
(1)、本公开提供的存储单元，通过在沟道内部设置导热芯，每个导热芯末端连接热偶，热偶可以以串或串组为单元产生热脉冲以使对导热芯加热，达到在沟道层、存储层及阻挡层之间形成温度梯度的目的。该存储单元可以在保证良好的写入的情况下，同时达到良好的数据存储。
(2)、通过在热偶操作之前读取环境温度，根据环境温度调节热偶产生的脉冲数量，以达到较佳的数据写入环境。
(3)、本公开提供的三维存储器写入操作时间不超过3ms。
附图说明
为了更完整地理解本公开及其优势，现在将参考结合附图的以下描述，其中：
图1示意性示出了根据本公开一实施例的存储单元的剖面的部分结构示意图；
图2示意性示出了根据图1的存储单元的温度梯度示意图；
图3A～图3I示意性示出了根据本公开一实施例的存储单元的制备方法各步骤对应的结构示意图；
图4示意性示出了根据本公开一实施例的三维存储器的操作方法的数据读取的操作方法流程图；
图5示意性示出了根据本公开一实施例的三维存储器的操作方法的数据擦除的操作方法流程图；
图6示意性示出了根据本公开一实施例的三维存储器的操作方法的 数据写入的操作方法流程图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本公开实施例的全面理解。然而，明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
应该理解的是，当元件(诸如层、膜、区域、或衬底)描述为在另一元件“上”时，该元件可直接在该另一元件上，或者也可存在中间元件。而且，在说明书以及权利要求书中，当描述有元件“连接”至另一元件时，该元件可“直接连接”至该另一元件，或者通过第三元件“连接”至该另一元件。
在详述本公开实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且示意图只是示例，其在此不应限制本公开保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
本公开的实施例提供了一种存储单元，包括：沟道层阵列，包括：N个沟道层，N个沟道层沿着第一方向垂直设置在衬底上，N个沟道层外侧依次设置隧穿层及存储层，N为正整数；N个导热芯，分别位于N个沟道层内，且贯穿衬底；热偶阵列，包括：沿着第一方向的负方向生长在衬底上的热偶字线层及位于热偶字线层上的N个热偶层，N个热偶层与N个导热芯一一对应连接；其中，在热偶字线层及N个热偶层中的部分热偶层之间施加第一电势差，对与该部分热偶层连接的导热芯进行加热处理，以使与该导热芯对应的沟道层及存储层在隧穿层的隔热作用下分别保持第一预置温度及第二预置温度。
本公开的实施例提供的存储单元，通过在沟道内部设置导热芯，每 个导热芯末端连接热偶，热偶可以以串或串组为单元产生热脉冲以使对导热芯加热，达到在沟道层、存储层及阻挡层之间形成温度梯度的目的。在保证良好的写入的情况下，同时达到良好的数据存储。
下面将结合本公开一具体的实施例中的三维存储器的结构，对本公开的技术方案进行详细说明。应当理解，图1中示出的三维存储器的结构中各部分的材料层、形状和结构仅是示例性的，以帮助本领域的技术人员理解本公开的技术方案，并非用以限制本公开的保护范围。
在本公开的第一个示例性实施例中，提供了一种存储单元。
图1示意性示出了根据本公开一实施例的存储单元的剖面的部分结构示意图。
如图1所示，本公开实施例的存储单元结构，包括：
衬底10。
堆叠层20，沿着第一方向(z轴正方向)层叠于衬底10之上。
沟道层阵列，包括：N个沟道层30，N个沟道层30沿着第一方向垂直设置在衬底10上，N个沟道层30外侧依次设置隧穿层40及存储层50，其中，N为正整数。
N个导热芯80，分别位于N个沟道层30内，且贯穿衬底10。
热偶阵列，包括：沿着第一方向的负方向(z轴负方向)生长在衬底10上的热偶字线层901及位于热偶字线层上的N个热偶层902，N个热偶层902与N个导热芯80一一对应连接。
其中，在热偶字线层901及N个热偶层中的部分热偶层902之间施加第一电势差，对与该部分热偶层连接的导热芯80进行加热处理，使与该导热芯80对应的沟道层30及存储层50在隧穿层40的隔热作用下分别保持第一预置温度及第二预置温度。
本公开的实施例中，衬底10可以为导电类型衬底10，包括：第一导电类型衬底101及第二导电类型衬底102，第一导电类型衬底101，第二导电类型衬底102的材料例如为多晶硅，只是二者的导电类型相反。
具体地，第一导电类型为p型，第二导电类型为n型，对应第一导电类型衬底101为p型衬底，第二导电类型衬底102为n型导通层，p 型衬底用于提供擦除操作需要的空穴，由第一导电类型衬底101提供空穴泵入沟道层30中实现擦除操作；n型导通层提供读取操作需要的电子，由第二导电类型导通层102(n型导通层)提供电子泵入沟道层30中实现读取操作。
根据本公开的实施例，堆叠层20包括：多个堆层对，每个堆层对包括第一叠层材料201和第二叠层材料202，其中，第二叠层材料202和第一叠层材料201依次叠层在衬底10上。在一实例中，第二叠层材料202为绝缘体层，如OX等，第一叠层材料201为金属介电层，其为字线层，其中，堆叠层20中与衬底10最靠近的一层字线层为下选择层，与衬底10距离最远的一层字线层为上选择层。具体地，通过刻蚀法该堆叠层20上形成沟道孔阵列。
本公开的实施例中，在堆叠层20刻蚀形成沟道孔阵列中依次生长形成阻挡层60、存储层50、隧穿层40及沟道层30，并去除部分阻挡层60、存储层50、隧穿层40使得沟道层30部分暴露，如图1所示。其中，沟道层30与导热芯80之间设置沟道绝缘层70。
具体地，隧穿层40为隔热层，用于防止存储层50的温度随着导热芯80的温度升高而骤升，其材料可以为氧化硅或氮化硅等。沟道绝缘层70为薄电学绝缘层，用于隔离沟道层30和导热芯80，其构成材料可以为氧化硅或氧化铝等。
本公开的实施例中，热偶字线901为小尺寸的金属线，热偶字线901的线宽小于沟道孔的宽度，热偶字线901的线宽约为100nm。如图1所示，热偶字线901在y轴方向与字线层201同方向，在x轴方向每个热偶字线901只覆盖一个串。字线层201为大尺寸的金属线，在x轴方向覆盖多个串，例如9串、16串、19串、24串等，字线层201的线宽可以为1600nm或3200nm等。需说明的是，本实施例中，如图1所示，沟道孔的宽度为每个沟道孔内两侧阻挡层60的距离。
如图1所示，每个沟道层30内设置导热芯80，每个导热芯80贯穿衬底10及热偶字线层901至与热偶层902连接；其中，热偶层902与存储单元的热偶位线903一一对应连接，或与位线组中的位线904 (8-bit-line or 16-bit-line)一一对应。本公开的实施例中，导热芯80为温度的良导体，其材料可以为金属或半导体，如钨、金、铜、碳化硅等。
具体地，为使沟道层30及存储层50温度升温至预置温度，通过热偶层902对与之相连的导热芯80进行加热时间与导热芯80的导热性能呈负相关，即导热芯80的导热性能越强，该加热时间越短，例如，若导热芯80的材料为导热性能较好的铜、金，其加热时间为1ms～5ms，若为导热性能较差的材料构成，其加热时间6～10ms。需说明的是，为保证高速的存储器写入速率，优选加热时间为毫秒级，以使快速对导热芯80加热后进行写入操作。
根据本公开的实施例，在对存储单元进行写入操作前，通过对热偶字线层901及N个热偶层中的部分热偶层902之间施加第一电势差，对与该部分热偶层902连接的导热芯80进行加热处理，使与该导热芯对应的沟道层30及存储层50在隧穿层40的隔热作用下分别保持第一预置温度及第二预置温度。
其中，N个热偶层中的部分热偶层902的选择可以通过逻辑控制电路进行选择控制，可以在选择的串或串组连接的热偶层进行偏置电压操作，使热偶的温度升高至小于450℃。导热芯80将热偶温度传导至所选择的串或串组，提升沟道层及存储层的温度至预设温度。其中，根据环境温度的差异，偏置电压的热脉冲数量为变量，当环境温度较高时，其相对于环境温度较低时施加的热脉冲数量少，而当沟道层及存储层的温度提升至预置温度之后，热脉冲停止。
具体地，该第一电势差可以为8V～10V，加热时间为1～10ms，在该电压偏置及加热时间下可使得被加热的导热芯80温度速度提升至接近热偶层温度(小于450℃)，进而使得沟道层30的温度保持在第一预置温度t 1为65℃～90℃，存储层50的温度保持在第二预置温度t 2为30℃～40℃，阻挡层60的温度保持在自然环境温度t 3，如-25℃～30℃，如图2所示。通过在沟道层30、存储层50及阻挡层60之间形成一温度梯度，使得存储单元可以在保证良好的写入的情况下，同时达到良好的数据存储，有效避免了在较高温度进行写入操作时对存储层温度不利于数据存 储的问题。
本公开提供的一种存储单元，通过热偶阵列对选中的导热芯进行加热，在沟道层、存储层及阻挡层之间形成一温度梯度，使得存储单元在进行写入操作时处于恒定温度进行，而不受环境温度变化的干扰。另外，在保证该存储单元良好的写入温度的情况下，同时达到良好的数据存储温度。
需说明的是，图1仅为本公开提供的存储单元的局部剖视图，其并不代表本公开提供的存储单元的层数及沟道层阵列的数量的限定，本公开提供的存储单元的层数、沟道层阵列可以根据实际应用情况进行设定，本公开的实施例对此不做限定。
在本公开的第二个示例性实施例中，提供了一种存储单元的制备方法。
图3A～图3I示意性示出了根据本公开一实施例的存储单元的制备方法各步骤对应的结构示意图，该方法步骤制备出的存储单元的结构如图1所示。
如图3A～图3I所示，该存储单元的制备方法，包括：
步骤301，如图3A所示，在衬底11上方的第一低浓度导电类型延伸层12和堆叠层20中制作N个沟道孔，并在该N个沟道孔内侧和底部依次沉积阻挡层60、存储层50、隧穿层40及沟道层30。其中，N为正整数。
本实施例中，第一低浓度导电类型延伸层12(p-型硅延伸层12)和堆叠层20依次(沿着z轴正方向)沉积于衬底之上。该第一低浓度导电类型延伸层12例如为p型硅衬底，后续步骤中，可以通过利用利用p-型硅对p型硅高选择比进行湿法刻蚀后停止在p-型硅延伸层上。
步骤302，如图3B所示，依次去除衬底11和第一低浓度导电类型延伸层12，使得露出部分阻挡层60。
本实施例中，该存储单元作为三维存储器的一部分，该存储单元的正面需要与逻辑控制单元的正面进行相互贴合。
在存储晶元/逻辑控制单元粘贴后，存储单元背面(衬底一面)用化 学机械磨平方法削去大部分厚度衬底11后，利用p-型硅对p型硅(掺杂浓度差异)的高选择比进行湿法刻蚀后停止在p-型硅延伸层12上。该步骤S302中去除衬底的湿法腐蚀的操作可以仅实施于器件的衬底11一面，无需将器件全部置于腐蚀液中。
本实施例中，可以利用氧化硅对硅的高选择比通过湿法刻蚀的方式去除P-型硅延伸层12，露出部分阻挡层60。
步骤303，如图3C所示，去除部分高度的阻挡层60、存储层50、隧穿层40及堆叠层20使得沟道层30部分暴露。
步骤304，如图3D所示，沟道层30暴露的上表面(z轴负方向)沉积第二导电类型覆盖层，并去除沟道层30凸出部分对应覆盖的第二导电类型覆盖层，使得第二导电类型覆盖层处于同一个水平面并暴露该沟道层30的凸出部分。
本实施例中，通过在沟道层30暴露的上表面沉积第二导电类型覆盖层，第二导电类型覆盖层例如为n型硅，第二导电类型覆盖层为后续器件结构中对应的第二导电类型衬底102的前身，经过图案化工艺之后便得到第二导电类型衬底102。
如图3D所示，去除沟道层30凸出部分对应覆盖的第二导电类型覆盖层，使得第二导电类型覆盖层处于同一个水平面并暴露该沟道层30的凸出部分，并将第二导电类型覆盖层图案化形成第二导电类型衬底102。
步骤305，如图3E所示，在第二导电类型衬底102上沉积第一导电类型衬底101，其中，形成的第一导电类型衬底101不覆盖沟道层30凸出部分的上方。
步骤306，如图3F所示，在第一导电类型衬底101上依次沉积形成绝缘体层202及热偶字线层901，其中，绝缘体层202及热偶字线层901覆盖沟道层30凸出部分的上方，且不覆盖沟道层30内部空腔上方。
步骤307，如图3G所示，在每个沟道层30内部依次沉积形成沟道绝缘层70及导热芯80至与热偶字线层901处于同一个水平面齐平。
步骤308，如图3H所示，在沟道绝缘层70及导热芯80上方沉积 形成热偶层902及热偶字线903，并在热偶层902上沉积绝缘体层。
步骤309，如图3I所示，位线引出端成型、金属沉积并形成位线904，完成存储单元的制作。
图3I示意的图与图1所示意的结构图为上下倒置的，在图3I中，可以理解的，去除部分结构的工艺不局限于上述提及的湿法腐蚀以及光刻的工艺，可以是二者结合或者采用其他干法刻蚀或湿法刻蚀的工艺均可。
需要说明的是，上述各个步骤的实施例仅作为示例，示例了如何在现有的常规器件结构上制作本公开的存储单元的制作工艺，本公开中，任何能够形成上述存储单元的各部分结构以及相互位置关系的制作工艺均在本公开的保护范围之内。
在本公开的第三个示例性实施例中，提供了一种三维存储器，包含本公开提及的任一种存储单元。
本实施例中，该三维存储器还包含：逻辑控制单元，该存储单元与高逻辑控制单元的正面相互对接。其中，该三维存储器可以为三维NAND存储器。
本实施例中，可以通过逻辑控制单元实现对热偶层的选定，其可以同时对一个热偶层或多个热偶层进行选定，并对相应的导热芯进行加热处理，以使提升沟道层、存储层的温度至预置温度，实现良好的数据写入及存储的过程。
在本公开的第四个示例性实施例中，提供了一种如上述的三维存储器的操作方法，包括：通过控制三维存储器中部分存储单元的衬底、漏极层、栅极层或热偶层的电压偏置，使三维存储器中的部分存储单元分别实现数据写入、读取及擦除操作。
该操作方法包括数据读取的操作方法、数据擦除的操作方法及数据写入的操作方法，其中，数据读取的操作方法、数据擦除的操作方法及数据写入的操作方法之间并无固定先后执行顺序。
如图4所示，该数据读取的操作方法包括以下步骤：
步骤S401，触发数据读取程序。
步骤S402，对漏极层施加偏置电压；将衬底接地；对未被选中的存储单元的栅极层施加导通电压；对被选中的存储单元的栅极层施加读取电压。
步骤S403，感测选中的存储单元的漏极层与衬底之间的电压，和/或电流变化以读取数据。
本实施例中，在对存储器进行数据读取操作时，漏极层施加偏置电压，衬底接地，使得在进行读取操作时，能够通过感测漏极层与衬底之间的电流变化来判断三维存储器所存储的数据状态。偏置电压的范围为1V～1.4V，优选可以为1.2V。在上述条件下，若沟道层导通，则导通电流与存储单元的阈值电压(VT)成反比，对于三维存储器而言，沟道层导通是因为在栅极施加了大于存储单元VT的电压。
对于没有被选中的存储单元，在读取操作时，栅极层施加导通电压，以使得沟道层导通，电流能够从漏极层流向衬底。导通电压是一个能够保证大于任何一个存储单元VT的电压，但导通电压不能太大，否则会使三维存储器发生隧穿效应。导通电压的范围可以在2V～8V之间。
对于被选中的存储单元，在读取操作时，栅极层施加读取电压，若读取电压大于存储单元的VT，则能够使沟道层导通。通过尝试对栅极层施加不同的读取电压，就可以知道存储单元所存储的电荷量，也就知道其所存储的数据。
如图5所示，该数据擦除的操作方法包括以下步骤：
步骤S501，触发数据擦除程序。
步骤S502，将栅极层浮置或接地；对衬底施加擦除电压；对漏极层施加擦除电压。
在对三维存储器进行数据擦除操作时，栅极层浮置或接地，半导体区施加擦除电压，漏极层施加擦除电压。由于漏极层处于高电位，能够吸引电荷捕获层中捕获的电子，而擦除电压足以使三维存储器发生隧穿效应，以使电子成功被漏极吸引，进而释放了电荷捕获层上的电子，半导体区与漏极层保持相同电位，以防止电子从漏极层流向半导体区。擦除电压的范围为14V～20V，优选可以为14V。
通过上述擦除方式，无需施加高电压，即可利用漏极层来进行数据，实现顶部擦除，提高了三维存储器擦除操作的效率。
如图6所示，该数据写入的操作方法包括以下步骤：
步骤S601，在热偶字线层及N个热偶层中的部分热偶层之间施加第一电势差，对与该部分热偶层连接的导热芯进行加热处理，使该导热芯对应的沟道层及存储层在隧穿层的隔热作用下分别保持第一预置温度及第二预置温度。
步骤S602，触发数据写入程序。
步骤S603，将衬底及与沟道层对应的漏极层接地，对栅极层施加写入电压。
本实施例中，在对存储器进行数据写入之前，首先通过对热偶字线层901及N个热偶层中的部分热偶层902之间施加第一电势差，对与该部分热偶层902连接的导热芯80进行加热处理，以使与该导热芯对应的沟道层30及存储层50在隧穿层40的隔热作用下分别保持第一预置温度及第二预置温度之后，再触发数据写入程序。该第一电势差可以为8V～10V，可以在毫秒级别将沟道层30及存储层50的温度分别提升至预置温度。
在对三维存储器进行数据写入操作时，漏极层接地，衬底接地，栅极层施加写入电压。由于栅极层处于高电位，能够吸引电子靠近，而写入电压足以使三维存储器发生隧穿效应，以使电子在靠近栅极层的过程中被电荷捕获层捕获。写入电压的范围为不高于25V，并且不同的编程电压决定了写入电荷捕获层中的电子数量，从而使用不同的编程电压能够实现三维存储器存储单元的不同数据状态。在上述实施例中，电子被吸引到栅极层，因此电流从栅极层流向衬底。
在本实施例中，操作方法并不仅限于该些步骤，省略说明的其他步骤均可根据实际情况来进行相应的调整。
本实施例提供的三维存储器的操作方法，无需施加高电压，即可利用漏极层来进行数据清除，同时方便进行数据读取及数据写入，从而较好地防止对器件造成损坏，提高了三维存储器的使用寿命。在保证该存 储单元良好的写入温度的情况下，同时达到良好的数据存储温度。
需说明的是，本公开的实施例中采取的制备工艺方法并不仅限于上述实施例所示，其可以为现有技术中成熟的其他工艺方法替换，其并不构成本公开实施例的限定。
从以上的描述中，可以看出，本公开上述的实施例至少实现了以下技术效果：
1)、本公开提供的存储单元，通过在沟道内部设置导热芯，每个导热芯末端连接热偶，热偶可以以串或串组为单元产生热脉冲以使对导热芯加热，达到在沟道层、存储层及阻挡层之间形成温度梯度的目的。该存储单元可以在保证良好的写入的情况下，同时达到良好的数据存储。
2)、通过在热偶操作之前读取环境温度，根据环境温度调节热偶产生的脉冲数量，以达到较佳的数据写入环境。
3)、本公开提供的三维存储器写入操作时间不超过3ms。尽管已经在附图和前面的描述中详细地图示和描述了本公开，但是这样的图示和描述应认为是说明性的或示例性的而非限制性的。
本领域技术人员可以理解，本公开的各个实施例和/或权利要求中记载的特征可以进行多种范围组合和/或结合，即使这样的组合或结合没有明确记载于本公开中。特别地，在不脱离本公开精神和教导的情况下，本公开的各个实施例和/或权利要求中记载的特征可以进行多种组合和/或结合。所有这些组合和/或结合均落入本公开的范围。
尽管已经参照本公开的特定示例性实施例示出并描述了本公开，但是本领域技术人员应该理解，在不背离所附权利要求及其等同物限定的本公开的精神和范围的情况下，可以对本公开进行形式和细节上的多种改变。因此，本公开的范围不应该限于上述实施例，而是应该不仅由所附权利要求来进行确定，还由所附权利要求的等同物来进行限定。

Claims (13)

  1. 一种存储单元，其特征在于，包括：
    沟道层阵列，包括：N个沟道层，所述N个沟道层沿着第一方向垂直设置在衬底上，所述N个沟道层外侧依次设置隧穿层及存储层，N为正整数；
    N个导热芯，分别位于所述N个沟道层内，且贯穿所述衬底；
    热偶阵列，包括：沿着第一方向的负方向生长在所述衬底上的热偶字线层及位于所述热偶字线层上的N个热偶层，所述N个热偶层与所述N个导热芯一一对应连接；
    其中，在所述热偶字线层及所述N个热偶层中的部分所述热偶层之间施加第一电势差，对与该部分所述热偶层连接的所述导热芯进行加热处理，使与该导热芯对应的所述沟道层及所述存储层在所述隧穿层的隔热作用下分别保持第一预置温度及第二预置温度。
  2. 根据权利要求1所述的存储单元，其特征在于，所述存储单元配置为：在所述沟道层阵列中的部分所述沟道层与其对应的所述存储层的温度分别保持在所述第一预置温度及所述第二预置温度之后，对所述存储单元的栅极层施加写入电压，将漏极层及衬底均接地，所述写入电压用于驱使所述存储单元中的部分存储单元进行写入操作。
  3. 根据权利要求1所述的存储单元，其特征在于，所述第一电势差的加热时间与所述N个导热芯的导热性能呈负相关。
  4. 根据权利要求1所述的存储单元，其特征在于，所述N个导热芯均由钨、金、铜及碳化硅中的一种或多种构成。
  5. 根据权利要求1所述的存储单元，其特征在于，还包括：
    沟道绝缘层，设置在所述沟道层与所述导热芯之间。
  6. 根据权利要求5所述的存储单元，其特征在于，所述沟道绝缘层用于隔离所述沟道层和所述导热芯，其由氧化硅或氧化铝构成。
  7. 根据权利要求1所述的存储单元，其特征在于，所述隧穿层由氧化硅或氮化硅构成。
  8. 根据权利要求1所述的存储单元，其特征在于，还包括：在所述存储层外侧设置阻挡层。
  9. 一种三维存储器，其特征在于，包括：
    如权利要求1～8中任意一项所述的存储单元。
  10. 一种如权利要求9所述的三维存储器的操作方法，其特征在于，包括：
    通过控制所述三维存储器中部分存储单元的衬底、漏极层、栅极层或所述热偶层的电压偏置，使所述三维存储器中的部分存储单元分别实现数据写入、读取及擦除操作。
  11. 根据权利要求10所述的操作方法，其特征在于，所述三维存储器中的部分存储单元实现数据写入操作，包括：
    在所述热偶字线层及所述N个热偶层中的部分所述热偶层之间施加第一电势差，对与该部分所述热偶层连接的所述导热芯进行加热处理，使与该导热芯对应的所述沟道层及所述存储层在所述隧穿层的隔热作用下分别保持第一预置温度及第二预置温度；
    触发数据写入程序；
    将所述衬底及与所述沟道层对应的漏极层接地，对所述栅极层施加写入电压，所述写入电压用于驱使所述三维存储器中的部分存储单元进行写入操作。
  12. 根据权利要求10所述的操作方法，所述三维存储器中的部分存储单元实现数据读取操作，包括：
    触发数据读取程序；
    对所述三维存储器的漏极层施加偏置电压；
    将所述衬底接地；
    对未被选中的存储单元的栅极层施加导通电压，对被选中的存储单元的栅极层施加读取电压；
    感测选中的存储单元的漏极层与衬底之间的电压，和/或电流变化以读取数据。
  13. 根据权利要求10所述的操作方法，所述三维存储器中的部分存储单元实现数据擦除操作，包括：
    触发数据擦除程序；
    将所述栅极层浮置或接地；
    对所述漏极层施加擦除电压，所述擦除电压足以使所述三维存储器发生隧穿效应，以使所述三维存储器中存储的电子被吸引至所述漏极层。
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