WO2023060692A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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WO2023060692A1
WO2023060692A1 PCT/CN2021/131719 CN2021131719W WO2023060692A1 WO 2023060692 A1 WO2023060692 A1 WO 2023060692A1 CN 2021131719 W CN2021131719 W CN 2021131719W WO 2023060692 A1 WO2023060692 A1 WO 2023060692A1
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semiconductor
layer
doped
conductive layer
gate conductive
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PCT/CN2021/131719
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to US17/805,510 priority Critical patent/US20230124494A1/en
Publication of WO2023060692A1 publication Critical patent/WO2023060692A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to but not limited to a method for fabricating a semiconductor structure and the semiconductor structure.
  • RCAT Recess Channel Access Transistor
  • the recessed channel array transistor is prone to gate-induced drain leakage (Gate-Induce Drain Leakage, GIDL for short), which affects the reliability of the dynamic random access memory.
  • the disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure.
  • a first aspect of the present disclosure provides a method for fabricating a semiconductor structure, the method for fabricating the semiconductor structure comprising:
  • the semiconductor doped layer fills the channel, and covers the gate conductive layer, the doping concentration of the semiconductor doped layer near the top surface of the gate conductive layer is The doping concentration is different from that of the semiconductor doped layer on the side away from the top surface of the gate conductive layer.
  • forming the semiconductor doped layer includes:
  • the first semiconductor doped layer covers the top surface of the gate conductive layer, the top surface of the first semiconductor doped layer is lower than the top surface of the substrate;
  • the doping concentration of the second doped semiconductor layer is different from that of the first doped semiconductor layer.
  • the conductivity type of the second doped semiconductor layer is the same as that of the first doped semiconductor layer.
  • the forming the first semiconductor doped layer includes:
  • the doping concentrations of the second doped region and the first doped region are different.
  • the forming the second semiconductor doped layer includes:
  • the doping concentrations of the fourth doped region and the third doped region are different.
  • the doping concentration of the second doped semiconductor layer is greater than the doping concentration of the first doped semiconductor layer.
  • the forming the gate conductive layer includes:
  • Etching back the initial gate conductive layer leaving the initial gate conductive layer with a height not less than one-third of the channel depth to form the gate conductive layer.
  • a second aspect of the present disclosure provides a semiconductor structure comprising:
  • a substrate comprising a channel
  • the semiconductor doped layer fills the channel and covers the gate conductive layer, the doping concentration of the semiconductor doped layer on the side close to the top surface of the gate conductive layer and A side of the semiconductor doped layer away from the top surface of the gate conductive layer has a different doping concentration.
  • the gate conductive layer in a direction perpendicular to the substrate, there is a first height between the bottom of the gate conductive layer and the top of the semiconductor doped layer, and the gate conductive layer has a first height. Two heights, the second height is not less than one-third of the first height.
  • the semiconductor doped layer includes:
  • the first semiconductor doped layer covers the top surface of the gate conductive layer, and the top surface of the first semiconductor doped layer is lower than the top surface of the substrate;
  • the doping concentration of the second doped semiconductor layer is different from that of the first doped semiconductor layer.
  • the first doped semiconductor layer includes a first dopant
  • the second doped semiconductor layer includes a second dopant
  • the first dopant and the The conductivity type of the second dopant is the same.
  • the doping concentration of the first dopant in the first semiconductor doped layer changes gradually in a direction perpendicular to the substrate.
  • the doping concentration of the second dopant in the second semiconductor doped layer changes gradually in a direction perpendicular to the substrate.
  • the first doped semiconductor layer in a direction perpendicular to the substrate, has a third height, and the third height is not greater than one-third of the first height, so
  • the second semiconductor-doped layer has a fourth height, and the fourth height is not greater than one-third of the first height.
  • the doping concentration of the first doped semiconductor layer is lower than the doping concentration of the second doped semiconductor layer.
  • the work function of the gate conductive layer and the channel of the semiconductor structure are quite different, and the work function of the semiconductor doped material in the semiconductor doped layer and the channel The difference is small, the threshold voltage of the semiconductor structure near the bottom of the channel is higher, and the threshold voltage near the top surface of the substrate is smaller, which can avoid gate-induced drain leakage.
  • Fig. 1 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 2 is a flow chart of forming a semiconductor doped layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 3 is a flowchart showing a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 4 is a schematic diagram of a substrate provided in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 5 is a schematic diagram of forming an initial gate conductive layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 6 is a schematic diagram of forming a gate conductive layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.
  • Fig. 7 is a schematic diagram of forming a semiconductor structure in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 8 is a schematic diagram of forming a first semiconductor doped layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 9 is a schematic diagram of forming a second semiconductor doped layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 10 is a schematic diagram of forming a first semiconductor doped layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 11 is a schematic diagram of a semiconductor structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 12 is a top view of a substrate provided in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 13 is a schematic cross-sectional view along plane A-A of Fig. 12 .
  • Fig. 14 is a schematic cross-sectional view along the B-B plane of Fig. 12 .
  • Fig. 15 is a schematic cross-sectional view of A-A plane for forming a gate conductive layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 16 is a schematic cross-sectional view of a B-B plane for forming a gate conductive layer in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 17 is a schematic cross-sectional view of plane A-A of a semiconductor structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 18 is a schematic cross-sectional view of a B-B plane of a semiconductor structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 19 is a schematic cross-sectional view of plane A-A of a semiconductor structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • Fig. 20 is a schematic cross-sectional view of a B-B plane of a semiconductor structure formed in a method for fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 1 shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 4 - FIG. 11 is a schematic diagram of various stages of the manufacturing method of the semiconductor structure. The manufacturing method of the semiconductor structure will be introduced below in conjunction with FIGS. 4-11 .
  • This embodiment does not limit the semiconductor structure.
  • the following will introduce the semiconductor structure as a recessed channel transistor (hereinafter referred to as a transistor) as an example, but this embodiment is not limited thereto.
  • the semiconductor structure in this embodiment can also be other structures. It should be understood that the semiconductor structure formed in this embodiment does not constitute a complete transistor, and this embodiment is only a process of forming the gate electrode of the transistor.
  • a method for fabricating a semiconductor structure includes the following steps:
  • the substrate 100 includes an active region 110 , and the active region 110 may be a P-type active region or an N-type active region.
  • the material of the active region 110 includes a semiconductor material.
  • the material of the active region 110 may include one or more of silicon, germanium, a silicon-germanium compound, and a silicon-carbon compound.
  • a channel 131 is formed in the active region 110 , and in this embodiment, the formed channel 131 is a gate channel.
  • the substrate 100 further includes a gate oxide layer 200 , and the channel 131 is surrounded by the gate oxide layer 200 ′.
  • the material of the gate oxide layer 200 is silicon oxide, for example, the material of the gate oxide layer 200 is silicon dioxide.
  • providing the substrate 100 includes: providing an initial substrate, etching the initial substrate to form a gate trench, forming a gate oxide layer 200 in the gate trench, and the gate oxide layer 200 covers the inner surface of the gate trench, The gate oxide layer 200 encloses the channel 131 in the gate trench.
  • the gate conductive layer 310 is located at the bottom of the channel 131 to fill part of the channel 131 and cover part of the gate oxide layer 200 .
  • the material of the gate conductive layer 310 may include metal nitride, such as titanium nitride or indium nitride. In this embodiment, the material of the gate conductive layer 310 includes titanium nitride.
  • forming the gate conductive layer 310 includes:
  • the gate conductive material can be deposited by atomic layer deposition (Atomic layer deposition, referred to as ALD), chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD), and the gate conductive material fills the trench 131 and covers the substrate On the top surface of 100, an initial gate conductive layer 301 is formed.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • a portion of the initial gate conductive layer 301 is removed by etching back to form a gate conductive layer 310 .
  • the height of the formed gate conductive layer 310 is greater than one third of the depth of the channel 131 .
  • S30 forming a semiconductor doped layer, the semiconductor doped layer fills the channel, and covers the gate conductive layer, the doping concentration of the semiconductor doped layer close to the top surface of the gate conductive layer and the semiconductor doped layer away from the gate The doping concentration is different on one side of the top surface of the conductive layer.
  • the semiconductor doped layer 320 can be formed by in-situ doping of the semiconductor material by a low pressure chemical vapor deposition process (Low Pressure Chemical Vapor Deposition, LPCVD), or the semiconductor material can be formed by depositing an undoped semiconductor material to fill the channel 131. layer, and then doping impurities are implanted into the semiconductor material layer through a thermal diffusion process or an ion implantation process to form a semiconductor doped layer 320 .
  • LPCVD Low Pressure Chemical Vapor Deposition
  • the threshold voltage (Threshold Voltage, TV) of the transistor is determined by the difference between the work function (Work function, WF) of the gate electrode and the gate channel.
  • the gate electrode includes a gate conductive layer arranged at the bottom of the gate channel and a semiconductor doped layer covering the top surface of the gate conductive layer, and the work function of the metal nitride in the gate conductive layer.
  • the difference between the work function of the gate channel and the gate channel is relatively large, and the difference between the work function of the semiconductor doped layer and the material forming the active region of the gate channel is small, that is, the threshold value of the gate electrode near the bottom of the gate channel
  • the voltage is large, and the threshold voltage near the top surface of the substrate is small.
  • the threshold voltage of the gate electrode near the bottom of the gate channel is relatively high, which can reduce the occurrence of charge leakage from the transistor to the adjacent transistor.
  • the threshold voltage of the gate electrode near the top surface of the substrate is small, and the gate-drain of the transistor The voltage at the overlapping interface is small, and the gate-induced drain leakage at the gate-drain overlapping interface of the transistor is avoided.
  • this embodiment is a further description of step S40 in the above embodiment.
  • forming a semiconductor doped layer includes:
  • S31 forming a first semiconductor doped layer, the first semiconductor doped layer covers the top surface of the gate conductive layer, and the top surface of the first semiconductor doped layer is lower than the top surface of the substrate.
  • the process of forming the first semiconductor doped layer 321 includes depositing the first semiconductor material to fill the trench 131, and etching back the first semiconductor material located in the trench 131. Etch back to be lower than the top surface of the substrate 100 , and implant dopants into the retained first semiconductor material by an ion implantation process to form a first semiconductor doped layer 321 .
  • forming the first semiconductor doped layer includes:
  • S31a depositing a first semiconductor material, and performing first doping on the first semiconductor material to form a first doped region, where the first doped region covers the top surface of the gate conductive layer.
  • the first doping of the undoped first semiconductor material may be performed by ion implantation.
  • S31b Doping the first semiconductor material a second time to form a second doped region, where the second doped region covers the top surface of the first doped region.
  • the doping concentrations of the second doped region 3212 and the first doped region 3211 are different.
  • the second doping can be performed on the first semiconductor material after the first doping by ion implantation, and the implantation depth of the second doping is smaller than the implantation depth of the first doping.
  • the region below the implantation depth of the second doping in the formed first semiconductor doped layer 321 is the first doped region 3211, and the region within the implantation depth of the second doping is the second doping region 3211.
  • the doping concentration of the second doping region 3212 is greater than that of the first doping region 3211 .
  • the first semiconductor material when depositing the first semiconductor material, may be doped only once. Doping the first semiconductor material while depositing the first semiconductor material, and the doping concentration gradually changes, the formed first semiconductor doped layer 321, along the direction perpendicular to the substrate 100, the concentration of the first semiconductor doped layer 321 gradually changes .
  • the doping concentration of the second semiconductor doped layer is different from that of the first semiconductor doped layer.
  • the doping concentration of the second semiconductor doped layer 322 can be greater than or less than the doping concentration of the first semiconductor doped layer 321, in this embodiment, the doping concentration of the second semiconductor doped layer 322 is greater than that of the first semiconductor doped layer 321 The doping concentration of the doped layer 321 .
  • the operation of forming the second semiconductor doped layer 322 includes: placing the semiconductor structure in the reaction chamber, supplying the reaction source gas, doping gas and carrier gas into the reaction chamber, using low pressure
  • the semiconductor doping material is deposited by chemical vapor phase, and the semiconductor doping material fills the trench 131 to form the second semiconductor doping layer 322 .
  • the second doped semiconductor layer 322 may include a semiconductor material containing silicon or germanium.
  • silicon source gas or germanium source gas can be used as the reaction source gas, one of phosphine (Phosphine, PH 3 ) or arsine (Hydrogen Arsenide, AsH 3 ) Or more than two kinds of dopant gas, with hydrogen (Hydrogen, H 2 ) as carrier gas, low-pressure chemical vapor deposition process deposits N-type doped semiconductor material, N-type doped semiconductor material fills the channel 131 to form the second semiconductor Doped layer 322 .
  • forming the second semiconductor doped layer includes:
  • S32a depositing a second semiconductor material, and performing first doping on the second semiconductor material to form a third doped region, where the third doped region covers the top surface of the first semiconductor doped layer.
  • S32b Doping the second semiconductor material a second time to form a fourth doped region, where the fourth doped region covers the top surface of the third doped region.
  • the doping concentrations of the fourth doped region and the third doped region are different.
  • the third doped region 3221 and the fourth doped region 3222 form the second semiconductor doped layer 322 .
  • the conductivity type of the second doped semiconductor layer 322 is the same as that of the first doped semiconductor layer 321.
  • the conductivity type of the first semiconductor doped layer 321 is N-type doped, and the conductivity type of the second semiconductor doped layer 322 is also N-type doped.
  • the conductivity type of the first semiconductor doped layer 321 is P-type doped, and the conductivity type of the second semiconductor doped layer 322 is also P-type doped.
  • the conductivity types of the first semiconductor doped layer 321 and the second semiconductor doped layer 322 are set according to the active region 110 . If the active region is a P-type active region, the conductivity type of the first semiconductor doped layer 321 and the second semiconductor doped layer 322 is set to be N-type doped.
  • the active region 110 is an N-type active region, and the conductivity type of the first semiconductor doped layer 321 and the second semiconductor doped layer 322 is set to be P-type doped.
  • the work function of semiconductor materials can be changed by doping ions.
  • the work function of semiconductor materials is equal to the difference between the vacuum energy level and Fermi energy level of semiconductor materials.
  • the Fermi energy level of semiconductor materials is related to the carrier density in semiconductor materials.
  • the carrier density in semiconductor materials is affected by doping impurities and doping concentration. Therefore, in this embodiment, the doping concentrations of the first doped semiconductor layer and the doped semiconductor layer are different, and the work functions of the doped semiconductor layer and the second doped semiconductor layer are different.
  • FIG. 3 shows a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIG. 12 - FIG. 20 is a schematic diagram of various stages of the manufacturing method of the semiconductor structure, and the manufacturing method of the semiconductor structure will be introduced below in conjunction with FIGS. 12-20 .
  • This embodiment does not limit the semiconductor structure.
  • the following will introduce the semiconductor structure as an example of a DRAM, but this embodiment is not limited thereto.
  • the semiconductor structure in this embodiment may also be other structures.
  • a method for fabricating a semiconductor structure includes the following steps:
  • Step S100 providing a substrate in which word line channels are formed.
  • FIG. 12 shows a top view of the substrate 500
  • FIG. 13 is a schematic cross-sectional view of the substrate in FIG. 12 along the direction A-A
  • FIG. 14 is a schematic cross-sectional view of the substrate in FIG. 12 along the direction B-B.
  • the A-A direction is the extending direction of the word line channel
  • the B-B direction is the extending direction of the active region.
  • the substrate 500 includes an active region 510 and a shallow trench isolation region 520 .
  • the multiple active regions 510 in the substrate 500 are independently arranged, and the shallow trench isolation region 520 separates the multiple active regions 510 .
  • the active region 510 can be a P-type active region or an N-type active region, and the material of the active region 510 includes a semiconductor material.
  • the material of the active region 510 includes a P-type doped semiconductor material.
  • the material of the shallow trench isolation region 520 may include silicon oxide.
  • a plurality of parallel word line channels 530 are formed in the substrate 500.
  • the word line channels 530 pass through the substrate 500 to expose part of the active region 510 and part of the shallow trench isolation region 520. Both ends of each active region 510 intersect with a word line channel 530 respectively.
  • the word line channel 530 includes a gate channel 531 passing through the active region 510 and a conductive channel 532 passing through the shallow trench isolation region 520 .
  • Step S200 forming a gate conductive layer, the gate conductive layer covers part of the word line channel.
  • step S200 The method for forming the gate conductive layer 710 in step S200 in this embodiment is the same as the implementation of step S20 in the above embodiment.
  • atomic layer deposition (Atomic layer deposition, referred to as ALD), chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) can be used to deposit the gate conductive material, and the gate conductive material fills part of the word
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the line channel 530 forms a gate conductive layer 710 at the bottom of the word line channel 530 .
  • the material of the gate conductive layer 710 may include metal nitride.
  • the material of the gate conductive layer 710 may include one or more of titanium nitride and indium nitride.
  • the material of the gate conductive layer 710 includes titanium nitride.
  • Step S300 forming a semiconductor doped layer, the semiconductor doped layer fills the word line channel, and covers the gate conductive layer, the doping concentration of the semiconductor doped layer on the side close to the top surface of the gate conductive layer and the semiconductor doped layer The doping concentration is different on the side away from the top surface of the gate conductive layer.
  • step S300 The method for forming the semiconductor doped layer 720 in step S300 is the same as the implementation of step S30 in the above embodiment.
  • a doped semiconductor material can be deposited to form a semiconductor doped layer 720, or an undoped semiconductor material can be deposited to fill the word line trench 530 to form a semiconductor material layer, and then pass A thermal diffusion process or an ion implantation process injects doping impurities into the semiconductor material layer to form the semiconductor doped layer 720 .
  • the structure of the semiconductor doped layer 720 formed in step S300 is the same as that of the semiconductor doped layer 320 formed in step S60 of the above-mentioned embodiment.
  • the semiconductor doped layer 720 may include a first semiconductor doped layer 721 and a second semiconductor doped layer 722, the first semiconductor doped layer 721 covers the top surface of the gate conductive layer 710, and the second semiconductor doped layer 722 covers the top surface of the gate conductive layer 710.
  • the doping concentration of the second semiconductor doped layer 722 is greater than the doping concentration of the first semiconductor doped layer 721 .
  • the conductivity type of the first semiconductor doped layer 721 is the same as that of the second semiconductor doped layer 722.
  • the first doped semiconductor layer 721 includes a first doped region 7211 and a doped semiconductor layer arranged in sequence.
  • the doping concentrations of the second doped region 7212, the first doped region 7211 and the second doped region 7212 are different.
  • the second doped semiconductor layer 722 includes a third doped region 7221 and a third doped region 7221 arranged in sequence.
  • the doping concentrations of the fourth doped region 7222, the third doped region 7221 and the fourth doped region 7222' are different.
  • the semiconductor doped layer 720 and the gate conductive layer 710 together form a word line structure 700 .
  • the word line structure 700 formed in this embodiment includes a first gate 700 a passing through the active region 510 and a second gate 700 b passing through the shallow trench isolation region 520 .
  • the first gate 700a and the second gate 700b in the word line structure 700 are connected.
  • the first gate 700 a is disposed in the gate channel 531
  • the second gate 700 b is disposed in the conductive channel 532 .
  • the first gate 700a includes a gate conductive layer 710a and a semiconductor doped layer 720a arranged in sequence, as shown in FIG. 15, FIG. 17,
  • the second gate 700b includes a gate conductive layer 710b and a semiconductor doped layer 720b arranged in sequence.
  • the first gate 700 a can be used as a gate electrode (also referred to as a gate or a control gate) of a transistor, and is used to control the turn-on and turn-off of the transistor.
  • the first gate 700a serves as the gate electrode of the recessed channel transistor.
  • the second gate 700b is disposed in the shallow trench isolation region 520 and adjacent to the active region 510 for connecting the first gate 700a in different active regions 510 to form a recessed channel array transistor.
  • the semiconductor structure formed in this embodiment can form a recessed channel array transistor, and the first gate serves as a gate electrode of the transistor and includes a gate conductive layer and a semiconductor doped layer.
  • the difference between the work function of the metal nitride in the gate conductive layer and the work function of the gate channel is relatively large, and the difference between the work function of the doped semiconductor material in the semiconductor doped layer and the work function of the gate channel is relatively small.
  • the conductive layer of the gate electrode of the transistor produces a high threshold voltage in the bottom region of the gate channel, and the semiconductor-doped layer produces a low threshold voltage above the gate electrode.
  • the transistor is refreshed and read many times, the gate electrode of the transistor is continuously turned on and off, and capacitive coupling interference may occur between adjacent transistors.
  • the recessed channel array transistor can change the trajectory of electrons through the changing electric field formed in the gate channel, so that the leaked electrons flow into the conductive layer of the first gate, reducing the hammer effect influence, improving the reliability of the device.
  • this embodiment is a further description of step S100 in the above embodiment.
  • providing a substrate includes: providing a semiconductor substrate, the semiconductor substrate is a P-type substrate, and the material of the semiconductor substrate includes a semiconductor material.
  • the material of the semiconductor substrate It may include one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.
  • a mask pattern is formed on the top surface of the semiconductor substrate, and part of the semiconductor substrate is removed according to the mask pattern to form a shallow trench, and the shallow trench separates the remaining part of the semiconductor substrate into independently provided active regions 510 .
  • the shallow trench isolation region 520 is formed by depositing a low-k dielectric material to fill the shallow trench.
  • the low-k dielectric material is silicon oxide.
  • a hard mask is formed, the hard mask covers the top surface of the active region 510 and the shallow trench isolation region 520, and the hard mask is patterned by self-aligned double patterning (SADP) to form a word line pattern, A part of the active region 510 and a part of the shallow trench isolation region 520 are removed by a dry etching process or a wet etching process according to the word line pattern to form a word line trench.
  • SADP self-aligned double patterning
  • the etching process when removing part of the active region 510 and part of the shallow trench isolation region 520, by controlling the etching selectivity of the etching process for the active region 510 and the shallow trench isolation region 520, the etching process removes The speed of the shallow trench isolation region 520 is greater than the removal speed of the active region 510 , and the depth of the word line trench formed in the shallow trench isolation region 520 is greater than that in the active region 510 .
  • the cross section of the word line groove is a concave-convex shape with ups and downs.
  • a gate oxide layer is formed, and the gate oxide layer covers the word line trenches.
  • the gate oxide layer material can be deposited by atomic layer deposition (Atomic layer deposition, ALD) or chemical vapor deposition (Chemical Vapor Deposition, CVD) to form a gate oxide layer 600, and the gate oxide layer 600 covers the word line
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the trench encloses a wordline channel 530 in the wordline trench.
  • the material of the gate oxide layer 600 is silicon oxide, and in this embodiment, the material of the gate oxide layer 600 is silicon dioxide.
  • the height of the second gate is greater than the height of the first gate, and the second gate is arranged between two adjacent first gates to isolate adjacent the first grid.
  • this embodiment provides a semiconductor structure, as shown in FIG. 7, referring to FIG. 4, including: a substrate 100, a channel 131 disposed in the substrate 100, and a gate conductive layer 310 and a semiconductor doped layer 320 .
  • the gate conductive layer 310 is disposed in the channel 131 and covers part of the channel 131
  • the semiconductor doped layer 320 covers the top surface of the gate conductive layer 310 and fills the remaining part of the channel 131 not filled by the gate conductive layer 310 .
  • the height of the gate conductive layer 310 is greater than one third of the channel depth.
  • the semiconductor structure further includes a gate oxide layer 200 disposed between the gate conductive layer 310 and the channel 131 and between the semiconductor doped layer 320 and the channel 131 .
  • the doping concentration of the semiconductor doped layer 320 on the side close to the top surface of the gate conductive layer 310 is different from the doping concentration of the semiconductor doped layer 320 on the side far from the top surface of the gate conductive layer 310 .
  • the gate conductive layer 310 forms a high threshold voltage at the bottom of the channel 131
  • the semiconductor doped layer 320 forms a low threshold voltage corresponding to the channel 131 above the gate conductive layer 310.
  • the part of the channel 131 covered by the layer 310 is used as the main channel, and the threshold voltage between the main channel and the top surface of the substrate 100 is used. Therefore, the voltage at the gate-drain overlap interface of the transistor formed with the semiconductor structure of this embodiment is small, and the gate-induced drain leakage at the gate-drain overlap interface of the transistor can be avoided.
  • most of the content of the semiconductor structure of this embodiment is the same as the above embodiment, the difference between this embodiment and the above embodiment is that in the direction perpendicular to the substrate 100, the gate conducts There is a first height between the bottom of the layer 310 and the top of the semiconductor doped layer 320 , the gate conductive layer 310 has a second height, and the second height is not less than one-third of the first height.
  • the semiconductor doped layer 320 includes : the first doped semiconductor layer 321 covering the top surface of the gate conductive layer 310 , the top surface of the first doped semiconductor layer 321 is lower than the top surface of the substrate 100 .
  • the semiconductor doped layer 320 also includes a second semiconductor doped layer 322 covering the top surface of the first semiconductor doped layer 321, the doping concentration of the second semiconductor doped layer 322 and the doping concentration of the first semiconductor doped layer 321 different.
  • the doping concentration of the first doped semiconductor layer 321 is lower than that of the second doped semiconductor layer 322 .
  • the first doped semiconductor layer 321 has a third height
  • the third height is not greater than one-third of the first height
  • the second doped semiconductor layer 322 has a third height.
  • the fourth height is not greater than one-third of the first height.
  • the gate conductive layer 310, the first semiconductor doped layer 321, and the second semiconductor doped layer 322 have different threshold voltages formed in the channel.
  • An electric field that changes from the bottom of the channel 131 to the top of the substrate 100 is formed.
  • the changing electric field can change the trajectory of electrons, make the leaked electrons flow into the gate conductive layer, reduce the influence of the hammer effect, and improve the reliability of the device.
  • most of the content of the semiconductor structure of this embodiment is the same as the above-mentioned embodiment, and the difference between this embodiment and the above-mentioned embodiment is that, referring to FIG. 9 , in the direction perpendicular to the substrate 100 , the doping concentration of the first dopant in the first semiconductor doped layer 321 changes gradually.
  • the doping concentration of the second dopant in the second semiconductor doped layer 322 changes gradually.
  • the doping concentration of the first semiconductor doped layer 321 near the top surface of the gate conductive layer 310 is 10 13 atoms/cm2, and the first semiconductor doped layer 321 is away from the top surface of the gate conductive layer 310
  • the doping concentration on one side is 10 14 atoms/cm2.
  • the doping concentration of the second doped semiconductor layer 322 near the top surface of the first doped semiconductor layer 321 is 10 14 atoms/cm2, and the doped semiconductor layer 322 is far away from the doped semiconductor layer 321.
  • the doping concentration on one side of the top surface of the impurity layer 321 was 10 15 atoms/cm 2 .
  • an electric field is formed in the channel 131 from the bottom of the channel 131 to the top surface of the substrate 100 with the threshold voltage gradually decreasing, and the threshold voltage of the semiconductor structure on the top surface of the substrate 100 is the smallest, then
  • the voltage at the gate-drain overlap interface of the transistor formed by the semiconductor structure of this embodiment is the smallest, which can avoid gate-induced drain leakage at the gate-drain overlap interface of the transistor.
  • the first doped semiconductor layer 321 includes a first doped region 3211 and a second doped region 3212
  • the second doped semiconductor layer 322 includes a third doped region 3221 and a fourth doped region 3222 .
  • the doping concentration of the first doped region 3211 is smaller than that of the second doped region 3212 .
  • the doping concentration of the first doped region 3211 is 10 13 atoms/cm 2
  • the doping concentration of the second doped region 3212 is 10 14 atoms/cm 2 .
  • the doping concentration of the second semiconductor doped layer 322 is 10 15 atoms/cm 2 .
  • a gradually decreasing threshold voltage is formed in the channel 131 from the bottom of the channel 131 to the top surface of the substrate 100, which reduces the electric field around the semiconductor structure and reduces The gate-induced drain leakage occurs at the gate-drain overlap interface, which can also reduce adjacent interference.
  • this embodiment provides a semiconductor structure, as shown in FIG. 17 and FIG. 18, or as shown in FIG. 19 and FIG. 20.
  • the semiconductor structure includes: a substrate 500, The word line channel 530 , the gate oxide layer 600 , the gate conductive layer 710 and the semiconductor doped layer 720 are disposed in the substrate 500 .
  • the gate oxide layer 600 covers the word line channel 530, the gate conductive layer 710 fills part of the word line channel 530, the gate conductive layer 710 and the substrate 100 are separated by the gate oxide layer 600, and the semiconductor doped layer 720 covers the gate conductive layer 710 and fill the rest of the word line trench 530 not filled by the gate conductive layer 710 , the semiconductor doped layer 730 and the substrate 100 are separated by the gate oxide layer 600 .
  • the gate conductive layer 710 and the semiconductor doped layer 720 together form the word line structure 700 .
  • the doping concentration of the semiconductor doped layer 720 near the top surface of the gate conductive layer 710 is different from the doping concentration of the semiconductor doped layer 720 away from the top surface of the gate conductive layer 710 .
  • the substrate 500 includes an active region 510 and a shallow trench isolation region 520, and the word line channel 530 passes through the substrate 100 to expose part of the active region 510 and part of the shallow trench isolation region 520, each Both ends of the active region 510 intersect with a word line channel 530 respectively.
  • the word line channel 530 includes a gate channel 531 passing through the active region 510 and a conductive channel 532 passing through the shallow trench isolation region 520 .
  • the word line structure 700 includes a first gate 700a passing through the active region 510 and a The second grid 700b.
  • the first gates 700a and the second gates 700b in the word line structure 700 are alternately arranged in sequence.
  • the first gate 700a includes a first gate conductive layer 710a and a first gate semiconductor doped layer 720a arranged in sequence
  • the second gate 700b includes a sequentially arranged The second gate conductive layer 710b and the second gate semiconductor doped layer 720b.
  • most of the content of the semiconductor structure of this embodiment is the same as that of the above-mentioned embodiment.
  • the difference between this embodiment and the above-mentioned embodiment is that, referring to FIG. 13 and FIG.
  • the depth is greater than the depth of the gate trench 531 , and along the extending direction of the word line trench 530 , the cross section of the word line trench 530 is a concavo-convex shape with ups and downs.
  • the bottom surface of the second gate 700b of the word line structure 700 is lower than the bottom surface of the first gate 700a, and the second gate 700b isolates two adjacent The effect of one first grid 700a is better, and the effect of reducing the interference between two adjacent first grids 700a is better, further reducing the hammer effect.
  • the manufacturing method and semiconductor structure provided by the present disclosure utilize the property that the work function of the semiconductor material can be changed, reduce the voltage of the semiconductor structure at the gate-drain overlap interface, and avoid the gate-drain overlap of the semiconductor structure. Gate induced drain leakage occurs at the interface.
  • the work function of the gate conductive layer and the channel of the semiconductor structure are quite different, and the work function of the semiconductor doped material in the semiconductor doped layer and the channel The difference is small, the threshold voltage of the semiconductor structure near the bottom of the channel is higher, and the threshold voltage near the top surface of the substrate is smaller, which can avoid gate-induced drain leakage.

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Abstract

本公开提供一种半导体结构的制作方法及半导体结构，半导体结构的制作方法包括，提供基底，基底内形成有沟道；形成栅极导电层，栅极导电层覆盖部分沟道；形成半导体掺杂层，半导体掺杂层填充沟道，且覆盖栅极导电层，半导体掺杂层靠近栅极导电层的顶面的一侧的掺杂浓度和半导体掺杂层远离栅极导电层的顶面的一侧的掺杂浓度不同。

Description

半导体结构的制作方法及半导体结构
本公开基于申请号为202111202940.5，申请日为2021年10月15日，申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的制作方法及半导体结构。
背景技术
随着动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)的发展，为提高半导体器件性能，通常将凹陷沟道阵列晶体管(Recess Channel Access Transistor，简称RCAT)应用于动态随机存取存储器中，以减小晶体管的栅极沟道长度，提高动态随机存取存储器的集成度。
但是，凹陷沟道阵列晶体管容易产生栅诱导漏极泄漏电流(Gate-Induce Drain Leakage，简称GIDL)，影响动态随机存取存储器的可靠性。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体结构的制作方法及半导体结构。
本公开的第一方面提供一种半导体结构的制作方法，所述半导体结构的制作方法包括：
提供基底，所述基底内形成有沟道；
形成栅极导电层，所述栅极导电层覆盖部分所述沟道；
形成半导体掺杂层，所述半导体掺杂层填充所述沟道，且覆盖所述 栅极导电层，所述半导体掺杂层靠近所述栅极导电层的顶面的一侧的掺杂浓度和所述半导体掺杂层远离所述栅极导电层的顶面的一侧的掺杂浓度不同。
根据本公开的一些实施例，形成所述半导体掺杂层包括：
形成第一半导体掺杂层，所述第一半导体掺杂层覆盖所述栅极导电层的顶面，所述第一半导体掺杂层的顶面低于所述基底的顶面；
形成第二半导体掺杂层，所述第二半导体掺杂层覆盖所述第一半导体掺杂层的顶面；
所述第二半导体掺杂层的掺杂浓度和所述第一半导体掺杂层的掺杂浓度不同。
根据本公开的一些实施例，所述第二半导体掺杂层和所述第一半导体掺杂层的导电类型相同。
根据本公开的一些实施例，所述形成第一半导体掺杂层，包括：
沉积第一半导体材料，对所述第一半导体材料进行第一次掺杂，形成第一掺杂区域，所述第一掺杂区域覆盖所述栅极导电层的顶面；
对所述第一半导体材料进行第二次掺杂，形成第二掺杂区域，所述第二掺杂区域覆盖所述第一掺杂区域的顶面；
其中，所述第二掺杂区域和所述第一掺杂区域的掺杂浓度不同。
根据本公开的一些实施例，所述形成第二半导体掺杂层，包括：
沉积第二半导体材料，对所述第二半导体材料进行第一次掺杂，形成第三掺杂区域，所述第三掺杂区域覆盖所述第一半导体掺杂层的顶面；
对所述第二半导体材料进行第二次掺杂，形成第四掺杂区域，所述第四掺杂区域覆盖所述第三掺杂区域的顶面；
其中，所述第四掺杂区域和所述第三掺杂区域的掺杂浓度不同。
根据本公开的一些实施例，所述第二半导体掺杂层的掺杂浓度大于所述第一半导体掺杂层的掺杂浓度。
根据本公开的一些实施例，所述形成栅极导电层，包括：
在所述沟道内填充初始栅极导电层；
回刻蚀所述初始栅极导电层，保留高度不小于所述沟道深度的三分 之一的所述初始栅极导电层形成所述栅极导电层。
本公开的第二方面提供了一种半导体结构，所述半导体结构包括：
基底，所述基底包括沟道；
栅极导电层，所述栅极导电层覆盖部分所述沟道；
半导体掺杂层，所述半导体掺杂层填充所述沟道，且覆盖所述栅极导电层，所述半导体掺杂层靠近所述栅极导电层的顶面的一侧的掺杂浓度和所述半导体掺杂层远离所述栅极导电层的顶面的一侧的掺杂浓度不同。
根据本公开的一些实施例，在垂直于所述基底的方向上，所述栅极导电层的底部至所述半导体掺杂层的顶部之间具有第一高度，所述栅极导电层具有第二高度，所述第二高度不小于所述第一高度的三分之一。
根据本公开的一些实施例，所述半导体掺杂层包括：
第一半导体掺杂层，所述第一半导体掺杂层覆盖所述栅极导电层的顶面，所述第一半导体掺杂层的顶面低于所述基底的顶面；
第二半导体掺杂层，所述第二半导体掺杂层覆盖所述第一半导体掺杂层的顶面；
所述第二半导体掺杂层的掺杂浓度和所述第一半导体掺杂层的掺杂浓度不同。
根据本公开的一些实施例，所述第一半导体掺杂层中包括第一掺杂剂，所述第二半导体掺杂层中包括第二掺杂剂，所述第一掺杂剂和所述第二掺杂剂的导电类型相同。
根据本公开的一些实施例，在垂直于所述基底的方向上，所述第一半导体掺杂层中的所述第一掺杂剂的掺杂浓度逐渐变化。
根据本公开的一些实施例，在垂直于所述基底的方向上，所述第二半导体掺杂层中的所述第二掺杂剂的掺杂浓度逐渐变化。
根据本公开的一些实施例，在垂直于所述基底的方向上，所述第一半导体掺杂层具有第三高度，所述第三高度不大于所述第一高度的三分之一，所述第二半导体掺杂层具有第四高度，所述第四高度不大于所述第一高度的三分之一。
根据本公开的一些实施例，所述第一半导体掺杂层的掺杂浓度低于 所述第二半导体掺杂层的掺杂浓度。
本公开实施例所提供的半导体结构的制作方法及半导体结构中，半导体结构的栅极导电层和沟道的功函数差异较大，半导体掺杂层中的半导体掺杂材料和沟道的功函数差异小，半导体结构靠近沟道的底部的阈值电压较大，而靠近基底顶面的阈值电压小，能够避免发生栅极诱导漏极漏电。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图2是根据一示例性实施例示出的一种半导体结构的制作方法中形成半导体掺杂层的流程图。
图3是根据一示例性实施例示出的一种半导体结构的制作方法的流程图。
图4是根据一示例性实施例示出的一种半导体结构的制作方法中提供的基底的示意图。
图5是根据一示例性实施例示出的一种半导体结构的制作方法中形成初始栅极导电层的示意图。
图6是根据一示例性实施例示出的一种半导体结构的制作方法中形成栅极导电层的示意图。
图7是根据一示例性实施例示出的一种半导体结构的制作方法中形成半导体结构的示意图。
图8是根据一示例性实施例示出的一种半导体结构的制作方法中形成第一半导体掺杂层的示意图。
图9是根据一示例性实施例示出的一种半导体结构的制作方法中形成第二半导体掺杂层的示意图。
图10是根据一示例性实施例示出的一种半导体结构的制作方法中形成第一半导体掺杂层的示意图。
图11是根据一示例性实施例示出的一种半导体结构的制作方法中形成的半导体结构的示意图。
图12是根据一示例性实施例示出的一种半导体结构的制作方法中提供的基底的俯视图。
图13是图12沿A-A面的剖面示意图。
图14是图12沿B-B面的剖面示意图。
图15是根据一示例性实施例示出的一种半导体结构的制作方法中形成栅极导电层的A-A面剖面示意图。
图16是根据一示例性实施例示出的一种半导体结构的制作方法中形成栅极导电层的B-B面剖面示意图。
图17是根据一示例性实施例示出的一种半导体结构的制作方法中形成的半导体结构的A-A面剖面示意图。
图18是根据一示例性实施例示出的一种半导体结构的制作方法中形成的半导体结构的B-B面剖面示意图。
图19是根据一示例性实施例示出的一种半导体结构的制作方法中形成的半导体结构的A-A面剖面示意图。
图20是根据一示例性实施例示出的一种半导体结构的制作方法中形成的半导体结构结构的B-B面剖面示意图。
附图标记：
100、基底；110、有源区；131、沟道；200、栅氧化层；301、初始栅极导电层；310、栅极导电层；320、半导体掺杂层；321、第一半导体掺杂层；3211、第一掺杂区域；3212、第二掺杂区域；322、第二半导体掺杂层；3221、第三掺杂区域；3222、第四掺杂区域；
500、基底；510、有源区；520、浅槽隔离区；530、字线沟道；531、栅极沟道；532、导电沟道；600、栅氧化层；700、字线结构； 700a、第一栅极；700b、第二栅极；710、栅极导电层；710a、第一栅极的导电层；710b、第二栅极的导电层；720、半导体掺杂层；720a、第一栅极的半导体掺杂层；720b、第二栅极的半导体掺杂层；721、第一半导体掺杂层；7211、第一掺杂区域；7212、第二掺杂区域；722、第二半导体掺杂层；7221、第三掺杂区域；7222、第四掺杂区域。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图1所示，图1示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图4-图11为半导体结构的制作方法的各个阶段的示意图，下面结合图4-图11对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为凹陷沟道晶体管(以下简称晶体管)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其它的结构。应当理解的是，本实施例形成的半导体结构并不构成完整的晶体管，本实施例仅为晶体管的栅极电极的形成过程。
如图1所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
S10：提供基底，基底内形成有沟道。
如图4所示，基底100包括有源区110，有源区110可以为P型有源区或N型有源区。有源区110的材料包括半导体材料，示例性的，有源区110的材料可以包括硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。沟道131形成于有源区110中，在本实施例中，形成的沟道131为栅极沟道。
如图4所示，基底100还包括栅氧化层200，沟道131由栅氧化层200， 围成。栅氧化层200的材料为硅氧化物，例如，栅氧化层200的材料为二氧化硅。
在一些实施例中，提供基底100，包括：提供初始基底，刻蚀初始基底形成栅极沟槽，在栅极沟槽中形成栅氧化层200，栅氧化层200覆盖栅极沟槽内表面，栅氧化层200在栅极沟槽中围成沟道131。
S20：形成栅极导电层，栅极导电层覆盖部分沟道。
如图6所示，参照图4，栅极导电层310位于沟道131的底部填充部分沟道131，覆盖部分栅氧化层200。栅极导电层310的材料可以包括金属氮化物，例如可以包括氮化钛或氮化铟。在本实施例中，栅极导电层310的材料包括氮化钛。
在本实施例中，形成栅极导电层310包括：
S21：在沟道内填充初始栅极导电层。
如图5所示，参照图4，可以采用原子层沉积(Atomic layer deposition，简称ALD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)沉积栅导电材料，栅导电材料填充沟道131并覆盖基底100顶面，形成初始栅极导电层301。
S22：回刻蚀初始栅极导电层，保留高度不小于沟道深度的三分之一的初始栅极导电层形成栅极导电层。
如图6所示，参照图5，通过回刻蚀去除部分初始栅极导电层301形成栅极导电层310。在本实施例中，形成的栅极导电层310的高度大于沟道131深度的三分之一。
S30：形成半导体掺杂层，半导体掺杂层填充沟道，且覆盖栅极导电层，半导体掺杂层靠近栅极导电层的顶面的一侧的掺杂浓度和半导体掺杂层远离栅极导电层的顶面的一侧的掺杂浓度不同。
如图7所示，可以通过低压化学气相沉积工艺(Low Pressure Chemical Vapor Deposition，简称LPCVD)原位掺杂半导体材料形成半导体掺杂层320，或者沉积无掺杂半导体材料填充沟道131形成半导体材料层，再通过热扩散工艺或离子注入工艺向半导体材料层中注入掺杂杂质，形成半导体掺杂层320。
晶体管的阈值电压(Threshold Voltage，TV)由栅极电极与栅极沟道的 功函数(Work function，WF)之间的差异决定。本实施例形成的半导体结构，栅极电极包括设置在栅极沟道底部的栅极导电层以及覆盖栅极导电层顶面的半导体掺杂层，栅极导电层中的金属氮化物的功函数和栅极沟道的功函数差异较大，半导体掺杂层和形成栅极沟道的有源区的材料的功函数差异较小，也即栅极电极在靠近栅极沟道的底部的阈值电压较大，而靠近基底顶面的阈值电压小。栅极电极在靠近栅极沟道的底部的阈值电压较大，能够减小晶体管向相邻晶体管发生电荷泄漏的发生，栅极电极在靠近基底顶面的阈值电压小，则晶体管的栅漏极交叠界面的电压小，避免在晶体管的栅漏极交叠界面发生栅极诱导漏极漏电。
根据本公开一个示例性的实施例，本实施例是对上述实施例中步骤S40的进一步说明。
如图2所示，形成半导体掺杂层包括：
S31：形成第一半导体掺杂层，第一半导体掺杂层覆盖栅极导电层的顶面，第一半导体掺杂层的顶面低于基底的顶面。
如图8所述，参照图1和图7，形成第一半导体掺杂层321的过程包括，沉积第一半导体材料填充沟道131，通过回刻蚀将位于沟道131中的第一半导体材料回刻蚀至低于基底100顶面，通过离子注入工艺向被保留的第一半导体材料中注入掺杂剂，形成第一半导体掺杂层321。
在一些实施例中，形成第一半导体掺杂层包括：
S31a：沉积第一半导体材料，对第一半导体材料进行第一次掺杂，形成第一掺杂区域，第一掺杂区域覆盖栅极导电层的顶面。
可以通过离子注入向无掺杂的第一半导体材料进行第一次掺杂。
S31b：对第一半导体材料进行第二次掺杂，形成第二掺杂区域，第二掺杂区域覆盖第一掺杂区域的顶面。
如图10所示，第二掺杂区域3212和第一掺杂区域3211的掺杂浓度不同。
可以通过离子注入向进行第一次掺杂后的第一半导体材料进行第二次掺杂，第二次掺杂的注入深度小于第一次掺杂的注入深度。如图10所示，形成的第一半导体掺杂层321中第二次掺杂的注入深度以下的区域为第一掺杂区域3211，第二次掺杂的注入深度以内的区域为第二掺杂区域3212，第二 掺杂区域3212的掺杂浓度大于第一掺杂区域3211的掺杂浓度。
在一些实施例中，沉积第一半导体材料时，可以仅对第一半导体材料进行一次掺杂。沉积第一半导体材料的同时掺杂第一半导体材料，且掺杂浓度逐渐变化，形成的第一半导体掺杂层321，沿垂直于基底100的方向，第一半导体掺杂层321的浓度逐渐变化。
S32：形成第二半导体掺杂层，第二半导体掺杂层覆盖第一半导体掺杂层的顶面。
第二半导体掺杂层的掺杂浓度和第一半导体掺杂层的掺杂浓度不同。例如，第二半导体掺杂层322的掺杂浓度可以大于或小于第一半导体掺杂层321的掺杂浓度，在本实施例中，第二半导体掺杂层322的掺杂浓度大于第一半导体掺杂层321的掺杂浓度。
如图9所示，参照图8，形成第二半导体掺杂层322的操作，包括：将半导体结构置于反应腔室，向反应腔室内提供反应源气体、掺杂气体和载气，采用低压化学气相沉积半导体掺杂材料，半导体掺杂材料填充沟道131形成第二半导体掺杂层322。
示例性的，第二半导体掺杂层322可以包括含硅或锗的半导体材料。在本示例中，可以硅源气体或锗源气体中的一种或两种以上作为反应源气体，磷化氢(Phosphine，PH 3)或砷化氢(Hydrogen Arsenide，AsH 3)中的一种或两种以上作为掺杂气体，以氢气(Hydrogen，H 2)作为载气，低压化学气相沉积工艺沉积N型掺杂的半导体材料，N型掺杂的半导体材料填充沟道131形成第二半导体掺杂层322。
在一些实施例中，形成第二半导体掺杂层包括：
S32a：沉积第二半导体材料，对第二半导体材料进行第一次掺杂，形成第三掺杂区域，第三掺杂区域覆盖第一半导体掺杂层的顶面。
S32b：对第二半导体材料进行第二次掺杂，形成第四掺杂区域，第四掺杂区域覆盖第三掺杂区域的顶面。
其中，第四掺杂区域和第三掺杂区域的掺杂浓度不同。
如图11所示，参照图10，第三掺杂区域3221和第四掺杂区域3222形成第二半导体掺杂层322。
在本实施例中，第二半导体掺杂层322和第一半导体掺杂层321的导电 类型相同。第一半导体掺杂层321的导电类型为N型掺杂，则第二半导体掺杂层322的导电类型也为N型掺杂。第一半导体掺杂层321的导电类型为P型掺杂，则第二半导体掺杂层322的导电类型也为P型掺杂。
第一半导体掺杂层321和第二半导体掺杂层322的导电类型根据有源区110设置。有源区为P型有源区，则将第一半导体掺杂层321和第二半导体掺杂层322的导电类型设置为N型掺杂。有源区110为N型有源区，则将第一半导体掺杂层321和第二半导体掺杂层322的导电类型设置为P型掺杂。
半导体材料的功函数可以通过掺杂离子改变，半导体材料的功函数等于半导体材料的真空能级和费米能级的差值，半导体材料的费米能级与半导体材料中的载流子密度有关，而半导体材料中载流子密度受到掺杂杂质和掺杂浓度影响。因此，本实施例中第一半导体掺杂层和第二半导体掺杂层的掺杂浓度不同，第一半导体掺杂层和第二半导体掺杂层的功函数不同。通过调制半导体材料的功函数，在栅极沟道形成分段式的变化电场，可以有效避免栅极沟道部分位置因电场强度太大而容易击穿并导致器件损坏失效的问题。
本公开示例性的实施例中提供一种半导体结构的制作方法，如图3所示，图3示出了根据本公开一示例性的实施例提供的半导体结构的制作方法的流程图，图12-图20为半导体结构的制作方法的各个阶段的示意图，下面结合图12-图20对半导体结构的制作方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其它的结构。
如图3所示，本公开一示例性的实施例提供的一种半导体结构的制作方法，包括如下的步骤：
步骤S100：提供基底，基底内形成有字线沟道。
图12示出了基底500的俯视图，图13是图12中的基底沿A-A方向的剖面示意图，图14是图12中的基底沿B-B方向的剖面示意图。在本实施例中，A-A方向为字线沟道的延伸方向，B-B方向为有源区的延伸方向。
如图12、图13、图14所示，基底500包括有源区510和浅槽隔离区520。基底500中的多个有源区510独立设置，浅槽隔离区520将多个有源区510隔开。有源区510可以为P型有源区或N型有源区，有源区510的材料 包括半导体材料。在本实施例中，有源区510的材料包括P型掺杂半导体材料。浅槽隔离区520的材料可以包括氧化硅。
如图12所示，基底500内形成有多条平行设置的字线沟道530，字线沟道530从基底500中穿过暴露出部分有源区510和部分浅沟道隔离区520，每个有源区510的两端分别与一条字线沟道530相交。字线沟道530包括从有源区510穿过的栅极沟道531以及从浅槽隔离区520穿过的导电沟道532。
步骤S200：形成栅极导电层，栅极导电层覆盖部分字线沟道。
本实施例中步骤S200中栅极导电层710的形成方法和上述实施例中步骤S20的实现方式相同。
如图15、图16，参照图13、图14，可以采用原子层沉积(Atomic layer deposition，简称ALD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)沉积栅导电材料，栅导电材料填充部分字线沟道530形成栅极导电层710，栅极导电层710位于字线沟道530的底部。栅极导电层710的材料可以包括金属氮化物，示例性的，栅极导电层710的材料可以包括氮化钛、氮化铟中的一种或两种以上。在本实施例中，栅极导电层710的材料包括氮化钛。
步骤S300：形成半导体掺杂层，半导体掺杂层填充字线沟道，且覆盖栅极导电层，半导体掺杂层靠近栅极导电层的顶面的一侧的掺杂浓度和半导体掺杂层远离栅极导电层的顶面的一侧的掺杂浓度不同。
步骤S300中半导体掺杂层720的形成方法和上述实施例中步骤S30的实现方式相同。
如图17、图18，参照图12、图15、图16，可以沉积掺杂半导体材料形成半导体掺杂层720，或者沉积无掺杂半导体材料填充字线沟道530形成半导体材料层，再通过热扩散工艺或离子注入工艺向半导体材料层中注入掺杂杂质，形成半导体掺杂层720。
步骤S300中形成的半导体掺杂层720和上述实施例步骤S60中形成的半导体掺杂层320的结构相同。如图17、图18所示，半导体掺杂层720可以包括第一半导体掺杂层721以及第二半导体掺杂层722，第一半导体掺杂层721覆盖栅极导电层710的顶面，第二半导体掺杂层722的掺杂浓度大于第一半导体掺杂层721的掺杂浓度。第一半导体掺杂层721的导电类型和第二 半导体掺杂层722的导电类型相同。
在一些实施例中，如图19、图20所示，沿栅极导电层710到第二半导体掺杂层722的方向，第一半导体掺杂层721包括依次设置的第一掺杂区域7211和第二掺杂区域7212，第一掺杂区域7211和第二掺杂区域7212的掺杂浓度不同。
在一些实施例中，如图19、图20所示，沿第一半导体掺杂层721到基底500的顶面的方向，第二半导体掺杂层722包括依次设置的第三掺杂区域7221和第四掺杂区域7222，第三掺杂区域7221和第四掺杂区域7222，的掺杂浓度不同。
本实施例形成的半导体结构，如图17、图18、图19所示，半导体掺杂层720和栅极导电层710共同形成了字线结构700。本实施例形成的字线结构700包括从有源区510穿过的第一栅极700a以及从浅槽隔离区520穿过的第二栅极700b。沿字线结构700的延伸方向，字线结构700中的第一栅极700a和第二栅极700b连接。如图17所示，参照图13，第一栅极700a设置在栅极沟道531中，第二栅极700b设置在导电沟道532中。
如图13、图17所示，自字线沟道530底部到基底100顶面，第一栅极700a包括依次设置的栅极导电层710a以及半导体掺杂层720a，如图15、图17、图19所示，第二栅极700b包括依次设置的栅极导电层710b以及半导体掺杂层720b。
如图19所示，第一栅极700a可以作为晶体管的栅极电极(也可以称之为栅极或控制栅)，用于控制晶体管的导通和截止。在本实施例中，第一栅极700a作为凹陷沟道晶体管的栅极电极。第二栅极700b设于浅槽隔离区520内且与有源区510相邻，用于连通不同有源区510中的第一栅极700a，形成凹陷沟道阵列晶体管。
本实施例形成的半导体结构，可形成凹陷沟道阵列晶体管，第一栅极作为晶体管的栅极电极包括栅极导电层以及半导体掺杂层。栅极导电层中金属氮化物的功函数和栅极沟道的功函数差异较大，半导体掺杂层中的掺杂半导体材料和栅极沟道的功函数差异较小。使得晶体管的栅极电极在靠近栅极沟道的底部的阈值电压较大，而靠近基底顶面的阈值电压小，晶体管的栅漏极交叠界面的电压小，避免晶体管的栅漏极交叠界面发生栅极诱导漏极漏电。
同时，晶体管的栅极电极的导电层在栅极沟道的底部区域产生高阈值电压，半导体掺杂层在栅极电极上方产生低阈值电压。产生自栅极沟道的底部向晶体管的栅漏交叠界面变化的电场。晶体管被多次刷新、读取，晶体管的栅极电极被不断的开启和关闭，相邻晶体管间可能发生电容耦合干扰。而本实施例形成的半导体结构，凹陷沟道阵列晶体管通过在栅极沟道形成的变化电场，能够改变电子运动轨迹，使泄漏电子流动到第一栅极的导电层中，减小行锤效应的影响，提高了器件的可靠性。
根据本公开一个示例性的实施例，本实施例是对上述实施例中步骤S100的进一步说明。
在本实施例中，提供基底，参照图13、图14，包括：提供半导体衬底，半导体衬底为P型衬底，半导体衬底的材料包括半导体材料，示例性的，半导体衬底的材料可以包括硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。在半导体衬底顶面形成掩膜图案，根据掩膜图案去除部分半导体衬底形成浅沟槽，浅沟槽将被保留的部分半导体衬底分隔成独立设置的有源区510。沉积低k介电材料填充浅沟槽形成浅槽隔离区520。在本实施例中，低k介电材料为氧化硅。
形成硬掩膜，硬掩膜覆盖有源区510和浅槽隔离区520的顶面，通过自对准双重成像技术(Self-aligned Double Patterning，简称SADP)图案化硬掩膜形成字线图案，根据字线图案采用干法刻蚀工艺或湿法刻蚀工艺去除部分有源区510和部分浅槽隔离区520，形成字线沟槽。
参照图13、图14，去除部分有源区510和部分浅槽隔离区520时，通过控制刻蚀工艺对有源区510和浅槽隔离区520的刻蚀选择比，以使刻蚀工艺去除浅槽隔离区520的速度大于去除有源区510的速度，形成的字线沟槽位于浅槽隔离区520的深度大于位于有源区510中的深度。沿字线沟槽的延伸方向，字线沟槽的截面为高低起伏的凹凸形。
形成栅氧化层，栅氧化层覆盖字线沟槽。
参照图13、图14，可以采用原子层沉积(Atomic layer deposition，简称ALD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)沉积栅氧化层材料形成栅氧化层600，栅氧化层600覆盖字线沟槽在字线沟槽中围成字线沟道530。栅氧化层600的材料为硅氧化物，在本实施例中，栅氧化层600 的材料为二氧化硅。
在本实施例的字线沟道中形成的字线结构，第二栅极的高度大于第一栅极的高度，第二栅极设置在相邻的两个第一栅极之间以隔离相邻的第一栅极。通过增加第二栅极的隔离高度增加第二栅极的隔离效果，减小晶体管的相邻干扰，避免晶体管向相邻晶体管发生电流泄漏，进一步减小行锤效应。
根据本公开一个示例性的实施例，本实施例提供了一种半导体结构，如图7所示，参照图4，包括：基底100、设置在基底100中的沟道131、栅极导电层310以及半导体掺杂层320。栅极导电层310设置在沟道131中并覆盖部分沟道131，半导体掺杂层320覆盖栅极导电层310的顶面并填充沟道131中未被栅极导电层310填充的其余部分。栅极导电层310的高度大于沟道深度的三分之一。半导体结构还包括栅氧化层200，栅氧化层200设置在栅极导电层310和沟道131之间以及半导体掺杂层320和沟道131之间。
在本实施例中，半导体掺杂层320靠近栅极导电层310的顶面的一侧的掺杂浓度和半导体掺杂层320远离栅极导电层310的顶面的一侧的掺杂浓度不同。
本实施例中的半导体结构，栅极导电层310在沟道131底部对应形成高阈值电压，半导体掺杂层320在栅极导电层310上方的沟道131对应形成低阈值电压，以栅极导电层310覆盖的部分沟道131作为主沟道，主沟道和基底100顶面之间的阈值电压。以使则本实施例的半导体结构形成的晶体管的栅漏极交叠界面的电压小，能够避免在晶体管的栅漏极交叠界面发生栅极诱导漏极漏电。
根据一个示例性实施例，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，在垂直于基底100的方向上，栅极导电层310的底部至半导体掺杂层320的顶部之间具有第一高度，栅极导电层310具有第二高度，第二高度不小于第一高度的三分之一。
根据一个示例性实施例，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图9所示，半导体掺杂层320包括：覆盖栅极导电层310的顶面的第一半导体掺杂层321，第一半导体掺杂层321的顶面低于基底100的顶面。半导体掺杂层320还包 括覆盖第一半导体掺杂层321的顶面的第二半导体掺杂层322，第二半导体掺杂层322的掺杂浓度和第一半导体掺杂层321的掺杂浓度不同。
在一些实施例中，第一半导体掺杂层321的掺杂浓度低于第二半导体掺杂层322的掺杂浓度。
如图9所示，在垂直于基底100的方向上，第一半导体掺杂层321具有第三高度，第三高度不大于第一高度的三分之一，第二半导体掺杂层322具有第四高度，第四高度不大于第一高度的三分之一。
本实施例的半导体结构，参照图4、图9所示，栅极导电层310、第一半导体掺杂层321、第二半导体掺杂层322在沟道形成的阈值电压不同，在半导体结构中形成自沟道131底部向基底100顶面变化的电场，变化电场能够改变电子运动轨迹，使泄漏电子流动到栅极导电层中，减小行锤效应的影响，提高了器件的可靠性。
根据一个示例性实施例，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，参照图9，在垂直于基底100的方向上，第一半导体掺杂层321中的第一掺杂剂的掺杂浓度逐渐变化。
在垂直于基底100的方向上，第二半导体掺杂层322中的第二掺杂剂的掺杂浓度逐渐变化。
示例性的，第一半导体掺杂层321靠近栅极导电层310的顶面的一侧的掺杂浓度为10 13原子/cm2，第一半导体掺杂层321远离栅极导电层310的顶面的一侧的掺杂浓度为10 14原子/cm2。
在本实施例中，第二半导体掺杂层322靠近第一半导体掺杂层321的顶面的一侧的掺杂浓度为10 14原子/cm2，第二半导体掺杂层322远离第一半导体掺杂层321的顶面的一侧的掺杂浓度为10 15原子/cm2。
本实施例的半导体结构，参照图4和图9，在沟道131形成自沟道131底面向基底100顶面阈值电压逐渐减小的电场，半导体结构在基底100顶面的阈值电压最小，则本实施例的半导体结构形成的晶体管的栅漏极交叠界面的电压最小，能够避免在晶体管的栅漏极交叠界面发生栅极诱导漏极漏电。
根据一个示例性实施例，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，如图11所示，在 垂直于基底100的方向上，第一半导体掺杂层321包括第一掺杂区域3211和第二掺杂区域3212，第二半导体掺杂层322包括第三掺杂区域3221和第四掺杂区域3222。
在本实施例中，第一掺杂区域3211的掺杂浓度小于第二掺杂区域3212的掺杂浓度。示例性的，第一掺杂区域3211的掺杂浓度为10 13原子/cm2，第二掺杂区域3212的掺杂浓度为10 14原子/cm2。
在本实施例中，第二半导体掺杂层322的掺杂浓度为10 15原子/cm2。
本实施例的半导体结构，参照图4和图11，在沟道131中形成了自沟道131底面向基底100顶面逐渐减小的渐变阈值电压，减小了半导体结构周围的电场，减小栅漏极交叠界面发生栅极诱导漏极漏电，还能减小相邻干扰。
根据本公开一个示例性的实施例，本实施例提供了一种半导体结构，如图17、图18所示，或如图19、图20所示，参照图12，半导体结构包括：基底500、设置在基底500中的字线沟道530、栅氧化层600、栅极导电层710以及半导体掺杂层720。栅氧化层600覆盖字线沟道530，栅极导电层710填充部分字线沟道530，栅极导电层710和基底100通过栅氧化层600隔开，半导体掺杂层720覆盖栅极导电层710的顶面并填充字线沟道530中未被栅极导电层710填充的其余部分，半导体掺杂层730和基底100通过栅氧化层600隔开。栅极导电层710和半导体掺杂层720共同形成字线结构700。半导体掺杂层720靠近栅极导电层710的顶面的一侧的掺杂浓度和半导体掺杂层720远离栅极导电层710的顶面的一侧的掺杂浓度不同。
参照图13、图14，基底500包括有源区510和浅槽隔离区520，字线沟道530从基底100中穿过暴露出部分有源区510和部分浅沟道隔离区520，每个有源区510的两端分别与一条字线沟道530相交。字线沟道530包括从有源区510穿过的栅极沟道531以及从浅槽隔离区520穿过的导电沟道532。
如图13、图17、图18所示，或如图19、图20所示，字线结构700包括从有源区510穿过的第一栅极700a以及从浅槽隔离区520穿过的第二栅极700b。沿字线结构700的延伸方向，字线结构700中的第一栅极700a和第二栅极700b依次交替排列。其中，自字线沟道530底部到基底100顶面，第一栅极700a包括依次设置的第一栅极导电层710a以及第一栅极半导体掺杂层720a，第二栅极700b包括依次设置的第二栅极导电层710b以及第二栅极半 导体掺杂层720b。
根据一个示例性实施例，本实施例的半导体结构的大部分内容和上述实施例相同，本实施例与上述实施例之间的区别之处在于，参照图13、图14，导电沟道532的深度大于栅极沟道531的深度，沿字线沟道530的延伸方向，字线沟道530的截面为高低起伏的凹凸形。
如图17、图18所示，或如图19、图20所示，字线结构700的第二栅极700b的底面低于第一栅极700a的底面，第二栅极700b隔离相邻两个第一栅极700a的效果更好，减小相邻的两个第一栅极700a之间的干扰的效果更好，进一步减小行锤效应。
本公开提供的半导体结构的制作方法及半导体结构，利用了半导体材料的功函数可以被改变的特性，减小了半导体结构在栅漏极交叠界面的电压，避免半导体结构在栅漏极交叠界面发生栅极诱导漏极漏电。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的制作方法及半导体结构中，半导体结构的栅极导电层和沟道的功函数差异较大，半导体掺杂层中的半导体掺杂材料和沟道的功函数差异小，半导体结构靠近沟道的底部的阈值电压较大，而靠近基底顶面的阈值电压小，能够避免发生栅极诱导漏极漏电。

Claims (15)

  1. 一种半导体结构的制作方法，所述半导体结构的制作方法包括：
    提供基底，所述基底内形成有沟道；
    形成栅极导电层，所述栅极导电层覆盖部分所述沟道；
    形成半导体掺杂层，所述半导体掺杂层填充所述沟道，且覆盖所述栅极导电层，所述半导体掺杂层靠近所述栅极导电层的顶面的一侧的掺杂浓度和所述半导体掺杂层远离所述栅极导电层的顶面的一侧的掺杂浓度不同。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，形成所述半导体掺杂层包括：
    形成第一半导体掺杂层，所述第一半导体掺杂层覆盖所述栅极导电层的顶面，所述第一半导体掺杂层的顶面低于所述基底的顶面；
    形成第二半导体掺杂层，所述第二半导体掺杂层覆盖所述第一半导体掺杂层的顶面；
    所述第二半导体掺杂层的掺杂浓度和所述第一半导体掺杂层的掺杂浓度不同。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，所述第二半导体掺杂层和所述第一半导体掺杂层的导电类型相同。
  4. 根据权利要求3所述的半导体结构的制作方法，其中，所述形成第一半导体掺杂层，包括：
    沉积第一半导体材料，对所述第一半导体材料进行第一次掺杂，形成第一掺杂区域，所述第一掺杂区域覆盖所述栅极导电层的顶面；
    对所述第一半导体材料进行第二次掺杂，形成第二掺杂区域，所述第二掺杂区域覆盖所述第一掺杂区域的顶面；
    其中，所述第二掺杂区域和所述第一掺杂区域的掺杂浓度不同。
  5. 根据权利要求2所述的半导体结构的制作方法，其中，所述形成第二半导体掺杂层，包括：
    沉积第二半导体材料，对所述第二半导体材料进行第一次掺杂，形成第三掺杂区域，所述第三掺杂区域覆盖所述第一半导体掺杂层的顶面；
    对所述第二半导体材料进行第二次掺杂，形成第四掺杂区域，所述第四 掺杂区域覆盖所述第三掺杂区域的顶面；
    其中，所述第四掺杂区域和所述第三掺杂区域的掺杂浓度不同。
  6. 根据权利要求2所述的半导体结构的制作方法，其中，所述第二半导体掺杂层的掺杂浓度大于所述第一半导体掺杂层的掺杂浓度。
  7. 根据权利要求1所述的半导体结构的制作方法，其中，所述形成栅极导电层，包括：
    在所述沟道内填充初始栅极导电层；
    回刻蚀所述初始栅极导电层，保留高度不小于所述沟道深度的三分之一的所述初始栅极导电层形成所述栅极导电层。
  8. 一种半导体结构，所述半导体结构包括：
    基底，所述基底包括沟道；
    栅极导电层，所述栅极导电层覆盖部分所述沟道；
    半导体掺杂层，所述半导体掺杂层填充所述沟道，且覆盖所述栅极导电层，所述半导体掺杂层靠近所述栅极导电层的顶面的一侧的掺杂浓度和所述半导体掺杂层远离所述栅极导电层的顶面的一侧的掺杂浓度不同。
  9. 根据权利要求8所述的半导体结构，其中，在垂直于所述基底的方向上，所述栅极导电层的底部至所述半导体掺杂层的顶部之间具有第一高度，所述栅极导电层具有第二高度，所述第二高度不小于所述第一高度的三分之一。
  10. 根据权利要求9所述的半导体结构，其中，所述半导体掺杂层包括：
    第一半导体掺杂层，所述第一半导体掺杂层覆盖所述栅极导电层的顶面，所述第一半导体掺杂层的顶面低于所述基底的顶面；
    第二半导体掺杂层，所述第二半导体掺杂层覆盖所述第一半导体掺杂层的顶面；
    所述第二半导体掺杂层的掺杂浓度和所述第一半导体掺杂层的掺杂浓度不同。
  11. 根据权利要求10所述的半导体结构，其中，所述第一半导体掺杂层中包括第一掺杂剂，所述第二半导体掺杂层中包括第二掺杂剂，所述第一掺杂剂和所述第二掺杂剂的导电类型相同。
  12. 根据权利要求11所述的半导体结构，其中，在垂直于所述基底的方向上，所述第一半导体掺杂层中的所述第一掺杂剂的掺杂浓度逐渐变化。
  13. 根据权利要求11所述的半导体结构的制作方法，其中，在垂直于所述基底的方向上，所述第二半导体掺杂层中的所述第二掺杂剂的掺杂浓度逐渐变化。
  14. 根据权利要求11所述的半导体结构，其中，在垂直于所述基底的方向上，所述第一半导体掺杂层具有第三高度，所述第三高度不大于所述第一高度的三分之一，所述第二半导体掺杂层具有第四高度，所述第四高度不大于所述第一高度的三分之一。
  15. 根据权利要求10所述的半导体结构，其中，所述第一半导体掺杂层的掺杂浓度低于所述第二半导体掺杂层的掺杂浓度。
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