WO2023051099A1 - 显示面板、栅极驱动电路及其驱动方法 - Google Patents

显示面板、栅极驱动电路及其驱动方法 Download PDF

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Publication number
WO2023051099A1
WO2023051099A1 PCT/CN2022/114090 CN2022114090W WO2023051099A1 WO 2023051099 A1 WO2023051099 A1 WO 2023051099A1 CN 2022114090 W CN2022114090 W CN 2022114090W WO 2023051099 A1 WO2023051099 A1 WO 2023051099A1
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Prior art keywords
node
transistor
control
pole
signal terminal
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PCT/CN2022/114090
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English (en)
French (fr)
Inventor
宗少雷
孙伟
刘蕊
孙继刚
彭宽军
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京东方科技集团股份有限公司
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Priority to US18/273,041 priority Critical patent/US12033586B2/en
Publication of WO2023051099A1 publication Critical patent/WO2023051099A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display panel, a gate driving circuit and a driving method thereof.
  • the gate drive circuit is an important auxiliary circuit in the display panel.
  • Existing gate drive circuits include multiple cascaded shift register units.
  • the display refresh rate of the display panel provided with the gate driving circuit is relatively low.
  • the purpose of the present disclosure is to provide a display panel, a gate driving circuit and a driving method thereof, which can improve the display refresh rate.
  • a gate drive circuit comprising:
  • a plurality of drive units each of which includes a plurality of cascaded shift registers; each of the shift registers includes an input subcircuit, a first reset subcircuit, and an output subcircuit;
  • the input subcircuit is connected to the first cascade input terminal and the first node, and is used to control the potential of the first node under the potential control of the first cascade input terminal;
  • the output subcircuit is used to The potential of the control signal output terminal under the control of the potential of the first node;
  • the first reset subcircuit is connected with the first node and the second cascade input terminal, and is used for controlling the potential of the second cascade input terminal. reset the first node;
  • the first cascaded input terminals of the first-stage shift registers in each of the driving units are connected to different start signal terminals; there are one or more driving units in multiple driving units including reset A control subcircuit, the reset control subcircuit is connected to the second cascaded input terminal of the last-stage shift register and one or more of the start signal terminals, and is used to control the end stage according to the potential of the start signal terminal.
  • the potential of the second cascade input end of the shift register; for one drive unit, the start signal end connected to the first cascade input end of the first stage shift register is connected to the The start signal terminals connected to the reset control subcircuit are different.
  • the reset control subcircuit includes:
  • One or more first transistors, the control pole and the first pole of the first transistor are connected to the same start signal terminal, and the second pole of the first transistor is connected to the second Cascade input.
  • the input subcircuit includes:
  • a second transistor the control pole of the second transistor is connected to the first cascade input terminal, the first pole of the second transistor is connected to the first scanning signal terminal, and the second pole of the second transistor is connected to the first scanning signal terminal.
  • the first node is connected.
  • the first reset subcircuit includes:
  • control pole of the third transistor is connected to the second cascade input terminal, the first pole of the third transistor is connected to the second scanning signal terminal, and the second pole of the third transistor is connected to the second scanning signal terminal.
  • the first node is connected.
  • the output subcircuit includes:
  • a fourth transistor the control pole of the fourth transistor is connected to the first node, the first pole of the fourth transistor is connected to the first clock signal terminal, and the second pole of the fourth transistor is connected to the signal terminal output connection.
  • the output subcircuit also includes:
  • a bootstrap capacitor the first pole of the bootstrap capacitor is connected to the first node, and the second pole of the bootstrap capacitor is connected to the second pole of the fourth transistor.
  • the shift register also includes:
  • a pull-down control subcircuit connected to the second clock signal terminal and the second node, and used to control the potential of the second node according to the potential of the second clock signal terminal;
  • the pull-down sub-circuit is connected with the second node, the signal output terminal and the power signal terminal, and is used for controlling the connection between the signal output terminal and the power signal terminal under the potential control of the second node.
  • the shift register also includes:
  • the storage sub-circuit is connected to the second node and used for maintaining the potential of the second node.
  • the pull-down control subcircuit includes a fifth transistor, the control electrode and the first electrode of the fifth transistor are both connected to the second clock signal terminal, the second electrode of the fifth transistor is connected to the first Two-node connection;
  • the pull-down sub-circuit includes a sixth transistor, the control pole of the sixth transistor is connected to the second node, the first pole of the sixth transistor is connected to the power signal terminal, and the first pole of the sixth transistor is connected to the power signal terminal.
  • the two poles are connected to the signal output terminal;
  • the storage sub-circuit includes a storage capacitor, the first pole of the storage capacitor is connected to the power signal terminal, and the second pole of the storage capacitor is connected to the second node;
  • the shift register also includes:
  • a noise control subcircuit connected to the first node, the second node, and the power signal terminal, for controlling the connection of the second node to the power signal terminal under the control of the potential of the first node , and is further used for controlling the connection between the first node and the power signal terminal under the control of the potential of the second node.
  • the noise control subcircuit includes:
  • a seventh transistor the control pole of the seventh transistor is connected to the second node, the first pole of the seventh transistor is connected to the power signal terminal, and the second pole of the seventh transistor is connected to the first a node connection;
  • An eighth transistor the control electrode of the eighth transistor is connected to the first node, the first electrode of the eighth transistor is connected to the power signal terminal, and the second electrode of the eighth transistor is connected to the first node. Two-node connection.
  • the shift register also includes:
  • the second reset subcircuit is connected to the first node, the power signal terminal and the reset signal terminal, and is used to control the connection of the first node to the power signal terminal under the control of the reset signal terminal.
  • the second reset subcircuit includes:
  • a ninth transistor the control pole of the ninth transistor is connected to the reset signal terminal, the first pole of the ninth transistor is connected to the power signal terminal, and the second pole of the ninth transistor is connected to the first Two-node connection.
  • a display panel including the above-mentioned gate driving circuit.
  • a driving method of a gate driving circuit is provided, the driving method adopts the above-mentioned gate driving circuit, and the driving method includes:
  • the input subcircuit is controlled to control the potential of the first node under the control of the potential of the first cascade input terminal, and the output subcircuit is controlled at the potential of the first node controlling the potential of the lower control signal output terminal, so that the reset control subcircuit controls the potential of the second cascaded input terminal of the final stage shift register according to the potential of the initial signal terminal, so that the first reset subcircuit The first node is reset under the control of the potential of the second cascade input terminal.
  • the input sub-circuit is used to control the potential of the first node under the control of the potential of the first cascade input end to charge the first node;
  • the reset control sub-circuit The circuit is connected with the second cascaded input terminal of the final stage shift register and one or more start signal terminals, and is used to control the potential of the second cascaded input terminal according to the potential of the start signal terminal; at the same time, for a driving unit, the first The initial signal terminal connected to the first cascaded input terminal of the first-stage shift register is different from the initial signal terminal connected to the reset control subcircuit, so that the reset process of the first node of the last-stage shift register of a drive unit can be Simultaneously with the charging process of the first node of the first-stage shift register of another drive unit, the display delay of the device is reduced, and the display refresh rate is improved; at the same time, there is no need to set the virtual shift register in the related art, saving The limited
  • FIG. 1 is a schematic diagram of a driving unit in a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 2 is a block diagram of a shift register in a driving unit according to an embodiment of the present disclosure.
  • FIG. 3 is a circuit diagram of a shift register in a driving unit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a first driving unit in a gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a second driving unit in the gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a third driving unit in the gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a fourth driving unit in the gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 8 is an operation timing diagram of the gate driving circuit according to the embodiment of the present disclosure.
  • the transistors used in the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one pole is called the first pole, and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, can be a base, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base pole, the first pole may be an emitter, and the second pole may be a collector.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or, the The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the gate driving circuit disposed in the peripheral area of the display panel is often divided into a plurality of driving units.
  • Each driving unit includes a plurality of cascaded shift registers.
  • the last shift register in the plurality of cascaded shift registers is a virtual shift register, and the rest of the shift registers are effective shift registers.
  • the active shift register is connected to the pixel rows of the display panel.
  • the virtual shift register is not connected to the pixel row, and is only responsible for resetting the upper effective shift register.
  • the display driver chip needs to sequentially drive multiple driving units.
  • the virtual shift register in the driving unit needs to reset the effective shift register of the previous stage before switching to the next driving unit.
  • the cache (buffer) of the display driver chip needs to store the data line misalignment problem caused by the virtual shift register; meanwhile, each drive unit is equipped with a virtual shift register, which increases the cache of the display driver chip ( buffer) storage area and cost.
  • the virtual shift register is not connected to the pixel row, and the working process occupies the display time, which increases the display delay of the device and reduces the display refresh rate.
  • the gate driving circuit may include a plurality of driving units.
  • Each driving unit may include a plurality of cascaded shift registers 100 .
  • each shift register 100 may include an input subcircuit 1, a first reset subcircuit 3, and an output subcircuit 2, and the input subcircuit 1 may be connected to the first cascaded input terminal OUT(n ⁇ 1) connected to the first node N1 for controlling the potential of the first node N1 under the control of the potential of the first cascade input terminal OUT(n ⁇ 1).
  • the output sub-circuit 2 is used for controlling the potential of the signal output terminal OUT(n) under the control of the potential of the first node N1.
  • the first reset sub-circuit 3 is connected to the first node N1 and the second cascade input terminal OUT(n+1), and is used to reset the first node under the potential control of the second cascade input terminal OUT(n+1). N1 is reset.
  • the first cascade input terminal OUT(n-1) of the first-stage shift register 100 in each driving unit is connected to different start signal terminals STV.
  • one or more driving units include the reset control sub-circuit 9 .
  • the reset control subcircuit 9 is connected to the second cascaded input terminal OUT(n+1) of the final stage shift register 100 and one or more start signal terminals STV, and is used to control the first signal terminal STV according to the potential of the start signal terminal STV The potential of the cascade input OUT(n+1).
  • the start signal terminal STV connected to the first cascade input terminal OUT(n ⁇ 1) of the shift register 100 of the first stage is different from the start signal terminal STV connected to the reset control sub-circuit 9 .
  • the input sub-circuit 1 is used to control the potential of the first node N1 under the control of the potential of the first cascaded input terminal OUT(n-1), so as to control the potential of the first node N1 Charging;
  • the reset control subcircuit 9 is connected with the second cascaded input terminal OUT (n+1) of the final stage shift register 100 and one or more start signal terminals STV, and is used for controlling the potential according to the start signal terminal STV The potential of the second cascade input terminal OUT(n+1); meanwhile, for a drive unit, the initial signal terminal STV connected to the first cascade input terminal OUT(n-1) of the first stage shift register 100 is connected to The start signal terminal STV connected to the reset control subcircuit 9 is different, so that the reset process of the first node N1 of the last stage shift register 100 of one driving unit can be compared with the first node N1 of the first stage shift register 100 of another driving unit.
  • the charging process of one node N1 is carried out at the same time, which reduces the display delay of the device and improves the display refresh rate; at the same time, there is no need to set the virtual shift register 100 in the related art, saving the storage resources of the buffer (buffer) in the display driver chip , reducing the storage area and cost of the buffer of the display driver chip.
  • the input sub-circuit 1 is used to control the potential of the first node N1.
  • the input sub-circuit 1 may be connected to the first node N1, the first scanning signal terminal CN and the first cascade input terminal OUT(n ⁇ 1).
  • the input sub-circuit 1 is used for controlling the connection of the first scanning signal terminal CN to the first node N1 under the control of the potential of the first cascade input terminal OUT(n ⁇ 1).
  • the input sub-circuit 1 may include a second transistor T2.
  • the control pole of the second transistor T2 is connected to the first cascade input terminal OUT(n-1), the first pole of the second transistor T2 is connected to the first scanning signal terminal CN, and the second pole of the second transistor T2 is connected to the first scanning signal terminal CN.
  • a node N1 is connected.
  • the first reset subcircuit 3 is connected to the first node N1, the second scan signal terminal CNB and the second cascade input terminal OUT(n+1), for the second cascade Under the control of the potential of the input terminal OUT(n+1), the first node N1 is controlled to be connected to the second scanning signal terminal CNB, so as to reset the first node N1.
  • the first reset subcircuit 3 may include a third transistor T3. The control pole of the third transistor T3 is connected to the second cascaded input terminal OUT(n+1), the first pole of the third transistor T3 is connected to the second scanning signal terminal CNB, and the second pole of the third transistor T3 is connected to the second scanning signal terminal CNB. A node N1 is connected.
  • the output sub-circuit 2 is used to control the potential of the signal output terminal OUT(n) under the control of the potential of the first node N1.
  • the output sub-circuit 2 is connected with the signal output terminal OUT(n), the first node N1 and the first clock signal terminal CK1, and is used to control the signal output terminal OUT(n) and the first clock signal terminal CK1 under the control of the potential of the first node N1.
  • a clock signal terminal CK1 is connected.
  • the output sub-circuit 2 may include a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is connected to the first node N1, the first electrode of the fourth transistor T4 is connected to the first clock signal terminal CK1, and the second electrode of the fourth transistor T4 is connected to the signal output terminal OUT(n).
  • the output sub-circuit 2 may also include a bootstrap capacitor C1.
  • the first pole of the bootstrap capacitor C1 is connected to the first node N1, and the second pole of the bootstrap capacitor C1 is connected to the second pole of the fourth transistor T4.
  • the shift register 100 in the embodiment of the present disclosure may further include a pull-down control sub-circuit 4 and a pull-down sub-circuit 5 .
  • the pull-down control sub-circuit 4 can be connected with the second clock signal terminal CK2 and the second node N2, and is used for controlling the potential of the second node N2 according to the potential of the second clock signal terminal CK2.
  • the pull-down control sub-circuit 4 may include a fifth transistor T5. Both the control electrode and the first electrode of the fifth transistor T5 are connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is connected to the second node N2.
  • the pull-down sub-circuit 5 is connected to the second node N2, the signal output terminal OUT(n) and the power signal terminal VGL, and is used to control the connection of the signal output terminal OUT(n) to the power signal terminal VGL under the control of the potential of the second node N2 .
  • the power signal terminal VGL can output a constant low voltage.
  • the pull-down sub-circuit 5 includes a sixth transistor T6.
  • the control electrode of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the power signal terminal VGL, and the second electrode of the sixth transistor T6 is connected to the signal output terminal OUT(n).
  • the shift register 100 in the embodiment of the present disclosure may further include a storage sub-circuit 6 .
  • the storage sub-circuit 6 is connected to the second node N2 for maintaining the potential of the second node N2.
  • the storage sub-circuit 6 may include a storage capacitor C2, the first pole of the storage capacitor C2 is connected to the power signal terminal VGL, and the second pole of the storage capacitor C2 is connected to the second node N2.
  • the shift register 100 of the embodiment of the present disclosure may further include a noise control subcircuit 7 .
  • the noise control sub-circuit 7 is connected to the first node N1, the second node N2 and the power signal terminal VGL, and is used to control the connection of the second node N2 to the power signal terminal VGL under the control of the potential of the first node N1, and is also used for The potential of the second node N2 controls the first node N1 to be connected to the power signal terminal VGL.
  • the noise control sub-circuit 7 may include a seventh transistor T7 and an eighth transistor T8.
  • the control electrode of the seventh transistor T7 is connected to the second node N2, the first electrode of the seventh transistor T7 is connected to the power signal terminal VGL, and the second electrode of the seventh transistor T7 is connected to the first node N1.
  • the control electrode of the eighth transistor T8 is connected to the first node N1, the first electrode of the eighth transistor T8 is connected to the power signal terminal VGL, and the second electrode of the eighth transistor T8 is connected to the second node N2.
  • the shift register 100 in the embodiment of the present disclosure may further include a second reset subcircuit 8 .
  • the second reset sub-circuit 8 is connected to the first node N1, the power signal terminal VGL and the reset signal terminal RESET, and is used to control the first node N1 to be connected to the power signal terminal VGL under the control of the reset signal terminal RESET.
  • the second reset subcircuit 8 may include a ninth transistor T9. The control electrode of the ninth transistor T9 is connected to the reset signal terminal RESET, the first electrode of the ninth transistor T9 is connected to the power signal terminal VGL, and the second electrode of the ninth transistor T9 is connected to the second node N2.
  • the first cascaded input terminal OUT(n-1) of the first-stage shift register 100 in each of the above driving units is connected to different start signal terminals STV.
  • the four driving units may include a first driving unit, a second driving unit, a third driving unit and a fourth driving unit.
  • the first cascaded input terminal OUT(n-1) of the first-stage shift register 100 in the first driving unit is connected to the first start signal terminal STV1, that is, STV(h) in FIG.
  • one or more driving units include the reset control sub-circuit 9 .
  • each drive unit includes a reset control sub-circuit 9 .
  • the reset control subcircuit 9 is connected to the second cascaded input terminal OUT(n+1) of the final stage shift register 100 and one or more start signal terminals STV, and is used to control the first signal terminal STV according to the potential of the start signal terminal STV The potential of the cascade input OUT(n+1).
  • the plurality of start signal terminals STV may include STV(x), STV(y), STV(z) and so on.
  • the start signal terminal STV connected to the first cascade input terminal OUT(n-1) of the first stage shift register 100 is different from the start signal terminal STV connected to the reset control sub-circuit 9, and reset
  • the start signal terminal STV connected to the control subcircuit 9 is the same as the start signal terminal STV connected to the first-stage shift register 100 of at least one of the other drive units.
  • each reset control sub-circuit 9 may include three first transistors T1; for the above-mentioned first drive unit, as shown in FIG. Both the control pole and the first pole of the transistor T1 are connected to the second start signal terminal STV2, the control pole and the first pole of the other first transistor T1 are both connected to the third start signal terminal STV3, and the last first transistor T1 The control poles and first poles of the three first transistors T1 are all connected to the fourth start signal terminal STV4, and the second poles of the three first transistors T1 are all connected to the second cascaded input terminal OUT(n+1) of the final stage shift register 100 ).
  • the control electrode and the first electrode of one first transistor T1 are both connected to the first start signal terminal STV1, and the control electrode and the first electrode of the other first transistor T1 are both connected to the first start signal terminal STV1. It is connected to the third start signal terminal STV3, and the control electrode and the first electrode of the last first transistor T1 are both connected to the fourth start signal terminal STV4.
  • the control electrode and the first electrode of the last first transistor T1 are both connected to the fourth start signal terminal STV4.
  • control electrode and the first electrode of one first transistor T1 are both connected to the second start signal terminal STV2, and the control electrode and the first electrode of the other first transistor T1 Both are connected to the first start signal terminal STV1, and the control electrode and the first electrode of the last first transistor T1 are both connected to the fourth start signal terminal STV4.
  • the control electrode and the first electrode of one first transistor T1 are both connected to the second start signal terminal STV2, and the control electrode and the first electrode of the other first transistor T1 Both are connected to the third start signal terminal STV3, and the control electrode and the first electrode of the last first transistor T1 are both connected to the first start signal terminal STV1.
  • the above-mentioned first transistor T1 can be replaced by a diode, the anode of the diode can be connected to the start signal terminal STV, and the cathode of the diode can be connected to the second cascaded input terminal OUT(n+1) of the last-stage shift register 100 )connect.
  • the reset control sub-circuit 9 when the reset control sub-circuit 9 is only connected to one start signal terminal STV, the reset control sub-circuit 9 can be a wire, so that the second cascaded input terminal OUT(n +1) Short circuit with the start signal terminal STV.
  • the embodiment of the present disclosure also provides a driving method of a gate driving circuit.
  • the driving method may use the gate driving circuit described in any one of the above implementation modes.
  • the driving method may include: for the final stage shift register 100, make the input subcircuit 1 control the potential of the first node N1 under the control of the potential of the first cascade input terminal OUT(n-1), and make the output subcircuit 2 control the potential of the first node N1 at The potential of the first node N1 controls the potential of the lower control signal output terminal OUT(n), so that the reset control subcircuit 9 controls the second cascaded input terminal OUT(n) of the last stage shift register 100 according to the potential of the start signal terminal STV. +1), so that the first reset sub-circuit 3 resets the first node N1 under the control of the potential of the second cascade input terminal OUT(n+1).
  • the working process of the gate driving circuit provided by the present disclosure will be described below with reference to the circuit timing diagram shown in FIG. 8 .
  • the shift register units of each level in the gate driving circuit are correspondingly connected to each pixel row in the display panel. All transistors in the gate drive circuit are N-type transistors.
  • the first cascade input terminal OUT(n-1) of the first-stage shift register 100 of one drive unit is connected to the start signal terminal STV (x), and the first pole and the control pole of the reset transistor of the drive unit are connected to the start signal terminal STV (y); the first cascaded input terminal OUT of the first stage shift register 100 of another drive unit (n-1) is connected to the start signal terminal STV(y).
  • the first stage S1 corresponds to the working process of a drive unit.
  • the second transistor T2 is turned on, and the signal output terminals of the shift registers 100 of each stage OUT(n) outputs high level sequentially to scan multiple pixel rows progressively.
  • the second cascaded input terminal OUT(n+1) of each stage of shift register 100 receives the signal output terminal OUT(n) of the next stage shift register 100 to output high level to reset the first node N1.
  • the second stage S2 corresponds to the working process of another drive unit.
  • the start signal terminal STV(y) is at a high level, due to the first pole and the control pole of the reset transistor of the last drive unit Both are connected to the start signal terminal STV(y), so that the reset transistor is turned on, and then the second cascaded input terminal OUT(n+1) of the final stage shift register 100 of the previous drive unit is written into a high level, To reset the first node N1 of the final shift register 100 of the last driving unit.
  • the embodiments of the present disclosure also provide a display panel.
  • the display panel may include the gate driving circuit described in any one of the above implementation manners.
  • the display panel may be an OLED display panel, but this is not specifically limited in the embodiments of the present disclosure.
  • the display panel, the gate driving circuit and the driving method of the gate driving circuit provided by the embodiments of the present disclosure belong to the same inventive concept, and the descriptions of relevant details and beneficial effects can be referred to each other, and will not be repeated here.

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Abstract

一种显示面板、栅极驱动电路及其驱动方法，栅极驱动电路包括多个驱动单元，各驱动单元中第一级移位寄存器（100）的第一级联输入端OUT(n-1)连接于不同的起始信号端STV；多个驱动单元中存在一个或多个驱动单元包括复位控制子电路（9），复位控制子电路（9）与末级移位寄存器（100）的第二级联输入端OUT(n+1)以及一个或多个起始信号端STV连接，并用于根据起始信号端STV的电位控制第二级联输入端OUT(n+1)的电位；对于一个驱动单元，第一级移位寄存器（100）的第一级联输入端OUT(n-1)连接的起始信号端STV与复位控制子电路（9）连接的起始信号端STV不同。显示面板、栅极驱动电路及其驱动方法能够提高显示刷新率。

Description

显示面板、栅极驱动电路及其驱动方法 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、栅极驱动电路及其驱动方法。
背景技术
栅极驱动电路是显示面板中一种重要的辅助电路。现有的栅极驱动电路包括多个级联的移位寄存单元。然而，设有该栅极驱动电路的显示面板的显示刷新率较低。
发明内容
本公开的目的在于提供一种显示面板、栅极驱动电路及其驱动方法，能够提高显示刷新率。
根据本公开的一个方面，提供一种栅极驱动电路，包括：
多个驱动单元，各所述驱动单元包括多个级联的移位寄存器；各所述移位寄存器包括输入子电路、第一复位子电路以及输出子电路；
所述输入子电路与第一级联输入端以及第一节点连接，用于在所述第一级联输入端的电位控制下控制所述第一节点的电位；所述输出子电路用于在所述第一节点的电位控制下控制信号输出端的电位；所述第一复位子电路与所述第一节点以及第二级联输入端连接，用于在所述第二级联输入端的电位控制下对所述第一节点进行复位；
其中，各所述驱动单元中第一级移位寄存器的所述第一级联输入端连 接于不同的起始信号端；多个所述驱动单元中存在一个或多个所述驱动单元包括复位控制子电路，所述复位控制子电路与末级移位寄存器的第二级联输入端以及一个或多个所述起始信号端连接，并用于根据所述起始信号端的电位控制所述末级移位寄存器的所述第二级联输入端的电位；对于一个所述驱动单元，所述第一级移位寄存器的所述第一级联输入端连接的所述起始信号端与所述复位控制子电路连接的所述起始信号端不同。
进一步地，所述复位控制子电路包括：
一个或多个第一晶体管，所述第一晶体管的控制极与第一极均连接于同一所述起始信号端，所述第一晶体管的第二极连接于末级移位寄存器的第二级联输入端。
进一步地，所述输入子电路包括：
第二晶体管，所述第二晶体管的控制极与所述第一级联输入端连接，所述第二晶体管的第一极与第一扫描信号端连接，所述第二晶体管的第二极与所述第一节点连接。
进一步地，所述第一复位子电路包括：
第三晶体管，所述第三晶体管的控制极与所述第二级联输入端连接，所述第三晶体管的第一极与第二扫描信号端连接，所述第三晶体管的第二极与所述第一节点连接。
进一步地，所述输出子电路包括：
第四晶体管，所述第四晶体管的控制极与所述第一节点连接，所述第四晶体管的第一极与第一时钟信号端连接，所述第四晶体管的第二极与所述信号输出端连接。
进一步地，所述输出子电路还包括：
自举电容，所述自举电容的第一极连接于所述第一节点，所述自举电 容的第二极连接于所述第四晶体管的第二极。
进一步地，所述移位寄存器还包括：
下拉控制子电路，与第二时钟信号端和第二节点连接，用于根据所述第二时钟信号端的电位控制所述第二节点的电位；
下拉子电路，与所述第二节点、所述信号输出端以及电源信号端连接，用于在所述第二节点的电位控制下控制所述信号输出端与所述电源信号端连接。
进一步地，所述移位寄存器还包括：
存储子电路，连接于所述第二节点，用于对所述第二节点的电位进行保持。
进一步地，所述下拉控制子电路包括第五晶体管，所述第五晶体管的控制极以及第一极均与所述第二时钟信号端连接，所述第五晶体管的第二极与所述第二节点连接；
所述下拉子电路包括第六晶体管，所述第六晶体管的控制极与所述第二节点连接，所述第六晶体管的第一极与所述电源信号端连接，所述第六晶体管的第二极与所述信号输出端连接；
所述存储子电路包括存储电容，所述存储电容的第一极与所述电源信号端连接，所述存储电容的第二极与所述第二节点连接；
进一步地，所述移位寄存器还包括：
噪声控制子电路，与所述第一节点、所述第二节点以及所述电源信号端连接，用于在所述第一节点的电位控制下控制所述第二节点与所述电源信号端连接，还用于在所述第二节点的电位控制下控制所述第一节点与所述电源信号端连接。
进一步地，所述噪声控制子电路包括：
第七晶体管，所述第七晶体管的控制极与所述第二节点连接，所述第七晶体管的第一极与所述电源信号端连接，所述第七晶体管的第二极与所述第一节点连接；
第八晶体管，所述第八晶体管的控制极与所述第一节点连接，所述第八晶体管的第一极与所述电源信号端连接，所述第八晶体管的第二极与所述第二节点连接。
进一步地，所述移位寄存器还包括：
第二复位子电路，与所述第一节点、电源信号端以及复位信号端连接，用于在复位信号端的控制下控制所述第一节点与所述电源信号端连接。
进一步地，所述第二复位子电路包括：
第九晶体管，所述第九晶体管的控制极与所述复位信号端连接，所述第九晶体管的第一极与所述电源信号端连接，所述第九晶体管的第二极与所述第二节点连接。
根据本公开的一个方面，提供一种显示面板，包括上述的栅极驱动电路。
根据本公开的一个方面，提供一种栅极驱动电路的驱动方法，所述驱动方法采用上述的栅极驱动电路，所述驱动方法包括：
对于所述末级移位寄存器，使所述输入子电路在所述第一级联输入端的电位控制下控制所述第一节点的电位，使所述输出子电路在所述第一节点的电位控制下控制信号输出端的电位，使所述复位控制子电路根据所述起始信号端的电位控制末级移位寄存器的所述第二级联输入端的电位，使所述第一复位子电路在所述第二级联输入端的电位控制下对所述第一节点进行复位。
本公开的显示面板、栅极驱动电路及其驱动方法，该输入子电路用于在第一级联输入端的电位的控制下控制第一节点的电位，以对第一节点进行 充电；复位控制子电路与末级移位寄存器的第二级联输入端以及一个或多个起始信号端连接，并用于根据起始信号端的电位控制第二级联输入端的电位；同时，对于一个驱动单元，第一级移位寄存器的第一级联输入端连接的起始信号端与复位控制子电路连接的起始信号端不同，从而使一个驱动单元的末级移位寄存器的第一节点的复位过程可以与另一个驱动单元的第一级移位寄存器的第一节点的充电过程同时进行，降低了设备的显示延迟，提高了显示刷新率；同时，无需设置相关技术中的虚拟移位寄存器，节约了显示驱动芯片内有限的缓存(buffer)的存储资源，降低了显示驱动芯片的缓存(buffer)的存储面积与成本。
附图说明
图1是本公开实施方式的栅极驱动电路中驱动单元的示意图。
图2是本公开实施方式的驱动单元中移位寄存器的框图。
图3是本公开实施方式的驱动单元中移位寄存器的电路图。
图4是本公开实施方式的栅极驱动电路中第一驱动单元的示意图。
图5是本公开实施方式的栅极驱动电路中第二驱动单元的示意图。
图6是本公开实施方式的栅极驱动电路中第三驱动单元的示意图。
图7是本公开实施方式的栅极驱动电路中第四驱动单元的示意图。
图8是本公开实施方式的栅极驱动电路的工作时序图。
附图标记说明：1、输入子电路；2、输出子电路；3、第一复位子电路；4、下拉控制子电路；5、下拉子电路；6、存储子电路；7、噪声控制子电路；8、第二复位子电路；9、复位控制子电路；100、移位寄存器。
具体实施方式
这里将详细地对示例性实施方式进行说明，其示例表示在附图中。下 面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施方式中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置的例子。
在本公开使用的术语是仅仅出于描述特定实施方式的目的，而非旨在限制本公开。除非另作定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“多个”或者“若干”表示两个及两个以上。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。在本公开说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
本公开中采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所 述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
相关技术中，光场显示的数据量大，为了节省显示资源，常常将设于显示面板的外围区的栅极驱动电路划分为多个驱动单元。各驱动单元包括多个级联的移位寄存器。多个级联的移位寄存器中的末级移位寄存器为虚拟移位寄存器，其余移位寄存器为有效移位寄存器。该有效移位寄存器与显示面板的像素行连接。该虚拟移位寄存器不与像素行连接，仅负责对上一级有效移位寄存器进行复位。在显示面板的显示过程中，显示驱动芯片需要依次驱动多个驱动单元。在一个驱动单元的驱动过程完成后，需要使该驱动单元中的虚拟移位寄存器对上一级有效移位寄存器进行复位，才能切换到下一个驱动单元。这一过程中，需要显示驱动芯片的缓存(buffer)存储由于虚拟移位寄存器所造成的的数据行错位问题；同时，各驱动单元均设有虚拟移位寄存器，增加了显示驱动芯片的缓存(buffer)的存储面积与成本。此外，虚拟移位寄存器不与像素行连接，且工作过程占用了显示时间，增加了设备的显示延迟，降低了显示刷新率。
本公开实施方式提供一种栅极驱动电路。如图1所示，该栅极驱动电路可以包括多个驱动单元。各驱动单元可以包括多个级联的移位寄存器100。如图2和图3所示，各移位寄存器100可以包括输入子电路1、第一复位子电路3以及输出子电路2，该输入子电路1可以与第一级联输入端OUT(n-1)以及第一节点N1连接，用于在第一级联输入端OUT(n-1)的电位的控制下控制第一节点N1的电位。该输出子电路2用于在第一节点N1的电位控制下控制信号输出端OUT(n)的电位。该第一复位子电路3与第一节点N1以及第二级联输入端OUT(n+1)连接，用于在第二级联输入端OUT(n+1)的电位控制下对第一节点N1进行复位。
其中，各驱动单元中第一级移位寄存器100的第一级联输入端OUT(n-1)连接于不同的起始信号端STV。多个驱动单元中存在一个或多个驱动单元包括复位控制子电路9。该复位控制子电路9与末级移位寄存器100的第二级联 输入端OUT(n+1)以及一个或多个起始信号端STV连接，并用于根据起始信号端STV的电位控制第二级联输入端OUT(n+1)的电位。对于一个驱动单元，第一级移位寄存器100的第一级联输入端OUT(n-1)连接的起始信号端STV与复位控制子电路9连接的起始信号端STV不同。
本公开实施方式的栅极驱动电路，该输入子电路1用于在第一级联输入端OUT(n-1)的电位的控制下控制第一节点N1的电位，以对第一节点N1进行充电；复位控制子电路9与末级移位寄存器100的第二级联输入端OUT(n+1)以及一个或多个起始信号端STV连接，并用于根据起始信号端STV的电位控制第二级联输入端OUT(n+1)的电位；同时，对于一个驱动单元，第一级移位寄存器100的第一级联输入端OUT(n-1)连接的起始信号端STV与复位控制子电路9连接的起始信号端STV不同，从而使一个驱动单元的末级移位寄存器100的第一节点N1的复位过程可以与另一个驱动单元的第一级移位寄存器100的第一节点N1的充电过程同时进行，降低了设备的显示延迟，提高了显示刷新率；同时，无需设置相关技术中的虚拟移位寄存器100，节约了显示驱动芯片内的缓存(buffer)的存储资源，降低了显示驱动芯片的缓存(buffer)的存储面积与成本。
下面对本公开实施方式的移位寄存单元的各部分进行详细描述：
如图2和图3所示，该输入子电路1用于控制第一节点N1的电位。其中，该输入子电路1可以与第一节点N1、第一扫描信号端CN以及第一级联输入端OUT(n-1)连接。该输入子电路1用于在第一级联输入端OUT(n-1)的电位控制下控制第一扫描信号端CN与第一节点N1连接。举例而言，该输入子电路1可以包括第二晶体管T2。该第二晶体管T2的控制极与第一级联输入端OUT(n-1)连接，第二晶体管T2的第一极与第一扫描信号端CN连接，第二晶体管T2的第二极与第一节点N1连接。
如图2和图3所示，该第一复位子电路3与第一节点N1、第二扫描信号端CNB以及第二级联输入端OUT(n+1)连接，用于在第二级联输入端 OUT(n+1)的电位控制下控制第一节点N1与第二扫描信号端CNB连接，以对第一节点N1进行复位。举例而言，该第一复位子电路3可以包括第三晶体管T3。该第三晶体管T3的控制极与第二级联输入端OUT(n+1)连接，第三晶体管T3的第一极与第二扫描信号端CNB连接，第三晶体管T3的第二极与第一节点N1连接。
如图2和图3所示，该输出子电路2用于在第一节点N1的电位控制下控制信号输出端OUT(n)的电位。其中，该输出子电路2与信号输出端OUT(n)、第一节点N1以及第一时钟信号端CK1连接，用于在第一节点N1的电位控制下控制信号输出端OUT(n)与第一时钟信号端CK1连接。举例而言，该输出子电路2可以包括第四晶体管T4。该第四晶体管T4的控制极与第一节点N1连接，第四晶体管T4的第一极与第一时钟信号端CK1连接，第四晶体管T4的第二极与信号输出端OUT(n)连接。此外，该输出子电路2还可以包括自举电容C1。该自举电容C1的第一极连接于第一节点N1，该自举电容C1的第二极连接于第四晶体管T4的第二极。在第四晶体管T4处于打开状态且第一时钟信号端CK1为高电平时，所设置的自举电容C1可以提高第一节点N1的电位，以进一步打开第四晶体管T4。
如图2和图3所示，本公开实施方式的移位寄存器100还可以包括下拉控制子电路4和下拉子电路5。该下拉控制子电路4可以与第二时钟信号端CK2和第二节点N2连接，用于根据第二时钟信号端CK2的电位控制第二节点N2的电位。该下拉控制子电路4可以包括第五晶体管T5。该第五晶体管T5的控制极以及第一极均与第二时钟信号端CK2连接，第五晶体管T5的第二极与第二节点N2连接。该下拉子电路5与第二节点N2、信号输出端OUT(n)以及电源信号端VGL连接，用于在第二节点N2的电位控制下控制信号输出端OUT(n)与电源信号端VGL连接。举例而言，该电源信号端VGL能够恒定输出低电压。该下拉子电路5包括第六晶体管T6。该第六晶体管T6的控制极与第二节点N2连接，第六晶体管T6的第一极与电源信号端VGL连接，第 六晶体管T6的第二极与信号输出端OUT(n)连接。本公开实施方式的移位寄存器100还可以包括存储子电路6。该存储子电路6连接于第二节点N2，用于对第二节点N2的电位进行保持。该存储子电路6可以包括存储电容C2，该存储电容C2的第一极与电源信号端VGL连接，存储电容C2的第二极与第二节点N2连接。
如图2和图3所示，本公开实施方式的移位寄存器100还可以包括噪声控制子电路7。该噪声控制子电路7与第一节点N1、第二节点N2以及电源信号端VGL连接，用于在第一节点N1的电位控制下控制第二节点N2与电源信号端VGL连接，还用于在第二节点N2的电位控制下控制第一节点N1与电源信号端VGL连接。举例而言，该噪声控制子电路7可以包括第七晶体管T7和第八晶体管T8。该第七晶体管T7的控制极与第二节点N2连接，第七晶体管T7的第一极与电源信号端VGL连接，第七晶体管T7的第二极与第一节点N1连接。该第八晶体管T8的控制极与第一节点N1连接，第八晶体管T8的第一极与电源信号端VGL连接，第八晶体管T8的第二极与第二节点N2连接。
如图2和图3所示，本公开实施方式的移位寄存器100还可以包括第二复位子电路8。该第二复位子电路8与第一节点N1、电源信号端VGL以及复位信号端RESET连接，用于在复位信号端RESET的控制下控制第一节点N1与电源信号端VGL连接。举例而言，该第二复位子电路8可以包括第九晶体管T9。该第九晶体管T9的控制极与复位信号端RESET连接，第九晶体管T9的第一极与电源信号端VGL连接，第九晶体管T9的第二极与第二节点N2连接。
上述各个驱动单元中第一级移位寄存器100的第一级联输入端OUT(n-1)连接于不同的起始信号端STV。以栅极驱动电路包括四个驱动单元为例，该四个驱动单元可以包括第一驱动单元、第二驱动单元、第三驱动单元以及第四驱动单元。如图4所示，第一驱动单元中第一级移位寄存器100 的第一级联输入端OUT(n-1)连接于第一起始信号端STV1，即图1中的STV(h)为STV1；如图5所示，第二驱动单元中第一级移位寄存器100的第一级联输入端OUT(n-1)连接于第二起始信号端STV2，即图1中的STV(h)为STV2；如图6所示，第三驱动单元中第一级移位寄存器100的第一级联输入端OUT(n-1)连接于第三起始信号端STV3，即图1中的STV(h)为STV3；如图7所示，第四驱动单元中第一级移位寄存器100的第一级联输入端OUT(n-1)连接于第四起始信号端STV4，即图1中的STV(h)为STV4。
多个驱动单元中存在一个或多个驱动单元包括复位控制子电路9。进一步地，各驱动单元均包括复位控制子电路9。该复位控制子电路9与末级移位寄存器100的第二级联输入端OUT(n+1)以及一个或多个起始信号端STV连接，并用于根据起始信号端STV的电位控制第二级联输入端OUT(n+1)的电位。该多个起始信号端STV可以包括STV(x)、STV(y)、STV(z)等。对于任意一个驱动单元，第一级移位寄存器100的第一级联输入端OUT(n-1)连接的起始信号端STV与复位控制子电路9连接的起始信号端STV不同，且复位控制子电路9连接的起始信号端STV与其它驱动单元中至少一个驱动单元的第一级移位寄存器100连接的起始信号端STV相同。
以复位控制子电路9与多个起始信号端STV连接为例，各复位控制子电路9可以包括三个第一晶体管T1；对于上述的第一驱动单元，如图4所示，一个第一晶体管T1的控制极与第一极均连接于第二起始信号端STV2，另一个第一晶体管T1的控制极与第一极均连接于第三起始信号端STV3，最后一个第一晶体管T1的控制极与第一极均连接于第四起始信号端STV4，且三个第一晶体管T1的第二极均连接于末级移位寄存器100的第二级联输入端OUT(n+1)。对于上述的第二驱动单元，如图5所示，一个第一晶体管T1的控制极与第一极均连接于第一起始信号端STV1，另一个第一晶体管T1的控制极与第一极均连接于第三起始信号端STV3，最后一个第一晶体管T1的控制极与第一极均连接于第四起始信号端STV4。对于上述的第三驱动单元，如图 6所示，一个第一晶体管T1的控制极与第一极均连接于第二起始信号端STV2，另一个第一晶体管T1的控制极与第一极均连接于第一起始信号端STV1，最后一个第一晶体管T1的控制极与第一极均连接于第四起始信号端STV4。对于上述的第四驱动单元，如图7所示，一个第一晶体管T1的控制极与第一极均连接于第二起始信号端STV2，另一个第一晶体管T1的控制极与第一极均连接于第三起始信号端STV3，最后一个第一晶体管T1的控制极与第一极均连接于第一起始信号端STV1。此外，上述的第一晶体管T1可以用二极管代替，该二极管的正极可以与起始信号端STV连接，该二极管的负极可以与末级移位寄存器100的第二级联输入端OUT(n+1)连接。
需要说明的是，在复位控制子电路9仅与一个起始信号端STV连接时，该复位控制子电路9可以为导线，以将末级移位寄存器100的第二级联输入端OUT(n+1)与起始信号端STV短接。
本公开实施方式还提供一种栅极驱动电路的驱动方法。该驱动方法可以采用上述任一实施方式所述的栅极驱动电路。该驱动方法可以包括：对于末级移位寄存器100，使输入子电路1在第一级联输入端OUT(n-1)的电位控制下控制第一节点N1的电位，使输出子电路2在第一节点N1的电位控制下控制信号输出端OUT(n)的电位，使复位控制子电路9根据起始信号端STV的电位控制末级移位寄存器100的第二级联输入端OUT(n+1)的电位，使第一复位子电路3在第二级联输入端OUT(n+1)的电位控制下对第一节点N1进行复位。
下面结合图8所示的电路时序图对本公开提供的栅极驱动电路工作过程作以描述。该栅极驱动电路中的各级移位寄存单元与显示面板中的各像素行对应连接。该栅极驱动电路中所有晶体管均为N型晶体管。
如图8所示，对于栅极驱动电路中的任意两个驱动单元，一个驱动单元的第一级移位寄存器100的第一级联输入端OUT(n-1)连接于起始信号端STV(x)，且该驱动单元的复位晶体管的第一极以及控制极均连接于起始信号 端STV(y)；另一个驱动单元的第一级移位寄存器100的第一级联输入端OUT(n-1)连接于起始信号端STV(y)。
如图8所示，该第一阶段S1对应于一个驱动单元的工作过程，在起始信号端STV(x)为高电平时，第二晶体管T2打开，各级移位寄存器100的信号输出端OUT(n)依次输出高电平，以对多个像素行进行逐行扫描。对于第一级至倒数第二级移位寄存器100，各级移位寄存器100的第二级联输入端OUT(n+1)接收下一级移位寄存器100的信号输出端OUT(n)输出的高电平，以对第一节点N1进行复位。
如图8所示，该第二阶段S2对应于另一个驱动单元的工作过程，在起始信号端STV(y)为高电平时，由于上一驱动单元的复位晶体管的第一极以及控制极均连接于起始信号端STV(y)，从而使复位晶体管打开，进而使上一驱动单元的末级移位寄存器100的第二级联输入端OUT(n+1)写入高电平，以对上一驱动单元的末级移位寄存器100的第一节点N1进行复位。
本公开实施方式还提供一种显示面板。该显示面板可以包括上述任一实施方式所述的栅极驱动电路。该显示面板可以为OLED显示面板，但本公开实施方式对此不做特殊限定。
本公开实施方式提供的显示面板、栅极驱动电路及栅极驱动电路的驱动方法属于同一发明构思，相关细节及有益效果的描述可互相参见，不再进行赘述。
以上所述仅是本公开的较佳实施方式而已，并非对本公开做任何形式上的限制，虽然本公开已以较佳实施方式揭露如上，然而并非用以限定本公开，任何熟悉本专业的技术人员，在不脱离本公开技术方案的范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施方式，但凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施方式所作的任何简单修改、等同变化与修饰，均仍属于本公开技术方案的范围 内。

Claims (15)

  1. 一种栅极驱动电路，其特征在于，包括：
    多个驱动单元，各所述驱动单元包括多个级联的移位寄存器；各所述移位寄存器包括输入子电路、第一复位子电路以及输出子电路；
    所述输入子电路与第一级联输入端以及第一节点连接，用于在所述第一级联输入端的电位控制下控制所述第一节点的电位；所述输出子电路用于在所述第一节点的电位控制下控制信号输出端的电位；所述第一复位子电路与所述第一节点以及第二级联输入端连接，用于在所述第二级联输入端的电位控制下对所述第一节点进行复位；
    其中，各所述驱动单元中第一级移位寄存器的所述第一级联输入端连接于不同的起始信号端；多个所述驱动单元中存在一个或多个所述驱动单元包括复位控制子电路，所述复位控制子电路与末级移位寄存器的第二级联输入端以及一个或多个所述起始信号端连接，并用于根据所述起始信号端的电位控制所述末级移位寄存器的所述第二级联输入端的电位；对于一个所述驱动单元，所述第一级移位寄存器的所述第一级联输入端连接的所述起始信号端与所述复位控制子电路连接的所述起始信号端不同。
  2. 根据权利要求1所述的栅极驱动电路，其特征在于，所述复位控制子电路包括：
    一个或多个第一晶体管，所述第一晶体管的控制极与第一极均连接于同一所述起始信号端，所述第一晶体管的第二极连接于末级移位寄存器的第二级联输入端。
  3. 根据权利要求1所述的栅极驱动电路，其特征在于，所述输入子电路包括：
    第二晶体管，所述第二晶体管的控制极与所述第一级联输入端连接，所述第二晶体管的第一极与第一扫描信号端连接，所述第二晶体管的第二极与所述第一节点连接。
  4. 根据权利要求1所述的栅极驱动电路，其特征在于，所述第一复位子电路包括：
    第三晶体管，所述第三晶体管的控制极与所述第二级联输入端连接，所述第三晶体管的第一极与第二扫描信号端连接，所述第三晶体管的第二极与所述第一节点连接。
  5. 根据权利要求1所述的栅极驱动电路，其特征在于，所述输出子电路包括：
    第四晶体管，所述第四晶体管的控制极与所述第一节点连接，所述第四晶体管的第一极与第一时钟信号端连接，所述第四晶体管的第二极与所述信号输出端连接。
  6. 根据权利要求5所述的栅极驱动电路，其特征在于，所述输出子电路还包括：
    自举电容，所述自举电容的第一极连接于所述第一节点，所述自举电容的第二极连接于所述第四晶体管的第二极。
  7. 根据权利要求1-6任一项所述的栅极驱动电路，其特征在于，所述移位寄存器还包括：
    下拉控制子电路，与第二时钟信号端和第二节点连接，用于根据所述第二时钟信号端的电位控制所述第二节点的电位；
    下拉子电路，与所述第二节点、所述信号输出端以及电源信号端连接，用于在所述第二节点的电位控制下控制所述信号输出端与所述电源信号端连接。
  8. 根据权利要求7所述的栅极驱动电路，其特征在于，所述移位寄存器还包括：
    存储子电路，连接于所述第二节点，用于对所述第二节点的电位进行保持。
  9. 根据权利要求8所述的栅极驱动电路，其特征在于，所述下拉控制子电路包括第五晶体管，所述第五晶体管的控制极以及第一极均与所述第二时 钟信号端连接，所述第五晶体管的第二极与所述第二节点连接；
    所述下拉子电路包括第六晶体管，所述第六晶体管的控制极与所述第二节点连接，所述第六晶体管的第一极与所述电源信号端连接，所述第六晶体管的第二极与所述信号输出端连接；
    所述存储子电路包括存储电容，所述存储电容的第一极与所述电源信号端连接，所述存储电容的第二极与所述第二节点连接。
  10. 根据权利要求7所述的栅极驱动电路，其特征在于，所述移位寄存器还包括：
    噪声控制子电路，与所述第一节点、所述第二节点以及所述电源信号端连接，用于在所述第一节点的电位控制下控制所述第二节点与所述电源信号端连接，还用于在所述第二节点的电位控制下控制所述第一节点与所述电源信号端连接。
  11. 根据权利要求10所述的栅极驱动电路，其特征在于，所述噪声控制子电路包括：
    第七晶体管，所述第七晶体管的控制极与所述第二节点连接，所述第七晶体管的第一极与所述电源信号端连接，所述第七晶体管的第二极与所述第一节点连接；
    第八晶体管，所述第八晶体管的控制极与所述第一节点连接，所述第八晶体管的第一极与所述电源信号端连接，所述第八晶体管的第二极与所述第二节点连接。
  12. 根据权利要求1-6任一项所述的栅极驱动电路，其特征在于，所述移位寄存器还包括：
    第二复位子电路，与所述第一节点、电源信号端以及复位信号端连接，用于在复位信号端的控制下控制所述第一节点与所述电源信号端连接。
  13. 根据权利要求12所述的栅极驱动电路，其特征在于，所述第二复位子电路包括：
    第九晶体管，所述第九晶体管的控制极与所述复位信号端连接，所述第 九晶体管的第一极与所述电源信号端连接，所述第九晶体管的第二极与所述第二节点连接。
  14. 一种显示面板，其特征在于，包括权利要求1-13任一项所述的栅极驱动电路。
  15. 一种栅极驱动电路的驱动方法，其特征在于，所述驱动方法采用权利要求1-13任一项所述的栅极驱动电路，所述驱动方法包括：
    对于所述末级移位寄存器，使所述输入子电路在所述第一级联输入端的电位控制下控制所述第一节点的电位，使所述输出子电路在所述第一节点的电位控制下控制信号输出端的电位，使所述复位控制子电路根据所述起始信号端的电位控制末级移位寄存器的所述第二级联输入端的电位，使所述第一复位子电路在所述第二级联输入端的电位控制下对所述第一节点进行复位。
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