WO2023050474A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023050474A1
WO2023050474A1 PCT/CN2021/123357 CN2021123357W WO2023050474A1 WO 2023050474 A1 WO2023050474 A1 WO 2023050474A1 CN 2021123357 W CN2021123357 W CN 2021123357W WO 2023050474 A1 WO2023050474 A1 WO 2023050474A1
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WIPO (PCT)
Prior art keywords
conductive
pad
display panel
conductive pad
pins
Prior art date
Application number
PCT/CN2021/123357
Other languages
English (en)
French (fr)
Inventor
董书亚
刘波
龚强
Original Assignee
武汉华星光电技术有限公司
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Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US17/613,509 priority Critical patent/US20240251610A1/en
Publication of WO2023050474A1 publication Critical patent/WO2023050474A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0549—Oxides composed of metals from groups of the periodic table being a combination of two or more materials provided in the groups H01L2924/0531 - H01L2924/0546
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1426—Driver

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • FIG. 1 it is a schematic plan view of a traditional display panel.
  • the display panel 100 has a display area 100a.
  • the display panel 100 includes a driver chip 200.
  • the driver chip 200 is bound to one side of the display area 100a of the display panel 100.
  • the driver chip 200 includes input pin 201, output pin 202 and redundant pin 203, input pin 201 and output pin 202 play the role of transmission signal, redundant pin 203 does not have input or output function, redundant pin 203 is only used to support the balance of the driver chip 200, the redundant pins 203 are arranged side by side in the local area of the driver chip 200 close to the display area 100a, and the input pins 201 and output pins 202 are arranged side by side on the redundant pins 203 away from the display area 100a, and the input pin 201 is located on the opposite side of the output pin 202, the driver chip 200 shown in FIG. 100, which in turn causes the performance of the display panel to degrade, or even fail to work normally.
  • the purpose of the present application is to provide a display panel to solve the problem that the driving chip cannot be bound to the display panel due to the lifting of some pins when it is bound to the array substrate.
  • a display panel the display panel has a display area and a pad area, the pad area is located on one side of the display area, the display panel includes:
  • a first conductive pad disposed on the bearing surface of the substrate, and located in the pad area;
  • a second conductive pad disposed on the carrying surface of the substrate, and located in the pad area;
  • the driver chip is bound to the pad area, and the driver chip includes:
  • the first pin is arranged corresponding to the first conductive pad
  • the second pin is set corresponding to the second conductive pad
  • a first conductive adhesive layer filled between the first conductive pad and the first lead, and electrically connecting the first conductive pad and the first lead;
  • a second conductive adhesive layer filled between the second conductive pad and the second pin, and electrically connecting the second conductive pad and the second pin;
  • the distance from the surface of the first conductive adhesive layer close to the first lead to the substrate is different from the distance from the surface of the second conductive adhesive layer close to the second lead to the substrate.
  • the present application also provides a display device, which includes the above-mentioned display panel.
  • the present application provides a display panel and a display device, through the distance from the surface of the first conductive adhesive layer close to the first pin to the substrate and electrically connecting the second conductive pad and the first pin.
  • the second conductive adhesive layer of the second pin has different distances from the surface of the second pin to the substrate to compensate for the height difference caused by the warping of the pins on the driver chip when binding the driver chip, so as to ensure that the driver chip can be bonded well. located on the display panel.
  • FIG. 1 is a schematic plan view of a conventional display panel
  • FIG. 2 is a schematic diagram of a display panel according to the first embodiment of the present application.
  • Fig. 3 is a schematic cross-sectional view of the first type along the tangent line A-A of the display panel shown in Fig. 2;
  • FIG. 4 is a schematic cross-sectional view of the driver chip in FIG. 2 being bound to the first conductive pad and the second conductive pad in FIG. 3;
  • FIG. 5 is a schematic plan view of a driver chip and a flexible printed circuit board bound to an array substrate;
  • Fig. 6 is a second cross-sectional schematic diagram along the tangent line A-A of the display panel shown in Fig. 2;
  • Fig. 7 is a schematic cross-sectional diagram of a third type along the tangent line A-A of the display panel shown in Fig. 2;
  • Fig. 8 is a fourth schematic cross-sectional view along the tangent line A-A of the display panel shown in Fig. 2;
  • Fig. 9 is a schematic cross-sectional diagram of a fifth type along the tangent line A-A of the display panel shown in Fig. 2;
  • Fig. 10 is a sixth cross-sectional schematic diagram along the tangent line A-A of the display panel shown in Fig. 2;
  • FIG. 11 is a schematic diagram of a display panel according to a second embodiment of the present application.
  • Fig. 12 is a schematic cross-sectional view along the B-B tangent line of the display panel shown in Fig. 11;
  • FIG. 13 is a schematic diagram of a display panel according to a third embodiment of the present application.
  • FIG. 14 is a schematic cross-sectional view along the C-C tangent line of the display panel shown in FIG. 13;
  • FIG. 15 is a schematic diagram of a display panel according to a fourth embodiment of the present application.
  • FIG. 16 is a schematic diagram of a display panel according to a fifth embodiment of the present application.
  • FIG. 17 is a schematic partial cross-sectional view of a display panel according to a sixth embodiment of the present application.
  • 300 display panel 300a display area; 300b pad area; 300b2 blank area; 31 array substrate; 311 first conductive pad; 311a first bonding surface; 312 second conductive pad; 312a second bonding surface; 313 substrate; 314 light shielding layer; 3141 light shielding pattern; 3142 light shielding member; 3143 first light shielding member; 3144 second light shielding member; 315 buffer layer; 316 semiconductor layer; 3161 active pattern; 3162 semiconductor member; 317 gate insulating layer; 318 3181 gate; 3182 first metal component; 3183 second metal component; 3184 fifth metal component; 3185 sixth metal component; 3186 ninth metal component; 319 interlayer insulating layer; 319a third via hole 319b fourth via hole; 320 second metal layer; 3201 source; 3202 drain; 3203 third metal component; 3204 fourth metal component; 3205 seventh metal component; 3206 eighth metal component; 3207 tenth metal component 321 planarization layer; 321a first opening; 322 first transparent conductive layer; 323 passivation layer; 3
  • the inventor found that the main reason why some pins on the driver chip are lifted is that the distribution of the pins on the driver chip is uneven, resulting in multiple pins on the driver chip when the driver chip is bound to the display panel.
  • the uneven distribution of the supporting force on the pins causes some pins on the driver chip to lift up and cannot be bound to the pads of the display panel.
  • this application connects the first The distance from the surface of the conductive pad and the first conductive adhesive layer of the first pin close to the first pin to the substrate is the same as the distance from the second conductive adhesive layer electrically connected to the second conductive pad and the second pin close to the surface of the second pin
  • the distances to the substrate are different, so that the raised pins on the driver chip are combined with the conductive first conductive adhesive layer and the conductive second conductive adhesive layer, which has a larger distance to the substrate, so as to ensure that the raised pins on the driver chip
  • the pins can be bonded to the display panel normally.
  • the first conductive pad and the second conductive pad are both disposed on the carrying surface of the substrate, and both are located in the pad area.
  • FIG. 2 is a schematic diagram of the display panel of the first embodiment of the present application
  • Figure 3 is a schematic cross-sectional view of the first type along the tangent line A-A of the display panel shown in Figure 2
  • Figure 4 is a schematic diagram of the driver chip in Figure 2.
  • FIG. 5 is a schematic plan view of the driver chip and the flexible printed circuit board bound on the array substrate.
  • the display panel 300 may be a liquid crystal display panel, and the display panel 300 may also be an organic light emitting diode display panel. Specifically, the display panel 300 is a fringe field switch (Fringe Field Switching, FFS) liquid crystal display panel.
  • FFS fringe field switch
  • the display panel 300 may also be an in-plane switching (In-Plane Switching, IPS) liquid crystal display panel or a vertical alignment (Vertical Alignment) LCD panel.
  • the display panel 300 has a display area 300a and a pad area 300b, and the pad area 300b is disposed on one side of the display area 300a.
  • the display panel 300 includes an array substrate 31 , a driver chip 33 and a flexible printed circuit board 34 , and the driver chip 33 and the flexible printed circuit board 34 are both bound to the pad area 300 b of the array substrate 31 .
  • the part of the display panel 300 corresponding to the display area 300a is used for displaying.
  • the array substrate 31 includes a plurality of thin film transistors arranged in an array, pixel electrodes, common electrodes, scan lines and data lines.
  • the pad area 300b is provided with a plurality of conductive pads, and the driving chip 33 is bound on the multiple conductive pads in the pad area 300b, that is, the driving chip 33 of the display panel 300 is bound on the glass (Chip On Glass , COG).
  • the glass Chip On Glass , COG
  • the plurality of conductive pads includes a plurality of first conductive pads 311 and a plurality of second conductive pads 312, the plurality of first conductive pads 311 are arranged side by side in a straight line along the first direction, and the plurality of second conductive pads 312 are arranged in a straight line along the first direction Arranged side by side, the second conductive pads 312 are located on the side of the first conductive pads 311 away from the display area 300a, and the plurality of second conductive pads 312 and the plurality of first conductive pads 311 are misaligned in the second direction, so that they are different from the second
  • the wiring connected to the conductive pads 312 may extend from a region between two adjacent first conductive pads 311 .
  • the second direction is a direction in which the display area 300a points to the pad area 300b, and the first direction is perpendicular to the second direction.
  • the driver chip 33 includes a substrate 330, a plurality of first pins 331 and a plurality of second pins 332, the driver chip 33 has a first edge 330a and a second edge 330b, and the first edge 330a is connected to the second edge 330b.
  • the edges 330b are opposite to each other.
  • the multiple first pins 331 and the multiple second pins 332 are all Set on the base 330 and close to the second edge 330b, that is, the distance from the first pin 331 to the first edge 330a is greater than the distance from the first pin 331 to the second edge 330b, and the distance from the second pin 332 to the first edge 330a is greater than the distance from the second pin 332 to the second edge 330b, and the multiple first pins 331 are located on the side of the multiple second pins 332 away from the second edge 330b, that is, the second pins 332 are located on the first edge 330b.
  • the pins 331 are away from the side of the display area 100a, and the first pins 331 and the second pins 332 are misaligned in the second direction.
  • the thickness of the first pin 331 is equal to the thickness of the second pin 332 .
  • the array substrate 31 includes a substrate 313, a light shielding layer 314, a buffer layer 315, a semiconductor layer 316, a gate insulating layer 317, a first metal layer 318, an interlayer insulating layer 319, and a second metal layer stacked in sequence. 320 , a planarization layer 321 , a first transparent conductive layer 322 , a passivation layer 323 and a second transparent conductive layer 324 .
  • the substrate 313 is a glass substrate, and the substrate 313 has a carrying surface 313a, and the carrying surface 313a is a flat horizontal surface.
  • the light-shielding layer 314 includes a light-shielding pattern 3141 and a light-shielding member 3142.
  • the light-shielding pattern 3141 is arranged on the bearing surface 313a of the substrate 313 and is located in the display area 300a.
  • the light shielding member 3142 is disposed corresponding to the second conductive pad 312 .
  • the light shielding layer 314 is a metal layer.
  • the thickness of the light-shielding layer 314 is 450 ⁇ -550 ⁇ .
  • the light-shielding layer 314 is made of at least one material selected from molybdenum, aluminum, titanium, copper and silver.
  • the buffer layer 315 covers the light shielding layer 314 and the substrate 313 , and the buffer layer 315 is located in the display area 300 a and the pad area 300 b.
  • the buffer layer 315 has a thickness of 2500-3500 angstroms.
  • the buffer layer 315 includes a silicon nitride layer and a silicon oxide layer, the silicon nitride layer is disposed close to the substrate 313 , and the silicon oxide layer is disposed away from the substrate 313 .
  • the semiconductor layer 316 is disposed on the buffer layer 315 , the semiconductor layer 316 includes an active pattern 3161 , and the active pattern 3161 is located in the display area 300 a and disposed corresponding to the light-shielding pattern 3141 .
  • the preparation material of the semiconductor layer 316 is selected from any one of amorphous silicon, polysilicon and metal oxide.
  • the thickness of the semiconductor layer 316 is 400-500 angstroms.
  • the gate insulating layer 317 covers the semiconductor layer 316 and the buffer layer 315, and the gate insulating layer 317 is located in the display area 300a and the pad area 300b.
  • the gate insulating layer 317 has a thickness of 1000 ⁇ -1500 ⁇ .
  • the preparation material of the gate insulating layer 317 is silicon nitride or silicon oxide.
  • the first metal layer 318 is disposed on the gate insulating layer 317 .
  • the first metal layer 318 includes a gate 3181, a first metal member 3182 and a second metal member 3183.
  • the gate 3181 is located in the display area 300a and is set corresponding to the active pattern 3161.
  • Both the first metal member 3182 and the second metal member 3183 are located in the In the pad area 300b, the second metal member 3183 is located on the side of the first metal member 3182 away from the display area 300a, the second metal member 3183 is located directly above the light shielding member 3142, the thickness of the gate 3181, the thickness of the first metal member 3182 And the thickness of the second metal member 3183 is the same.
  • the thickness of the first metal layer 318 is 2500-3500 angstroms.
  • the first metal layer 318 is made of at least one material selected from molybdenum, aluminum, titanium, copper and silver.
  • the interlayer insulating layer 319 covers the first metal layer 318 and the gate insulating layer 317 , and the interlayer insulating layer 319 is located in the display area 300 a and the bonding pad area 300 b.
  • the thickness of the interlayer insulating layer 319 is 5500-6500 angstroms.
  • the interlayer insulating layer 319 is made of at least one material selected from silicon nitride and silicon oxide.
  • the second metal layer 320 is disposed on the interlayer insulating layer 319 .
  • the second metal layer 320 includes a source 3201, a drain 3202, a third metal member 3203, and a fourth metal member 3204.
  • the source 3201 and the drain 3202 are located in the display area 300a and are arranged on opposite sides of the gate 3181.
  • the source 3201 is in contact with the active pattern 3161 through the first via hole penetrating the interlayer insulating layer 319 and the gate insulating layer 317
  • the drain 3202 is in contact with the active pattern 3161 through the second via hole penetrating the interlayer insulating layer 319 and the gate insulating layer 317.
  • the pattern 3161 contacts, the third metal member 3203 is arranged corresponding to the first metal member 3182 and is electrically connected to the first metal member 3182 through the third via hole 319a penetrating the interlayer insulating layer 319, and the fourth metal member 3204 corresponds to the second metal member 3183 is disposed and electrically connected to the second metal member 3183 through the fourth via hole 319 b penetrating the interlayer insulating layer 319 , and the source 3201 , the drain 3202 , the third metal member 3203 and the fourth metal member 3204 have the same thickness.
  • the thickness of the second metal layer 320 is 4000-6500 angstroms.
  • the second metal layer 320 is made of at least one material selected from molybdenum, aluminum, titanium, copper and silver.
  • the planarization layer 321 covers the second metal layer 320 and the interlayer insulating layer 319, the planarization layer 321 includes a first opening 321a located in the pad region 300b, the first opening 321a enables the third metal member 3203 and The fourth metal members 3204 are all exposed.
  • the thickness of the planarization layer 321 is 2.0 microns-3.0 microns.
  • the preparation material of the planarization layer 321 is polyimide or polyacrylate.
  • the first transparent conductive layer 322 is disposed on the planarization layer 321 and located in the display area 300a, and the first transparent conductive layer 322 is a common electrode layer.
  • the preparation material of the first transparent conductive layer 322 is indium tin oxide.
  • the thickness of the first transparent conductive layer 322 is 500-700 angstroms.
  • the passivation layer 323 covers the first transparent conductive layer 322; As well as the fourth metal member 3204 , the passivation layer 323 is provided with a second opening 323 a corresponding to the third metal member 3203 , and the passivation layer 323 is provided with a third opening 323 b corresponding to the fourth metal member 3204 .
  • the passivation layer 323 has a thickness of 800 ⁇ -1200 ⁇ .
  • the passivation layer 323 is made of any one of silicon nitride or silicon oxide.
  • the second transparent conductive layer 324 of the display area 300a is disposed on the passivation layer 323, and the second transparent conductive layer 324 includes a plurality of mutually independent pixel electrodes 3241, a first transparent conductive member 3242 and a second transparent conductive member 3242.
  • the conductive member 3243, at least part of the first transparent conductive member 3242 is located in the second opening 323a and on the third metal member 3203, at least part of the second transparent conductive member 3243 is located in the third opening 323b and located on the fourth metal member 3204
  • the pixel electrode 3241, the first transparent conductive member 3242 and the second transparent conductive member 3243 have the same thickness.
  • the preparation material of the second transparent conductive layer 324 is indium tin oxide.
  • the thickness of the second transparent conductive layer 324 is 450-550 angstroms.
  • the first metal member 3182, the third metal member 3203 and the first transparent conductive member 3242 form the first conductive pad 311
  • the first conductive pad 311 has a first joint surface 311a connected to the driver chip 33
  • the second At least part of a joint surface 311a is parallel to the bearing surface 313a.
  • the second metal member 3183, the fourth metal member 3204, and the second transparent conductive member 3243 form the second conductive pad 312.
  • the second conductive pad 312 has a second bonding surface 312a connected to the driver chip 33. At least the second bonding surface 312a A portion is parallel to the bearing surface 313a.
  • the thickness of the first conductive pad 311 is equal to the thickness of the second conductive pad 312 .
  • the second conductive pad 312 is elevated relative to the first conductive pad 311, and at least part of the first bonding surface 311a parallel to the bearing surface 313a reaches the bottom of the substrate 313.
  • the distance is smaller than the distance from at least part of the second bonding surface 312 a parallel to the bearing surface 313 a to the substrate 313 .
  • the first bonding surface 311a and the second bonding surface 312a are parallel to the carrying surface 313a and are used for bonding with the driver chip 33. It can be understood that the first bonding surface 311a and the second bonding surface 312a can also be Including a portion that is not parallel to the carrying surface 313a.
  • the display panel further includes a first conductive adhesive layer 401 and a second conductive adhesive layer 402. Both the first conductive adhesive layer 401 and the second conductive adhesive layer 402 have conductivity.
  • the conductive adhesive layer 401 is filled between the first conductive pad 311 and the first pin 331 and is electrically connected to the first conductive pad 311 and the first pin 331, and the second conductive adhesive layer 402 is filled between the second conductive pad 312 and the first pin 331.
  • the two pins 332 are electrically connected to the second conductive pad 312 and the second pin 332, and the first conductive adhesive layer 401 and the second conductive adhesive layer 402 are connected and electrically insulated by an anisotropic conductive adhesive.
  • the thickness of the first conductive adhesive layer 401 is the same as that of the second conductive adhesive layer 402 .
  • the preparation materials of the first conductive adhesive layer 401 and the second conductive adhesive layer 402 are anisotropic conductive adhesive, and the first conductive adhesive layer 401 and the second conductive adhesive layer 402 are bonded to the anisotropic conductive adhesive layer.
  • the conductive particles 40a in the anisotropic conductive adhesive are pressed and contacted with each other after the anisotropic conductive adhesive layer is pressed, that is, the first conductive adhesive layer 401 and the second conductive adhesive layer 402 are anisotropic
  • the anisotropic conductive adhesive has a conductive adhesive layer after being pressed, and the thickness of the first conductive adhesive layer 401 and the thickness of the second conductive adhesive layer 402 are the thickness corresponding to the conductivity of the anisotropic conductive adhesive after being pressed; the first conductive adhesive
  • the conductive particles 40a in the anisotropic conductive adhesive between the adhesive layer 401 and the second conductive adhesive layer 402 are not stressed and dispersed so that no conductive path is formed, so that the first conductive adhesive layer 401 and the second conductive adhesive layer 402 Electrically insulated.
  • the thickness of the first conductive adhesive layer 401 is the same as the thickness of the second conductive adhesive layer 402, and the first conductive adhesive layer 401 is close to the second conductive adhesive layer.
  • the distance from the first surface 401 a of a lead 331 to the substrate 313 is smaller than the distance from the second surface 402 a of the second conductive adhesive layer 402 close to the second lead 332 to the substrate 313 .
  • the distance from the first bonding surface 311a to the substrate 313 may also be equal to the distance from the second bonding surface 312a to the substrate 313. At this time, the thickness of the first conductive adhesive layer 401 is smaller than that of the second conductive adhesive layer 401.
  • the thickness of the adhesive layer 402; or, the thickness of the first conductive adhesive layer 401 is less than the thickness of the second conductive adhesive layer 402, and the distance from the first bonding surface 311a to the substrate 313 is less than the distance from the second bonding surface 312a to the substrate 313, so as to The distance from the first surface 401a of the first conductive adhesive layer 401 close to the first pin 331 to the substrate 313 is smaller than the distance from the second surface 402a of the second conductive adhesive layer 402 close to the second pin 332 to the substrate 313 .
  • a plurality of first pins 331 are provided in a one-to-one correspondence with a plurality of first conductive pads 311 and through the first After the conductive adhesive layer 401 is electrically connected, the end of the driver chip 33 near the display area 300a is unsupported and tilts downward.
  • the plurality of second pins 332 of the driver chip 33 will be lifted, and the plurality of raised second pins 332 will be lifted.
  • the pins 332 are provided in one-to-one correspondence with the plurality of second conductive pads 312 raised by the light shielding member 3142 and are electrically connected through the second conductive adhesive layer 402 .
  • the flexible printed circuit board 34 includes a first binding portion 342, a second binding portion 343 and a main body portion 341, the first binding portion 342 and the second binding portion 343 are both Connected to the main body part 341, the first binding part 342 and the second binding part 343 are both bound to the pad area 300b and located on opposite sides of the drive chip 33 in a direction perpendicular to the display area 300a and directed to the pad area 300b .
  • the design and binding method of the flexible printed circuit board 34 make the display panel 300 a display panel with narrow borders.
  • the array substrate 31 also includes flexible printed circuit board binding areas (not shown) disposed on opposite sides of the pad area, the flexible printed circuit board binding area of the array substrate is also provided with pads, and the flexible printed circuit board The electrical connection between the circuit board and the pads in the bonding area of the flexible printed circuit board is based on the prior art and will not be described in detail here.
  • a light-shielding member is provided under the second conductive pad corresponding to the raised second pin on the driving chip to raise the second conductive pad, and the raised second conductive pad and the raised second lead Binding and electrical connection can be realized between the pins.
  • FIG. 6 is a second schematic cross-sectional view along the tangent line A-A of the display panel shown in FIG. 2 .
  • the display panel shown in FIG. 6 is basically similar to the display panel shown in FIG. 3, except that the semiconductor layer 316 includes a semiconductor component 3162, the semiconductor component 3162 is located in the pad region 300b and is disposed corresponding to the second conductive pad 312, and the light shielding layer 314 does not It includes a light shielding member disposed on the pad region 300b.
  • the display panel shown in FIG. Pad 312 is used for padding.
  • FIG. 7 is a third schematic cross-sectional view along the tangent line A-A of the display panel shown in FIG. 2 .
  • the display panel shown in FIG. 7 is basically similar to the display panel shown in FIG. 3.
  • the light-shielding layer 314 includes a light-shielding member 3142. While the light-shielding member 3142 is located in the pad region 300b and is arranged corresponding to the second conductive pad 312, the semiconductor layer 316 also includes a semiconductor member. 3162 , the semiconductor component 3162 is located in the pad region 300 b and is disposed corresponding to the light shielding component 3142 .
  • FIG. 8 is a fourth schematic cross-sectional view along the tangent line A-A of the display panel shown in FIG. 2 .
  • the display panel shown in FIG. 8 is basically similar to the display panel shown in FIG. 7. The difference includes that, in the thickness direction of the display panel 300, a first film layer is provided between the first conductive pad 311 and the substrate 313, and the second conductive A second film layer is provided between the pad 312 and the substrate 313, the first film layer is located in the pad area 300b and is arranged corresponding to the first conductive pad 311, the second film layer is located in the pad area 300b and is provided corresponding to the second conductive pad 312, The first film layer and the second film layer are arranged on the same layer, and the thickness of the first film layer is smaller than that of the second film layer.
  • the light-shielding layer 314 includes a first light-shielding member 3143 disposed on the pad region 300b and a second light-shielding member 3144 disposed on the pad region 300b, the first film layer is the first light-shielding member 3143, and the second film layer is the second light-shielding member 3144.
  • Two light-shielding members 3144 the first light-shielding member 3143 is disposed corresponding to the first conductive pad 311
  • the second light-shielding member 3144 is disposed corresponding to the second conductive pad 312
  • the thickness of the first light-shielding member 3143 is smaller than that of the second light-shielding member 3144 .
  • first film layer can also be other film layers between the first conductive pad and the substrate
  • second film layer can also be other film layers between the second conductive pad and the substrate, such as the first film layer Both the active pattern and the second film layer are in the same layer.
  • the number of film layers between the first conductive pad 311 and the substrate 313 is smaller than the number of film layers between the second conductive pad 312 and the substrate 313, so that The distance from at least part of the first bonding surface 311a of the first conductive pad 311 parallel to the carrying surface 313a of the substrate 313 to the substrate 313 is less than at least part of the second bonding surface 312a of the second conductive pad 312 parallel to the carrying surface 313a of the substrate 313 The distance to the substrate 313.
  • the thickness of the first film layer between the first conductive pad 311 and the substrate 313 is smaller than that of the second film layer between the second conductive pad 312 and the substrate 313 and the same layer as the first film layer. Thickness, so that the first joint surface 311a of the first conductive pad 311 is parallel to the bearing surface 313a of the substrate 313, and at least part of the distance to the substrate 313 is smaller than the second joint surface 312a of the second conductive pad 312 and the bearing surface 313a of the substrate 313 Parallel to at least part of the distance to the substrate 313 .
  • the film layers include but not limited to metal layers, insulating layers and planarization layers. layer to raise the second conductive pad 312 , and realize bonding and electrical connection between the raised second conductive pad 312 and the raised second pin 332 .
  • FIG. 9 is a schematic cross-sectional diagram of a fifth type along the tangent line A-A of the display panel shown in FIG. 2 .
  • the display panel shown in FIG. 9 is similar to the display panel substrate shown in FIG. 3, except that the thickness of the first conductive pad 311 is smaller than the thickness of the second conductive pad 312, and the light shielding layer 314 shown in FIG. A light-shielding member of the panel 300b.
  • the number of film layers of the first conductive pad 311 is smaller than the number of film layers of the second conductive pad 312 .
  • the first conductive pad 311 is composed of the first metal member 3182, the third metal member 3203 and the first transparent conductive member 3242
  • the second conductive pad 312 is composed of the second metal member 3183, the fourth metal member 3204, the second transparent
  • the conductive member 3243 and the conductive member 325 are composed of the conductive member 325 arranged on the second transparent conductive member 3243, that is, the number of film layers of the second conductive pad 312 is increased, so that the number of film layers of the first conductive pad 311 is smaller than that of the second conductive pad 312 layers.
  • the conductive member 325 may be a transparent conductive layer or a metal conductive layer.
  • the first conductive pad 311 can also be composed of the first metal member 3182 and the third metal member 3203
  • the second conductive pad 312 can be composed of the second metal member 3183, the fourth metal member 3204 and the second transparent conductive member 3243 composition, that is, reducing the number of film layers of the first conductive pad 311 so that the number of film layers of the first conductive pad 311 is smaller than the number of film layers of the second conductive pad 312 .
  • the display panel shown in FIG. 9 adds a conductive member 325 on the second transparent conductive member 3243, so that the second bonding surface 312a where the second conductive pad 312 is combined with the driving chip 33 is higher, which is beneficial to the connection between the second conductive pad 312 and the driving chip.
  • the raised second pins 332 on the chip 33 are bonded and electrically connected. It is also possible to reduce the number of film layers of the first conductive pad 311 so that the second conductive pad 312 can be combined with the second bonding surface 312 a where the driving chip 33 is bonded.
  • FIG. 10 is a sixth cross-sectional view along the tangent line A-A of the display panel shown in FIG. 2 .
  • the display panel shown in FIG. 10 is basically similar to the display panel shown in FIG. 3, except that the first conductive pad 311 includes a first conductive film, the second conductive pad 312 includes a second conductive film, and the second conductive film is the same as the first conductive film.
  • the conductive films are arranged in the same layer, the thickness of the first conductive film is smaller than that of the second conductive film, and the light-shielding layer 314 shown in FIG. 10 does not include a light-shielding member disposed on the pad region 300b.
  • the first conductive pad 311 is composed of the first metal member 3182, the third metal member 3203 and the first transparent conductive member 3242
  • the second conductive pad 312 is composed of the second metal member 3183, the fourth metal member 3204 and the second transparent
  • the thickness of the first metal member 3182 is equal to the thickness of the second metal member 3183
  • the thickness of the third metal member 3203 is smaller than the thickness of the fourth metal member 3204
  • the thickness of the first transparent conductive member 3242 is equal to the thickness of the second transparent conductive member.
  • the thickness of member 3243 is the thickness of member 3243.
  • the thickness of the first metal member 3182 may also be smaller than the thickness of the second metal member 3183, the thickness of the third metal member 3203 is equal to the thickness of the fourth metal member 3204, and the thickness of the first transparent conductive member 3242 is equal to the second The thickness of the transparent conductive member 3243 .
  • the display panel shown in FIG. 10 makes the thickness of the conductive film making up the first conductive pad 311 smaller than the thickness of the conductive film making up the second conductive pad 312, so that the distance from the second bonding surface 312a of the second conductive pad 312 to the substrate 313
  • the distance between the first bonding surface 311 a of the first conductive pad 311 and the substrate 313 is greater than the distance between the raised second pin 332 on the driving chip 33 and the second bonding surface 312 a of the second conductive pad 312 .
  • the display panel shown in FIG. 9 and the display panel shown in FIG. 10 adjust the number of film layers of the first conductive pad 311 to be smaller than the number of film layers of the second conductive pad 312, or adjust the thickness of the conductive film layer of the first conductive pad 311 to be less than
  • the thickness of the conductive film layer of the second conductive pad 312 is such that the thickness of the first conductive pad 311 is smaller than the thickness of the second conductive pad 312, so that the distance from the second bonding surface 312a of the second conductive pad 312 to the substrate is greater than the first
  • the distance between the first bonding surface 311 a of the conductive pad 311 and the substrate is such that the second bonding surface 312 a is connected to the raised second pin 332 on the driving chip 33 .
  • the number of film layers of the first conductive pad 311 shown in FIG. 9 is smaller than the number of film layers of the second conductive pad 312, and the thickness of the first conductive film of the first conductive pad 311 shown in FIG. 10 is smaller than that of the second conductive pad.
  • the thickness of the second conductive pad of 312, the number of film layers between the first conductive pad and the substrate shown in Figure 3, Figure 6, and Figure 7 is less than the number of film layers between the second conductive pad and the substrate, and as shown in Figure 8 Showing that the thickness of the first film layer between the first conductive pad 311 and the substrate 313 is smaller than the thickness of the second film layer between the second conductive pad and the substrate and the same layer as the first film layer can be combined with each other, so that the second conductive The distance from the second bonding surface 312 a of the pad 312 to the substrate is greater than the distance from the first bonding surface 311 a of the first conductive pad 311 .
  • FIG. 11 is a schematic diagram of the display panel according to the second embodiment of the present application
  • FIG. 12 is a schematic cross-sectional diagram along the B-B tangent line of the display panel shown in FIG. 11
  • the display panel shown in FIG. 11 is basically similar to the display panel shown in FIG. 3.
  • the array substrate 31 includes a first conductive pad 311, a second conductive pad 312, a third conductive pad 326 and redundant
  • the conductive pad 327, the first conductive pad 311, the second conductive pad 312, the third conductive pad 326 and the redundant conductive pad 327 are all arranged in the pad area 300b, the first conductive pad 311, the second conductive pad 312, the third conductive pad
  • the pads 326 both transmit electrical signals, and the redundant conductive pads 327 do not transmit signals.
  • a plurality of redundant conductive pads 327 are arranged side by side in a straight line along the first direction, and a plurality of first conductive pads 311 are arranged side by side in a straight line along the first direction, and the plurality of redundant conductive pads 327 are located near the first conductive pad 311 to display
  • a plurality of second conductive pads 312 and a plurality of third conductive pads 326 are arranged on the side of the plurality of first conductive pads 311 away from the display region 300a, and the plurality of second conductive pads 312 and the plurality of third
  • the conductive pads 326 are arranged side by side in a straight line along the first direction, and the plurality of second conductive pads 312 are symmetrically arranged on opposite sides of the plurality of third conductive pads 326 in the first direction.
  • the two second conductive pads 312 are arranged adjacent to each other in the second direction (the direction in which the display area 300a points to the pad area 300b ), and the first conductive pad 311 and the plurality of second conductive pads 312 are arranged in dislocation in the second direction, and the other part
  • the first conductive pad 311 and the plurality of third conductive pads 326 are also adjacent to each other in the second direction and arranged in a dislocation manner, and the plurality of second conductive pads 312 are located on opposite sides of the plurality of redundant conductive pads 327 in the first direction , and some of the first conductive pads 311 are also located on opposite sides of the plurality of redundant conductive pads 327 in the first direction.
  • the first conductive pad 311 is the same as the first conductive pad in FIG. 3 above
  • the second conductive pad 312 is the same as the second conductive pad in FIG. 3 above
  • the third conductive pad 326 is composed of the fifth metal member 3184 , the seventh metal member 3205 and the third transparent conductive member 3244 .
  • the redundant conductive pad 327 is composed of the sixth metal member 3185 , the eighth metal member 3206 and the fourth transparent conductive member 3245 .
  • the first conductive pad 311 has a first bonding surface 311a
  • the second conductive pad 312 has a second bonding surface 312a
  • the third conductive pad 326 has a third bonding surface 326a
  • the third bonding surface 326a is parallel to the bearing surface
  • the third bonding surface 326a is provided with a conductive adhesive layer
  • the redundant conductive pad 327 has a redundant joint surface 327a
  • the redundant joint surface 327a is parallel to the bearing surface 313a
  • the distance from at least part of the first joint surface 311a parallel to the bearing surface 313a to the substrate 313 is less than
  • the distance from at least part of the second joint surface 312a parallel to the bearing surface 313a to the substrate 313, the distance from at least part of the third joint surface 326a parallel to the bearing surface 313a to the substrate 313 is less than at least the distance from the second joint surface 312a parallel to the bearing surface 313a Part of the distance to the substrate 313, at least part of the distance from the
  • the driver chip 33 includes a first pin 331 , a second pin 332 , a third pin 333 and a redundant pin 334 .
  • the driver chip 33 has a first edge 330a and a second edge 330b, the first edge 330a is opposite to the second edge 330b, when the driver chip 33 is bound on the display panel 300, the first edge 330a is close to the display area 300a, and the second edge 330b away from the display area 300a.
  • the redundant pins 334 are arranged side by side in a straight line near the first edge 330a so that a plurality of redundant pins 334 are arranged near the display area 300a, and the redundant pins 334 will not receive electrical signals.
  • the first pins 331 are arranged side by side in a straight line near the second edge 330b, the multiple second pins 332 and the multiple third pins 333 are located on the side of the multiple first pins 331 away from the display area 300a, and the multiple first pins 331 are located on the side away from the display area 300a.
  • the two pins 332 are arranged on opposite sides of a plurality of third pins 333 in the first direction, and part of the first pins 331 are adjacent to the second pins 332 in the second direction.
  • the feet 331 are located on the opposite sides of the plurality of redundant pins 334 in the first direction, and the other part of the first pins 331 is staggered adjacent to the plurality of third pins 333 in the second direction, and the plurality of second pins
  • the pins 332 are symmetrically located on opposite sides of the plurality of redundant pins 334 in the first direction, the thickness of the first pin 331, the thickness of the second pin 332, the thickness of the third pin 333 and the thickness of the redundant pins
  • the feet 334 are all equal in thickness.
  • a plurality of redundant pins 334 and a plurality of redundant conductive pads 327 are arranged and connected one-to-one, and a plurality of first pins 331 are connected to a plurality of first conductive pads 311 one by one.
  • a plurality of third pins 333 and a plurality of third conductive pads 326 are arranged one-to-one, and a conductive glue layer is filled between the third bonding surface 326a and the third pins 333, due to the plurality of The wiring area 300b1 on opposite sides of the redundant conductive pad 327 is provided with a plurality of wiring lines, resulting in no redundant conductive pad 327 in the wiring area 300b1, and the driver chip 33 is tilted down without support in the wiring area 300b1.
  • the driver chip 33 The plurality of second pins 332 are lifted, and the second bonding surface 312a of the plurality of lifted second pins 332 and the raised second conductive pad 312 passes through the second conductive adhesive layer 402 filled between the two. Combining and electrically connecting the second pins 332 to the second conductive pads 312, so that multiple second pins 332 can be bound on the array substrate and the second pins 332 are electrically connected to the corresponding second conductive pads 312 .
  • the plurality of second pins 332 are located on opposite sides of the plurality of redundant electrical pads 327 in the first direction and are supported by the redundant electrical pads 327 differently, the plurality of second pins 332 The degree of tilting is also different. The farther the second pin 332 is from the redundant conductive pad 327, the smaller the support force obtained. 312a is parallel to the carrying surface 313a, and at least part of the distance to the substrate 313 increases from close to the third conductive pad 326 to away from the third conductive pad 326, so as to accommodate the second lead that is lifted when the driver chip 33 is bound on the array substrate. The distance from the pin 332 to the substrate 313 increases gradually from close to the third conductive pad 326 to far away from the third conductive pad 326 .
  • the distance from at least part of the first bonding surface 311a of the first conductive pad 311 parallel to the carrying surface to the substrate is smaller than the distance from at least part of the second bonding surface 312a of the second conductive pad 312 parallel to the carrying surface to the substrate It can be realized by the aforementioned methods, and details are not described here.
  • FIG. 13 is a schematic diagram of the display panel according to the third embodiment of the present application
  • FIG. 14 is a schematic cross-sectional diagram along the C-C tangent line of the display panel shown in FIG. 13
  • the display panel shown in FIG. 13 is basically similar to the display panel shown in FIG. 12. The difference includes that the array substrate 31 further includes at least two rows of fourth conductive pads 328 and at least one row of fifth conductive pads 329, and at least two rows of fourth conductive pads 329.
  • Pads 328 are located at least one row of fifth conductive pads 329 away from the side of the display area 300a, at least two rows of fourth conductive pads 328 and at least one row of fifth conductive pads 329 are arranged along the second direction and are located redundantly in the second direction.
  • the conductive pad 327 is away from the side of the display area 300a, and at least two rows of fourth conductive pads 328 are located on opposite sides of the second conductive pad 312 in the first direction, so at least two rows of fourth conductive pads 328 are also located in the first direction.
  • each fourth conductive pad 328 has a fourth bonding surface 328a, the fourth bonding surface 328a is parallel to the bearing surface 313a, and each fifth conductive pad 329 has a fifth bonding surface 329a, The fifth bonding surface 329a is parallel to the bearing surface 313a; the driver chip 33 also includes at least two rows of fourth pins 335 and at least one row of fifth pins 336, at least two rows of fourth pins 335 are located at least one row of fifth pins 336 away from the side of the display area, at least two rows of fourth pins 335 and at least one row of fifth pins 336 are arranged along the second direction and located on the side of the redundant pins 334 away from the display area 300
  • the fourth joint surface 328a is opposite to the fourth pin 335 and filled with a conductive glue layer therebetween
  • the fifth joint surface 329a is opposite to the fifth pin 336 and filled with a conductive glue layer therebetween
  • the fifth The distance from at least part of the fifth bonding surface 329a of the conductive pad 329 parallel to the carrying surface 313a to the substrate 313 is less than that of at least part of the fourth bonding surface 328a of the fourth conductive pad 328 close to the fifth conductive pad 329 parallel to the carrying surface 313a.
  • the distance from the substrate 313, the distance from at least part of the fifth bonding surface 329a of the fifth conductive pad 329 parallel to the carrying surface 313a to the substrate 313 is equal to at least part of the first bonding surface 311a of the first conductive pad 311 parallel to the carrying surface to the substrate.
  • the distance from the fourth joint surface 328a of at least two rows of fourth conductive pads 328 parallel to the bearing surface 313a to the substrate 313 increases from close to the display area 300a to away from the display area 300a, so as to adapt to the fourth conductive pad 328
  • the degree of tilting of the corresponding fourth pin 335 increases gradually from close to the display area 300a to away from the display area 300a.
  • each fourth conductive pad 328 is composed of a ninth metal member 3186, a tenth metal member 3207, and a fifth transparent conductive member 3246.
  • the thickness of the ninth metal member 3186 of multiple fourth conductive pads 328 is the same, and multiple The thickness of the fifth transparent conductive member 3246 of the fourth conductive pad 328 is the same, and the thickness of the tenth metal member 3207 of at least two rows of fourth conductive pads 328 increases gradually from close to the display area 300a to far away from the display area 300a, so that at least two rows of the fourth conductive pad 328 have an increasing thickness.
  • the fourth bonding surface 328 a of the four conductive pads 328 is parallel to the bearing surface 313 a and at least part of the distance from the substrate 313 increases in the second direction from close to the display area 300 a to away from the display area 300 a.
  • the opposite sides of the plurality of redundant conductive pads are blank areas where no redundant conductive pads are provided. Supported and tilted downward, the farther the fourth pin 335 from the display area 300a is lifted, the higher the fourth bonding surface 328a of the fourth conductive pad 328 corresponding to the fourth pin 335 is required.
  • the first direction since the plurality of fourth conductive pads 328 are located on opposite sides of the plurality of redundant conductive pads 327 in the first direction, the farther the plurality of fourth conductive pads 328 are from the redundant conductive pads 327, the second The smaller the four conductive pads 328 are supported by the redundant conductive pads 327, the higher the fourth pin 335 on the driver chip is raised.
  • the fourth joint surface 328a of at least two rows of fourth conductive pads 328 At least part of the distance to the substrate 313 parallel to the bearing surface 313a increases from close to the second conductive pad 312 to away from the second conductive pad 312, and the fourth bonding surface 328a of the fourth conductive pad 328 adjacent to the second conductive pad 312 At least part of the distance from the substrate 313 parallel to the carrying surface 313 a is greater than the distance from at least part of the second bonding surface 312 a of the second conductive pad 312 adjacent to the fourth conductive pad 328 parallel to the carrying surface 313 a to the substrate 313 .
  • FIG. 15 is a schematic diagram of a display panel according to a fourth embodiment of the present application.
  • the display panel shown in FIG. 15 is basically similar to the display panel shown in FIG. 2.
  • the display panel 300 includes a plurality of first conductive pads 311, a plurality of second conductive pads 312, and a plurality of third conductive pads 326.
  • the plurality of third conductive pads 326 are arranged in two rows, the two rows of first conductive pads 311 are respectively arranged obliquely on opposite sides of the two rows of third conductive pads 326 in the first direction, and the two rows of second conductive pads 312 are obliquely arranged in the first direction. They are arranged on opposite sides of the two rows of third conductive pads 326 respectively.
  • the two rows of second conductive pads 312 are respectively located on the side of the two rows of first conductive pads 311 away from the display area 300a in the second direction.
  • One row of first conductive pads 311 is adjacent to and parallel to a row of second conductive pads 312, and the angle between the straight line of a row of first conductive pads 311 and the straight line of a row of third conductive pads 326 is greater than 0 and less than 90 degrees;
  • the driver chip 33 includes The first pin 331 corresponding to the first conductive pad 311 one-to-one, the second pin 332 corresponding to the second conductive pad 312 one-to-one, and the third pin 333 corresponding to the third conductive pad 326 one-to-one, a plurality of The third pins 333 are arranged in two rows in the middle of the driver chip 33 in the second direction, and the plurality of first pins 331 are divided into two rows and arranged obliquely on opposite sides of the two rows of third pins 333 , a plurality of
  • composition of the first conductive pad 311 shown in Figure 15 and the composition of the second conductive pad 312 are the same as the composition of the first conductive pad 311 shown in Figure 2 and the composition of the second conductive pad 312, and will not be described in detail here.
  • the composition of the third conductive pad 326 shown in FIG. 15 is the same as that of the first conductive pad 311 shown in FIG. 15 .
  • the end of the driving chip 33 close to the display area 300a has no support, and the plurality of first pins 331 of the driving chip 33 are bound on the first conductive pad 311 and the second
  • the end of the driver chip 33 close to the display area 300a will be tilted downward, and the multiple second pins 332 of the driver chip 33 will be lifted, and the first conductive pad 311 will tilt up.
  • a bonding surface 311a parallel to the bearing surface 313a is at least partly at least a part away from the substrate 313, which is less than the distance from at least a part of the second bonding surface 312a of the second conductive pad 312 parallel to the bearing surface 313a to the substrate 313, so that the driver chip 33 is upturned
  • the raised second pin 332 is combined with the second joint surface 312a of the second conductive pad 312 corresponding to the raised height.
  • FIG. 16 is a schematic diagram of a display panel according to a fifth embodiment of the present application.
  • the display panel shown in FIG. 16 is basically similar to the display panel shown in FIG. 15, except that the array substrate 31 further includes a plurality of redundant conductive pads 327, and the redundant conductive pads 327 are arranged on the first conductive pad in the second direction.
  • first conductive pads 311 close to the side of the display area 300a, at least two rows of first conductive pads 311 are respectively located on opposite sides of a plurality of redundant conductive pads 327 and two rows of third conductive pads 326 in the first direction, at least two rows of second conductive pads 311
  • the pads 312 are located on opposite sides of the plurality of redundant conductive pads 327 and the two rows of third conductive pads 326 in the first direction, and at least two rows of second conductive pads 312 are located at least two rows of first conductive pads 311 away from the display area 300a.
  • the driver chip 33 On one side, at least two rows of second conductive pads 312 and at least two rows of first conductive pads 311 are obliquely arranged and parallel to each other; the driver chip 33 also includes a plurality of redundant pins 334, and the redundant pins 334 are arranged on the third lead.
  • the pin 333 is close to the position of the first edge 330a, at least two rows of first pins 331 are located on opposite sides of the plurality of redundant pins 334 and the two rows of third pins 333 in the first direction, and at least two rows of second pins
  • the feet 332 are located on opposite sides of the plurality of redundant pins 334 and the two rows of third pins 333 in the first direction, and at least two rows of second pins 332 are located on a side of the at least two rows of first pins 331 away from the display area. On the side, at least two rows of second pins 332 and at least two rows of second pins 332 are obliquely arranged and parallel to each other.
  • the third conductive pad 326 is electrically connected to the third pin through the conductive adhesive layer, and the first conductive pad 311 and the first pin 331 are connected through the first conductive adhesive layer.
  • the second conductive pad 312 and the second pin 332 are electrically connected one-to-one through the second conductive adhesive layer, and the redundant conductive pad 327 and the redundant pin 334 are arranged and connected one-to-one, At least part of the distance from the second bonding surface 312a of the second conductive pad 312 in at least two rows of second conductive pads 312 parallel to the carrying surface to the substrate 313 increases from close to the display area 300a to far away from the display area 300a to accommodate the driver chip 33
  • the degree of warping of the second pin 332 increases from being close to the display area 300a to being away from the display area 300a.
  • FIG. 17 is a partial cross-sectional schematic diagram of a display panel according to a sixth embodiment of the present application.
  • the display panel shown in FIG. 17 is basically similar to the display panel shown in FIG. 4, except that the first conductive pad 311 and the second conductive pad 312 have the same composition and the same thickness, and the thickness of the first pin 331 is less than The thickness of the second pin 332 is such that the raised second pin 332 can be electrically connected to the second conductive pad 312 , ensuring that the driver chip 33 is bound to the array substrate 31 .
  • the thickness of the first lead is different from the thickness of the second lead, so that the distance between the first lead and the second lead and the substrate is compensated to ensure that the first lead and the second lead are
  • the raised one of the second pins can be bound on the array substrate and electrically connected with the corresponding conductive pad.
  • the thickness differentiation of the pins on the control driver chip in this embodiment can be used in combination with the height differentiation of the bonding surface of the conductive pad on the array substrate as shown in Figures 3 to 16 to ensure that the driver chip is warped. All the pins can be electrically connected with corresponding conductive pads on the array substrate.
  • the present application also provides a display device, which includes any one of the above display panels and a backlight module, and the display panel is located on the light emitting side of the backlight module.

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Abstract

一种显示面板(300)及显示装置，通过电性连接第一导电垫（311）和第一引脚（331）的第一导电胶层（401）靠近第一引脚（331）的表面（401a）至基板（313）的距离与电性连接第二导电垫（312）和第二引脚（332）的第二导电胶层（402）靠近第二引脚（332）的表面（402a）至基板（313）的距离不同，以补偿绑定驱动芯片（33）时驱动芯片（33）上引脚部分翘曲导致的高度差异，保证驱动芯片（33）能良好地绑定于显示面板（300）上。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板及显示装置。
 背景技术
如图1所示，其为传统显示面板的平面示意图，显示面板100具有显示区100a，显示面板100包括驱动芯片200，驱动芯片200绑定于显示面板100的显示区100a的一侧，驱动芯片200包括输入引脚201、输出引脚202以及冗余引脚203，输入引脚201和输出引脚202起到传输信号的作用，冗余引脚203不具有输入或输出功能，冗余引脚203只用于支撑驱动芯片200的平衡，冗余引脚203并排设置于驱动芯片200靠近显示区100a的局部区域，输入引脚201和输出引脚202并排设置于冗余引脚203远离显示区100a的一侧，且输入引脚201位于输出引脚202的相对两侧，图1所示驱动芯片200会导致部分远离冗余引脚203的输入引脚201翘起而无法绑定于显示面板100上，进而导致显示面板性能降低，甚至不能正常工作。
因此，有必要提出一种技术方案以解决部分远离冗余引脚的输入引脚翘起而无法绑定于显示面板上导致显示面板不能正常工作的问题。
 技术问题
本申请的目的在于提供一种显示面板，以解决驱动芯片绑定于阵列基板上时由于部分引脚翘起而无法绑定于显示面板上的问题。
 技术解决方案
为实现上述目的，技术方案如下：
一种显示面板，所述显示面板具有显示区和焊盘区，所述焊盘区位于所述显示区的一侧，所述显示面板包括：
基板，具有承载面；
第一导电垫，设置于所述基板的所述承载面上，且位于所述焊盘区；
第二导电垫，设置于所述基板的所述承载面上，且位于所述焊盘区；
驱动芯片，绑定于所述焊盘区，所述驱动芯片包括：
第一引脚，与所述第一导电垫对应设置；以及
第二引脚，与所述第二导电垫对应设置；
第一导电胶层，填充于所述第一导电垫与所述第一引脚之间，且电性连接所述第一导电垫与所述第一引脚；以及
第二导电胶层，填充于所述第二导电垫与所述第二引脚之间，且电性连接所述第二导电垫与所述第二引脚；
其中，所述第一导电胶层靠近所述第一引脚的表面至所述基板的距离与所述第二导电胶层靠近所述第二引脚的表面至所述基板的距离不同。
本申请还提供一种显示装置，所述显示装置包括上述显示面板。
 有益效果
本申请提供一种显示面板及显示装置，通过电性连接第一导电垫和第一引脚的第一导电胶层靠近第一引脚的表面至基板的距离与电性连接第二导电垫和第二引脚的第二导电胶层靠近第二引脚的表面至基板的距离不同，以补偿绑定驱动芯片时驱动芯片上引脚部分翘曲导致的高度差异，保证驱动芯片能良好地绑定于显示面板上。
 附图说明
图1为传统显示面板的平面示意图；
图2为本申请第一实施例显示面板的示意图；
图3为沿图2所示显示面板A-A切线的第一种截面示意图；
图4为图2中驱动芯片绑定于图3中第一导电垫和第二导电垫的截面示意图；
图5为驱动芯片、柔性印刷电路板绑定于阵列基板上的平面示意图；
图6为沿图2所示显示面板A-A切线的第二种截面示意图；
图7为沿图2所示显示面板A-A切线的第三种截面示意图；
图8为沿图2所示显示面板A-A切线的第四种截面示意图；
图9为沿图2所示显示面板A-A切线的第五种截面示意图；
图10为沿图2所示显示面板A-A切线的第六种截面示意图；
图11为本申请第二实施例显示面板的示意图；
图12为沿图11所示显示面板的B-B切线的截面示意图；
图13为本申请第三实施例显示面板的示意图；
图14为沿图13所示显示面板的C-C切线的截面示意图；
图15为本申请第四实施例显示面板的示意图；
图16为本申请第五实施例显示面板的示意图；
图17为本申请第六实施例显示面板的局部截面示意图。
附图标记：
300 显示面板；300a显示区；300b 焊盘区；300b2 空白区域；31 阵列基板； 311 第一导电垫；311a 第一结合面；312 第二导电垫；312a 第二结合面；313 基板；313a 承载面；314 遮光层；3141 遮光图案；3142 遮光构件；3143第一遮光构件；3144 第二遮光构件；315 缓冲层；316 半导体层；3161 有源图案；3162 半导体构件；317 栅极绝缘层；318 第一金属层；3181 栅极；3182第一金属构件；3183 第二金属构件；3184 第五金属构件；3185 第六金属构件；3186 第九金属构件；319 层间绝缘层；319a 第三过孔；319b第四过孔；320 第二金属层；3201 源极；3202 漏极；3203 第三金属构件；3204第四金属构件；3205 第七金属构件；3206 第八金属构件；3207 第十金属构件；321 平坦化层；321a 第一开口；322 第一透明导电层；323 钝化层；323a第二开口；323b第三开口；324第二透明导电层；3241像素电极；3242第一透明导电构件；3243第二透明导电构件；3244 第三透明导电构件；3245第四透明导电构件；3246 第五透明导电构件；325 导电构件；326 第三导电垫；326a 第三结合面；327 冗余导电垫；327a 冗余结合面；328 第四导电垫；328a 第四结合面；329 第五导电垫；329a 第五结合面；33 驱动芯片；330 基体；331 第一引脚；332 第二引脚；333 第三引脚；334 冗余引脚；335 第四引脚；336 第五引脚；330a 第一边缘；330b 第二边缘；34 柔性印刷电路板；341 主体部；342 第一绑定部；343 第二绑定部； 401 第一导电胶层；401a 第一表面；402 第二导电胶层；402a 第二表面；40a导电粒子。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
针对背景技术的问题，发明人发现驱动芯片上的部分引脚翘起的主要原因在于，驱动芯片上的引脚分布不均，导致驱动芯片绑定于显示面板上时，驱动芯片上的多个引脚受的支撑力分布不均，支撑力分布不均导致驱动芯片上的部分引脚出现翘起而无法绑定于显示面板的焊盘上，有鉴于此，本申请通过电性连接第一导电垫和第一引脚的第一导电胶层靠近第一引脚的表面至基板的距离与电性连接第二导电垫和第二引脚的第二导电胶层靠近第二引脚的表面至基板的距离不同，使得驱动芯片上翘起的引脚与导电的第一导电胶层和导电的第二导电胶层中至基板的距离较大的一者结合，保证驱动芯片上翘起的引脚能正常地绑定于显示面板。其中，第一导电垫与第二导电垫均设置于基板的承载面上，且两者均位于焊盘区。
请参阅图2-图5，图2为本申请第一实施例显示面板的示意图，图3为沿图2所示显示面板A-A切线的第一种截面示意图，图4为图2中驱动芯片绑定于图3中第一导电垫和第二导电垫的截面示意图，图5为驱动芯片、柔性印刷电路板绑定于阵列基板上的平面示意图。显示面板300可以为液晶显示面板，显示面板300也可以为有机发光二极管显示面板。具体地，显示面板300为边缘场开关（Fringe Field Switching，FFS）液晶显示面板。可以理解的是，显示面板300也可以为平面转换（In-Plane Switching，IPS）液晶显示面板或者垂直配向（Vertical Alignment）液晶显示面板。显示面板300具有显示区300a和焊盘区300b，焊盘区300b设置于显示区300a的一侧。显示面板300包括阵列基板31、驱动芯片33以及柔性印刷电路板34，驱动芯片33和柔性印刷电路板34均绑定于阵列基板31的焊盘区300b。
在本实施例中，显示面板300对应显示区300a的部分用于显示。在显示区300a，阵列基板31包括多个阵列排布的薄膜晶体管、像素电极、公共电极、扫描线以及数据线。
在本实施例中，焊盘区300b设置有多个导电垫，驱动芯片33绑定于焊盘区300b的多个导电垫上，即显示面板300的驱动芯片33绑定于玻璃上（Chip On Glass，COG）。部分导电垫用于输入电信号且传输至驱动芯片33，以为驱动芯片33工作提供工作信号；部分导电垫用于输出电信号至显示面板300的显示区300a，以为显示面板300提供显示信号。多个导电垫包括多个第一导电垫311和多个第二导电垫312，多个第一导电垫311沿第一方向呈直线并排设置，多个第二导电垫312沿第一方向呈直线并排设置，第二导电垫312位于第一导电垫311远离显示区300a的一侧，多个第二导电垫312与多个第一导电垫311在第二方向上错位设置，以使得与第二导电垫312连接的布线可以从相邻两个第一导电垫311之间的区域之间延伸出。其中，第二方向为显示区300a指向焊盘区300b的方向，第一方向与第二方向垂直。
在本实施例中，驱动芯片33包括基体330、多个第一引脚331以及多个第二引脚332，驱动芯片33具有第一边缘330a和第二边缘330b，第一边缘330a与第二边缘330b相对，驱动芯片33绑定于阵列基板31上时，第一边缘330a靠近显示区300a且第二边缘330b远离显示区300a，多个第一引脚331以及多个第二引脚332均设置于基体330上且靠近第二边缘330b设置，即第一引脚331至第一边缘330a的距离大于第一引脚331至第二边缘330b的距离，且第二引脚332至第一边缘330a的距离大于第二引脚332至第二边缘330b的距离，多个第一引脚331位于多个第二引脚332远离第二边缘330b的一侧，即第二引脚332位于第一引脚331远离显示区100a的一侧，第一引脚331与第二引脚332在第二方向上错位设置。第一引脚331的厚度等于第二引脚332的厚度。
在本实施例中，阵列基板31包括依次堆叠的基板313、遮光层314、缓冲层315、半导体层316、栅极绝缘层317、第一金属层318、层间绝缘层319、第二金属层320、平坦化层321、第一透明导电层322、钝化层323以及第二透明导电层324。
在本实施例中，基板313为玻璃基板，基板313具有承载面313a，承载面313a为平坦的水平表面。
在本实施例中，遮光层314包括遮光图案3141和遮光构件3142，遮光图案3141设置于基板313的承载面313a上且位于显示区300a，遮光图案3141起到遮光的作用，遮光构件3142设置于基板313上且位于焊盘区300b，遮光构件3142对应第二导电垫312设置。遮光层314为金属层。遮光层314的厚度为450埃-550埃。遮光层314的制备材料选自钼、铝、钛、铜以及银中的至少一种。
在本实施例中，缓冲层315覆盖遮光层314以及基板313，缓冲层315位于显示区300a和焊盘区300b。缓冲层315的厚度为2500埃-3500埃。缓冲层315包括氮化硅层和氧化硅层，氮化硅层靠近基板313设置，氧化硅层远离基板313设置。
在本实施例中，半导体层316设置于缓冲层315上，半导体层316包括有源图案3161，有源图案3161位于显示区300a且对应遮光图案3141设置。半导体层316的制备材料选自非晶硅、多晶硅以及金属氧化物中的任意一种。半导体层316的厚度为400埃-500埃。
在本实施例中，栅极绝缘层317覆盖半导体层316和缓冲层315，栅极绝缘层317位于显示区300a和焊盘区300b。栅极绝缘层317的厚度为1000埃-1500埃。栅极绝缘层317的制备材料为氮化硅或者氧化硅。
在本实施例中，第一金属层318设置于栅极绝缘层317上。第一金属层318包括栅极3181、第一金属构件3182以及第二金属构件3183，栅极3181位于显示区300a且对应有源图案3161设置，第一金属构件3182和第二金属构件3183均位于焊盘区300b，第二金属构件3183位于第一金属构件3182远离显示区300a的一侧，第二金属构件3183位于遮光构件3142的正上方，栅极3181的厚度、第一金属构件3182的厚度以及第二金属构件3183的厚度均相同。第一金属层318的厚度为2500埃-3500埃。第一金属层318的制备材料选自钼、铝、钛、铜以及银中的至少一种。
在本实施例中，层间绝缘层319覆盖第一金属层318和栅极绝缘层317，层间绝缘层319位于显示区300a和焊盘区300b。层间绝缘层319的厚度为5500埃-6500埃。层间绝缘层319的制备材料选自氮化硅、氧化硅中的至少一种。
在本实施例中，第二金属层320设置于层间绝缘层319上。第二金属层320包括源极3201、漏极3202、第三金属构件3203以及第四金属构件3204，源极3201和漏极3202位于显示区300a且设置于栅极3181的相对两侧，源极3201通过贯穿层间绝缘层319和栅极绝缘层317的第一过孔与有源图案3161接触，漏极3202通过贯穿层间绝缘层319和栅极绝缘层317的第二过孔与有源图案3161接触，第三金属构件3203对应第一金属构件3182设置且通过贯穿层间绝缘层319的第三过孔319a与第一金属构件3182电性连接，第四金属构件3204对应第二金属构件3183设置且通过贯穿层间绝缘层319的第四过孔319b与第二金属构件3183电性连接，源极3201、漏极3202、第三金属构件3203以及第四金属构件3204的厚度均相同。第二金属层320的厚度为4000埃-6500埃。第二金属层320的制备材料选自钼、铝、钛、铜以及银中的至少一种。
在本实施例中，平坦化层321覆盖第二金属层320和层间绝缘层319，平坦化层321包括位于焊盘区300b的第一开口321a，第一开口321a使第三金属构件3203以及第四金属构件3204均暴露。平坦化层321的厚度为2.0微米-3.0微米。平坦化层321的制备材料为聚酰亚胺或者聚丙烯酸酯。
在本实施例中，第一透明导电层322设置于平坦化层321上且位于显示区300a，第一透明导电层322为公共电极层。第一透明导电层322的制备材料为氧化铟锡。第一透明导电层322的厚度为500埃-700埃。
在本实施例中，在显示区300a，钝化层323覆盖第一透明导电层322；在焊盘区300b，钝化层323覆盖平坦化层321、层间绝缘层319、第三金属构件3203以及第四金属构件3204，钝化层323对应第三金属构件3203设置有第二开口323a，钝化层323对应第四金属构件3204设置有第三开口323b。钝化层323的厚度为800埃-1200埃。钝化层323的制备材料为氮化硅或氧化硅中的任意一种。
在本实施例中，显示区300a的第二透明导电层324设置于钝化层323上，第二透明导电层324包括多个相互独立的像素电极3241、第一透明导电构件3242以及第二透明导电构件3243，第一透明导电构件3242的至少部分位于第二开口323a内且位于第三金属构件3203上，第二透明导电构件3243的至少部分位于第三开口323b内且位于第四金属构件3204上，像素电极3241、第一透明导电构件3242以及第二透明导电构件3243的厚度相同。第二透明导电层324的制备材料为氧化铟锡。第二透明导电层324的厚度为450埃-550埃。
在本实施例中，第一金属构件3182、第三金属构件3203以及第一透明导电构件3242组成第一导电垫311，第一导电垫311具有与驱动芯片33连接的第一结合面311a，第一结合面311a的至少部分与承载面313a平行。第二金属构件3183、第四金属构件3204以及第二透明导电构件3243组成第二导电垫312，第二导电垫312具有与驱动芯片33连接的第二结合面312a，第二结合面312a的至少部分与承载面313a平行。第一导电垫311的厚度等于第二导电垫312的厚度相同。由于第二导电垫312与基板313之间设置有遮光构件3142，使得第二导电垫312相对于第一导电垫311垫高，第一结合面311a与承载面313a平行的至少部分至基板313的距离小于第二结合面312a与承载面313a平行的至少部分至基板313的距离。如图3所示，第一结合面311a和第二结合面312a均与承载面313a平行且用于与驱动芯片33结合，可以理解的是，第一结合面311a和第二结合面312a也可以包括与承载面313a不平行的部分。
在本实施例中，如图4所示，显示面板还包括第一导电胶层401和第二导电胶层402，第一导电胶层401和第二导电胶层402均具有导电性，第一导电胶层401填充于第一导电垫311与第一引脚331之间且电性连接第一导电垫311与第一引脚331，第二导电胶层402填充于第二导电垫312与第二引脚332之间且电性连接第二导电垫312与第二引脚332，第一导电胶层401与第二导电胶层402之间通过各向异性导电胶连接且电性绝缘，第一导电胶层401的厚度与第二导电胶层402的厚度相同。其中，第一导电胶层401和第二导电胶层402的制备材料均为各向异性导电胶，第一导电胶层401和第二导电胶层402通过将各向异性导电胶层贴合至阵列基板上且使各向异性导电胶层受压后各向异性导电胶中的导电粒子40a受压相互接触导通而得到，即第一导电胶层401和第二导电胶层402是各向异性导电胶受压后具有导电性的胶层，且第一导电胶层401的厚度和第二导电胶层402的厚度为各向异性导电胶受压后具有导电性对应的厚度；第一导电胶层401与第二导电胶层402之间的各向异性导电胶中的导电粒子40a没有受力而分散设置导致没有形成导电通路，使得第一导电胶层401与第二导电胶层402之间电性绝缘。由于第一结合面311a至基板313的距离小于第二结合面312a至基板313的距离，第一导电胶层401的厚度与第二导电胶层402的厚度相同，第一导电胶层401靠近第一引脚331的第一表面401a至基板313的距离小于第二导电胶层402靠近第二引脚332的第二表面402a至基板313的距离。
需要说明的是，在其他实施例中，第一结合面311a至基板313的距离也可以等于第二结合面312a至基板313的距离，此时，第一导电胶层401的厚度小于第二导电胶层402的厚度；或者，第一导电胶层401的厚度小于第二导电胶层402的厚度，配合第一结合面311a至基板313的距离小于第二结合面312a至基板313的距离，以使得第一导电胶层401靠近第一引脚331的第一表面401a至基板313的距离小于第二导电胶层402靠近第二引脚332的第二表面402a至基板313的距离。
如图2及图4所示，由于焊盘区300b靠近显示区300a的空白区域300b2没有设置导电垫，多个第一引脚331与多个第一导电垫311一一对应设置且通过第一导电胶层401电性连接后，驱动芯片33靠近显示区300a的一端无支撑而向下倾斜，对应地，驱动芯片33的多个第二引脚332会翘起，多个翘起的第二引脚332与多个通过遮光构件3142垫高的第二导电垫312一一对应设置且通过第二导电胶层402电性连接。
在本实施例中，如图5所示，柔性印刷电路板34包括第一绑定部342、第二绑定部343以及主体部341，第一绑定部342与第二绑定部343均与主体部341连接，第一绑定部342和第二绑定部343均绑定于焊盘区300b且在垂直于显示区300a指向焊盘区300b的方向上位于驱动芯片33的相对两侧。柔性印刷电路板34的设计以及绑定方式使得显示面板300为窄边框的显示面板。
需要说明的是，阵列基板31还包括设置于焊盘区相对两侧的柔性印刷电路板绑定区（未示意出），阵列基板的柔性印刷电路板绑定区也设置有焊盘，柔性印刷电路板与柔性印刷电路板绑定区的焊盘之间电性连接，此处采用现有技术，不做详述。
本实施例显示面板在对应驱动芯片上翘起的第二引脚的第二导电垫的下方设置遮光构件，以垫高第二导电垫，垫高的第二导电垫与翘起的第二引脚之间能实现绑定且电性连接。
请参阅图6，其为沿图2所示显示面板A-A切线的第二种截面示意图。图6所示显示面板与图3所示显示面板基本相似，不同之处在于，半导体层316包括半导体构件3162，半导体构件3162位于焊盘区300b且对应第二导电垫312设置，遮光层314不包括设置于焊盘区300b的遮光构件。
相对于图3所示显示面板采用遮光层314中的遮光构件3142对第二导电垫312进行垫高，图6所示显示面板采用与有源图案3161同层设置的半导体构件3162对第二导电垫312进行垫高。
请参阅图7，其为沿图2所示显示面板A-A切线的第三种截面示意图。图7所示显示面板与图3所示显示面板基本相似，遮光层314包括遮光构件3142，遮光构件3142位于焊盘区300b且对应第二导电垫312设置的同时，半导体层316还包括半导体构件3162，半导体构件3162位于焊盘区300b且对应遮光构件3142设置。
相对于图3和图6所示显示面板中仅在第二导电垫312和基板313之间增设一个膜层，图7所示显示面板通过同时增设遮光构件3142和半导体构件3162，能将第二导电垫312垫得更高，更加有利于第二导电垫312与翘起得更高的第二引脚332之间进行绑定。
请参阅图8，其为沿图2所示显示面板A-A切线的第四种截面示意图。图8所示显示面板与图7所示显示面板基本相似，不同之处包括，在显示面板300的厚度方向上，第一导电垫311与基板313之间设置有第一膜层，第二导电垫312与基板313之间设置有第二膜层，第一膜层位于焊盘区300b且对应第一导电垫311设置，第二膜层位于焊盘区300b且对应第二导电垫312设置，第一膜层与第二膜层同层设置且第一膜层的厚度小于第二膜层的厚度。
具体地，遮光层314包括设置于焊盘区300b的第一遮光构件3143和设置于焊盘区300b的第二遮光构件3144，第一膜层为第一遮光构件3143，第二膜层为第二遮光构件3144，第一遮光构件3143对应第一导电垫311设置，第二遮光构件3144对应第二导电垫312设置，第一遮光构件3143的厚度小于第二遮光构件3144的厚度。可以理解的是，第一膜层也可以为第一导电垫与基板之间的其他膜层，第二膜层也可以为第二导电垫与基板之间的其他膜层，例如第一膜层和第二膜层均与有源图案同层。
在图3、图6、图7以及图8所示显示面板中，第一导电垫311与基板313之间的膜层数目小于第二导电垫312与基板313之间的膜层数目，以使得第一导电垫311的第一结合面311a与基板313的承载面313a平行的至少部分至基板313的距离小于第二导电垫312的第二结合面312a与基板313的承载面313a平行的至少部分至基板313的距离。在图8所示显示面板中，第一导电垫311与基板313之间的第一膜层的厚度小于第二导电垫312与基板313之间与第一膜层同层的第二膜层的厚度，以使得第一导电垫311的第一结合面311a与基板313的承载面313a平行的至少部分至基板313的距离小于第二导电垫312的第二结合面312a与基板313的承载面313a平行的至少部分至基板313的距离。可以理解的是，也可以通过在第二导电垫312与基板313之间增设显示区300a中不包括的其他一个或者多个膜层，该膜层包括但不限于金属层、绝缘层以及平坦化层，以对第二导电垫312进行垫高，垫高的第二导电垫312与翘起的第二引脚332之间实现绑定且电性连接。
请参阅图9，其为沿图2所示显示面板A-A切线的第五种截面示意图。图9所示显示面板与图3所示显示面板基板相似，不同之处在于，第一导电垫311的厚度小于第二导电垫312的厚度，且图9所示遮光层314不包括设置于焊盘区300b的遮光构件。
在本实施例中，第一导电垫311的膜层数目小于第二导电垫312的膜层数目。具体地，第一导电垫311由第一金属构件3182、第三金属构件3203以及第一透明导电构件3242组成，第二导电垫312由第二金属构件3183、第四金属构件3204、第二透明导电构件3243以及导电构件325组成，导电构件325设置于第二透明导电构件3243上，即增加第二导电垫312的膜层数目，以使第一导电垫311的膜层数目小于第二导电垫312的膜层数目。其中，导电构件325可以为透明导电层或者金属导电层。可以理解的是，也可以是第一导电垫311由第一金属构件3182以及第三金属构件3203组成，第二导电垫312由第二金属构件3183、第四金属构件3204以及第二透明导电构件3243组成，即减小第一导电垫311的膜层数目，以使第一导电垫311的膜层数目小于第二导电垫312的膜层数目。
图9所示显示面板通过在第二透明导电构件3243上增设导电构件325，以使得第二导电垫312与驱动芯片33结合的第二结合面312a更高，有利于第二导电垫312与驱动芯片33上翘起的第二引脚332之间绑定且电性连接。也可以通过减少第一导电垫311的膜层数目，以使得第二导电垫312与驱动芯片33结合的第二结合面312a结合。
请参阅图10，其为沿图2所示显示面板A-A切线的第六种截面示意图。图10所示显示面板与图3所示显示面板基本相似，不同之处在于，第一导电垫311包括第一导电膜，第二导电垫312包括第二导电膜，第二导电膜与第一导电膜同层设置，第一导电膜的厚度小于第二导电膜的厚度，且图10所示遮光层314不包括设置于焊盘区300b的遮光构件。
具体地，第一导电垫311由第一金属构件3182、第三金属构件3203以及第一透明导电构件3242组成，第二导电垫312由第二金属构件3183、第四金属构件3204以及第二透明导电构件3243组成，第一金属构件3182的厚度等于第二金属构件3183的厚度，第三金属构件3203的厚度小于第四金属构件3204的厚度，第一透明导电构件3242的厚度等于第二透明导电构件3243的厚度。可以理解的是，也可以第一金属构件3182的厚度小于第二金属构件3183的厚度，第三金属构件3203的厚度等于第四金属构件3204的厚度，第一透明导电构件3242的厚度等于第二透明导电构件3243的厚度。
图10所示显示面板通过使组成第一导电垫311的导电膜的厚度小于组成第二导电垫312的导电膜的厚度，以使得第二导电垫312的第二结合面312a至基板313的距离大于第一导电垫311的第一结合面311a至基板313的距离，有利于驱动芯片33上翘起的第二引脚332与第二导电垫312的第二结合面312a结合。
图9所示显示面板和图10所示显示面板通过调整第一导电垫311的膜层数目小于第二导电垫312的膜层数目，或者，调整第一导电垫311的导电膜层的厚度小于第二导电垫312的导电膜层的厚度，以使第一导电垫311的厚度小于第二导电垫312的厚度，进而使得第二导电垫312的第二结合面312a至基板的距离大于第一导电垫311的第一结合面311a至基板的距离，使得第二结合面312a与驱动芯片33上翘起的第二引脚332连接。
需要说明的是，图9所示第一导电垫311的膜层数目小于第二导电垫312的膜层数目，图10所示第一导电垫311的第一导电膜的厚度小于第二导电垫312的第二导电垫的厚度，图3、图6、图7中所示第一导电垫与基板之间的膜层数目小于第二导电垫与基板之间的膜层数目，以及图8所示第一导电垫311与基板313之间的第一膜层的厚度小于第二导电垫与基板之间与第一膜层同层的第二膜层的厚度可以相互组合，以使得第二导电垫312的第二结合面312a至基板的距离大于第一导电垫311的第一结合面311a的距离。
请参阅图11及图12，图11为本申请第二实施例显示面板的示意图，图12为沿图11所示显示面板的B-B切线的截面示意图。图11所示显示面板与图3所示显示面板基本相似，阵列基板31包括设置于基板313的承载面313a上的第一导电垫311、第二导电垫312、第三导电垫326以及冗余导电垫327，第一导电垫311、第二导电垫312、第三导电垫326以及冗余导电垫327均设置于焊盘区300b，第一导电垫311、第二导电垫312、第三导电垫326均会传输电信号，冗余导电垫327不会传输信号。多个冗余导电垫327沿第一方向呈直线形并排设置，多个第一导电垫311沿第一方向呈直线形并排设置，且多个冗余导电垫327位于第一导电垫311靠近显示区300a的一侧，多个第二导电垫312以及多个第三导电垫326设置于多个第一导电垫311远离显示区300a的一侧，多个第二导电垫312以及多个第三导电垫326沿第一方向呈直线形并排设置，且多个第二导电垫312在第一方向上对称地设置于多个第三导电垫326的相对两侧，一部分第一导电垫311与多个第二导电垫312在第二方向（显示区300a指向焊盘区300b的方向）上相邻设置且第一导电垫311与多个第二导电垫312在第二方向上错位设置，另一部分第一导电垫311与多个第三导电垫326与在第二方向上也相邻且错位设置，在第一方向上多个第二导电垫312位于多个冗余导电垫327的相对两侧，且部分第一导电垫311在第一方向上也位于多个冗余导电垫327的相对两侧。其中，第一导电垫311与上述图3中的第一导电垫相同，第二导电垫312与上述图3中的第二导电垫相同。第三导电垫326由第五金属构件3184、第七金属构件3205以及第三透明导电构件3244组成。冗余导电垫327由第六金属构件3185、第八金属构件3206以及第四透明导电构件3245组成。第一导电垫311具有第一结合面311a，第二导电垫312具有第二结合面312a，第三导电垫326具有第三结合面326a，第三结合面326a与承载面平行，第三结合面326a上设置有导电胶层，冗余导电垫327具有冗余结合面327a，冗余结合面327a与承载面313a平行，第一结合面311a与承载面313a平行的至少部分至基板313的距离小于第二结合面312a与承载面313a平行的至少部分至基板313的距离，第三结合面326a与承载面313a平行的至少部分至基板313的距离小于第二结合面312a与承载面313a平行的至少部分至基板313的距离，第三结合面326a与承载面313a平行的至少部分至基板313的距离等于第一结合面311a与承载面313a平行的至少部分至基板313的距离，冗余结合面327a与承载面313a平行的至少部分至基板313的距离等于第一结合面311a与承载面313a平行的至少部分至基板313的距离。
在本实施例中，驱动芯片33包括第一引脚331、第二引脚332、第三引脚333以及冗余引脚334。驱动芯片33具有第一边缘330a和第二边缘330b，第一边缘330a与第二边缘330b相对，驱动芯片33绑定于显示面板300上时，第一边缘330a靠近显示区300a，第二边缘330b远离显示区300a。冗余引脚334靠近第一边缘330a呈直线形并排设置使得多个冗余引脚334靠近显示区300a设置，冗余引脚334不会接入电信号。第一引脚331靠近第二边缘330b呈直线形并排设置，多个第二引脚332与多个第三引脚333位于多个第一引脚331远离显示区300a的一侧，多个第二引脚332在第一方向上设置于多个第三引脚333的相对两侧，部分第一引脚331在第二方向上与第二引脚332相邻错开设置且该部分第一引脚331在第一方向上位于多个冗余引脚334的相对两侧，另一部分第一引脚331在第二方向上与多个第三引脚333相邻错开设置，且多个第二引脚332在第一方向上对称地位于多个冗余引脚334的相对两侧，第一引脚331的厚度、第二引脚332的厚度、第三引脚333的厚度以及冗余引脚334的厚度均相等。
驱动芯片33绑定于显示面板300上时，多个冗余引脚334与多个冗余导电垫327一对一设置且连接，多个第一引脚331与多个第一导电垫311一对一设置且电性连接，多个第三引脚333与多个第三导电垫326一对一设置且第三结合面326a与第三引脚333之间填充有导电胶层，由于多个冗余导电垫327的相对两侧的布线区域300b1设置有多个布线，导致布线区域300b1没有设置冗余导电垫327，驱动芯片33在布线区域300b1无支撑而下倾，对应地，驱动芯片33的多个第二引脚332翘起，多个翘起的第二引脚332与垫高的第二导电垫312的第二结合面312a通过填充于两者之间的第二导电胶层402结合且第二引脚332与第二导电垫312电性连接，进而使得多个第二引脚332能绑定于阵列基板上且第二引脚332与对应的第二导电垫312电性连接。
在本实施例中，由于多个第二引脚332在第一方向上位于多个冗余电垫327的相对两侧而受到冗余电垫327的支撑力不同，多个第二引脚332翘起的程度也不同，第二引脚332距离冗余导电垫327越远则获得的支撑力越小，第二引脚332翘起越高，多个第二导电垫312的第二结合面312a与承载面313a平行的至少部分至基板313的距离从靠近第三导电垫326至远离第三导电垫326而递增，以适应驱动芯片33绑定于阵列基板上时，翘起的第二引脚332至基板313的距离从靠近第三导电垫326至远离第三导电垫326递增。
需要说明的是，第一导电垫311的第一结合面311a与承载面平行的至少部分至基板的距离小于第二导电垫312的第二结合面312a与承载面平行的至少部分至基板的距离可以通过前述方法实现，此处不做详述。
请参阅图13及图14，图13为本申请第三实施例显示面板的示意图，图14为沿图13所示显示面板的C-C切线的截面示意图。图13所示显示面板与图12所示显示面板基本相似，不同之处包括，阵列基板31还包括至少两排第四导电垫328和至少一排第五导电垫329，至少两排第四导电垫328位于至少一排第五导电垫329远离显示区300a的一侧，至少两排第四导电垫328和至少一排第五导电垫329沿第二方向设置且在第二方向上位于冗余导电垫327远离显示区300a的一侧，至少两排第四导电垫328在第一方向上位于第二导电垫312的相对两侧，故至少两排第四导电垫328在第一方向上也位于冗余导电垫327的相对两侧，至少一排第五导电垫329在第一方向上位于第一导电垫311的相对两侧，故至少一排第五导电垫329在第一方向上也位于冗余导电垫327的相对两侧，每个第四导电垫328具有第四结合面328a，第四结合面328a与承载面313a平行，每个第五导电垫329具有第五结合面329a，第五结合面329a与承载面313a平行；驱动芯片33还包括至少两排第四引脚335以及至少一排第五引脚336，至少两排第四引脚335位于至少一排第五引脚336远离显示区的一侧，至少两排第四引脚335与至少一排第五引脚336沿第二方向设置且在第二方向上位于冗余引脚334远离显示区300a的一侧，至少两排第四引脚335与至少两排第四导电垫328一一对应设置且电性连接，至少一排第五引脚336与至少一排第五导电垫329一一对应设置且电性连接，第四结合面328a与第四引脚335相对且两者之间填充有导电胶层，第五结合面329a与第五引脚336相对且两者之间填充有导电胶层，第五导电垫329的第五结合面329a与承载面313a平行的至少部分至基板313的距离小于靠近第五导电垫329的第四导电垫328的第四结合面328a与承载面313a平行的至少部分至基板313的距离，第五导电垫329的第五结合面329a与承载面313a平行的至少部分至基板313的距离等于第一导电垫311的第一结合面311a与承载面平行的至少部分至基板的距离，至少两排第四导电垫328的第四结合面328a与承载面313a平行的至少部分至基板313的距离从靠近显示区300a至远离显示区300a递增，以适应与第四导电垫328对应的第四引脚335从靠近显示区300a至远离显示区300a的翘起程度递增。
具体地，每个第四导电垫328由第九金属构件3186、第十金属构件3207以及第五透明导电构件3246组成，多个第四导电垫328的第九金属构件3186的厚度相同，多个第四导电垫328的第五透明导电构件3246的厚度相同，至少两排第四导电垫328的第十金属构件3207的厚度从靠近显示区300a至远离显示区300a递增，进而使得至少两排第四导电垫328的第四结合面328a与承载面313a平行的至少部分至基板313的距离在第二方向上从靠近显示区300a至远离显示区300a递增。
需要说明的是，在第二方向上，多个冗余导电垫的相对两侧为未设置冗余导电垫的空白区域，驱动芯片33绑定阵列基板上时，驱动芯片33在空白区域处无支撑而下倾，导致距离显示区300a越远的第四引脚335翘起越高，对应地，需要与第四引脚335对应的第四导电垫328的第四结合面328a越高。在第一方向上，由于多个第四导电垫328在第一方向上位于多个冗余导电垫327的相对两侧，多个第四导电垫328距离冗余导电垫327越远，则第四导电垫328得到冗余导电垫327支撑越小，则驱动芯片上的第四引脚335翘起得越高，在第一方向上，至少两排第四导电垫328的第四结合面328a与承载面313a平行的至少部分至基板313的距离从靠近第二导电垫312至远离第二导电垫312而递增，与第二导电垫312相邻的第四导电垫328的第四结合面328a与承载面313a平行的至少部分至基板313的距离大于与第四导电垫328相邻的第二导电垫312的第二结合面312a与承载面313a平行的至少部分至基板313的距离。
请参阅图15，其为本申请第四实施例显示面板的示意图。图15所示显示面板与图2所示显示面板基本相似，显示面板300包括多个第一导电垫311、多个第二导电垫312以及多个第三导电垫326，多个第三导电垫326呈两排设置，两排第一导电垫311在第一方向上分别倾斜地设置于两排第三导电垫326的相对两侧，且两排第二导电垫312在第一方向上倾斜地分别设置于两排第三导电垫326的相对两侧，两排第二导电垫312在第二方向上分别位于两排第一导电垫311远离显示区300a的一侧，一排第一导电垫311与一排第二导电垫312相邻且平行设置，一排第一导电垫311所在直线与一排第三导电垫326所在直线之间的夹角大于0且小于90度；驱动芯片33包括与第一导电垫311一一对应的第一引脚331、与第二导电垫312一一对应的第二引脚332以及与第三导电垫326一一对应的第三引脚333，多个第三引脚333在第二方向上呈两排设置于驱动芯片33的中间位置，且多个第一引脚331分为两排分别倾斜地设置于两排第三引脚333的相对两侧，多个第二引脚332分为两排分别倾斜地设置于两排第三引脚333的相对两侧，两排第一引脚331和两排第二引脚332靠近驱动芯片33的第二边缘330b设置。图15所示第一导电垫311的组成和第二导电垫312的组成分别与图2所示第一导电垫311的组成和第二导电垫312的组成相同，此处不做详述，图15所示第三导电垫326的组成与图15所示第一导电垫311的组成相同。
具体地，由于驱动芯片33绑定于显示面板300上时，驱动芯片33靠近显示区300a的一端无支撑，驱动芯片33的多个第一引脚331绑定于第一导电垫311上且第三引脚333绑定于第三导电垫326上时，驱动芯片33靠近显示区300a的一端下倾，且驱动芯片33的多个第二引脚332会翘起，第一导电垫311的第一结合面311a与承载面313a平行的至少部分至基板313的距离小于第二导电垫312的第二结合面312a与承载面313a平行的至少部分至基板313的距离，以使得驱动芯片33上翘起的第二引脚332与对应垫高的第二导电垫312的第二结合面312a结合。
请参阅图16，其为本申请第五实施例显示面板的示意图。图16所示显示面板与图15所示显示面板基本相似，不同之处在于，阵列基板31还包括多个冗余导电垫327，冗余导电垫327在第二方向上设置于第一导电垫311靠近显示区300a的一侧，至少两排第一导电垫311在第一方向上分别位于多个冗余导电垫327和两排第三导电垫326的相对两侧，至少两排第二导电垫312在第一方向上位于多个冗余导电垫327和两排第三导电垫326的相对两侧，至少两排第二导电垫312位于至少两排第一导电垫311远离显示区300a的一侧，至少两排第二导电垫312与至少两排第一导电垫311均倾斜设置且相互平行；驱动芯片33还包括多个冗余引脚334，冗余引脚334设置于第三引脚333靠近第一边缘330a的位置，至少两排第一引脚331在第一方向上位于多个冗余引脚334和两排第三引脚333的相对两侧，至少两排第二引脚332在第一方向上位于多个冗余引脚334和两排第三引脚333的相对两侧，至少两排第二引脚332位于至少两排第一引脚331远离显示区的一侧，至少两排第二引脚332与至少两排第二引脚332均倾斜设置且相互平行。
驱动芯片33绑定于阵列基板31上时，第三导电垫326与第三引脚通过导电胶层电性连接，第一导电垫311与第一引脚331之间通过第一导电胶层一对一电性连接，第二导电垫312与第二引脚332之间通过第二导电胶层一对一电性连接，冗余导电垫327与冗余引脚334一对一设置且连接，至少两排第二导电垫312中的第二导电垫312的第二结合面312a与承载面平行的至少部分至基板313的距离从靠近显示区300a至远离显示区300a递增，以适应驱动芯片33绑定于阵列基板上时第二引脚332从靠近显示区300a至远离显示区300a的翘起程度增加的情况。
请参阅图17，其为本申请第六实施例显示面板的局部截面示意图。图17所示显示面板与图4所示显示面板基本相似，不同之处在于，第一导电垫311与第二导电垫312的组成相同且两者的厚度相同，第一引脚331的厚度小于第二引脚332的厚度，以使得翘起的第二引脚332能与第二导电垫312之间实现电性连接，保证驱动芯片33绑定于阵列基板31上。
本实施例通过使第一引脚的厚度与第二引脚的厚度不同，以使补偿第一引脚和第二引脚中翘起的一者与基板之间距离，保证第一引脚和第二引脚中翘起的一者能绑定于阵列基板上且与对应的导电垫电性连接。
需要说明的是，本实施例控制驱动芯片上的引脚的厚度差异化与图3-图16控制阵列基板上导电垫的结合面的高度差异化可以结合使用，以保证驱动芯片上翘起的引脚均能与阵列基板上对应的导电垫电性连接。
本申请还提供一种显示装置，显示装置包括上述任意一种显示面板和背光模组，显示面板位于背光模组的出光侧。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其中，所述显示面板具有显示区和焊盘区，所述焊盘区位于所述显示区的一侧，所述显示面板包括：
    基板，具有承载面；
    第一导电垫，设置于所述基板的所述承载面上，且位于所述焊盘区；
    第二导电垫，设置于所述基板的所述承载面上，且位于所述焊盘区；
    驱动芯片，绑定于所述焊盘区，所述驱动芯片包括：
    第一引脚，与所述第一导电垫对应设置；以及
    第二引脚，与所述第二导电垫对应设置；
    第一导电胶层，填充于所述第一导电垫与所述第一引脚之间，且电性连接所述第一导电垫与所述第一引脚；以及
    第二导电胶层，填充于所述第二导电垫与所述第二引脚之间，且电性连接所述第二导电垫与所述第二引脚；
    其中，所述第一导电胶层靠近所述第一引脚的表面至所述基板的距离与所述第二导电胶层靠近所述第二引脚的表面至所述基板的距离不同。
  2. 根据权利要求1所述的显示面板，其中，所述第一导电垫具有与所述承载面至少部分平行且与所述第一导电胶层接触的第一结合面，所述第二导电垫具有与所述承载面至少部分平行且与所述第二导电胶层接触的第二结合面，所述第一结合面与所述承载面平行的至少部分至所述基板的距离与所述第二结合面与所述承载面平行的至少部分至所述基板的距离不同。
  3. 根据权利要求2所述的显示面板，其中，所述第二导电垫位于所述第一导电垫远离所述显示区的一侧，所述第二引脚位于所述第一引脚远离所述显示区的一侧，所述第一结合面与所述承载面平行的至少部分至所述基板的距离小于所述第二结合面与所述承载面平行的至少部分至所述基板的距离。
  4. 根据权利要求3所述的显示面板，其中，所述第一导电垫的厚度小于所述第二导电垫的厚度。
  5. 根据权利要求4所述的显示面板，其中，组成所述第一导电垫的膜层数目小于组成所述第二导电垫的膜层数目。
  6. 根据权利要求4所述的显示面板，其中，所述第一导电垫包括第一导电膜，所述第二导电垫包括与所述第一导电膜同层设置的第二导电膜，所述第一导电膜的厚度小于所述第二导电膜的厚度。
  7. 根据权利要求3所述的显示面板，其中，所述第一导电垫的厚度等于所述第二导电垫的厚度。
  8. 根据权利要求3所述的显示面板，其中，在所述显示面板的厚度方向上，所述第一导电垫与所述基板之间的膜层数目小于所述第二导电垫与所述基板之间的膜层数目。
  9. 根据权利要求3所述的显示面板，其中，在所述显示面板的厚度方向上，所述第一导电垫与所述基板之间设置有第一膜层，所述第二导电垫与所述基板之间设置有第二膜层，所述第一膜层位于焊盘区且对应所述第一导电垫设置，所述第二膜层位于焊盘区且对应所述第二导电垫设置，所述第一膜层与所述第二膜层同层设置且所述第一膜层的厚度小于所述第二膜层的厚度。
  10. 根据权利要求3所述的显示面板，其中，所述显示面板包括多个所述第二导电垫，所述显示面板还包括：
    多个冗余导电垫，设置于所述基板的所述承载面上，且位于所述焊盘区，多个所述冗余导电垫位于所述第一导电垫靠近所述显示区的一侧，且多个所述第二导电垫在垂直于所述显示区指向所述焊盘区的方向上位于多个所述冗余导电垫的相对两侧；
    所述驱动芯片包括多个所述第二引脚，所述驱动芯片还包括：
    多个冗余引脚，与多个所述冗余导电垫一一对应设置，位于所述第一引脚靠近所述显示区的一侧，且多个所述第二引脚在垂直于所述显示区指向所述焊盘区的方向上位于多个所述冗余引脚的相对两侧。
  11. 根据权利要求10所述的显示面板，其中，所述第一引脚的厚度小于或等于所述第二引脚的厚度。
  12. 根据权利要求10所述的显示面板，其中，所述第一导电垫为多个，所述显示面板还包括：
    第三导电垫，设置于所述焊盘区，在所述显示区指向所述焊盘区的方向上位于多个所述第一导电垫远离所述显示区的一侧且与部分所述第一导电垫相邻且错开设置，且所述第三导电垫具有与所述承载面至少部分平行的第三结合面，多个所述第二导电垫在垂直于所述显示区指向所述焊盘区的方向上位于所述第三导电垫的相对两侧；
    所述第一引脚为多个，所述驱动芯片还包括：
    第三引脚，与所述第三导电垫一一对应设置且电性连接，在所述显示区指向所述焊盘区的方向上位于所述第一引脚远离所述显示区的一侧且与部分所述第一引脚相邻且错开设置，多个所述第二引脚在垂直于所述显示区指向所述焊盘区的方向上位于所述第三引脚的相对两侧；
    其中，所述第三结合面与所述第三引脚之间填充有导电胶层，且所述第三结合面与所述承载面平行的至少部分至所述基板的距离小于所述第二结合面与所述承载面平行的至少部分至所述基板的距离。
  13. 根据权利要求12所述的显示面板，其中，多个所述第二导电垫的所述第二结合面与所述承载面平行的至少部分至所述基板的距离沿从靠近所述第三导电垫至远离所述第三导电垫的方向而递增。
  14. 根据权利要求12所述的显示面板，其中，所述第三结合面与所述承载面平行的至少部分至所述基板的距离等于所述第一结合面与所述承载面平行的至少部分至所述基板的距离。
  15. 根据权利要求10所述的显示面板，其中，所述显示面板还包括：
    至少两排设置于所述焊盘区的第四导电垫，至少两排第四导电垫位于所述第一导电垫远离所述显示区的一侧，至少两排第四导电垫在垂直于显示区指向焊盘区的方向上位于所述第二导电垫的相对两侧，每排所述第四导电垫包括至少两个并排设置的所述第四导电垫，至少两排所述第四导电垫沿所述显示区指向所述焊盘区的方向排布，每个所述第四导电垫具有第四结合面；
    所述驱动芯片还包括：
    至少两排第四引脚，与至少两排所述第四导电垫一一对应设置且电性连接，位于所述第一引脚远离所述显示区的一侧，且在垂直于显示区指向焊盘区的方向上位于所述第二引脚的相对两侧；
    其中，所述第四结合面与所述第四引脚之间填充有导电胶层，至少两排所述第四导电垫的所述第四结合面与所述承载面平行的至少部分至所述基板的距离在所述显示区指向所述焊盘区的方向上从靠近显示区至远离所述显示区递增。
  16. 根据权利要求15所述的显示面板，其中，在垂直于所述显示区指向所述焊盘区的方向上，至少两排所述第四导电垫的所述第四结合面与所述承载面平行的至少部分至所述基板的距离从靠近第二导电垫至远离所述第二导电垫递增。
  17. 根据权利要求1所述的显示面板，其中，所述第二导电垫位于所述第一导电垫远离所述显示区的一侧，所述第一导电胶层与所述第二导电胶层连接且所述第一导电胶层与所述第二导电胶层之间电性绝缘，所述第一导电胶层的厚度小于所述第二导电胶层的厚度。
  18. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    柔性印刷电路板，包括第一绑定部、第二绑定部以及主体部，所述第一绑定部与所述第二绑定部均与所述主体部连接，所述第一绑定部和所述第二绑定部均绑定于所述焊盘区且在垂直于所述显示区指向焊盘区的方向上位于所述驱动芯片的相对两侧。
  19. 根据权利要求1所述的显示面板，其中，所述第一引脚和所述第二引脚均为多个，多个所述第一引脚和多个所述第二引脚设置在所述驱动芯片远离所述显示区的一侧，所述驱动芯片还包括设置在靠近所述显示区的多个冗余引脚，在所述显示区指向所述焊盘区的方向上多个所述第二引脚位于多个所述第一引脚远离多个所述冗余引脚的一侧且至少部分所述第一引脚与多个所述第二引脚相邻设置；
    在垂直于所述显示区指向所述焊盘区的方向上，至少部分所述第一引脚分别位于多个所述冗余引脚的相对两侧，且多个所述第二引脚均分别位于多个所述冗余引脚的相对两侧。
  20. 一种显示装置，其中，所述显示装置包括如权利要求1所述的显示面板。
PCT/CN2021/123357 2021-09-30 2021-10-12 显示面板及显示装置 WO2023050474A1 (zh)

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