WO2023050055A9 - 显示面板及其测试方法、显示装置 - Google Patents

显示面板及其测试方法、显示装置 Download PDF

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Publication number
WO2023050055A9
WO2023050055A9 PCT/CN2021/121293 CN2021121293W WO2023050055A9 WO 2023050055 A9 WO2023050055 A9 WO 2023050055A9 CN 2021121293 W CN2021121293 W CN 2021121293W WO 2023050055 A9 WO2023050055 A9 WO 2023050055A9
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WIPO (PCT)
Prior art keywords
test
display area
signal line
display panel
signal
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Application number
PCT/CN2021/121293
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English (en)
French (fr)
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WO2023050055A1 (zh
Inventor
袁志东
徐攀
李永谦
袁粲
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/121293 priority Critical patent/WO2023050055A1/zh
Priority to CN202180002735.6A priority patent/CN116235236A/zh
Publication of WO2023050055A1 publication Critical patent/WO2023050055A1/zh
Publication of WO2023050055A9 publication Critical patent/WO2023050055A9/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes

Definitions

  • At least one embodiment of the present disclosure relates to a display panel, a testing method thereof, and a display device.
  • an organic light emitting diode (OLED) display device includes a display panel, a gate driving device, a data driver, and a timing controller.
  • the display panel includes a pixel array, which includes multiple rows and columns of pixels, as well as data lines and gate lines that control the operation of each row of pixels.
  • the usual working method is that when a gate drive signal is provided to a gate line, the pixels in the pixel row corresponding to the gate line are provided with the data voltage of the data line, and the pixels emit light of different brightnesses according to the size of the data voltage.
  • the gate driving device provides gate driving signals to the gate lines, and the gate driving device includes a scan driving circuit.
  • the scan drive circuit needs to be tested to determine whether the scan drive circuit is working properly.
  • At least one embodiment of the present disclosure provides a display panel, which includes: a base substrate, a pixel array, a scan driver circuit, a test circuit board, and test leads.
  • the base substrate includes a display area and a non-display area at least partially surrounding the display area;
  • a pixel array is located in the display area on the base substrate and includes a plurality of pixel rows extending along the first direction, so Each pixel row of the plurality of pixel rows includes a first signal line and a sub-pixel, the sub-pixel includes a pixel circuit, and the first signal line is configured to provide a scanning signal to the pixel circuit in the pixel row in which it is located.
  • the scan driving circuit is configured to provide the scan signal to the pixel circuit, and includes a shift register and a clock signal line located in the display area; a test circuit board is located in the non-display area, and includes a test pad; test The lead is located in the non-display area and is electrically connected to the test pad.
  • the first signal line includes a first part located in the display area and a second part located in the non-display area and connected to the first part. , the first part extends as a whole along the first direction, and the second part is connected to the first part; before testing the display panel, the first signal line and the test lead are in different layers.
  • test leads and the second part of the first signal line are configured to be connected to each other, and the test circuit board is configured to pass through the test pad and the second part of the first signal line.
  • the test lead acquires the test signal from the first signal line.
  • the orthographic projection of the second part of the first signal line on the base substrate before testing the display panel, is aligned with the test lead on the display panel.
  • the orthographic projection on the base substrate at least partially overlaps; when testing the display panel, the orthographic projection of the second part of the first signal line on the base substrate is in the same position as the test lead. Portions where orthographic projections overlap on the base substrate are configured to be connected to each other.
  • the display panel provided by at least one embodiment of the present disclosure further includes an interlayer insulating layer.
  • the interlayer insulating layer is located between the first signal line and the test lead to The two are insulated, and the first signal line, the interlayer insulating layer and the test lead are configured to be melted by the laser at a preset position so that the first signal line and the test lead are at the preset position.
  • the preset position is electrically connected, and the preset position is located in the overlapping area of the orthographic projection of the first signal line on the base substrate and the orthographic projection of the test lead on the base substrate.
  • the test lead before testing the display panel, is located on a side of the first signal line away from the base substrate, and the third No conductive layer is provided between a signal line and the base substrate; or, the test lead is located on a side of the first signal line close to the base substrate, and the test lead is connected to the substrate. There is no conductive layer between the substrates.
  • the first signal line is a gate line.
  • the display panel provided by at least one embodiment of the present disclosure, there is a gap area between adjacent pixel rows in the plurality of pixel rows, and the shift register and the clock signal line are located in the gap area.
  • each of the plurality of pixel rows includes a plurality of the first signal lines
  • the display panel includes a plurality of the test pads and A plurality of test leads
  • each of the plurality of test pads is electrically connected to at least one test lead of the plurality of test leads in the non-display area; before testing the display panel, An orthographic projection of each of the plurality of test leads on the substrate is aligned with a second portion of the plurality of first signal lines in at least one of the pixel rows of the display panel on the substrate. The orthographic projections on the substrate at least partially overlap.
  • the orthographic projection of each of the plurality of test leads on the base substrate is consistent with the plurality of pixels.
  • the orthographic projections of the second portions of the plurality of first signal lines of the same pixel row in the row on the substrate at least partially overlap, or the projections of each of the plurality of test leads on the substrate are
  • the orthographic projection at least partially overlaps with the orthographic projection of the second portions of the plurality of first signal lines of adjacent pixel rows among the plurality of pixel rows on the base substrate.
  • no switching device is provided between each of the plurality of first signal lines and the test lead overlapping its orthographic projection.
  • each of the plurality of test leads includes a main lead and a plurality of sub-leads.
  • the main body lead includes a first end connected to the test pad and a second end far away from the test pad.
  • the second end extends along a second direction, and the second direction is connected to the first
  • the direction is basically vertical; a plurality of sub-leads are connected to the second end of the main body lead, protrude from the second end, and correspond to the plurality of first signal lines one-to-one; when testing the display panel First, an orthographic projection of each of the plurality of sub-leads on the base substrate at least partially overlaps with an orthographic projection of the corresponding second part of the first signal line on the base substrate.
  • the end of the second part of each of the plurality of first signal lines close to the corresponding sub-lead is The first test pad has a first test pad, the width of the first test pad in the line width direction of the first signal line is greater than the line width of the first signal line; the first end of each of the plurality of sub-leads Connected to the main body lead, the second end of each of the plurality of sub-leads has a second test disk, and the width of the second test disk in the line width direction of the sub-lead is greater than the line width of the sub-lead;
  • the orthographic projection of the second test disk on the base substrate at least partially overlaps the orthographic projection of the corresponding first test disk on the base substrate of the first signal line.
  • the first test pads of the plurality of first signal lines are arranged at intervals along the second direction, corresponding to the plurality of first signal lines in a one-to-one manner.
  • the plurality of sub-leads are spaced apart from each other along the second direction, and the second test pads of the plurality of sub-leads are spaced apart from each other along the second direction.
  • the second part includes a first lateral part.
  • a first lateral portion extends along the first direction and is connected to the first portion, an end of the first lateral portion away from the first portion includes the first test pad, and the plurality of first signal lines
  • the first transverse portions are aligned along said second direction.
  • the second part includes a first lateral part, a first longitudinal part and a second lateral part.
  • a first transverse portion extends along the first direction and is connected to the first portion; a first longitudinal portion is connected to the first transverse portion and extends along the second direction; a second transverse portion is connected to the first longitudinal portion are partially connected and extend along the first direction; the end of the second transverse portion away from the first longitudinal portion includes the first test pad, and the first transverse portions of the plurality of first signal lines extend along Arrangement in the second direction, second lateral portions of the plurality of first signal lines are arranged along the second direction, and first test pads of the plurality of first signal lines are not located on the same straight line extending along the second direction.
  • the pixel circuit includes a light-emitting element, a driving transistor, a data writing transistor and a storage capacitor;
  • the data writing transistor is configured to operate under the control of the scanning signal.
  • the data signal is transmitted to the driving transistor, and the driving transistor is configured to control the size of the driving current flowing through the light-emitting element according to the data signal;
  • the storage capacitor includes a first plate and a second plate , the first electrode plate is electrically connected to the gate of the driving transistor, and the orthographic projection of the second electrode plate on the base substrate is the same as the orthogonal projection of the first electrode plate on the base substrate.
  • the projections at least partially overlap; before testing the display panel, the first signal line and the first plate of the storage capacitor are arranged on the same layer, and the test lead and the second plate of the storage capacitor are arranged on the same layer, or the first signal line and the first plate of the storage capacitor are arranged on the same layer, and the display panel further includes a light-shielding layer located close to the first signal line
  • the orthographic projection of the channel region of the driving transistor on the base substrate is located within the orthographic projection of the light shielding layer on the base substrate, and the test lead is connected to The light-shielding layer is arranged on the same layer.
  • the display panel provided in at least one embodiment of the present disclosure further includes a plurality of alignment marks.
  • the patterns of the plurality of alignment marks are different from each other and are arranged in one-to-one correspondence with the plurality of first signal lines, and are respectively spaced from the overlapping areas of the corresponding first signal lines; in the display When the panel is tested, the plurality of alignment marks are configured to be recognized by the alignment device respectively to locate the preset positions in the overlapping area of the corresponding first signal line; the alignment marks It is provided in the same layer as any one of the active layer of the driving transistor, the first signal line and the test lead.
  • the test circuit board is a chip-on-film (COF), and the plurality of test pads are arranged at intervals in the chip-on-film.
  • COF chip-on-film
  • the non-display area includes a first non-display area, a second non-display area and a third non-display area, and the first non-display area and the third non-display area
  • Two non-display areas are respectively located on the first side and the second side of the display area in the first direction
  • the third non-display area is located on the first side of the display area in the second direction
  • the base substrate includes a first edge close to the first non-display area and extending along the second direction, a second edge close to the second non-display area and extending along the second direction, and a second edge close to the second non-display area and extending along the second direction.
  • the first signal line of a pixel row is connected to the test lead in the first non-display area; the plurality of test pads are located in the third non-display area and arranged along the third edge of the base substrate , or the plurality of test pads are located in the first non-display area and arranged along the first edge of the base substrate.
  • a first portion of the first signal lines of the plurality of pixel rows extends from the display area to the first non-display area, so The first part of the first signal line is connected to the test lead in the first non-display area; the second part of the first signal line among the first signal lines of the plurality of pixel rows extends from the display area to the The second non-display area, the second part of the first signal line is connected to the test lead in the second non-display area; the first part of the test pads among the plurality of test pads is located in the first The non-display area is arranged along the first edge of the base substrate.
  • a second part of the test pads among the plurality of test pads is located in the second non-display area and is arranged along the first edge of the base substrate. Two edges are arranged, or the first part of the test pads and the second part of the test pads are located in the third non-display area and arranged along the third edge of the base substrate.
  • At least one embodiment of the present disclosure also provides a display panel, which includes a substrate substrate, a pixel array, a scan driving circuit, a test circuit board, and test leads.
  • the base substrate includes a display area and a non-display area at least partially surrounding the display area;
  • a pixel array is located in the display area on the base substrate and includes a plurality of pixel rows extending along the first direction, wherein , each pixel row of the plurality of pixel rows includes a first signal line and a sub-pixel, the sub-pixel includes a pixel circuit, and the first signal line is configured to provide a pixel circuit in the pixel row in which it is located.
  • a scan drive circuit is configured to provide the scan signal to the pixel circuit, and includes a shift register and a clock signal line located in the display area;
  • a test circuit board is located in the non-display area, and includes a test pad ;
  • the test lead is located in the non-display area and is electrically connected to the test pad, wherein the first signal line includes a first part located in the display area and a first part located in the non-display area and connected to the first part
  • the second part of the first part extends along the first direction as a whole, and the second part is connected to the first part;
  • the first signal line and the test lead are arranged in different layers and insulated from each other, so An orthographic projection of the second portion of the first signal line on the base substrate at least partially overlaps an orthographic projection of the test lead on the base substrate.
  • At least one embodiment of the present disclosure further provides a display device, which includes any display panel provided by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a test method for a display panel.
  • the test method includes: obtaining a test signal output from the first signal line through the test circuit board to detect whether the scan driving circuit operates normally.
  • each pixel row in the plurality of pixel rows includes a plurality of the first signal lines
  • the display panel includes a plurality of the first signal lines.
  • Test pads and a plurality of test leads each of the plurality of test pads is electrically connected to at least one test lead of the plurality of test leads in the non-display area, and the display is Before the panel is tested, the first signal line and the test lead are arranged in different layers and insulated from each other through an interlayer insulating layer.
  • the test method further includes: when testing each of the plurality of first signal lines, using a laser irradiation preset The test lead, the interlayer insulating layer and the first signal line under test are positioned so that the test lead, the interlayer insulating layer and the first signal line under test are melted and Fusion, so that the fused test lead and the first signal line are electrically connected at the preset position, and the preset position is located between the first signal line to be tested and the corresponding test lead. within the overlapping area in the direction perpendicular to the base substrate.
  • each of the plurality of test leads includes a body lead and a plurality of sub-leads, and the body lead includes a third lead connected to the test pad.
  • the plurality of sub-leads are connected to the second end of the main body lead, protrude from the second end, and are connected to the plurality of first
  • the signal lines are in one-to-one correspondence, wherein, before testing the display panel, the orthographic projection of each of the plurality of sub-leads on the substrate substrate corresponds to the second portion of the corresponding first signal line.
  • the preset position is located at the overlap between the orthographic projection of the second part of the first signal line under test and the orthographic projection of the corresponding sub-lead. within the area.
  • the laser is incident on the display panel from a side of the substrate substrate away from the first signal line and the test lead. Preset position; the laser reaches the substrate substrate, the first signal line and the test lead in sequence and does not pass through any conductive layer between the first signal line and the substrate substrate; or , the laser reaches the base substrate, the test lead and the first signal line in sequence and does not pass through any conductive layer between the test lead and the base substrate.
  • a display panel testing method includes: sequentially acquiring test signals output from the plurality of first signal lines to sequentially test the plurality of first signal lines. After the previous first signal line among the plurality of first signal lines is tested, and before the next first signal line among the plurality of first signal lines is tested, the previous first signal line is cut off to A fracture is formed at the position where the previous first signal line is cut, and the fracture is located in the non-display area; the first signal line that has completed testing includes a non-connected part and a connected part separated by the fracture, The non-connected part is disconnected from the corresponding test lead, and the connecting part is connected to the corresponding test lead.
  • a laser is used to cut off the previous first signal line.
  • the fractures of a plurality of first signal lines that have been tested are arranged in a second direction perpendicular to the first direction.
  • Figure 1 is a schematic plan view of a display panel provided by at least one embodiment of the present disclosure
  • Figure 2 is a schematic diagram of the arrangement of a pixel circuit and a scan driving circuit of a display panel according to at least one embodiment of the present disclosure
  • Figure 3 is a schematic diagram of the arrangement of the gate lines of the pixel circuit and the scan driving circuit of the display panel shown in Figure 2;
  • FIG. 4A is an equivalent circuit diagram of a pixel circuit of two adjacent sub-pixels in a display panel provided by an embodiment of the present disclosure
  • Figure 4B is a working timing diagram of the pixel circuit shown in Figure 4A provided by an embodiment of the present disclosure
  • FIG. 5A is a schematic diagram of the pixel structure of a display panel provided by an embodiment of the present disclosure.
  • Figure 5B is a schematic structural diagram of two adjacent sub-pixels of the display panel shown in Figure 5A;
  • FIG. 6A is a schematic structural diagram of a display panel showing a shift register unit provided by an embodiment of the present disclosure
  • Figure 6B is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure.
  • Figure 6C is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
  • 6D is a schematic structural diagram of a display panel showing a scan driving circuit provided by an embodiment of the present disclosure
  • FIG. 7A is a schematic diagram of the part D1 including the second part of the first signal line and the test lead in the non-display area in FIG. 1 , or the part D2 including the second part of the first signal line and the test lead in FIG. 5A schematic diagram;
  • Figure 7B is a single-layer schematic diagram of the second part of the first signal line in Figure 7A;
  • Figure 7C is a single-layer schematic diagram of the test lead in Figure 7A;
  • FIG. 8A is a schematic structural diagram of sub-pixels in a display area of a display panel according to an embodiment of the present disclosure
  • Figure 8B is a schematic cross-sectional view along line I-I’ in Figure 8A and along line A-A’ in Figure 7A;
  • Figure 8C is another schematic cross-sectional view along line I-I’ in Figure 8A and along line A-A’ in Figure 7A;
  • Figure 9A is a schematic diagram of the semiconductor layer of the display panel shown in Figure 8A;
  • Figure 9B is an enlarged schematic view of the semiconductor layer in the display area of the display panel in Figure 9A;
  • Figure 9C is a schematic diagram of the first conductive layer of the display panel shown in Figure 8A;
  • FIG. 9D is another schematic diagram of the first conductive layer of the display panel provided by at least one embodiment of the present disclosure.
  • Figure 9E is a schematic diagram of the superposition of the semiconductor layer shown in Figure 9A and the first conductive layer shown in Figure 9D;
  • Figure 9F is a schematic diagram of the second conductive layer of the display panel shown in Figure 8A;
  • Figure 9G is a schematic diagram of the overlay of the semiconductor layer shown in Figure 9A, the first conductive layer shown in Figure 9D, and the second conductive layer shown in Figure 9F;
  • Figure 9H is a schematic diagram of the third conductive layer of the display panel shown in Figure 8A;
  • Figure 9I is a schematic diagram of the stacking of the semiconductor layer shown in Figure 9A, the first conductive layer shown in Figure 9D, the second conductive layer shown in Figure 9F, and the third conductive layer shown in Figure 9H;
  • Figure 9J is a schematic diagram of the fourth conductive layer of the display panel shown in Figure 8A;
  • FIG. 9K shows the semiconductor layer shown in FIG. 9A, the first conductive layer shown in FIG. 9D, the second conductive layer shown in FIG. 9F, the third conductive layer shown in FIG. 9H, and the fourth conductive layer shown in FIG. 9J.
  • FIG. 9L shows the semiconductor layer shown in FIG. 9A , the first conductive layer shown in FIG. 9D , the second conductive layer shown in FIG. 9F , the third conductive layer shown in FIG. 9H , and the fourth conductive layer shown in FIG. 9J Schematic diagram of the superposition of layers and anode layers;
  • 10A-10B are schematic diagrams of a detection method for detecting a display panel provided by at least one embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display panel, which includes: a base substrate, a pixel array, a scan driver circuit, a test circuit board, and test leads.
  • the base substrate includes a display area and a non-display area at least partially surrounding the display area;
  • a pixel array is located in the display area on the base substrate and includes a plurality of pixel rows extending along the first direction, so Each pixel row of the plurality of pixel rows includes a first signal line and a sub-pixel, the sub-pixel includes a pixel circuit, and the first signal line is configured to provide a scanning signal to the pixel circuit in the pixel row in which it is located.
  • the scan driving circuit is configured to provide the scan signal to the pixel circuit, and includes a shift register and a clock signal line located in the display area; a test circuit board is located in the non-display area, and includes a test pad; test The lead is located in the non-display area and is electrically connected to the test pad.
  • the first signal line includes a first part located in the display area and a second part located in the non-display area and connected to the first part. , the first part extends as a whole along the first direction, and the second part is connected to the first part; before testing the display panel, the first signal line and the test lead are in different layers.
  • test lead and the second part of the first signal line are configured to be connected to each other, and the test circuit board is configured to pass through the test pad and the The test lead acquires the test signal from the first signal line.
  • the test circuit board can obtain the test signal on the first signal line that provides the scan signal for the pixel circuit through the test pad to detect the scan driver. Whether the circuit is working properly.
  • This method has a simple structure and does not require the test leads and test pads to be directly connected to the scan drive circuit, such as the shift register or clock signal line of the scan circuit. Instead, it is directly connected to the first signal line of the pixel circuit, simplifying the test leads. The structure saves space and reduces the difficulty of making test leads.
  • FIG. 1 is a schematic diagram of the overall structure of a display panel provided by at least one embodiment of the present disclosure.
  • the display panel 10 includes a base substrate 01 , a pixel array, a scan driving circuit 03 , a test circuit board 06 and a test lead 05 .
  • the base substrate 01 includes a display area 01A and a non-display area 01B at least partially surrounding the display area 01A.
  • the pixel array is located in the display area 01A on the base substrate 01 and includes a plurality of pixel rows extending along the first direction (i.e., the first row, the second row...the Nth row in the figure), and each of the plurality of pixel rows A pixel row includes a first signal line 04 and a sub-pixel 02.
  • the pixel circuit may include a 2T1C (ie, two transistors and a capacitor) pixel circuit, 4T2C, 5T1C, 7T1C or nTmC (n and m are positive integers) pixel circuits.
  • the pixel circuit may further include a compensation subcircuit, which may include an internal compensation subcircuit or an external compensation subcircuit, and the compensation subcircuit may include a transistor, a capacitor, or the like.
  • the pixel circuit may further include a reset circuit, a light emission control sub-circuit, a detection circuit, etc.
  • the display panel 10 is an organic light-emitting diode (OLED) display panel, and the light-emitting element is an OLED.
  • OLED organic light-emitting diode
  • the first signal line 04 is configured to provide a scanning signal to the pixel circuit in the pixel row in which it is located. At least some of the plurality of sub-pixels include a light-emitting element and a pixel circuit that drives the light-emitting element to emit light.
  • the scan driving circuit 03 is configured to provide a scan signal to the pixel circuit, and includes a shift register and a clock signal line located in the display area 01A.
  • the test circuit board 06 is located in the non-display area 01B, and includes a test circuit 060 and a plurality of test pads 061 connected to the test circuit 060, for example, a plurality of test pads 061.
  • the test circuit board 06 is a chip-on-film (COF), and a plurality of test pads 061 are arranged at intervals in the chip-on-film (COF). It should be noted that the test circuit board 06 can be folded on the back side opposite to the display side of the display panel 10 .
  • the test lead 05 is located in the non-display area 01B and is electrically connected to the test pad 061.
  • Each first signal line 04 includes a first part 041 located in the display area 01A and a second part 042 located in the non-display area 01B and connected to the first part.
  • the first part 041 extends along the first direction as a whole, and the second part is connected to the first part; before testing the display panel 10 , the first signal line 04 and the test lead 05 are arranged in different layers and insulated from each other.
  • the test lead and the second part of the first signal line are configured to be connected to each other, and the test circuit board is configured to obtain the test signal from the first signal line through the test pad and the test lead.
  • the scan driving circuit is a gate driving circuit.
  • the feature "the first part of the first signal line extends as a whole along the first direction” means that the routing trend of the first part of the first signal line is along the first direction, for example, the first signal line extends along the first direction.
  • the first part of the line may be a straight line extending along the first direction, or the first part of the first signal line may have a certain bend or an inclination relative to the first direction, but from the starting end of the first part of the first signal line The direction to the terminating end is along the first direction.
  • test lead 05 is directly connected to the first signal line 04.
  • the direct connection here means that there is no other circuit structure or is not connected between the test lead 05 and the first signal line 04.
  • the circuit structure can be any including Electronic components such as thin film transistors, capacitors, etc.
  • the test circuit board 06 can obtain the test signal on the first signal line 04 that provides the scan signal for the pixel circuit through the test pad 061, so as to Check whether the scan driving circuit 03 is working normally.
  • This method has a simple structure and does not require the test leads and test pads to be directly connected to the scan drive circuit, such as the shift register or clock signal line of the scan circuit. Instead, it is directly connected to the first signal line of the pixel circuit, simplifying the test leads. The structure saves space and reduces the difficulty of making test leads.
  • the display panel 10 provided by the embodiment of the present disclosure is a display panel in which the scan drive circuit 03 is arranged in the display area 01A (gate drive in array, GIA), that is, a GIA display panel.
  • the connection between the test leads and the scan driver circuit of the display panel provided in the embodiment of the present disclosure is different from that of the display panel using GOA (Gate on array).
  • GOA Gate on array
  • the test leads used to test whether the scan drive circuit operates normally are connected to the scan drive circuit.
  • the test lead 05 is directly connected to the first signal line 04 , and the test lead 05 and the first signal line 04 do not exist or are not connected to any other circuit structure.
  • test pads are connected to test leads, and the test leads are connected to signal lines of the GOA scan drive circuit, such as signal lines connected to the input terminals of the shift registers of the GOA scan drive circuit, to obtain the signals of these signal lines.
  • signal lines connected to the input end of the shift register include, for example, clock signal lines.
  • the shift register and these signal lines connected to the input end of the shift register are located in the non-display area and do not extend from the display area to non-display area, and in this case, at least a GOA scan driver circuit is connected between the test lead and the pixel circuit.
  • FIG. 2 is a schematic diagram of the arrangement of the pixel circuit and the scan drive circuit of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 3 is the arrangement of the pixel circuit and the gate lines of the scan drive circuit of the display panel shown in FIG. 2 Schematic diagram.
  • each pixel 02 may include: a light-emitting control circuit 021 , a light-emitting driving circuit 022 and a light-emitting element 023 .
  • the first signal line 04 is a gate line
  • the gate line includes, for example, a scanning line, a reset control line, and a light-emitting control line.
  • the gate line refers to a signal line directly connected to the gate of the transistor to provide a scanning signal or a control signal.
  • the display panel 10 includes a plurality of first signal lines 04
  • the plurality of first signal lines 04 include a plurality of light emission control lines EM1 to EMn and a plurality of scanning lines G1 to Gm.
  • the display panel 10 further includes a plurality of driving signal lines such as L1 to Li as shown in FIG. 2 .
  • the input terminal of the scan driver circuit 03 is connected to the plurality of drive signal lines L1 to Li, and the output terminal of the scan driver circuit 03 is connected to the plurality of light emission control lines EM1 to EMn and the plurality of scan lines G1 to Gm.
  • the plurality of light emitting control lines EM1 to EMn may be connected to the light emitting control circuit 021 included in each sub-pixel 02 in the corresponding pixel row, and the plurality of scanning lines G1 to Gm may be connected to the light emitting control circuit 021 included in each sub-pixel 02 in the corresponding pixel row.
  • Drive circuit 022 is connected.
  • the scan driving circuit 03 may be configured to output light-emitting control signals to a plurality of light-emitting control lines and output gate driving signals to a plurality of gate lines in response to driving signals provided by the plurality of driving signal lines. That is, the scan driving circuit 03 can operate under driving signals provided by the plurality of driving signal lines L1 to Li.
  • each row of sub-pixels 02 can be connected to multiple first signal lines 04.
  • each row of sub-pixels 02 is connected to one scan line and two reset control lines. and a light-emitting control line, the two reset control lines are respectively a first reset control line and a second reset control line. That is, among multiple sub-pixels 02 located in the same row, the light-emitting control circuit 021 included in the pixel circuit of each sub-pixel 02 can be connected to the same light-emitting control line, and the light-emitting driving circuit 022 included in each sub-pixel 02 can be connected to the same scan line.
  • the display panel 10 includes the same number of scan lines and the same number of rows of pixels.
  • At least two pixels 02 can share the same light-emitting control circuit 021 , that is, at least two pixels 02 can work under the driving of the same light-emitting control circuit 021 . Since at least two sub-pixels 02 can share the same light-emitting control circuit 021, if the at least two sub-pixels 02 are located in the same row, the number of required light-emitting control circuits 021 can be reduced accordingly; if the at least two sub-pixels 02 If they are located in the same column, the number of light-emitting control circuits 021 that need to be set can be reduced accordingly, and the number of light-emitting control lines that need to be set can be reduced.
  • the effect of pixel space optimization can be achieved without affecting the normal display of the sub-pixel 02 , that is, the area occupied by the sub-pixel 02 on the substrate 01 is reduced compared to the related technology. Furthermore, the area of the remaining space on the base substrate 01 is increased, and the remaining space can be used to reliably set the scan drive circuit 03 and the drive signal lines required to connect the scan drive circuit 03 .
  • the display panel 10 in which the scan drive circuit 03 is arranged in the substrate (gate drive in array, GIA) shown in FIG. 2-3 is obtained, that is, the GIA display panel.
  • the light-emitting control circuit 021 can also be connected to the light-emitting driving circuit 022 , and the light-emitting driving circuit 022 can also be connected to the light-emitting element 023 .
  • the lighting control circuit 021 may be configured to output a DC power signal to the connected lighting driving circuit 022 in response to the lighting control signal provided by the connected lighting control line.
  • the light-emitting driving circuit 022 may be used to output a driving signal to the connected light-emitting element 023 in response to the gate driving signal provided by the connected gate line and the received DC power signal, so as to drive the light-emitting element 023 to emit light.
  • the display panel provided by the embodiment of the present disclosure at least two pixels located on the base substrate 01 can share the same light-emitting control circuit connected to the light-emitting control line, so the number of light-emitting control circuits required in the display panel can be reduced. Or further reduce the number of light-emitting control lines required on the display panel, which ultimately results in each pixel occupying a smaller area of the substrate.
  • the scanning driving circuit that provides signals for the signal lines connected to the pixels and the driving signals connected to the scanning driving circuit can be disposed on the base substrate.
  • the display panel provided by the embodiments of the present disclosure has a higher resolution.
  • the display panel 10 provided by the embodiment of the present disclosure at least two sub-pixels 02 sharing the same light emission control circuit 021 may be located in the same column.
  • the number of light-emitting control circuits 021 that need to be provided on the base substrate 01 can be reduced, but also the number of light-emitting control lines that need to be provided on the base substrate 01 can be reduced.
  • the display panel includes a total of m rows of sub-pixels 02. If at least two sub-pixels 02 located in the same column share the same light-emitting control circuit 021, the number of light-emitting control lines provided on the substrate 01 is smaller than the number of rows of sub-pixels 02. number. That is, n in Figure 2 is smaller than m, where both m and n can be integers greater than 1.
  • At least two sub-pixels 02 sharing the same light emission control circuit 021 are not only located in the same column, but may also be adjacent. In this way, layout and signal routing can be facilitated.
  • FIG. 3 shows another display panel, taking as an example that every two adjacent sub-pixels 02 located in the same column share the same light-emitting control circuit 021 .
  • FIG. 3 only schematically shows that the adjacent n-th row sub-pixel 02 and the n+1-th row sub-pixel 02 share the same light emitting control circuit 021, and the adjacent n+2-th row sub-pixel 02 and the n-th row sub-pixel 02 share the same light emitting control circuit 021.
  • the +3 row sub-pixels 02 share the same light emitting control circuit 021.
  • Figure 4A is an equivalent circuit diagram of a pixel circuit of two adjacent sub-pixels in a display panel provided by an embodiment of the present disclosure.
  • Figure 4B is an operating timing diagram of the pixel circuit shown in Figure 4A provided by an embodiment of the present disclosure.
  • FIG. 5A is a schematic structural diagram of a pixel of a display panel provided by an embodiment of the present disclosure.
  • FIG. 5B is a schematic structural diagram of two adjacent sub-pixels of the display panel shown in FIG. 5A .
  • FIG. 5A in order to clearly express the parts of the display panel 10 including the first signal line and the pixel circuit, structures such as test leads and test pads are omitted in FIG. 5A .
  • the omitted test leads and test pads are The positions of the isostructures are the same as in Figure 1.
  • the n-th row sub-pixel 02 and the n+1-th row sub-pixel 02 located in the first column and adjacent to each other are taken as an example.
  • Two sub-pixels 02 sharing the same light-emitting control circuit 021 can be symmetrically arranged on both sides of the light-emitting control line EMn connected to the shared light-emitting control circuit 021. That is, among the two sub-pixels 02 , the transistors included in one sub-pixel 02 and the connected signal lines can be symmetrically arranged with the transistors included in the other sub-pixel 02 and the connected signal lines. Both sides of the control line EMn.
  • Such a design can not only further facilitate layout layout and signal routing, but also enable centralized arrangement of signal lines, further optimizing the pixel space.
  • the display panel 10 may further include: a plurality of data lines located on the base substrate 01.
  • the plurality of scan lines may include: a plurality of first scan lines, a plurality of second scan lines, and a plurality of third scan lines.
  • the number of data lines can be the same as the number of pixel columns, and the number of first scanning lines, the number of second scanning lines, and the number of third scanning lines can be the same as the number of pixel rows.
  • 4A and 5B only show one data line D1, two first scan lines G1n and G1(n+1), two second scan lines G2n and G2(n+1), and two third scan lines. G3n and G3(n+1).
  • the light emission control circuit 021 may include: a light emission control transistor T1 .
  • the light emitting driving circuit may include: a data writing transistor T2, a reset transistor T3, a driving transistor T4, a compensation transistor T5 and a storage capacitor Cst.
  • the data writing transistor T2 is configured to transmit the data signal to the driving transistor under the control of the scan signal
  • the driving transistor T4 is configured to control the size of the driving current flowing through the light emitting element 023 according to the data signal.
  • the gate electrode of the data writing transistor T2 may be connected to a first scan line, the first electrode may be connected to the gate electrode of the driving transistor T4, and the second electrode may be connected to a data line D1.
  • the gate electrode of the data writing transistor T2 in the n-th row sub-pixel 02 is connected to the first scanning line G1n, and the gate electrode of the data writing transistor T2 in the n+1-th row sub-pixel 02 is connected to the first scanning line G1n. (n+1) connection.
  • the first pole of the driving transistor T4 can be connected to the first pole of the light-emitting control transistor T1, and the second pole can be connected to the light-emitting element 023.
  • the light-emitting element 023 can also be connected to the first power supply terminal VSS.
  • the gate of the light-emitting control transistor T1 may be connected to a light-emitting control line EMn, and the second electrode of the light-emitting control transistor T1 may be connected to the second power terminal VDD.
  • the gate electrode of the reset transistor T3 may be connected to a second scan line, the first electrode may be connected to the first initial signal terminal Vin1, and the second electrode may be connected to the second electrode of the driving transistor T4.
  • the gate electrode of the reset transistor T3 in the n-th row sub-pixel 02 is connected to the second scan line G2n, and the gate electrode of the reset transistor T3 in the n+1-th row sub-pixel 02 is connected to the second scan line G2(n+1). connect.
  • the gate electrode of the compensation transistor T5 may be connected to a third scan line, the first electrode may be connected to the second initial signal terminal Vin2, and the second electrode may be connected to the gate electrode of the driving transistor T4.
  • the gate electrode of the compensation transistor T5 in the n-th row sub-pixel 02 is connected to the third scan line G3n, and the gate electrode of the compensation transistor T5 in the n+1-th row sub-pixel 02 is connected to the third scan line G3(n+1 )connect.
  • the above only schematically illustrates an optional structure of the sub-pixel 02, which is a 5T1C (ie, five transistors and one capacitor) structure.
  • the embodiment of the present disclosure does not limit the structure of the sub-pixel 02, and it can also be other structures, such as a 7T1C structure.
  • the following embodiments all illustrate optional structures of the display substrate by taking the example of two adjacent sub-pixels 02 located in the same column and sharing the same light-emitting control circuit 021 .
  • two adjacent sub-pixels 02 may not share the same light-emitting control circuit 021.
  • the pixel circuit of each sub-pixel includes a light-emitting control circuit 021, which is not limited by the present disclosure.
  • each driving signal line Li connected to the scanning driving circuit 03 may be located between two adjacent columns of sub-pixels 02 .
  • FIG. 6 which shows yet another display substrate. Since it is located in the same column and every two adjacent sub-pixels 02 share the same light-emitting control circuit 021 , it is possible to predetermine between each two adjacent columns of sub-pixels 02 . Additional areas are left, area 5 and area 6 shown in Figure 6.
  • the drive signal line Li connected to the scan drive circuit 03 may be disposed in the areas 5 and 6 .
  • the scan driving circuit 03 may include: a plurality of cascaded shift register units 031. At least two cascaded shift register units 031 may be located between two adjacent rows of sub-pixels 02 . For example, there is a gap area between adjacent pixel rows in multiple pixel rows, and the shift register and the clock signal line are located in the gap area.
  • FIG. 5A since they are located in the same column and every two adjacent sub-pixels 02 share the same light-emitting control circuit 021 , additional areas can be reserved between every two adjacent rows of sub-pixels 02 , as shown in FIG. 6 shows area 1, area 2, area 3 and area 4.
  • at least two cascaded shift register units 031 may be disposed in areas 1 to 4 between every two adjacent rows of sub-pixels 02 .
  • At least two cascaded shift register units 031 may be located between two adjacent rows of target sub-pixels 02 .
  • the light-emitting control circuit connected to one row of target sub-pixels 02 is different from the light-emitting control circuit connected to the other row of target sub-pixels 02 . That is, two less cascaded shift register units 031 may be located between two rows of sub-pixels 02 that do not share the light emission control circuit 021 .
  • FIG. 6A is a schematic structural diagram of yet another display substrate provided by an embodiment of the present disclosure.
  • only two cascaded shift register units 031 may be provided between each two adjacent rows of target sub-pixels 02 .
  • one shift register unit 031 can be connected to one row of target sub-pixels 02, and another shift register unit 031 can be connected to another row of target sub-pixels 02 (not shown in FIG. 6A).
  • the two cascaded shift register units 031 may be symmetrically arranged between the two rows of target pixels. That is, each transistor included in one shift register unit 031 is arranged symmetrically with each transistor included in another shift register unit 031 .
  • some driving signal lines eg, power signals that provide DC signals
  • the GIA space that is, reducing the area of the substrate 01 that the shift register unit 031 needs to occupy.
  • FIG. 6B is a schematic structural diagram of a shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit 031 may include: an input sub-circuit 0311, a pull-down control sub-circuit 0312, a pull-down sub-circuit 0313, and an output sub-circuit 0314.
  • the input sub-circuit 0311 may be connected to the first input terminal IN1, the second input terminal IN2, the first control signal terminal CN, the second control signal terminal CNB and the pull-up node PU respectively.
  • the input sub-circuit 0311 may be configured to output the first control signal provided by the first control signal terminal CN to the pull-up node PU in response to the first input signal provided by the first input terminal IN1, and in response to the first control signal provided by the second input terminal IN2.
  • Two input signals, the pull-up node PU outputs the second control signal provided by the second control signal terminal CNB.
  • the input sub-circuit 0311 may output the first control signal provided by the first control signal terminal CN to the pull-up node PU when the potential of the first input signal provided by the first input terminal IN1 is the first potential. And, when the potential of the second input signal provided by the second input terminal IN2 is the first potential, the second control signal provided by the second control signal terminal CNB can be output to the pull-up node PU.
  • the first input terminal IN1 can be connected to the output terminal of the upper stage shift register unit 031, and the second input terminal IN2 can be connected to the output terminal of the next stage shift register unit 031.
  • the potential of the first control signal and the potential of the second control signal may be complementary. That is, when the potential of the first control signal is the first potential, the potential of the second control signal is the second potential; when the potential of the first control signal is the second potential, the potential of the second control signal is the first potential.
  • the first potential may be an effective potential, and the second potential may be an ineffective potential.
  • the transistor is an N-type transistor, the first potential may be a high potential relative to the second potential; when the transistor is a P-type transistor, the first potential may be a low potential relative to the second potential.
  • the pull-down control subcircuit 0312 may be connected to the first clock signal terminal CK, the pull-up node PU, the pull-down power supply terminal VGL, the pull-down node PD and the output terminal OUT respectively.
  • the pull-down control subcircuit 0312 may be configured to output the first clock signal to the pull-down node PD in response to the first clock signal provided by the first clock signal terminal CK, and in response to the potential of the pull-up node PU and the output signal provided by the output terminal OUT. , the pull-down node PD outputs the pull-down power signal provided by the pull-down power terminal VGL.
  • the pull-down control subcircuit 0312 may output the first clock signal to the pull-down node PD when the potential of the first clock signal provided by the first clock signal terminal CK is the first potential, so as to charge the pull-down node PD.
  • the pull-down control subcircuit 0312 can output the pull-down power signal provided by the pull-down power terminal VGL to the pull-down node PD when the potential of the pull-up node PU is the first potential.
  • the potential of the pull-down power signal can be the second potential to realize the pull-down. Noise reduction of node PD.
  • the pull-down control sub-circuit 0312 can output the pull-down power signal to the pull-down node PD when the potential of the output signal provided by the output terminal OUT is the first potential, so as to achieve noise reduction of the pull-down node PD.
  • the pull-down sub-circuit 0313 can be connected to the reset signal terminal RST, the pull-down node PD, the pull-down power supply terminal VGL, the pull-up node PU and the output terminal OUT respectively.
  • the pull-down subcircuit 0313 may be used to output a pull-down power signal to the pull-up node PU and the output terminal OUT in response to the potential of the pull-down node PD, and to output a pull-down power signal to the pull-up node PU in response to the reset signal provided by the reset signal terminal RST.
  • the pull-down sub-circuit 0313 can output a pull-down power signal to the pull-up node PU and the output terminal OUT when the potential of the pull-down node PD is the first potential, so as to achieve noise reduction of the pull-up node PU and the output terminal OUT. Furthermore, when the potential of the reset signal provided by the reset signal terminal RST is the first potential, the pull-up node PU can output the pull-down power signal to achieve noise reduction of the pull-up node PU.
  • the output sub-circuit 0314 may be connected to the pull-up node PU, the second clock signal terminal CKB and the output terminal OUT respectively.
  • the output subcircuit 0314 may be configured to output the second clock signal provided by the second clock signal terminal CKB to the output terminal OUT in response to the potential of the pull-up node PU.
  • the output subcircuit 0314 may output the second clock signal provided by the second clock signal terminal CKB to the output terminal OUT when the potential of the pull-up node PU is the first potential.
  • the second clock signal may be provided to the gate line as a gate drive signal, or as a light emission control signal to the light emission control line.
  • FIG. 6C is a schematic structural diagram of another shift register unit provided by an embodiment of the present disclosure.
  • the input sub-circuit 0311 may include a first input transistor M1 and a second input transistor M2.
  • the pull-down control sub-circuit 0312 may include: a first pull-down control transistor M3, a second pull-down control transistor M4, and a third pull-down control transistor M5.
  • the pull-down sub-circuit 0313 may include: a first pull-down transistor M6, a second pull-down transistor M7, a third pull-down transistor M8 and a pull-down capacitor C2.
  • Output sub-circuit 0314 may include: output transistor M9 and output capacitor C3.
  • the gate of the first input transistor M1 may be connected to the first input terminal IN1, the first pole may be connected to the first control signal terminal CN, and the second pole may be connected to the pull-up node PU.
  • the first input transistor M1 can output the first control signal provided by the first control signal terminal CN to the pull-up node PU when the potential of the first input signal provided by the first input terminal IN1 is the first potential, thereby realizing the pull-up node PU. Pull node PU charging.
  • the gate electrode of the second input transistor M2 may be connected to the second input terminal IN2, the first electrode may be connected to the second control signal terminal CNB, and the second electrode may be connected to the pull-up node PU.
  • the second input transistor M2 can output the second control signal provided by the second control signal terminal CNB to the upward pull-up node PU when the potential of the second input signal provided by the second input terminal IN2 is the first potential, so as to achieve Pull the reset of node PU.
  • the gate electrode and the first electrode of the first pull-down control transistor M3 may both be connected to the first clock signal terminal CK, and the second electrode may be connected to the pull-down node PD.
  • the first pull-down control transistor M3 can output the first clock signal to the pull-down node PD when the potential of the first clock signal provided by the first clock signal terminal CK is the first potential, thereby charging the pull-down node PD.
  • the gate of the second pull-down control transistor M4 may be connected to the pull-up node PU, the first pole may be connected to the pull-down power supply terminal VGL, and the second pole may be connected to the pull-down node PD.
  • the second pull-down control transistor M4 can output a pull-down power signal to the pull-down node PD when the potential of the pull-up node PU is the first potential, thereby achieving noise reduction on the pull-down node PD.
  • the gate of the third pull-down control transistor M5 may be connected to the output terminal OUT, the first electrode may be connected to the pull-down power supply terminal VGL, and the second electrode may be connected to the pull-down node PD.
  • the third pull-down control transistor M5 can output the pull-down power signal to the pull-down node PD when the potential of the output signal provided by the output terminal OUT is the first potential, thereby achieving noise reduction on the pull-down node PD.
  • the gate of the first pull-down transistor M6 may be connected to the reset signal terminal RST, the first pole may be connected to the pull-down power supply terminal VGL, and the second pole may be connected to the pull-up node PU.
  • the first pull-down transistor M6 can output the pull-down power signal provided by the pull-down power terminal VGL to the pull-up node PU when the potential of the reset signal provided by the reset signal terminal RST is the first potential, thereby lowering the pull-up node PU. noise.
  • the gate electrode of the second pull-down transistor M7 and the gate electrode of the third pull-down transistor M8 can both be connected to the pull-down node PD.
  • the first electrode of the second pull-down transistor M7 and the first electrode of the third pull-down transistor M8 can both be connected to the pull-down power terminal.
  • VGL is connected
  • the second pole of the second pull-down transistor M7 can be connected to the pull-up node PU
  • the second pole of the third pull-down transistor M8 can be connected to the output terminal OUT.
  • the second pull-down transistor M7 can output the pull-down power signal to the pull-up node PU when the potential of the pull-down node PD is the first potential, thereby achieving noise reduction on the pull-up node PU.
  • the third pull-down transistor M8 can output a pull-down power signal to the output terminal OUT when the potential of the pull-down node PD is the first potential, thereby achieving noise reduction on the output terminal OUT.
  • One end of the pull-down capacitor C2 can be connected to the pull-down node PD, and the other end can be connected to the pull-down power supply terminal VGL.
  • the pull-down capacitor C2 can be used to maintain the potential of the pull-down node PD.
  • One end of the output capacitor C3 can be connected to the pull-up node PU, and the other end can be connected to the output terminal OUT.
  • the output capacitor C3 can be used to maintain the potential of the pull-up node PU.
  • the gate of the output transistor M9 may be connected to the pull-up node PU, the first pole may be connected to the second clock signal terminal CKB, and the second pole may be connected to the output terminal OUT.
  • the drive signal lines connected to the scan drive circuit 03 include: the signal line connected to the first control signal terminal CN. , the signal line connected to the second control signal terminal CNB, the signal line connected to the reset signal terminal RST, the signal line connected to the first clock signal terminal CK, the signal line connected to the second clock signal terminal CKB, and Pull down the signal line connected to the power terminal VGL.
  • the two shift register units 031 are symmetrically arranged between the two rows of target sub-pixels 02, the two shift register units 031 can share a signal line connected to the pull-down power terminal VGL.
  • the shift register unit 031 shown in FIG. 6B shows the circuit structure of the shift register unit 031 located between two adjacent rows of sub-pixels 02 and the optional setting position of the driving signal line. . It can be seen from FIG. 6 to FIG. 6C that during layout, the relatively larger transistors in the shift register unit 031 can be arranged in the relatively larger areas 1 and 2, and the relatively larger transistors in the shift register unit 031 can be arranged. Small transistors are provided in regions 3 and 4 which are relatively small in area.
  • two transistors can also be connected in series to form a transistor (for example, the two transistors M7 shown in Figure 6D), or two capacitors can be connected in series to form a capacitor (such as the two transistors M7 shown in Figure 6D).
  • capacitance C2, and two capacitance C3 so that all transistors in the shift register unit 031 can be reliably set within the limited space of the substrate substrate 01.
  • the embodiment of the present disclosure multiplexes the same light-emitting control circuit 021 by setting at least two sub-pixels 02, so that the base substrate 01 is Areas other than the area where sub-pixel 02 is located are larger.
  • This provides effective technical support for the scan driving circuit 03 to be disposed on the base substrate 01, that is, it provides technical support for a high-resolution (per pixel inch, PPI) GIA display substrate.
  • Figure 6D is An embodiment of the present disclosure provides a pixel working timing diagram.
  • the second gate line G2n connected to the reset transistor T3 provides a gate drive signal at the first potential, and the reset transistor T3 is turned on.
  • the third gate line G3n connected to the compensation transistor T5 also provides a gate drive signal at the first potential, and the compensation transistor T5 is turned on.
  • the first initial signal terminal Vin1 can output the first initial signal at the second potential to the second pole of the driving transistor T4 in the n-th row sub-pixel 02 through the reset transistor T3, thereby realizing the first reset of the driving transistor T4. Diode reset.
  • the second initial signal terminal Vin2 can output a second initial signal to the gate of the driving transistor T4 in the n-th row sub-pixel 02 through the compensation transistor T5, and the second initial signal can be used as the compensation data Vref1.
  • the t1 stage can also be called the reset stage when driving the nth row sub-pixel 02.
  • the third gate line G3n connected to the compensation transistor T5 continues to provide a gate driving signal at the first potential. Compensation transistor T5 remains on.
  • the second initial signal terminal Vin2 can continue to output the second initial signal to the gate of the driving transistor T4 in the n-th row sub-pixel 02 through the compensation transistor T5.
  • the potential of the gate of the driving transistor T4 can change with the potential of the second pole of the driving transistor T4 until it becomes Vref1-Vth1, where Vth1 is the threshold voltage of the driving transistor T4.
  • the t2 stage can be called the compensation stage when driving the nth row sub-pixel 02.
  • stage t3 in the n-th row sub-pixel 02, the first gate line G1n connected to the data writing transistor T2 begins to provide a gate drive signal at the first potential, and the data writing transistor T2 is turned on.
  • the data line D1 outputs a data signal to the gate of the drive transistor T4 through the data writing transistor T2.
  • the t3 stage can be called the data writing stage when driving the nth row sub-pixel 02.
  • the second gate line G2(n+1) connected to the reset transistor T3 provides a gate drive signal at the first potential, and the reset transistor T3 is turned on.
  • the third gate line G3(n+1) connected to the compensation transistor T5 also provides a gate drive signal at the first potential, and the compensation transistor T5 is turned on.
  • the first initial signal terminal Vin1 can output the first initial signal at the second potential to the second pole of the driving transistor T4 in the n+1th row sub-pixel 02 through the reset transistor T3, thereby realizing the driving of the Reset of the second pole of transistor T4.
  • the second initial signal terminal Vin2 can output the second initial signal to the gate of the driving transistor T4 in the n+1th row sub-pixel 02 through the compensation transistor T5.
  • the second initial signal can be used as the compensation data Vref2 when driving the pixel in the row.
  • the t4 stage can be called the reset stage when driving the n+1th row sub-pixel 02.
  • stage t5 in the sub-pixel 02 of the n+1th row, the third gate line G3(n+1) connected to the compensation transistor T5 continues to provide the gate driving signal at the first potential. Compensation transistor T5 remains on.
  • the second initial signal terminal Vin2 can continue to output the second initial signal to the gate of the driving transistor T4 in the n+1th row sub-pixel 02 through the compensation transistor T5.
  • the potential of the gate of the driving transistor T4 of the row of sub-pixels 02 can change with the potential of its second pole until it becomes Vref2-Vth2, and Vth2 is Threshold voltage of drive transistor T4.
  • the t5 stage can be called the compensation stage when driving the n+1th row sub-pixel 02.
  • stage t6 in the sub-pixel 02 of the n+1th row, the first gate line G1(n+1) connected to the data writing transistor T2 begins to provide a gate drive signal at the first potential, and the data writing transistor T2 is turned on. .
  • the data line D1 can output a data signal to the gate of the driving transistor T4 in the row of sub-pixels 02 through the data writing transistor T2.
  • the t6 stage can be called the data writing stage when driving the n+1th row sub-pixel 02.
  • the light-emitting control lines connected to the light-emitting control transistor T1 multiplexed by the n-th row sub-pixel 02 and the n+1-th row sub-pixel 02 EMn always provides the light emission control signal at the first potential.
  • the DC power terminal VDD can output a DC power signal to the first pole of the driving transistor T4 included in each row of sub-pixels 02 in the two rows of sub-pixels 02 through the light-emitting control transistor T1.
  • the driving transistor T4 can output a driving signal to the connected light-emitting element 023 based on the DC power signal and the data signal to drive the n-th row light-emitting element 023 to emit light.
  • the driving transistor T4 can output a driving signal to the connected light-emitting element 023 based on the DC power signal and the data signal to drive the light-emitting element 023 of the n+1th row. glow.
  • the examples of the scan driving circuit (GIA) disposed in the display array of the display area and the specific structure of the pixel circuit described in the embodiments of the present disclosure are only exemplary.
  • the embodiments of the present disclosure are not applicable to the scanning circuit and the pixels.
  • the specific structure of the circuit is not limited. For example, there are no restrictions on the arrangement of the pixel circuits, whether the light-emitting control circuit is shared, the number of first signal lines corresponding to each row of sub-pixels, etc. Those skilled in the art can design according to specific needs.
  • FIG. 7A is a schematic diagram of the part D1 including the second part of the first signal line and the test lead in the non-display area in FIG. 1 , or the part D2 including the second part of the first signal line and the test lead in FIG. 5A Schematic diagram;
  • Figure 7B is a single-layer schematic diagram of the second part of the first signal line in Figure 7A;
  • Figure 7C is a single-layer schematic diagram of the test lead in Figure 7A;
  • Figure 8A (similar to the structure of the sub-pixel in Figure 5A, Figure 5A (some functional layers are omitted compared with Figure 8A) is a schematic structural diagram of sub-pixels in the display area of a display panel provided by an embodiment of the present disclosure;
  • Figure 8B is a diagram along the II' line and along the line II' in Figure 8A A schematic cross-sectional view of line AA' in Figure 7A.
  • the first signal line 04 and the test lead 05 are arranged in different layers and insulated from each other.
  • the second part 042 of the first signal line 04 is on the base substrate.
  • the orthographic projection and the orthographic projection of the test lead 05 on the base substrate at least partially overlap; when testing the display panel 10 , the orthographic projection of the second portion 042 of the first signal line 04 on the base substrate 01 overlaps the test lead 05 Portions where orthographic projections overlap on the base substrate are configured to be connected to each other.
  • each of the plurality of pixel rows includes a plurality of first signal lines 04
  • the display panel 10 includes a plurality of test pads 061 and a plurality of test leads 05
  • each of the plurality of test pads is connected to a plurality of test leads 05 .
  • At least one of the test leads 05 is electrically connected in the non-display area; for example, with multiple test leads 05 to reduce the number of test pads 061, save space on the test circuit board, and reduce the difficulty of manufacturing the test pads.
  • the orthographic projection of each of the plurality of test leads 05 on the base substrate 01 is in contact with the second portion 042 of the plurality of first signal lines 04 in at least one pixel row of the display panel 10 .
  • the orthographic projections on the base substrate 01 at least partially overlap.
  • the second part G3n2/G1n2/G2n2/EMn2 of the four first signal lines G3n/G1n/G2n/EMn connected to the pixel circuit of the same sub-pixel 02 in FIG. 5A is used as an example to illustrate the first
  • the relationship between the signal lines and the test leads is described, for example, this is true for each first signal line 04 .
  • the orthographic projection of each of the plurality of test leads 05 on the base substrate is consistent with the second portion 042 of the plurality of first signal lines 04 of the same pixel row in the plurality of pixel rows.
  • the orthographic projections on the base substrate at least partially overlap, as shown in Figures 7A-7C.
  • the orthographic projection of each of the plurality of test leads 05 on the base substrate is identical to the orthographic projection of the plurality of first signal lines 04 of adjacent pixel rows in the plurality of pixel rows.
  • Orthographic projections of the second portion 042 on the base substrate at least partially overlap. In this way, multiple first signal lines 04 are connected to the same test pad, which can reduce the number of test pads 061, save space on the test circuit board, and reduce the difficulty of manufacturing the test pads.
  • no switching device is provided between each of the plurality of first signal lines 04 and the test lead 05 overlapping its orthographic projection on the base substrate 01, and the switching device includes a thin film transistor (TFT) or the like.
  • TFT thin film transistor
  • the display panel 10 further includes a plurality of alignment marks M1/M2/M3/M4.
  • the patterns of the plurality of alignment marks M1/M2/M3/M4 are different from each other and are different from the plurality of first lines.
  • the signal lines 04 are arranged in one-to-one correspondence and are spaced apart from the overlapping areas of the corresponding first signal lines 04 .
  • 7A-7B take four alignment marks M1/M2/M3/M4 corresponding to the four first signal lines G3n/G1n/G2n/EMn as an example.
  • a plurality of alignment marks M1 / M2 / M3 / M4 are configured to be recognized by the alignment device respectively to locate the preset positions in the overlapping area of the corresponding first signal line 04 .
  • registration marks are opaque.
  • the alignment mark is provided in the same layer as any one of the active layer of the driving transistor T4, the first signal line 04, and the test lead 05.
  • the active layer of the driving transistor T4, the first signal line 04 and the test lead 05 are located on the same layer as the target structure for alignment, that is, the first signal line 04 and the test lead 05, or are relatively close to the layer where the target structure is located. Markers are placed in these layers to facilitate alignment identification accuracy.
  • each of the plurality of test leads 05 includes a main body lead 0520 and a plurality of sub-leads 0521/0522/0523/0524.
  • the body lead 0520 includes a first end 051 connected to the test pad 061 and a second end 052 away from the test pad 061.
  • the first end 051 of the body lead 0520 of a plurality of test leads 05 is connected to a plurality of test leads 052.
  • Pads 06 are connected in one-to-one correspondence.
  • the second end 052 extends along a second direction, and the second direction is substantially perpendicular to the first direction; a plurality of sub-leads 0521/0522/0523/0524 are connected to the second end 052 of the main lead 0520 and protrude from the second end.
  • the second part of G1n/G2n/EMn, G3n2/G1n2/G2n2/EMn2, corresponds to multiple sub-leads 0521/0522/0523/0524 one-to-one, thereby reducing the number of test pads. As shown in FIGS.
  • the orthographic projection of each of the plurality of sub-leads 0521/0522/0523/0524 on the base substrate 01 is aligned with the corresponding first signal line G3n/G1n/
  • the orthographic projections of the second part G3n2/G1n2/G2n2/EMn2 of G2n/EMn on the base substrate 01 at least partially overlap.
  • the end of the second portion of each of the plurality of first signal lines 04 close to the corresponding sub-lead 0521/0522/0523/0524 has a first Test disk PAD G1/PAD G2/PAD G4/PAD G4.
  • the width w1 of the first test disk PAD G1/PAD G2/PAD G4/PAD G4 in the line width direction of the first signal line 04 is greater than the line width w2 of the first signal line 04.
  • the first end of each of the plurality of sub-leads 0521/0522/0523/0524 is connected to the main lead 0520, and the second end of each of the plurality of sub-leads 0521/0522/0523/0524 has a second test disk PAD T1/PAD T2 /PAD T3/PAD T4, the width w3 of the second test disk PAD T1/PAD T2/PAD T3/PAD T4 in the line width direction of the sub-lead 0521/0522/0523/0524 is greater than that of the sub-lead 0521/0522/0523/ The line width of 0524 is w4.
  • the orthographic projection of the second test disk PAD T1/PAD T2/PAD T3/PAD T4 on the substrate substrate 01 and the corresponding first test disk PAD G1/PAD G2/PAD G4/PAD G4 of the first signal line 04 are on the backing
  • the orthographic projections on the base substrate 01 at least partially overlap. That is, the second portion of the first signal line 04 and the end portions of the corresponding sub-leads that are close to each other are overlapped with each other in a direction perpendicular to the base substrate 01 .
  • the width of the first test disk PAD G1/PAD G2/PAD G4/PAD G4 in the line width direction of the first signal line 04 is greater than the line width of the first signal line 04, the width of the first test disk PAD G1/PAD G2/PAD G4/PAD G4 can be increased.
  • the overlapping area of the second part of the signal line 04 and the corresponding sub-lead in the direction perpendicular to the base substrate 01 ensures that the overlapping part can be electrically connected when the display panel 10 needs to be tested.
  • the first power line VSS line includes a plurality of openings O, for example, a plurality of strip-shaped openings O.
  • the plurality of openings O and the plurality of first signal lines 04 are at least Partially overlap to reduce the overlapping area of the first power line VSS line and the plurality of first signal lines 04, and reduce the probability of short circuit at the overlap between the two due to poor charge accumulation.
  • the pixel circuit of each sub-pixel 02 of the display panel 10 includes a thin film transistor (TFT) such as a light-emitting control transistor T4, a light-emitting element 180 and a storage capacitor Cst.
  • TFT thin film transistor
  • the thin film transistor includes an active layer 120, a gate electrode 121 and a source and drain electrode 122/123; the storage capacitor Cst includes a first plate CE1 and a second capacitor plate CE2.
  • the light-emitting element 180 includes a cathode 183, an anode 181, and a light-emitting layer 182 between the cathode 183 and the anode 181.
  • the anode 181 is electrically connected to one of the source and drain electrodes 122/123 of the thin film transistor TFT, such as the drain electrode 123.
  • the anode 181 and the drain electrode 123 of the thin film transistor TFT can also be electrically connected through a transfer electrode.
  • the light-emitting element may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED).
  • the light-emitting layer 182 is an organic light-emitting layer or a quantum dot light-emitting layer.
  • the display panel 10 further includes an interlayer insulating layer 152 .
  • the interlayer insulating layer 152 is located between the first signal line 04 and the test lead 05 to insulate the two, and , the first signal line 04, the interlayer insulating layer 152 and the test lead 05 are configured to be melted by the laser at a preset position so that the first signal line 04 and the test lead 05 are electrically connected at the preset position, and the preset position is located at the first
  • the orthographic projection of a signal line 04 on the base substrate 01 and the orthographic projection of the test lead 05 on the base substrate 01 are within the overlapping area.
  • a laser is used to irradiate the test lead 05, the interlayer insulation layer and the first signal line to be tested 04 at a preset position and cause the test lead 05, the interlayer insulation layer and the first signal line to be tested to 04
  • the three are melted and fused, so that the fused test lead 05 is electrically connected to the first signal line 04 at a preset position, so that the first signal line 04 is electrically connected to the corresponding test pad 061 through the corresponding test lead 05 , so that the test signal output by the first signal line 04 can be obtained through the test circuit board 06 to detect whether the scan driving circuit 03 of the display panel 10 operates normally.
  • the material of the interlayer insulating layer 152 may be silicon nitride or silicon oxide or silicon oxynitride, so that the first signal line 04 , the interlayer insulating layer 152 and the test lead 05 are configured to be melted by the laser at a preset position.
  • the first signal line 04 and the test lead 05 are electrically connected at the preset position.
  • the substrate substrate 01 is a heat-resistant, temperature-resistant substrate such as a glass substrate or a quartz substrate. Therefore, the first signal line 04, the interlayer insulating layer 152 and the test lead 05 are configured to be melted by the laser at a preset position. During the process, the structure and performance of the base substrate 01 will not be affected.
  • the material of the first signal line 04 and the test lead 05 is a metallic material, such as metal or alloy.
  • metal or alloy For example, copper, aluminum, copper alloy, aluminum alloy, etc.
  • the materials listed above are only exemplary, and the embodiment of the present disclosure does not limit the materials of the first signal line 04 and the test lead 05 .
  • the test lead 05 before testing the display panel 10 , the test lead 05 is located on a side of the first signal line 04 away from the base substrate, between the first signal line 04 and the base substrate. There is no conductive layer between them. In this way, when testing the display panel 10, after the laser passes through the substrate 01 at the preset position, by controlling the intensity and other parameters of the laser, the laser can only act on the first tested part in sequence. A signal line 04, the interlayer insulating layer 152 and the test lead 05 will not act on any other conductive layer, thereby preventing any impact on other conductive layers.
  • the display panel 10 further includes a first gate insulating layer 151 located between the active layer 120 and the gate electrode 121 , a second gate insulating layer 152 located above the gate electrode 121 , and an interlayer insulating layer 160 , the second gate insulating layer 152 is located between the first plate CE1 and the second capacitor plate CE2, so that the first plate CE1, the second gate insulating layer 152 and the second capacitor plate CE2 form the storage capacitor Cst.
  • the interlayer insulating layer 160 covers the second capacitor plate CE2.
  • the display panel 10 further includes an insulating layer 113 (eg, passivation layer) covering the pixel circuit and a first planarization layer 112 .
  • the display area 201 also includes a pixel defining layer 170 for defining a plurality of sub-pixels and structures such as spacers (not shown) on the pixel defining layer 170 . As shown in FIG. 8B , the display panel 10 further includes an insulating layer 113 (eg, passivation layer) covering the pixel circuit and a first planarization layer 112 .
  • the display area 201 also includes a pixel defining layer 170 for defining a plurality of sub-pixels and structures such as spacers (not shown) on the pixel defining layer 170 . As shown in FIG.
  • the insulating layer 113 is located above the source and drain electrodes 122/123 (for example, a passivation layer formed of silicon oxide, silicon nitride, silicon oxynitride, or other materials), and is provided above the insulating layer 113 There is a first planarization layer 112 , and the anode 181 is electrically connected to the drain electrode 123 through a via hole penetrating the first planarization layer 112 and the insulating layer 113 .
  • the display panel further includes an encapsulation layer 190
  • the encapsulation layer 190 includes a plurality of encapsulation sub-layers 191/192/193.
  • the first encapsulation layer 291 and the first encapsulation sub-layer 191 in the encapsulation layer 190 are arranged at the same layer
  • the second encapsulation layer 292 and the second encapsulation sub-layer 192 in the encapsulation layer 190 are arranged at the same layer
  • the third encapsulation layer 293 and The third packaging sub-layer 193 in the packaging layer 190 is arranged on the same layer.
  • the first packaging layer 291 and the third packaging layer 293 can both include inorganic packaging materials, such as silicon oxide, silicon nitride or silicon oxynitride.
  • the second encapsulation layer 292 may include organic materials, such as resin materials.
  • the multi-layer packaging structure of the display panel 10 can achieve a better packaging effect to prevent impurities such as water vapor or oxygen from penetrating into the interior of the display panel 10 .
  • the display panel 10 further includes a buffer layer 111 located on the substrate 210 .
  • the buffer layer 111 serves as a transition layer and can prevent harmful substances in the substrate 1 from invading the interior of the display panel 10 .
  • Entering the display area 01A can increase the adhesion of the film layer in the display panel 10 to the substrate 1 .
  • the material of the buffer layer 111 may include a single-layer or multi-layer structure formed of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the storage capacitor Cst of the pixel circuit includes a first plate CE1 and a second plate CE2.
  • the first plate CE1 is electrically connected to the gate of the driving transistor T4, and the orthographic projection of the second plate CE2 on the base substrate 01 At least partially overlaps with the orthographic projection of the first electrode plate CE1 on the base substrate 01 .
  • the first signal line 04 is placed on the same layer as the first plate CE1 of the storage capacitor Cst, and the test lead 05 is on the same layer as the first plate CE1 of the storage capacitor Cst.
  • the second electrode plate CE2 is arranged on the same layer to form the first signal line 04 and the first electrode plate CE1 through the same patterning process, and the test lead 05 and the bottom second electrode plate CE2 are formed through the same patterning process, thereby simplifying the display panel 10 layer structure and manufacturing process.
  • the display surface 10 includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer which are sequentially arranged on the base substrate 01. conductive layer.
  • the semiconductor layer includes active patterns A1-A5 of first to fifth transistors T1-T5 (shown in FIG. 4A).
  • the alignment marks M1/M2/M3/M4 are located on the semiconductor layer and are arranged on the same layer as the active patterns A1-A5, that is, the active layer of the driving transistor T4.
  • the first conductive layer includes the gate of each transistor of the pixel circuit, the first signal line 04 and the first plate CE1.
  • the gate line G1n is a scanning line
  • the gate line G3n is a first reset control line
  • the gate line G2n is a second reset control line
  • the gate line EMn is a light emitting control line.
  • the second conductive layer includes the second plate CE2 of the pixel circuit and the test lead 05 ( FIG. 9F only shows the second end 052 of the test lead 05 ).
  • the second conductive layer also includes a first reset signal line Vin1 and a second reset signal line Vin2, that is, the first reset signal line Vin1 and the second reset signal line Vin2 shown in FIG. 4A.
  • the third conductive layer includes a data line D and a first power line VDD line, and a plurality of connection structures P1-P8.
  • the plurality of connection structures P1-P8 are configured to connect FIG. 4B and FIG. 8A
  • Each electrode of the thin film transistor T1-5T is connected, each electrode of the thin film transistor T1-5T is connected to the active layer, and the electrode of the thin film transistor is connected to the data line or the VDD line.
  • the fourth conductive layer includes an auxiliary electrode 171 .
  • the auxiliary electrode 171 connects the drain electrode and the anode 181 of the thin film transistor T4.
  • Figure 8C is another schematic cross-sectional view along line I-I' in Figure 8A and line A-A' in Figure 7A.
  • the test lead 05 is located on the side of the first signal line 04 close to the base substrate 01 , and no conductive layer is provided between the test lead 05 and the base substrate 01 .
  • the interlayer insulating layer located between the test lead 05 and the first signal line 04 is the first gate insulating layer 151 .
  • the laser when testing the display panel 10, after the laser passes through the base substrate 01 at a preset position, by controlling the intensity and other parameters of the laser, the laser can only act on the test lead 05, the interlayer insulating layer 151 and the substrate in sequence.
  • the first signal line 04 under test will not affect any other conductive layers, thereby preventing effects on other conductive layers.
  • the first signal line 04 is arranged on the same layer as the first plate CE1 of the storage capacitor Cst, and the display panel 10 also includes a light-shielding layer 110 located on the first signal line.
  • the orthographic projection of the channel area of the driving transistor T4 on the base substrate 01 is located within the orthographic projection of the light shielding layer 110 on the base substrate 01, and the test lead 05 is connected to the bottom light shielding
  • the layer 110 is arranged on the same layer to form the test leads 05 and the bottom light shielding layer 110 through the same patterning process, thereby simplifying the layer structure and manufacturing process of the display panel 10 .
  • the first test pads PAD G1/PAD G2/PAD G4/PAD G4 of the plurality of first signal lines 04 are arranged at intervals along the second direction and are in contact with the plurality of first signal lines 04.
  • Multiple sub-leads 0521/0522/0523/0524 in one-to-one correspondence are arranged at intervals along the second direction
  • the second test pads PAD T1/PAD T2/PAD T3/PAD T4 of the multiple sub-leads 0521/0522/0523/0524 They are arranged spaced apart from each other along the second direction to rationally utilize the limited space of the non-display area 01B.
  • each first signal line 04 includes a first lateral portion
  • the first lateral portion of the second portion of each first signal line is, for example, a plurality of first lines shown in FIGS. 5A and 7A .
  • the second part of the signal line G3n/G1n/G2n/EMn is G3n2/G1n2/G2n2/EMn2.
  • the first lateral portion G3n2/G1n2/G2n2/EMn2 extends along the first direction and is connected to the corresponding first portion of the first signal line G3n/G1n/G2n/EMn, and the distance between the first lateral portion G3n2/G1n2/G2n2/EMn2 corresponds to
  • the ends of the first part of the first signal lines G3n/G1n/G2n/EMn respectively include the first test disk PAD G1/PAD G2/PAD G4/PAD G4, and the first lateral parts G3n2/ of the plurality of first signal lines 04 G1n2/G2n2/EMn2 are arranged along the second direction to fully utilize the size of the non-display area 01B in the second direction.
  • the second portions G3n2/G1n2/G2n2/EMn2 of the plurality of first signal lines G3n/G1n/G2n/EMn respectively include the first lateral portions TP1/TP2/TP3/TP4.
  • the second portion of the first signal line G3n includes a first lateral portion.
  • TP11, first longitudinal portion VP1 and second transverse portion TP21 extends along the first direction and is connected to the first part;
  • the first longitudinal portion VP1 is connected to the first transverse portion TP11 and extends along the second direction;
  • the second transverse portion TP21 is connected to the first longitudinal portion VP1 and extends along the second direction. Extending in one direction, the end of the second transverse portion TP21 away from the first longitudinal portion VP1 includes the first test disk PAD G1.
  • first signal lines The first lateral portions of the plurality of first signal lines G3n/G1n/G2n/EMn are arranged along the second direction, and the second lateral portions of the plurality of first signal lines G3n/G1n/G2n/EMn are also arranged along the second direction, indicating that The first test pads of the plurality of first signal lines on the panel are not located on the same straight line extending in the second direction. In this way, the positions of the first test disks of the multiple first signal lines of the entire display panel 10 can be staggered, making full use of the limited space to set up more first test disks, thereby setting as many pixel rows as possible to meet the requirements of high PPI display. panel requirements.
  • FIG. 10 is a schematic plan view of another display panel provided by at least one embodiment of the present disclosure.
  • the non-display area 01B includes a first non-display area 01B-1, a second non-display area 01B-2 and a third non-display area 01B-3, and the first non-display area 01B-1 and the second non-display area 01B- 2 are respectively located on the first side and the second side of the display area in the first direction, and the third non-display area 01B-3 is located on the first side of the display area in the second direction;
  • the base substrate 01 includes a The first edge 011 of the area 01B-1 and extending along the second direction, the second edge 012 close to the second non-display area 01B-2 and extending along the second direction, and the second edge 012 close to the third non-display area 01B-3 and extending along the second direction.
  • a third edge 013 extending in one direction.
  • the first signal lines 04 of multiple pixel rows extend from the display area 01A to the first non-display area 01B-1, and the first signal lines 04 of the multiple pixel rows extend from the display area 01A to the first non-display area 01B-1.
  • a non-display area 01B-1 is connected to the test lead 05, and a plurality of test pads 061 are located in the first non-display area 01B-1 and arranged along the third edge 013 of the base substrate 01.
  • the first signal lines 04 of the plurality of pixel rows are connected to the test leads 05 in the first non-display area 01B-1, and the plurality of test pads 061 are located in the first non-display area 01B-1 and along the The first edge arrangement of the base substrate 01 is arranged along the second direction; or, in other embodiments, the first signal lines 04 of multiple pixel rows are connected to the test leads 05 in the second non-display area 01B-2, The plurality of test pads 061 are located in the second non-display area 01B-1 and are arranged along the first edge of the base substrate 01, that is, arranged along the second direction.
  • the first part of the first signal lines 04 of the plurality of pixel rows extends from the display area to the first non-display area 01B-1, and the first part of the first signal line 04 is in the first non-display area 01B -1 is connected to the test lead 05;
  • the second part of the first signal line 04 of the first signal lines 04 of the plurality of pixel rows extends from the display area 01A to the second non-display area 01B-2, and the second part of the first signal line 04 extends from the display area 01A to the second non-display area 01B-2.
  • 04 is connected to the test lead 05 in the second non-display area 01B-2.
  • the first part of the test pads 06 is located in the first non-display area 01B-1 and is arranged along the first edge 011 of the substrate 01
  • the second part of the test pads 06 is Located in the second non-display area 01B-2 and arranged along the second edge 012 of the base substrate 01; alternatively, the first part of the test pads and the second part of the test pads are both located in the third non-display area 01B-3 and arranged along the second edge 012 of the base substrate 01.
  • the third edge 013 of the base substrate 01 is aligned.
  • the plurality of test circuit boards 06 are flexible, such as the aforementioned chip-on-film (COF), and can be bent to the back of the display panel 10 .
  • the first non-display area 01B-1 and/or the second non-display area 01B-2 where the test lead 05 is provided can also be a flexible circuit board, which can be bent or bent to the back of the display panel 10 to reduce the display area.
  • the border width of the panel can be used to reduce the display area.
  • At least one embodiment of the present disclosure also provides a display device, which includes any of the above display panels 10 provided by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a testing method for any of the above display panels provided by the embodiment of the present disclosure.
  • the testing method includes: obtaining the test signal output by the first signal line 04 through the test circuit board 06 to detect the display panel. Is the scan driver circuit 03 of 10 working properly? For example, the test signal from the first signal line 04 is sent to an oscilloscope, and the waveform of the oscilloscope is used to determine whether the pixel circuit of the display panel 10 that receives the scanning signal from the first signal line 04 is operating normally, thereby determining whether the scan driving circuit 03 normal work.
  • the test method includes: when testing each of the plurality of first signal lines 04 , using a laser to irradiate the test lead 05 at a preset position, the interlayer insulation layer and the first signal to be tested.
  • the wire 04 melts and fuses the test lead 05, the interlayer insulating layer and the first signal line 04 under test, so that the fused test lead 05 and the first signal line 04 are electrically connected at a preset position.
  • the preset The position is located in the overlapping area of the first signal line 04 to be tested and the corresponding test lead 05 in the direction perpendicular to the base substrate 01 .
  • the preset position is located in the overlapping area of the orthographic projection of the second part 042 of the first signal line 04 under test and the orthographic projection of the corresponding sub-lead 0521/0522/0523/0524, that is, located in each first signal line.
  • the first test pad and the corresponding second test pad of 04 are fused under the action of the laser and then electrically connected to each other.
  • laser light is incident on the preset position of the display panel 10 from the side of the substrate substrate 01 away from the first signal line 04 and the test lead 05 ; the laser light reaches the substrate in sequence.
  • the laser After the laser passes through the substrate 01 at a preset position, by controlling the intensity and other parameters of the laser, the laser can only act on the first signal line 04, the interlayer insulation layer 152 and the test lead 05 under test in sequence, without Act on any other conductive layer to prevent impact on other conductive layers.
  • the laser when testing the display panel 10 shown in FIG. 8C , the laser reaches the base substrate 01 , the test lead 05 and the first signal line 04 in sequence. Since there is no installation between the test lead 05 and the base substrate 01 The laser does not pass through any conductive layer between the test lead 05 and the base substrate 01 . After the laser passes through the substrate 01 at a preset position, by controlling the intensity of the laser and other parameters, the laser can only act on the test lead 05, the interlayer insulating layer 151 and the first signal line 04 under test in sequence, without Act on any other conductive layer to prevent impact on other conductive layers.
  • the testing method further includes: sequentially acquiring test signals output from the plurality of first signal lines 04 to sequentially test the plurality of first signal lines 04 .
  • the previous first signal line 04 is Cutting is performed to form a break at the position where the previous first signal line 04 was cut, and the break is located in the non-display area 01B.
  • the test signals output by the first signal line G3n, the first signal line G1n, the first signal line G2n and the first signal line EMn are sequentially obtained, so as to sequentially test the first signal line G3n/G1n/G2n/EMn.
  • a signal line G1n, a first signal line G2n and a first signal line EMn are tested.
  • the first signal line G1n is cut at position 1 to form a break OP1 at position 1.
  • the tested first signal line G3n includes non-connected portions and connections separated by the break OP1.
  • the non-connected part is disconnected from the corresponding test lead 05, and the connected part is connected to the corresponding test lead 05.
  • a laser can be used to cut off the previous first signal line 04 .
  • the first signal line G1n is tested using the same method used to test the first signal line G3n, and the first signal line G1n is cut off at position 2 to form a break OP2 at position 2.
  • the first signal line G2n and the first signal line EMn are subsequently tested, and the fracture OP3 and the fracture OP4 are formed at positions 3 and 4 respectively. In this way, the test of all the first signal lines 04 of the display panel 10 can be completed.
  • the fractures of a plurality of first signal lines 04 that have been tested are arranged in a second direction perpendicular to the first direction.
  • the non-display area 01B has sufficient space in the second direction, which is conducive to accurate laser positioning.
  • the plurality of breaks of the second parts of the plurality of first signal lines 04 located on the same side of the display area 01A in the first direction are not located on the same straight line extending along the second direction, or are substantially located along the second direction. on the extended straight line to facilitate positioning and maintain the consistency of the second portions of the plurality of first signal lines, thereby maintaining the consistency of the signal transmission performance of the plurality of first signal lines.

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Abstract

一种显示面板（10）及测试方法、显示装置，显示面板（10）的像素阵列的子像素（02）包括像素电路，第一信号线（04）配置为给所在像素行中的像素电路提供扫描信号；扫描驱动电路（03）配置为给像素电路提供扫描信号，且包括位于显示区（01A）的移位寄存器和时钟信号线；测试电路板（06）位于非显示区域（01B）且包括测试焊盘（061）；测试引线（05）位于非显示区域（01B），与测试焊盘（061）电连接，第一信号线（04）包括位于显示区域（01A）的第一部分（041）和位于非显示区域（01B）的第二部分（042），第一部分（041）整体上沿第一方向延伸；在对显示面板（10）进行测试前，第一信号线（04）与测试引线（05）异层设置且彼此绝缘；在对显示面板（10）进行测试时，测试引线（05）与第一信号线（04）的第二部分（042）配置为彼此连接，测试电路板（06）配置为通过测试焊盘（061）和测试引线（05）获取来自第一信号线（04）的测试信号。

Description

显示面板及其测试方法、显示装置 技术领域
本公开至少一实施例涉及一种显示面板及其测试方法、显示装置。
背景技术
通常，有机发光二极管(OLED)显示装置包括显示面板、栅极驱动装置、数据驱动器和时序控制器。显示面板包括像素阵列，像素阵列包括多行多列像素以及控制每一行像素工作的数据线和栅线。通常工作方式为，当栅极驱动信号被提供至栅线时，该栅线对应的像素行的像素被提供数据线的数据电压，像素根据数据电压的大小发出不同亮度的光。
栅极驱动装置给栅线提供栅极驱动信号，栅极驱动装置包括扫描驱动电路。需要对扫描驱动电路进行测试，以判断扫描驱动电路是否正常工作。
发明内容
本公开至少一实施例提供一种显示面板，该显示面板包括：衬底基板、像素阵列、扫描驱动电路、测试电路板以及测试引线。衬底基板包括显示区域和至少部分围绕所述显示区域的非显示区域；像素阵列位于所述衬底基板上的所述显示区域，且包括沿所述第一方向延伸的多个像素行，所述多个像素行的每个像素行包括第一信号线以及子像素，所述子像素包括像素电路，所述第一信号线配置为给其所在的所述像素行中的像素电路提供扫描信号；扫描驱动电路配置为给所述像素电路提供所述扫描信号，且包括位于所述显示区的移位寄存器和时钟信号线；测试电路板位于所述非显示区域，且包括测试焊盘；测试引线位于所述非显示区域，与所述测试焊盘电连接，所述第一信号线包括位于所述显示区域的第一部分和位于所述非显示区域且与所述第一部分连接的第二部分，所述第一部分整体上沿所述第一方向延伸，所述第二部分与所述第一部分连接；在对所述显示面板进行测试前，所述第一信号线与所述测试引线异层设置且彼此绝缘；在对所述显示面板进行测试时， 所述测试引线与所述第一信号线的第二部分配置为彼此连接，所述测试电路板配置为通过所述测试焊盘和所述测试引线获取来自所述第一信号线的测试信号。
例如，本公开至少一实施例提供的显示面板中，在对所述显示面板进行测试前，所述第一信号线的第二部分在所述衬底基板上的正投影与所述测试引线在所述衬底基板上的正投影至少部分重叠；在对所述显示面板进行测试时，所述第一信号线的第二部分在所述衬底基板上的正投影与所述测试引线在所述衬底基板上的正投影重叠的部分配置为彼此连接。
例如，本公开至少一实施例提供的显示面板还包括层间绝缘层，在对所述显示面板进行测试前，所述层间绝缘层位于所述第一信号线与所述测试引线之间以使两者绝缘，并且，所述第一信号线、所述层间绝缘层和所述测试引线配置为可被激光在预设位置熔融以使所述第一信号线和所述测试引线在所述预设位置处电连接，所述预设位置位于所述第一信号线在所述衬底基板上的正投影与所述测试引线在所述衬底基板上的正投影的重叠区域内。
例如，在本公开至少一实施例提供的显示面板中，在对所述显示面板进行测试前，所述测试引线位于所述第一信号线的远离所述衬底基板的一侧，所述第一信号线与所述衬底基板之间不设置任何导电层；或者，所述测试引线位于所述第一信号线的靠近所述衬底基板的一侧，所述测试引线与所述衬底基板之间不设置任何导电层。
例如，在本公开至少一实施例提供的显示面板中，所述第一信号线为栅线。
例如，在本公开至少一实施例提供的显示面板中，所述多个像素行中相邻的像素行之间具有间隙区域，所述移位寄存器和所述时钟信号线位于所述间隙区域内。
例如，在本公开至少一实施例提供的显示面板中，所述多个像素行中的每个像素行包括多条所述第一信号线，所述显示面板包括多个所述测试焊盘和多条所述测试引线，所述多个测试焊盘中的每个与所述多条测试引线中的至少一条测试引线在所述非显示区域电连接；在对所述显示面板进行测试前，所述多条测试引线的每条在所述衬底基板上的正投影与所述显示面板的至少 一个所述像素行中的多条所述第一信号线的第二部分在所述衬底基板上的正投影至少部分重叠。
例如，在本公开至少一实施例提供的显示面板中，在对所述显示面板进行测试前，所述多条测试引线的每条在所述衬底基板上的正投影与所述多个像素行中的同一像素行的多条第一信号线的第二部分在所述衬底基板上的正投影至少部分重叠，或者，所述多条测试引线的每条在所述衬底基板上的正投影与所述多个像素行中的相邻的像素行的多条第一信号线的第二部分在所述衬底基板上的正投影至少部分重叠。
例如，在本公开至少一实施例提供的显示面板中，所述多条第一信号线中的每条和与其正投影重叠的所述测试引线之间不设置任何开关器件。
例如，在本公开至少一实施例提供的显示面板中，所述多条测试引线的每条包括主体引线和多个子引线。主体引线包括与所述测试焊盘连接的第一端部和远离所述测试焊盘的第二端部，所述第二端部沿第二方向延伸，所述第二方向与所述第一方向基本垂直；多个子引线与所述主体引线的第二端部连接，突出于所述第二端部，且与所述多条第一信号线一一对应；在对所述显示面板进行测试前，所述多个子引线的每个在所述衬底基板上的正投影与对应的所述第一信号线的第二部分在所述衬底基板上的正投影至少部分重叠。
例如，在本公开至少一实施例提供的显示面板中，在对所述显示面板进行测试前，所述多条第一信号线的每条的第二部分的靠近对应的所述子引线的端部具有第一测试盘，所述第一测试盘在该条第一信号线的线宽方向上的宽度大于该条第一信号线的线宽；所述多个子引线的每个的第一端与所述主体引线连接，所述多个子引线的每个的第二端具有第二测试盘，所述第二测试盘在该子引线的线宽方向的宽度大于该子引线的线宽；所述第二测试盘在所述衬底基板上的正投影与对应的所述第一信号线的第一测试盘在所述衬底基板上的正投影至少部分重叠。
例如，在本公开至少一实施例提供的显示面板中，所述多条第一信号线的第一测试焊盘沿所述第二方向间隔排列，与所述多条第一信号线一一对应的所述多个子引线沿所述第二方向彼此间隔排列，且所述多个子引线的第二 测试焊盘沿所述第二方向彼此间隔排列。
例如，在本公开至少一实施例提供的显示面板中，所述第二部分包括第一横向部分。第一横向部分沿所述第一方向延伸且与所述第一部分连接，所述第一横向部分的远离所述第一部分的端部包括所述第一测试盘，所述多条第一信号线的第一横向部分沿所述第二方向排列。
例如，在本公开至少一实施例提供的显示面板中，所述第二部分包括第一横向部分、第一纵向部分和第二横向部分。第一横向部分沿所述第一方向延伸且与所述第一部分连接；第一纵向部分与所述第一横向部分连接且沿所述第二方向延伸；第二横向部分与所述第一纵向部分连接且沿所述第一方向延伸；所述第二横向部分的远离所述第一纵向部分的端部包括所述第一测试盘，所述多条第一信号线的第一横向部分沿所述第二方向排列，所述多条第一信号线的第二横向部分沿所述第二方向排列，多条第一信号线的第一测试盘非位于同一沿第二方向延伸的直线上。
例如，在本公开至少一实施例提供的显示面板中，所述像素电路包括发光元件、驱动晶体管、数据写入晶体管和存储电容；所述数据写入晶体管配置为在所述扫描信号的控制下将所述数据信号传输至所述驱动晶体管，所述驱动晶体管配置为根据所述数据信号控制流经所述发光元件的驱动电流的大小；所述存储电容包括第一极板和第二极板，所述第一极板与所述驱动晶体管的栅极电连接，所述第二极板在所述衬底基板上的正投影与所述第一极板在所述衬底基板上的正投影至少部分重叠；在对所述显示面板进行测试前，所述第一信号线与所述存储电容的第一极板同层设置，且所述测试引线与所述存储电容的第二极板同层设置，或者，所述第一信号线与所述存储电容的第一极板同层设置，并且，所述显示面板还包括遮光层，所述遮光层位于所述第一信号线的靠近所述衬底基板的一侧，所述驱动晶体管的沟道区在所述衬底基板上的正投影位于所述遮光层在所述衬底基板上的正投影之内，所述测试引线与所述遮光层同层设置。
例如，在本公开至少一实施例提供的显示面板还包括多个对位标记。所述多个对位标记的图案彼此不同且与所述多条第一信号线一一对应设置，且分别与对应的所述第一信号线的所述重叠区域间隔开；在对所述显示面板进 行测试时，所述多个对位标记配置为分别被对准装置识别以对对应的所述第一信号线的所述重叠区域内的所述预设位置进行定位；所述对位标记与所述驱动晶体管的有源层、所述第一信号线和所述测试引线中的任意一者同层设置。
例如，在本公开至少一实施例提供的显示面板中，所述测试电路板为覆晶薄膜(COF)，所述多个测试焊盘在所述覆晶薄膜中间隔排列。
例如，在本公开至少一实施例提供的显示面板中，所述非显示区域包括第一非显示区域、第二非显示区域和第三非显示区域，所述第一非显示区域和所述第二非显示区域分别位于所述显示区域在所述第一方向上的第一侧和第二侧，所述第三非显示区域位于所述显示区域在所述第二方向上的第一侧；所述衬底基板包括靠近所述第一非显示区域且沿所述第二方向延伸的第一边缘、靠近所述第二非显示区域且沿所述第二方向延伸的第二边缘、以及靠近所述第三非显示区域且沿所述第一方向延伸的第三边缘；所述多个像素行的第一信号线均从所述显示区域延伸至所述第一非显示区域，所述多个像素行的第一信号线在所述第一非显示区域与所述测试引线连接；所述多个测试焊盘位于所述第三非显示区域且沿所述衬底基板的第三边缘排列，或者，所述多个测试焊盘位于所述第一非显示区域且沿所述衬底基板的第一边缘排列。
例如，在本公开至少一实施例提供的显示面板中，所述多个像素行的第一信号线中的第一部分第一信号线从所述显示区域延伸至所述第一非显示区域，所述第一部分第一信号线在所述第一非显示区域与所述测试引线连接；所述多个像素行的第一信号线中的第二部分第一信号线从所述显示区域延伸至所述第二非显示区域，所述第二部分第一信号线在所述第二非显示区域与所述测试引线连接；所述多个测试焊盘中的第一部分测试焊盘位于所述第一非显示区域，且沿所述衬底基板的第一边缘排列，所述多个测试焊盘中的第二部分测试焊盘位于所述第二非显示区域，且沿所述衬底基板的第二边缘排列，或者，所述第一部分测试焊盘和所述第二部分测试焊盘均位于所述第三非显示区域，且沿所述衬底基板的第三边缘排列。
本公开至少一实施例还提供一种显示面板，该显示面板包括衬底基板、像素阵列、扫描驱动电路、测试电路板和测试引线。衬底基板包括显示区域 和至少部分围绕所述显示区域的非显示区域；像素阵列位于所述衬底基板上的所述显示区域，且包括沿所述第一方向延伸的多个像素行，其中，所述多个像素行的每个像素行包括第一信号线以及子像素，所述子像素包括像素电路，所述第一信号线配置为给其所在的所述像素行中的像素电路提供扫描信号；扫描驱动电路配置为给所述像素电路提供所述扫描信号，且包括位于所述显示区的移位寄存器和时钟信号线；测试电路板位于所述非显示区域，且包括测试焊盘；测试引线位于所述非显示区域，与所述测试焊盘电连接，其中，所述第一信号线包括位于所述显示区域的第一部分和位于所述非显示区域且与所述第一部分连接的第二部分，所述第一部分整体上沿所述第一方向延伸，所述第二部分与所述第一部分连接；所述第一信号线与所述测试引线异层设置且彼此绝缘，所述第一信号线的第二部分在所述衬底基板上的正投影与所述测试引线在所述衬底基板上的正投影至少部分重叠。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的任意一种显示面板。
本公开至少一实施例还提供一种显示面板的测试方法，该测试方法包括：通过所述测试电路板获取所述第一信号线输出的测试信号以检测所述扫描驱动电路是否正常工作。
例如，在本公开至少一实施例提供的显示面板的测试方法中，在所述多个像素行中的每个像素行包括多条所述第一信号线，所述显示面板包括多个所述测试焊盘和多条所述测试引线，所述多个测试焊盘中的每个与所述多条测试引线中的至少一条测试引线在所述非显示区域电连接，且在对所述显示面板进行测试前，所述第一信号线与所述测试引线异层设置且通过层间绝缘层彼此绝缘，所述第一信号线的第二部分在所述衬底基板上的正投影与所述测试引线在所述衬底基板上的正投影至少部分重叠的情况下，所述测试方法还包括：在对所述多条第一信号线中的每条进行测试时，采用激光照射预设位置的所述测试引线、所述层间绝缘层和被测试的所述第一信号线并使所述测试引线、所述层间绝缘层和被测试的所述第一信号线三者熔融且融合，以使融合后的所述测试引线与所述第一信号线在所述预设位置电连接，所述预设位置位于被测试的所述第一信号线与对应的所述测试引线在垂直于衬底基 板的方向上的重叠区域内。
例如，在本公开至少一实施例提供的显示面板的测试方法中，在所述多条测试引线的每条包括主体引线和多个子引线，所述主体引线包括与所述测试焊盘连接的第一端部和远离所述测试焊盘的第二端部，所述多个子引线与所述主体引线的第二端部连接，突出于所述第二端部，且与所述多条第一信号线一一对应，其中，在对所述显示面板进行测试前，所述多个子引线的每个在所述衬底基板上的正投影与对应的所述第一信号线的第二部分在所述衬底基板上的正投影至少部分重叠的情况下，所述预设位置位于被测试的所述第一信号线的第二部分的正投影与对应的所述子引线的正投影的重叠区域内。
例如，在本公开至少一实施例提供的显示面板的测试方法中，所述激光从所述衬底基板的远离所述第一信号线和所述测试引线的一侧入射至所述显示面板的预设位置；所述激光依次到达所述衬底基板、所述第一信号线和所述测试引线且不穿过所述第一信号线与所述衬底基板之间的任何导电层；或者，所述激光依次到达所述衬底基板、所述测试引线和所述第一信号线且不穿过所述测试引线与所述衬底基板之间的任何导电层。
例如，在本公开至少一实施例提供的显示面板的测试方法包括：依次获取所述多条第一信号线输出的测试信号以依次对所述多条第一信号线进行测试，在对所述多条第一信号线中前一条第一信号线测试完成之后，且对所述多条第一信号线中下一条第一信号线进行测试之前，将所述前一条第一信号线切断以在所述前一条第一信号线被切断的位置形成断口，所述断口位于所述非显示区域；所述已完成测试的第一信号线包括被所述断口间隔开的非连接部分和连接部分，所述非连接部分与对应的所述测试引线断开，所述连接部分与对应的所述测试引线连接。
例如，在本公开至少一实施例提供的显示面板的测试方法中，采用激光将所述前一条第一信号线切断。
例如，在本公开至少一实施例提供的显示面板的测试方法中，多条已完成测试的所述第一信号线的断口在与所述第一方向垂直的第二方向上排列。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的一种显示面板的平面示意图；
图2是本公开至少一实施例提供的一种显示面板的像素电路和扫描驱动电路的设置方式示意图；
图3是图2所示的显示面板的像素电路和扫描驱动电路的栅线的设置方式示意图；
图4A是本公开实施例提供的一种显示面板中相邻两个子像素的像素电路的等效电路图；
图4B是本公开实施例提供的一种图4A所示的像素电路的工作时序图；
图5A是本公开实施例提供的一种显示面板的像素结构示意图；
图5B为图5A所示的显示面板的相邻两个子像素的结构示意图；
图6A是本公开实施例提供的一种示出了移位寄存器单元的显示面板的结构示意图；
图6B是本公开实施例提供的一种移位寄存器单元的结构示意图；
图6C是本公开实施例提供的另一种移位寄存器单元的结构示意图；
图6D是本公开实施例提供的一种示出了扫描驱动电路的显示面板的结构示意图；
图7A为图1中的非显示区域中包括第一信号线的第二部分以及测试引线的局部D1的示意图，或者是图5A中包括第一信号线的第二部分以及测试引线的局部D2的示意图；
图7B是图7A中的第一信号线的第二部分的单层示意图；
图7C是图7A中的测试引线的单层示意图；
图8A为本公开一实施例提供的一种显示面板的显示区域的子像素的结构示意图；
图8B为沿图8A中的I-I’线和沿图7A中的A-A’线的一种截面示意图；
图8C为沿图8A中的I-I’线和沿图7A中的A-A’线的另一种截面示意图；
图9A为图8A所示的显示面板的半导体层的示意图；
图9B为图9A中的显示面板的显示区域的半导体层的放大示意图；
图9C为图8A所示的显示面板的第一导电层的一种示意图；
图9D为本公开至少一实施例提供的显示面板的第一导电层的另一种示意图；
图9E为图9A所示的半导体层与图9D所示的第一导电层的叠加示意图；
图9F为图8A所示的显示面板的第二导电层的示意图；
图9G为图9A所示的半导体层、图9D所示的第一导电层、以及图9F所示的第二导电层的叠加示意图；
图9H为图8A所示的显示面板的第三导电层的示意图；
图9I为图9A所示的半导体层、图9D所示的第一导电层、图9F所示的第二导电层、以及图9H所示的第三导电层的叠加示意图；
图9J为图8A所示的显示面板的第四导电层的示意图；
图9K为图9A所示的半导体层、图9D所示的第一导电层、图9F所示的第二导电层、图9H所示的第三导电层、以及图9J的所示的第四导电层的叠加示意图；
图9L为图9A所示的半导体层、图9D所示的第一导电层、图9F所示的第二导电层、图9H所示的第三导电层、图9J的所示的第四导电层以及阳极层的叠加示意图；
图10A-10B为本公开至少一实施例提供的显示面板进行检测的检测方法的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。以下所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现在该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开至少一实施例提供一种显示面板，该显示面板包括：衬底基板、像素阵列、扫描驱动电路、测试电路板以及测试引线。衬底基板包括显示区域和至少部分围绕所述显示区域的非显示区域；像素阵列位于所述衬底基板上的所述显示区域，且包括沿所述第一方向延伸的多个像素行，所述多个像素行的每个像素行包括第一信号线以及子像素，所述子像素包括像素电路，所述第一信号线配置为给其所在的所述像素行中的像素电路提供扫描信号；扫描驱动电路配置为给所述像素电路提供所述扫描信号，且包括位于所述显示区的移位寄存器和时钟信号线；测试电路板位于所述非显示区域，且包括测试焊盘；测试引线位于所述非显示区域，与所述测试焊盘电连接，所述第一信号线包括位于所述显示区域的第一部分和位于所述非显示区域且与所述第一部分连接的第二部分，所述第一部分整体上沿所述第一方向延伸，所述第二部分与所述第一部分连接；在对所述显示面板进行测试前，所述第一信号线与所述测试引线异层设置且彼此绝缘；在对所述显示面板进行测试时，所述测试引线与所述第一信号线的第二部分配置为彼此连接，所述测试电路板配置为通过所述测试焊盘和所述测试引线获取来自所述第一信号线的测试信号。
对本公开实施例提供的显示面板的该扫描驱动电路(GIA)进行测试时，测试电路板可通过测试焊盘获取为像素电路提供扫描信号的第一信号线上的测试信号，以检测该扫描驱动电路是否正常工作。这种方式结构简单，不需要测试引线和测试焊盘与扫描驱动电路例如与扫描电路的移位寄存器或时钟信号线直接连接，而是与像素电路的第一信号线直接连接，简化了测试引线 的结构，节省了空间，且降低了测试引线的制作难度。
图1为本公开至少一实施例提供的一种显示面板的整体结构示意图。如图1所示，显示面板10包括衬底基板01、像素阵列、扫描驱动电路03、测试电路板06以及测试引线05。衬底基板01包括显示区域01A和至少部分围绕显示区域01A的非显示区域01B。像素阵列位于衬底基板01上的显示区域01A，且包括沿第一方向延伸的多个像素行(即图中的第一行、第二行……第N行)，多个像素行的每个像素行包括第一信号线04以及子像素02，例如，像素电路可以包括2T1C(即两个晶体管和一个电容)像素电路、4T2C、5T1C、7T1C或nTmC(n、m为正整数)像素电路。例如，在不同的实施例中，像素电路还可以包括补偿子电路，该补偿子电路包括内部补偿子电路或外部补偿子电路，补偿子电路可以包括晶体管、电容等。例如，根据需要，该像素电路还可以进一步包括复位电路、发光控制子电路、检测电路等。例如，该显示面板10是有机发光二极管(OLED)显示面板，该发光元件为OLED。
第一信号线04配置为给其所在的像素行中的像素电路提供扫描信号。多个子像素中的至少部分子像素包括发光元件和驱动发光元件发光的像素电路。扫描驱动电路03配置为给像素电路提供扫描信号，且包括位于显示区域01A的移位寄存器和时钟信号线。测试电路板06位于非显示区域01B，且包括测试电路060和与测试电路060连接的多个测试焊盘061，例如包括多个测试焊盘061。例如，测试电路板06为覆晶薄膜(COF)，多个测试焊盘061在覆晶薄膜中间隔排列。需要说明的是，测试电路板06可折叠于与显示面板10的显示侧相对的背侧。测试引线05位于非显示区域01B，与测试焊盘061电连接，每条第一信号线04包括位于显示区域01A的第一部分041和位于非显示区域01B且与第一部分连接的第二部分042，第一部分041整体上沿第一方向延伸，第二部分与第一部分连接；在对显示面板10进行测试前，第一信号线04与测试引线05异层设置且彼此绝缘。在对显示面板10进行测试时，测试引线与第一信号线的第二部分配置为彼此连接，测试电路板配置为通过测试焊盘和测试引线获取来自第一信号线的测试信号。例如，该扫描驱动电路为栅极驱动电路。
需要说明的是，特征“所述第一信号线的第一部分整体上沿所述第一方向延伸”是指，第一信号线的第一部分的走线趋势是沿第一方向，例如第一信号线的第一部分可以为沿第一方向延伸的直线型，或者，第一信号线的第一部分具有一定的弯折或者相对于第一方向的倾斜，但是从第一信号线的第一部分的起始端到终止端的方向是沿第一方向的。
例如，测试引线05与第一信号线04直接连接，这里的直接连接是指测试引线05与第一信号线04之间不存在或不连接其他任何的电路结构，该电路结构可以是任意的包括电子元件例如薄膜晶体管、电容等。
对本公开实施例提供的显示面板的该扫描驱动电路(GIA)03进行测试时，测试电路板06可通过测试焊盘061获取为像素电路提供扫描信号的第一信号线04上的测试信号，以检测该扫描驱动电路03是否正常工作。这种方式结构简单，不需要测试引线和测试焊盘与扫描驱动电路例如与扫描电路的移位寄存器或时钟信号线直接连接，而是与像素电路的第一信号线直接连接，简化了测试引线的结构，节省了空间，且降低了测试引线的制作难度。
本公开实施例提供的显示面板10是将扫描驱动电路03设置于显示区域01A内(gate drive in array，GIA)的显示面板，即GIA显示面板。在本公开实施例提供的显示面板的测试引线与扫描驱动电路的连接区别于采用GOA(Gate on array)的显示面板。在采用GOA的显示面板中，用于测试扫描驱动电路是否正常工作的测试引线与扫描驱动电路的连接。在本公开实施例提供的显示面板10中，测试引线05与第一信号线04直接连接，测试引线05与第一信号线04这件不存在或不连接其他任何的电路结构。然而，在GOA显示面板中，测试焊盘与测试引线连接，测试引线与GOA扫描驱动电路的信号线例如与GOA扫描驱动电路的移位寄存器的输入端连接的信号线连接以获取这些信号线的信号，这些与移位寄存器的输入端连接的信号线例如包括时钟信号线等，移位寄存器以及与移位寄存器的输入端连接的这些信号线均位于非显示区域中，不是从显示区域延伸到非显示区域，并且，这种情况下，在测试引线与像素电路之间至少连接有GOA扫描驱动电路。
图2是本公开至少一实施例提供的一种显示面板的像素电路和扫描驱动电路的设置方式示意图，图3是图2所示的显示面板的像素电路和扫描驱动 电路的栅线的设置方式示意图。如图1-3所示，每个像素02均可以包括：发光控制电路021、发光驱动电路022和发光元件023。
例如第一信号线04为栅线，该栅线例如包括扫描线、复位控制线和发光控制线。这里栅线是指与晶体管的栅极直接连接以提供扫描信号或控制信号的信号线。例如，如图2-3所示，显示面板10包括多条第一信号线04，多条第一信号线04包括多条发光控制线EM1至EMn、多条扫描线G1至Gm。例如，显示面板10还包括多条驱动信号线例如如图2示出的L1至Li。
扫描驱动电路03的输入端与多条驱动信号线L1至Li连接，扫描驱动电路03的输出端与多条发光控制线EM1至EMn和多条扫描线G1至Gm连接。多条发光控制线EM1至EMn可以与对应的像素行中的各个子像素02包括的发光控制电路021连接，多条扫描线G1至Gm可以与对应的像素行中的各子像素02包括的发光驱动电路022连接。扫描驱动电路03可以用于响应于多条驱动信号线提供的驱动信号，向多条发光控制线输出发光控制信号，并向多条栅线输出栅极驱动信号。即，扫描驱动电路03可以在多条驱动信号线L1至Li提供的驱动信号的驱动下工作。
例如，多行子像素02可与多条第一信号线04对应连接，例如在本公开至少一实施例提供的显示面板中，每行子像素02分别对应连接一条扫描线、两条复位控制线和一条发光控制线，该两条复位控制线分别为第一复位控制线和第二复位控制线。即位于同一行的多个子像素02中，每个子像素02的像素电路包括的发光控制电路021可以与同一条发光控制线连接，每个子像素02包括的发光驱动电路022可以与同一条扫描线连接。例如，在本公开至少一实施例中，显示面板10包括的扫描线的条数和像素的行数相同。
例如，如图2-3所示，至少两个像素02可以共用同一个发光控制电路021，即至少两个像素02可以在同一个发光控制电路021的驱动下工作。由于至少两个子像素02可以共用同一个发光控制电路021，因此若该至少两个子像素02位于同一行，则相应的可以减少所需设置的发光控制电路021的数量；若该至少两个子像素02位于同一列，则相应的既可以减少所需设置的发光控制电路021的数量，且可以减少所需设置的发光控制线的数量。如此，均可以在不影响子像素02正常显示的前提下，达到优化像素空间的效果，即相对于相关技术减小子像素02在衬底基板01上所占用的面积。进而，即增 大了衬底基板01上剩余空间的面积，该剩余空间可以用于可靠设置扫描驱动电路03和扫描驱动电路03所需连接的驱动信号线。由此，即得到了图2-3所示的将扫描驱动电路03设置于基板内(gate drive in array，GIA)的显示面板10，即GIA显示面板。
另外，继续参考图2，每个子像素02中，发光控制电路021还可以与发光驱动电路022连接，发光驱动电路022还可以与发光元件023连接。发光控制电路021可以用于响应于所连接的发光控制线提供的发光控制信号，向所连接的发光驱动电路022输出直流电源信号。发光驱动电路022可以用于响应于所连接的栅线提供的栅极驱动信号和接收到的直流电源信号，向所连接的发光元件023输出驱动信号，以驱动发光元件023发光。
本公开实施例提供的显示面板中，位于衬底基板01上的至少两个像素可以共用同一个连接发光控制线的发光控制电路，因此可以减少显示面板中所需设置的发光控制电路的数量，或是再减少显示面板上所需设置的发光控制线的数量，即最终使得每个像素所需占用衬底基板的面积较小。进而，可以使得为像素所连接的信号线提供信号的扫描驱动电路，以及扫描驱动电路所连接的驱动信号均能够设置于衬底基板上。本公开实施例提供的显示面板的分辨率较高。
例如，如图2所示，在本公开实施例提供的显示面板10中，共用同一个发光控制电路021的至少两个子像素02可以位于同一列。如此，结合上述实施例记载，相对于相关技术，不仅可以减少衬底基板01上所需设置的发光控制电路021的数量，而且可以减少衬底基板01上所需设置的发光控制线的数量。
例如，假设显示面板共包括m行子像素02，若位于同一列的至少两个子像素02共用同一个发光控制电路021，则衬底基板上01设置的发光控制线的数量小于子像素02的行数。即，图2中n小于m，其中m和n均可以为大于1的整数。
例如，共用同一个发光控制电路021的至少两个子像素02不仅位于同一列，且可以相邻。如此，可以便于版图布局，以及信号走线。
例如，图3以位于同一列且相邻的每两个子像素02共用同一个发光控制电路021为例示出又一种显示面板。且，图3仅示意性示出相邻的第n行子 像素02和第n+1行子像素02共用同一个发光控制电路021，以及相邻的第n+2行子像素02和第n+3行子像素02共用同一个发光控制电路021。结合图3可以进一步看出，在共用同一个发光控制电路021的两个子像素02位于同一列时，相邻两个子像素02也可以共用同一条发光控制线(如，EMn和EM(n+1))。
图4A是本公开实施例提供的一种显示面板中相邻两个子像素的像素电路的等效电路图，图4B是本公开实施例提供的一种图4A所示的像素电路的工作时序图，图5A是本公开实施例提供的一种显示面板的像素结构示意图，图5B为图5A所示的显示面板的相邻两个子像素的结构示意图。需要说明的是，在图5A中为了清楚地表达显示面板10中包括第一信号线以及像素电路的局部，图5A省略了测试引线、测试焊盘等结构，被省略的测试引线、测试焊盘等结构的位置与图1中的相同。
结合图3、图4A和图5A-5B，以位于第一列且相邻的第n行子像素02和第n+1行子像素02为例。共用同一个发光控制电路021的两个子像素02，可以对称排布于其所共用的发光控制电路021连接的发光控制线EMn的两侧。即，该两个子像素02中，一个子像素02包括的各晶体管和所连接的各条信号线，与另一个子像素02包括的各晶体管和所连接的各条信号线均可以对称设置于发光控制线EMn的两侧。如此设计，不仅可以进一步便于版图布局，信号走线，且可以使得信号线集中设置，进一步优化了像素空间。
结合图4A和图5B，在本公开实施例中，为了可靠驱动子像素02包括的发光元件023发光，该显示面板10还可以包括：位于衬底基板01上的多条数据线。多条扫描线可以包括：多条第一扫描线、多条第二扫描线和多条第三扫描线。
数据线的条数与像素列数可以相同，第一扫描线的条数、第二扫描线的条数和第三扫描线的条数均可以与像素行数相同。图4A和图5B仅示出一条数据线D1，两条第一扫描线G1n和G1(n+1)，两条第二扫描线G2n和G2(n+1)，以及两条第三扫描线G3n和G3(n+1)。
继续参考图4A和图5B，每个子像素02中，发光控制电路021可以包括：发光控制晶体管T1。发光驱动电路可以包括：数据写入晶体管T2、复 位晶体管T3、驱动晶体管T4、补偿晶体管T5和存储电容Cst。数据写入晶体管T2配置为在扫描信号的控制下将数据信号传输至驱动晶体管，驱动晶体管T4配置为根据数据信号控制流经发光元件023的驱动电流的大小。
数据写入晶体管T2的栅极可以与一条第一扫描线连接，第一极可以与驱动晶体管T4的栅极连接，第二极可以与一条数据线D1连接。其中，第n行子像素02中的数据写入晶体管T2的栅极与第一扫描线G1n连接，第n+1行子像素02中的数据写入晶体管T2的栅极与第一扫描线G1(n+1)连接。
驱动晶体管T4的第一极可以与发光控制晶体管T1的第一极连接，第二极可以与发光元件023连接，发光元件023还可以与第一电源端VSS连接。
发光控制晶体管T1的栅极可以与一条发光控制线EMn连接，发光控制晶体管T1的第二极可以与第二电源端VDD连接。
复位晶体管T3的栅极可以与一条第二扫描线连接，第一极可以与第一初始信号端Vin1连接，第二极可以与驱动晶体管T4的第二极连接。第n行子像素02中的复位晶体管T3的的栅极与第二扫描线G2n连接，第n+1行子像素02中的复位晶体管T3的栅极与第二扫描线G2(n+1)连接。
补偿晶体管T5的栅极可以与一条第三扫描线连接，第一极可以与第二初始信号端Vin2连接，第二极可以与驱动晶体管T4的栅极连接。其中，第n行子像素02中的补偿晶体管T5的的栅极与第三扫描线G3n连接，第n+1行子像素02中的补偿晶体管T5栅极与第三扫描线G3(n+1)连接。
需要说明的是，以上仅是示意性示出一种子像素02的可选结构，为5T1C(即，五个晶体管和一个电容)结构。当然，本公开实施例对子像素02的结构不做限定，其还可以是其他结构，如7T1C结构。
下述实施例均以位于同一列且每相邻两个子像素02共用同一个发光控制电路021为例示出显示基板的可选结构。当然，在本公开的其他一些实施例中，相邻两个子像素02也可以不共用同一个发光控制电路021，每个子像素的像素电路都包括一个发光控制电路021，本公开对此不作限定。
例如，在本公开实施例中，扫描驱动电路03所连接的每条驱动信号线Li可以均位于相邻两列子像素02之间。例如，参考图6，其示出了再一种显示基板，由于位于同一列且每相邻两个子像素02共用同一个发光控制电路 021，因此使得在每相邻两列子像素02之间可以预留有额外区域，如图6示出的区域5和区域6。相应地，扫描驱动电路03所连接的驱动信号线Li可以设置于该区域5和6中。
由于每相邻两列子像素02之间的区域有限，因此为了确保驱动信号线的可靠设置，每相邻两列子像素02之间，可以设置有至多两条驱动信号线。
在本公开实施例中，扫描驱动电路03可以包括：级联的多个移位寄存器单元031。至少两个级联的移位寄存器单元031可以位于相邻两行子像素02之间。例如，多个像素行中相邻的像素行之间具有间隙区域，移位寄存器和时钟信号线位于间隙区域内。
例如，再结合图5A，由于位于同一列且每相邻两个子像素02共用同一个发光控制电路021，因此使得在每相邻两行子像素02之间也可以预留有额外区域，如图6示出的区域1、区域2、区域3和区域4。相应的，至少两个级联的移位寄存器单元031可以设置于每相邻两行子像素02之间的区域1至区域4中。
并且，为了便于信号走线，结合图5A，至少两个级联的移位寄存器单元031可以位于相邻两行目标子像素02之间。该两行目标子像素02中，一行目标子像素02所连接的发光控制电路，与另一行目标子像素02所连接的发光控制电路不同。即，少两个级联的移位寄存器单元031可以位于为未共用发光控制电路021的两行子像素02之间。
例如，图6A是本公开实施例提供的再一种显示基板的结构示意图。如图6A所示，每相邻两行目标子像素02之间可以仅设置有两个级联的移位寄存器单元031。其中，一个移位寄存器单元031可以与一行目标子像素02连接，另一个移位寄存器单元031可以与另一行目标子像素02连接(图6A未示出)。
例如，该两个级联的移位寄存器单元031可以对称排布于该两行目标像素之间。即一个移位寄存器单元031包括的各晶体管，与另一个移位寄存器单元031包括的各晶体管均对称设置。如此，可以使得一些驱动信号线(如，提供直流信号的电源信号)可以被共用，进一步优化了GIA空间，即减少了移位寄存器单元031所需占用衬底基板01的面积。
图6B是本公开实施例提供的一种移位寄存器单元的结构示意图。如图6B所示，移位寄存器单元031可以包括：输入子电路0311、下拉控制子电路0312、下拉子电路0313和输出子电路0314。
输入子电路0311可以分别与第一输入端IN1、第二输入端IN2、第一控制信号端CN、第二控制信号端CNB和上拉节点PU连接。输入子电路0311可以用于响应于第一输入端IN1提供的第一输入信号，向上拉节点PU输出第一控制信号端CN提供的第一控制信号，以及响应于第二输入端IN2提供的第二输入信号，向上拉节点PU输出第二控制信号端CNB提供的第二控制信号。
例如，输入子电路0311可以在第一输入端IN1提供的第一输入信号的电位为第一电位时，向上拉节点PU输出第一控制信号端CN提供的第一控制信号。以及，可以在第二输入端IN2提供的第二输入信号的电位为第一电位时，向上拉节点PU输出第二控制信号端CNB提供的第二控制信号。
例如，第一输入端IN1可以与上一级移位寄存器单元031的输出端连接，第二输入端IN2可以与下一级移位寄存器单元031的输出端连接。第一控制信号的电位和第二控制信号的电位可以互补。即在第一控制信号的电位为第一电位时，第二控制信号的电位为第二电位；在第一控制信号的电位为第二电位时，第二控制信号的电位为第一电位。其中，第一电位可以为有效电位，第二电位可以为无效电位。在晶体管为N型晶体管时，第一电位相对于第二电位可以为高电位；在晶体管为P型晶体管时，第一电位相对于第二电位可以为低电位。
下拉控制子电路0312可以分别与第一时钟信号端CK、上拉节点PU、下拉电源端VGL、下拉节点PD和输出端OUT连接。下拉控制子电路0312可以用于响应于第一时钟信号端CK提供的第一时钟信号，向下拉节点PD输出第一时钟信号，以及响应于上拉节点PU的电位和输出端OUT提供的输出信号，向下拉节点PD输出下拉电源端VGL提供的下拉电源信号。
示例的，下拉控制子电路0312可以在第一时钟信号端CK提供的第一时钟信号的电位为第一电位时，向下拉节点PD输出第一时钟信号，以实现对下拉节点PD的充电。下拉控制子电路0312可以在上拉节点PU的电位为第一电位时，向下拉节点PD输出下拉电源端VGL提供的下拉电源信号，该下 拉电源信号的电位可以为第二电位，以实现对下拉节点PD的降噪。以及，下拉控制子电路0312可以在输出端OUT提供的输出信号的电位为第一电位时，向下拉节点PD输出下拉电源信号，以实现对下拉节点PD的降噪。
下拉子电路0313可以分别与复位信号端RST、下拉节点PD、下拉电源端VGL、上拉节点PU和输出端OUT连接。下拉子电路0313可以用于响应于下拉节点PD的电位，向上拉节点PU和输出端OUT输出下拉电源信号，以及响应于复位信号端RST提供的复位信号，向上拉节点PU输出下拉电源信号。
示例的，下拉子电路0313可以在下拉节点PD的电位为第一电位时，向上拉节点PU和输出端OUT输出下拉电源信号，以实现对上拉节点PU和输出端OUT的降噪。以及，可以在复位信号端RST提供的复位信号的电位为第一电位时，向上拉节点PU输出下拉电源信号，以实现对上拉节点PU的降噪。
输出子电路0314可以分别与上拉节点PU、第二时钟信号端CKB和输出端OUT连接。输出子电路0314可以用于响应于上拉节点PU的电位，向输出端OUT输出第二时钟信号端CKB提供的第二时钟信号。
示例的，输出子电路0314可以在上拉节点PU的电位为第一电位时，向输出端OUT输出第二时钟信号端CKB提供的第二时钟信号。该第二时钟信号可以作为栅极驱动信号提供至栅线，或，作为发光控制信号提供至发光控制线。
图6C是本公开实施例提供的另一种移位寄存器单元的结构示意图。如图6C所示，输入子电路0311可以包括：第一输入晶体管M1和第二输入晶体管M2。下拉控制子电路0312可以包括：第一下拉控制晶体管M3、第二下拉控制晶体管M4和第三下拉控制晶体管M5。下拉子电路0313可以包括：第一下拉晶体管M6、第二下拉晶体管M7、第三下拉晶体管M8和下拉电容C2。输出子电路0314可以包括：输出晶体管M9和输出电容C3。
其中，第一输入晶体管M1的栅极可以与第一输入端IN1连接，第一极可以与第一控制信号端CN连接，第二极可以与上拉节点PU连接。相应的，第一输入晶体管M1可以在第一输入端IN1提供的第一输入信号的电位为第一电位时，向上拉节点PU输出第一控制信号端CN提供的第一控制信号， 实现对上拉节点PU的充电。
第二输入晶体管M2的栅极可以与第二输入端IN2连接，第一极可以与第二控制信号端CNB连接，第二极可以与上拉节点PU连接。相应的，第二输入晶体管M2可以在第二输入端IN2提供的第二输入信号的电位为第一电位时，向上拉节点PU输出第二控制信号端CNB提供的第二控制信号，实现对上拉节点PU的复位。
第一下拉控制晶体管M3的栅极和第一极可以均与第一时钟信号端CK连接，第二极可以与下拉节点PD连接。相应的，第一下拉控制晶体管M3可以在第一时钟信号端CK提供的第一时钟信号的电位为第一电位时，向下拉节点PD输出第一时钟信号，实现对下拉节点PD的充电。
第二下拉控制晶体管M4的栅极可以与上拉节点PU连接，第一极可以与下拉电源端VGL连接，第二极可以与下拉节点PD连接。相应的，第二下拉控制晶体管M4可以在上拉节点PU的电位为第一电位时，向下拉节点PD输出下拉电源信号，实现对下拉节点PD的降噪。
第三下拉控制晶体管M5的栅极可以与输出端OUT连接，第一极可以与下拉电源端VGL连接，第二极可以与下拉节点PD连接。相应的，第三下拉控制晶体管M5可以在输出端OUT提供的输出信号的电位为第一电位时，向下拉节点PD输出下拉电源信号，实现对下拉节点PD的降噪。
第一下拉晶体管M6的栅极可以与复位信号端RST连接，第一极可以与下拉电源端VGL连接，第二极可以与上拉节点PU连接。相应的，第一下拉晶体管M6可以在复位信号端RST提供的复位信号的电位为第一电位时，向上拉节点PU输出下拉电源端VGL提供的下拉电源信号，实现对上拉节点PU的降噪。
第二下拉晶体管M7的栅极和第三下拉晶体管M8的栅极均可以与下拉节点PD连接，第二下拉晶体管M7的第一极和第三下拉晶体管M8的第一极均可以与下拉电源端VGL连接，第二下拉晶体管M7的第二极可以与上拉节点PU连接，第三下拉晶体管M8的第二极可以与输出端OUT连接。相应的，第二下拉晶体管M7可以在下拉节点PD的电位为第一电位时，向上拉节点PU输出下拉电源信号，实现对上拉节点PU的降噪。第三下拉晶体管M8可以在下拉节点PD的电位为第一电位时，向输出端OUT输出下拉电源 信号，实现对输出端OUT的降噪。
下拉电容C2的一端可以与下拉节点PD连接，另一端可以与下拉电源端VGL连接。下拉电容C2可以用于保持下拉节点PD的电位。
输出电容C3的一端可以与上拉节点PU连接，另一端可以与输出端OUT连接。输出电容C3可以用于保持上拉节点PU的电位。
输出晶体管M9的栅极可以与上拉节点PU连接，第一极可以与第二时钟信号端CKB连接，第二极可以与输出端OUT连接。
相应的，对于图6A和图6B示出的移位寄存器单元031所属扫描驱动电路03而言，该扫描驱动电路03所连接的驱动信号线即包括：第一控制信号端CN所连接的信号线，第二控制信号端CNB所连接的信号线，复位信号端RST所连接的信号线，第一时钟信号端CK端所连接的信号线，第二时钟信号端CKB端所连接的信号线，以及下拉电源端VGL所连接的信号线。如此，若两个移位寄存器单元031对称排布于两行目标子像素02之间，则两个移位寄存器单元031可以共用一条下拉电源端VGL所连接的信号线。
再结合图6D，其以图6B示出的移位寄存器单元031，示出了位于相邻两行子像素02之间的移位寄存器单元031的电路结构，以及驱动信号线的可选设置位置。结合图6至图6C可知，在布局时，可以将移位寄存器单元031中尺寸相对较大的晶体管设置于面积相对较大的区域1和区域2中，将移位寄存器单元031中尺寸相对较小的晶体管设置于面积相对较小的区域3和区域4中。另，再参考图6D，还可以将两个晶体管串联形成一个晶体管(如，图6D示出的两个晶体管M7)，或，将两个电容串联形成一个电容(如，图6D示出的两个电容C2，和两个电容C3)，从而使得可以在衬底基板01有限的空间内，可靠设置下移位寄存器单元031中的所有晶体管。
在衬底基板01面积确定的情况下，对比未复用发光控制电路021的相关技术，本公开实施例通过设置至少两个子像素02复用同一个发光控制电路021，使得衬底基板01中除子像素02所在区域之外的其他区域面积较大。由此，为扫描驱动电路03设置于衬底基板01上提供了有效的技术支持，即为高分辨率(per pixel inch，PPI)的GIA显示基板提供了技术支持。
假设子像素02中的晶体管均为N型晶体管，结合图4示出的复用同一个发光控制电路021的相邻两个子像素02，对本公开实施例提供的像素工作 原理进行介绍：图6D是本公开实施例提供的一种像素工作时序图。
参考图4B，在t1阶段，第n行子像素02中，复位晶体管T3连接的第二栅线G2n提供处于第一电位的栅极驱动信号，复位晶体管T3开启。补偿晶体管T5连接的第三栅线G3n也提供处于第一电位的栅极驱动信号，补偿晶体管T5开启。相应的，第一初始信号端Vin1可以通过复位晶体管T3，向第n行子像素02中的驱动晶体管T4的第二极输出处于第二电位的第一初始信号，从而实现对驱动晶体管T4的第二极的复位。第二初始信号端Vin2可以通过补偿晶体管T5，向第n行子像素02中的驱动晶体管T4的栅极输出第二初始信号，第二初始信号可以作为补偿数据Vref1。t1阶段也可以称为驱动第n行子像素02时的复位阶段。
在t2阶段，第n行子像素02中，补偿晶体管T5连接的第三栅线G3n持续提供处于第一电位的栅极驱动信号。补偿晶体管T5保持开启。第二初始信号端Vin2可以通过补偿晶体管T5，继续向第n行子像素02中的驱动晶体管T4的栅极输出第二初始信号。在存储电容Cst耦合作用下，驱动晶体管T4的栅极的电位可以随着驱动晶体管T4的第二极电位变化，直至变为Vref1-Vth1，Vth1为该驱动晶体管T4的阈值电压。t2阶段可以称为驱动第n行子像素02时的补偿阶段。
在t3阶段，第n行子像素02中，数据写入晶体管T2连接的第一栅线G1n开始提供处于第一电位的栅极驱动信号，数据写入晶体管T2开启。数据线D1通过该数据写入晶体管T2向驱动晶体管T4的栅极输出数据信号。t3阶段可以称为驱动第n行子像素02时的数据写入阶段。
在t4阶段，第n+1行子像素02中，复位晶体管T3连接的第二栅线G2(n+1)提供处于第一电位的栅极驱动信号，该复位晶体管T3开启。补偿晶体管T5连接的第三栅线G3(n+1)也提供处于第一电位的栅极驱动信号，该补偿晶体管T5开启。相应的，第一初始信号端Vin1可以通过该复位晶体管T3，向第n+1行子像素02中的驱动晶体管T4的第二极输出处于第二电位的第一初始信号，从而实现对该驱动晶体管T4的第二极的复位。第二初始信号端Vin2可以通过补偿晶体管T5，向第n+1行子像素02中的驱动晶体管T4的栅极输出第二初始信号，第二初始信号可以作为该行像素驱动时的补偿数据Vref2。t4阶段可以称为驱动第n+1行子像素02时的复位阶段。
在t5阶段，第n+1行子像素02中，补偿晶体管T5连接的第三栅线G3(n+1)持续提供处于第一电位的栅极驱动信号。补偿晶体管T5保持开启。第二初始信号端Vin2可以通过补偿晶体管T5，继续向第n+1行子像素02中的驱动晶体管T4的栅极输出第二初始信号。在该行子像素02中存储电容Cst的耦合作用下，该行子像素02的驱动晶体管T4的栅极的电位可以随着其第二极的电位变化，直至变为Vref2-Vth2，Vth2为该驱动晶体管T4的阈值电压。t5阶段可以称为驱动第n+1行子像素02时的补偿阶段。
在t6阶段，第n+1行子像素02中，数据写入晶体管T2连接的第一栅线G1(n+1)开始提供处于第一电位的栅极驱动信号，该数据写入晶体管T2开启。数据线D1可以通过该数据写入晶体管T2，向该行子像素02中驱动晶体管T4的栅极输出数据信号。t6阶段可以称为驱动第n+1行子像素02时的数据写入阶段。
需要说明的是，参考图6D，在阶段t1、阶段t2、阶段t4和阶段t5中，第n行子像素02和第n+1行子像素02复用的发光控制晶体管T1连接的发光控制线EMn一直提供处于第一电位的发光控制信号。直流电源端VDD可以通过该发光控制晶体管T1向该两行子像素02中，每行子像素02包括的驱动晶体管T4的第一极输出直流电源信号。在t3阶段之后，第n行子像素02中，驱动晶体管T4即可以基于该直流电源信号和数据信号，向所连接的发光元件023输出驱动信号，以驱动第n行发光元件023发光。在t6阶段之后，第n+1行子像素02中，驱动晶体管T4即可以基于该直流电源信号和数据信号，向所连接的发光元件023输出驱动信号，以驱动第n+1行发光元件023发光。
需要说明的是，本公开实施例中描述的设置于显示区域的显示阵列中的扫描驱动电路(GIA)的示例以及像素电路的具体结构只是示例性的，本公开实施例对该扫描电路和像素电路的具体结构不作限定，例如对于像素电路的排列、是否共用发光控制电电路、每行子像素对应的第一信号线的条数等不作限定，本领域技术人员可根据具体需求进行设计。
图7A为图1中的非显示区域中包括第一信号线的第二部分以及测试引线的局部D1的示意图，或者是图5A中包括第一信号线的第二部分以及测试引线的局部D2的示意图；图7B是图7A中的第一信号线的第二部分的单层 示意图；图7C是图7A中的测试引线的单层示意图；图8A(与图5A中的子像素的结构相似，图5A与图8A相比省略了一些功能层)为本公开一实施例提供的一种显示面板的显示区域的子像素的结构示意图；图8B为沿图8A中的I-I’线和沿图7A中的A-A’线的一种截面示意图。结合图1、图7A-8B，在对显示面板10进行测试前，第一信号线04与测试引线05异层设置且彼此绝缘，第一信号线04的第二部分042在衬底基板上的正投影与测试引线05在衬底基板上的正投影至少部分重叠；在对显示面板10进行测试时，第一信号线04的第二部分042在衬底基板01上的正投影与测试引线05在衬底基板上的正投影重叠的部分配置为彼此连接。例如，多个像素行中的每个像素行包括多条第一信号线04，显示面板10包括多个测试焊盘061和多条测试引线05，多个测试焊盘中的每个与多条测试引线05中的至少一条测试引线05在非显示区域电连接；例如与多条测试引线05，以减少测试焊盘061的数量，节省测试电路板的空间以及降低测试焊盘的制作难度。在对显示面板10进行测试前，多条测试引线05的每条在衬底基板01上的正投影与显示面板10的至少一个像素行中的多条第一信号线04的第二部分042在衬底基板01上的正投影至少部分重叠。需要说明的是，图7A中以图5A中连接同一子像素02的像素电路的四条第一信号线G3n/G1n/G2n/EMn的第二部分G3n2/G1n2/G2n2/EMn2为例来对第一信号线与测试引线的关系进行描述，例如，对于每条第一信号线04均是如此。
例如，在对显示面板10进行测试前，多条测试引线05的每条在衬底基板上的正投影与多个像素行中的同一像素行的多条第一信号线04的第二部分042在衬底基板上的正投影至少部分重叠，如图7A-7C所示。或者，在本公开的至少另一实施例中，多条测试引线05的每条在衬底基板上的正投影与多个像素行中的相邻的像素行的多条第一信号线04的第二部分042在衬底基板上的正投影至少部分重叠。如此，多条第一信号线04连接到同一个测试焊盘，可减少测试焊盘061的数量，节省测试电路板的空间以及降低测试焊盘的制作难度。
例如，多条第一信号线04中的每条和与其在衬底基板01上的正投影重叠的测试引线05之间不设置任何开关器件，该开关器件包括薄膜晶体管 (TFT)等。
例如，如图7A-7B所示，显示面板10还包括多个对位标记M1/M2/M3/M4，多个对位标记M1/M2/M3/M4的图案彼此不同且与多条第一信号线04一一对应设置，且分别与对应的第一信号线04的重叠区域间隔开。图7A-7B以对应于四条第一信号线G3n/G1n/G2n/EMn的四个对位标记M1/M2/M3/M4为例。在对显示面板10进行测试时，多个对位标记M1/M2/M3/M4配置为分别被对准装置识别以对对应的第一信号线04的重叠区域内的预设位置进行定位。例如，对位标记是不透光的。例如，对位标记与驱动晶体管T4的有源层、第一信号线04和测试引线05中的任意一者同层设置。驱动晶体管T4的有源层、第一信号线04和测试引线05所在的层与进行对位的目标结构即第一信号线04和测试引线05同层或者较为靠近目标结构所在的层，对位标记设置在这些层中，利于对位识别的准确性。
例如，如图7A-7C所示，多条测试引线05的每条包括主体引线0520和多个子引线0521/0522/0523/0524。主体引线0520包括与测试焊盘061连接的第一端部051和远离测试焊盘061的第二端部052，例如，多条测试引线05的主体引线0520的第一端部051与多个测试焊盘06一一对应地连接。例如，第二端部052沿第二方向延伸，第二方向与第一方向基本垂直；多个子引线0521/0522/0523/0524与主体引线0520的第二端部052连接，突出于第二端部052，且与多条第一信号线G3n/G1n/G2n/EMn的第二部分G3n2/G1n2/G2n2/EMn2一一对应，由于一个主体引线0520上设置有与多条第一信号线G3n/G1n/G2n/EMn的第二部分G3n2/G1n2/G2n2/EMn2一一对应的多个子引线0521/0522/0523/0524，从而测试焊盘的个数减少。如图7A-7C所示，在对显示面板10进行测试前，多个子引线0521/0522/0523/0524的每个在衬底基板01上的正投影与对应的第一信号线G3n/G1n/G2n/EMn的第二部分G3n2/G1n2/G2n2/EMn2在衬底基板01上的正投影至少部分重叠。
例如，如图7B所示，在对显示面板10进行测试前，多条第一信号线04的每条的第二部分的靠近对应的子引线0521/0522/0523/0524的端部具有第一测试盘PAD G1/PAD G2/PAD G4/PAD G4。如图7B所示，第一测试盘PAD G1/PAD G2/PAD G4/PAD G4在该条第一信号线04的线宽方向上的宽 度w1大于该条第一信号线04的线宽w2。多个子引线0521/0522/0523/0524的每个的第一端与主体引线0520连接，多个子引线0521/0522/0523/0524的每个的第二端具有第二测试盘PAD T1/PAD T2/PAD T3/PAD T4，第二测试盘PAD T1/PAD T2/PAD T3/PAD T4在该子引线0521/0522/0523/0524的线宽方向的宽度w3大于该子引线0521/0522/0523/0524的线宽w4。第二测试盘PAD T1/PAD T2/PAD T3/PAD T4在衬底基板01上的正投影与对应的第一信号线04的第一测试盘PAD G1/PAD G2/PAD G4/PAD G4在衬底基板01上的正投影至少部分重叠。即，使第一信号线04的第二部分与对应的子引线的彼此靠近的端部在垂直于衬底基板01方向上彼此重叠。并且，由于第一测试盘PAD G1/PAD G2/PAD G4/PAD G4在该条第一信号线04的线宽方向上的宽度大于该条第一信号线04的线宽，从而可增大第一信号线04的第二部分与对应的子引线在垂直于衬底基板01方向上的重叠面积，保障当需要对显示面板10进行测试时，该重叠部分可以电连接。
如图7A所示，第一电源线VSS线包括多个开口O，例如为多个条形开口O，多个开口O与多条第一信号线04在垂直于衬底基板01的方向上至少部分重叠，以减少第一电源线VSS线与多条第一信号线04的交叠面积，降低因电荷聚集不良引发两者交叠处发生短路的概率。
如图8B所示，显示面板10的每个子像素02的像素电路包括薄膜晶体管(TFT)例如为发光控制晶体管T4、发光元件180和存储电容Cst。薄膜晶体管包括有源层120、栅极121和源漏极122/123；存储电容Cst包括第一极板CE1和第二电容极板CE2。发光元件180包括阴极183、阳极181以及阴极183和阳极181之间的发光层182，阳极181与薄膜晶体管TFT的源漏极122/123中之一，例如漏极123，电连接。当然，在其他实施例中，阳极181与薄膜晶体管TFT的漏极123也可通过转接电极电连接。例如，该发光元件例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)，相应地，发光层182为有机发光层或量子点发光层。
如图8B所示，显示面板10还包括层间绝缘层152，在对显示面板10进行测试前，层间绝缘层152位于第一信号线04与测试引线05之间以使两者绝缘，并且，第一信号线04、层间绝缘层152和测试引线05配置为可被 激光在预设位置熔融以使第一信号线04和测试引线05在预设位置处电连接，预设位置位于第一信号线04在衬底基板01上的正投影与测试引线05在衬底基板01上的正投影的重叠区域内。对显示面板10进行测试时，采用激光照射预设位置的测试引线05、层间绝缘层和被测试的第一信号线04并使测试引线05、层间绝缘层和被测试的第一信号线04三者熔融且融合，以使融合后的测试引线05与第一信号线04在预设位置电连接，从而使得第一信号线04通过对应的测试引线05与对应的测试焊盘061电连接，从而可通过测试电路板06获取第一信号线04输出的测试信号以检测显示面板10的扫描驱动电路03是否正常工作。
例如，层间绝缘层152的材料可以为氮化硅或氧化硅或氮氧化硅，以使得第一信号线04、层间绝缘层152和测试引线05配置为可被激光在预设位置熔融以使第一信号线04和测试引线05在预设位置处电连接。例如，衬底基板01为玻璃基板、石英基板等耐热、性质温度的基板，从而，在第一信号线04、层间绝缘层152和测试引线05配置为可被激光在预设位置熔融的过程中，衬底基板01的结构和性能不会受到影响。
例如，第一信号线04和测试引线05的材料是金属材料，例如金属或合金。例如铜、铝、铜合金、铝合金等。上述列举的材料只是示例性的，本公开实施例对第一信号线04和测试引线05的材料不作限定。
例如，在一个示例中，如图8B所示，在对显示面板10进行测试前，测试引线05位于第一信号线04的远离衬底基板的一侧，第一信号线04与衬底基板之间不设置任何导电层，如此，在对显示面板10进行测试时，激光在预设位置穿过衬底基板01之后，通过控制激光的强度等参数，可使激光仅依次作用于被测试的第一信号线04、层间绝缘层152和测试引线05，而不会作用于其他任何导电层，从而防止对其他导电层造成影响。
例如，如图8B所示，显示面板10还包括位于有源层120与栅极121之间的第一栅绝缘层151、位于栅极121上方的第二栅绝缘层152以及层间绝缘层160，第二栅绝缘层152位于第一极板CE1和第二电容极板CE2之间，使得第一极板CE1、第二栅绝缘层152和第二电容极板CE2构成存储电容Cst。层间绝缘层160覆盖在第二电容极板CE2上。
例如，如图8B所示，显示面板10还包括覆盖像素电路的绝缘层113(例如钝化层)和第一平坦化层112。显示区域201还包括用于限定多个子像素的像素界定层170以及像素界定层170上的隔垫物(未示出)等结构。如图2所示，在一些实施例中，绝缘层113位于源漏极122/123上方(例如钝化层，由氧化硅、氮化硅或者氮氧化硅等材料形成)，绝缘层113上方设置有第一平坦化层112，阳极181通过贯穿第一平坦化层112和绝缘层113的过孔与漏极123电连接。
例如，如图8B所示，显示面板还包括封装层190，封装层190包括多个封装子层191/192/193。例如，第一封装层291与封装层190中的第一封装子层191同层设置，第二封装层292与封装层190中的第二封装子层192同层设置，第三封装层293与封装层190中的第三封装子层193同层设置，例如，第一封装层291和第三封装层293均可以包括无机封装材料，例如包括氧化硅、氮化硅或者氮氧化硅等，第二封装层292可以包括有机材料，例如包括树脂材料等。显示面板10的多层封装结构可以达到更好的封装效果，以防止水汽或氧气等杂质渗入显示面板10内部。
在一些实施例中，如图8B所示，显示面板10还包括位于衬底210上的缓冲层111，缓冲层111作为过渡层，可以防止衬底1中的有害物质侵入显示面板10的内部例如进入显示区域01A，又可以增加显示面板10中的膜层在衬底1上的附着力。例如，缓冲层111的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料形成的单层或多层结构。
例如，像素电路的存储电容Cst包括第一极板CE1和第二极板CE2，第一极板CE1与驱动晶体管T4的栅极电连接，第二极板CE2在衬底基板01上的正投影与第一极板CE1在衬底基板01上的正投影至少部分重叠。例如，在如图8B所示的实施例中，在对显示面板10进行测试前，第一信号线04与存储电容Cst的第一极板CE1同层设置，且测试引线05与存储电容Cst的第二极板CE2同层设置，以通过同一次构图工艺形成第一信号线04与第一极板CE1，且通过同一次构图工艺形成测试引线05与底部第二极板CE2，从而简化显示面板10的层结构以及制作工艺。
结合图8A-8B和图9A-9L可知，显示面10包括依次设置于衬底基板01 上的半导体层、第一导电层、第二导电层、第三导电层、第四导电层以及第五导电层。
例如，如图9A-9B所示，该半导体层包括第一到第五晶体管T1-T5(如图4A所示)的有源图案A1-A5。例如，对位标记M1/M2/M3/M4位于半导体层，与有源图案A1-A5同层设置，即与驱动晶体管T4的有源层。
例如，如图9D-9E所示，该第一导电层包括像素电路的每个晶体管的栅极以及第一信号线04以及第一极板CE1。例如，栅线G1n为扫描线，栅线G3n为第一复位控制线，栅线G2n为第二复位控制线，栅线EMn为发光控制线。
如图9F所示，该第二导电层包括像素电路的第二极板CE2和测试引线05(图9F仅示出了测试引线05的第二端部052)。第二导电层还包括第一复位信号线Vin1和第二复位信号线Vin2，即图4A中所示的第一复位信号线Vin1和第二复位信号线Vin2。
如图9H-9I所示，该第三导电层包括数据线D和第一电源线VDD线、以及多个连接结构P1-P8，该多个连接结构P1-P8配置为将图4B和图8A中的薄膜晶体管T1-5T的各个电极连接、薄膜晶体管T1-5T的各个电极与有源层连接、以及薄膜晶体管的电极与数据线或VDD线连接。
结合图9J-9L和图8B，该第四导电层包括辅助电极171。辅助电极171连接薄膜晶体管T4的漏极和阳极181。
图8C为沿图8A中的I-I’线和沿图7A中的A-A’线的另一种截面示意图。又例如，在另一个实施例中，如图8C所示，测试引线05位于第一信号线04的靠近衬底基板01的一侧，测试引线05与衬底基板01之间不设置任何导电层。在这种情况下，位于测试引线05与第一信号线04之间的层间绝缘层为第一栅绝缘层151。如此，在对显示面板10进行测试时，激光在预设位置穿过衬底基板01之后，通过控制激光的强度等参数，可使激光仅依次作用于测试引线05、层间绝缘层151和被测试的第一信号线04，而不会作用于其他任何导电层，从而防止对其他导电层造成影响。
例如，在如图8C所示的实施例中，第一信号线04与存储电容Cst的第一极板CE1同层设置，并且，显示面板10还包括遮光层110，遮光层110 位于第一信号线04的靠近衬底基板01的一侧，驱动晶体管T4的沟道区在衬底基板01上的正投影位于遮光层110在衬底基板01上的正投影之内，测试引线05与底部遮光层110同层设置，以通过同一次构图工艺形成测试引线05与底部遮光层110，从而简化显示面板10的层结构以及制作工艺。
例如，如图1和图5A所示，多条第一信号线04的第一测试焊盘PAD G1/PAD G2/PAD G4/PAD G4沿第二方向间隔排列，与多条第一信号线04一一对应的多个子引线0521/0522/0523/0524沿第二方向彼此间隔排列，且多个子引线0521/0522/0523/0524的第二测试焊盘PAD T1/PAD T2/PAD T3/PAD T4沿第二方向彼此间隔排列，以合理利用非显示区域01B的有限空间。
例如，至少部分第一信号线04的每条的第二部分包括第一横向部分，各个第一信号线的第二部分的第一横向部分例如为图5A和图7A所示的多条第一信号线G3n/G1n/G2n/EMn的第二部分G3n2/G1n2/G2n2/EMn2。第一横向部分G3n2/G1n2/G2n2/EMn2沿第一方向延伸且与对应的第一信号线G3n/G1n/G2n/EMn的第一部分连接，第一横向部分G3n2/G1n2/G2n2/EMn2的远离对应的第一信号线G3n/G1n/G2n/EMn的第一部分的端部分别包括第一测试盘PAD G1/PAD G2/PAD G4/PAD G4，多条第一信号线04的第一横向部分G3n2/G1n2/G2n2/EMn2沿第二方向排列，以充分利用非显示区域01B在第二方向上的尺寸。或者，再参考图9C，以多条第一信号线G3n/G1n/G2n/EMn的第二部分G3n2/G1n2/G2n2/EMn2分别包括第一横向部分TP1/TP2/TP3/TP4。
例如，在另一实施例中，如图9D所示，至少部分第一信号线04中的每条，以第一信号线G3n为例，第一信号线G3n的第二部分包括第一横向部分TP11、第一纵向部分VP1和第二横向部分TP21。第一横向部分TP11沿第一方向延伸且与第一部分连接，第一纵向部分VP1与第一横向部分TP11连接且沿第二方向延伸；第二横向部分TP21与第一纵向部分VP1连接且沿第一方向延伸，第二横向部分TP21的远离第一纵向部分VP1的端部包括第一测试盘PAD G1。类似地，其他的第一信号线也是如此。多条第一信号线G3n/G1n/G2n/EMn的第一横向部分沿第二方向排列，多条第一信号线G3n/G1n/G2n/EMn的第二横向部分也沿第二方向排列，显示面板的多条第一信号线 的第一测试盘非位于同一沿第二方向延伸的直线上。如此，可以将整个显示面板10的多条第一信号线的第一测试盘的位置错开，充分利用有限的空间设置更多的第一测试盘，从而设置尽量多个像素行，满足高PPI显示面板的需求。
图10为本公开至少一实施例提供的另一种显示面板的平面示意图。例如，非显示区域01B包括第一非显示区域01B-1、第二非显示区域01B-2和第三非显示区域01B-3，第一非显示区域01B-1和第二非显示区域01B-2分别位于显示区域在第一方向上的第一侧和第二侧，第三非显示区域01B-3位于显示区域在第二方向上的第一侧；衬底基板01包括靠近第一非显示区域01B-1且沿第二方向延伸的第一边缘011、靠近第二非显示区域01B-2且沿第二方向延伸的第二边缘012、以及靠近第三非显示区域01B-3且沿第一方向延伸的第三边缘013。例如，在图1所示的实施例中，多个像素行的第一信号线04均从显示区域01A延伸至第一非显示区域01B-1，多个像素行的第一信号线04在第一非显示区域01B-1与测试引线05连接，多个测试焊盘061位于第一非显示区域01B-1且沿衬底基板01的第三边缘013排列。或者，在其他实施例中，多个像素行的第一信号线04在第一非显示区域01B-1与测试引线05连接，多个测试焊盘061位于第一非显示区域01B-1且沿衬底基板01的第一边缘排列即沿第二方向排列；又或者，在其他实施例中，多个像素行的第一信号线04在第二非显示区域01B-2与测试引线05连接，多个测试焊盘061位于第二非显示区域01B-1且沿衬底基板01的第一边缘排列即沿第二方向排列。
又例如，多个像素行的第一信号线04中的第一部分第一信号线04从显示区域延伸至第一非显示区域01B-1，第一部分第一信号线04在第一非显示区域01B-1与测试引线05连接；多个像素行的第一信号线04中的第二部分第一信号线04从显示区域01A延伸至第二非显示区域01B-2，第二部分第一信号线04在第二非显示区域01B-2与测试引线05连接。多个测试焊盘06中的第一部分测试焊盘位于第一非显示区域01B-1，且沿衬底基板01的第一边缘011排列，多个测试焊盘06中的第二部分测试焊盘位于第二非显示区域01B-2，且沿衬底基板01的第二边缘012排列；或者，第一部分测试焊盘和 第二部分测试焊盘均位于第三非显示区域01B-3，且沿衬底基板01的第三边缘013排列。
例如，多个测试电路板06是柔性的，例如上述覆晶薄膜(COF)，可以弯折到显示面板10的背面。例如设置测试引线05的第一非显示区域01B-1和/或第二非显示区域01B-2也可以采用柔性电路板，是可以弯曲的或者弯折到显示面板10的背面，以减小显示面板的边框宽度。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的上述任意一种显示面板10。
本公开至少一实施例还提供一种本公开实施例提供的上述任意一种显示面板的测试方法，该测试方法包括：通过测试电路板06获取第一信号线04输出的测试信号以检测显示面板10的扫描驱动电路03是否正常工作。例如，将来自第一信号线04的测试信号输送给示波器，通过示波器的波形等判断显示面板10的接受来自第一信号线04的扫描信号的像素电路是否正常工作，从而判断扫描驱动电路03是否正常工作。
例如，参考图7A，该测试方法包括：在对多条第一信号线04中的每条进行测试时，采用激光照射预设位置的测试引线05、层间绝缘层和被测试的第一信号线04并使测试引线05、层间绝缘层和被测试的第一信号线04三者熔融且融合，以使融合后的测试引线05与第一信号线04在预设位置电连接，预设位置位于被测试的第一信号线04与对应的测试引线05在垂直于衬底基板01的方向上的重叠区域内。例如，预设位置位于被测试的第一信号线04的第二部分042的正投影与对应的子引线0521/0522/0523/0524的正投影的重叠区域内，即位于每条第一信号线04的第一测试焊盘与对应的第二测试焊盘的重叠区域内，第一测试焊盘与对应的第二测试焊盘在激光的作用下融合后彼此电连接。
例如，在对图8B所示的显示面板10进行测试时，激光从衬底基板01的远离第一信号线04和测试引线05的一侧入射至显示面板10的预设位置；激光依次到达衬底基板01、第一信号线04和测试引线05，由于第一信号线04与衬底基板01之间不设置任何导电层，因此，激光不穿过第一信号线04与衬底基板01之间的任何导电层。激光在预设位置穿过衬底基板01之后， 通过控制激光的强度等参数，可使激光仅依次作用于被测试的第一信号线04、层间绝缘层152和测试引线05，而不会作用于其他任何导电层，从而防止对其他导电层造成影响。
或者，又例如，在对图8C所示的显示面板10进行测试时，激光依次到达衬底基板01、测试引线05和第一信号线04，由于测试引线05与衬底基板01之间不设置任何导电层，因此，激光不穿过测试引线05与衬底基板01之间的任何导电层。激光在预设位置穿过衬底基板01之后，通过控制激光的强度等参数，可使激光仅依次作用于测试引线05、层间绝缘层151和被测试的第一信号线04，而不会作用于其他任何导电层，从而防止对其他导电层造成影响。
图10A-10B为本公开至少一实施例提供的显示面板进行检测的检测方法的示意图。例如，参考图10A，该测试方法还包括：依次获取多条第一信号线04输出的测试信号以依次对多条第一信号线04进行测试。在对多条第一信号线04中前一条第一信号线04测试完成之后，且对多条第一信号线04中下一条第一信号线04进行测试之前，将前一条第一信号线04切断以在前一条第一信号线04被切断的位置形成断口，断口位于非显示区域01B。以四条第一信号线G3n/G1n/G2n/EMn为例，依次获取第一信号线G3n、第一信号线G1n、第一信号线G2n和第一信号线EMn输出的测试信号，以依次对第一信号线G1n、第一信号线G2n和第一信号线EMn进行测试。已被测试完第一信号线G3n之后，在位置1将第一信号线G1n切断以在位置1形成断口OP1，已被测试完第一信号线G3n包括被断口OP1间隔开的非连接部分和连接部分，非连接部分与对应的测试引线05断开，连接部分与对应的测试引线05连接。例如，可采用激光将所述前一条第一信号线04切断。然后，采用对第一信号线G3n进行测试的相同的方法，对第一信号线G1n进行测试并在位置2将第一信号线G1n切断以在位置2形成断口OP2。同理，后续依次对第一信号线G2n和第一信号线EMn进行测试，在位置3和位置4分别形成断口OP3和断口OP4。如此，可完成对显示面板10的全部的第一信号线04的测试。
例如，多条已完成测试的第一信号线04的断口在与第一方向垂直的第二 方向上排列。非显示区域01B在第二方向上的空间充足，利于激光定位准确。
例如，位于显示区域01A在第一方向上的同一侧的多条第一信号线04的第二部分的多个断口不位于同一条沿第二方向延伸的直线上，或基本位于沿第二方向延伸的直线上以便于定位以及保持多条第一信号线的第二部分的一致性，从而保持多条第一信号线传输信号性能的一致性。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围根据权利要求书所界定的范围确定。

Claims (28)

  1. 一种显示面板，包括：
    衬底基板，包括显示区域和至少部分围绕所述显示区域的非显示区域；
    像素阵列，位于所述衬底基板上的所述显示区域，且包括沿所述第一方向延伸的多个像素行，其中，所述多个像素行的每个像素行包括第一信号线以及子像素，所述子像素包括像素电路，所述第一信号线配置为给其所在的所述像素行中的像素电路提供扫描信号；
    扫描驱动电路，配置为给所述像素电路提供所述扫描信号，且包括位于所述显示区的移位寄存器和时钟信号线；
    测试电路板，位于所述非显示区域，且包括测试焊盘；以及
    测试引线，位于所述非显示区域，与所述测试焊盘电连接，其中，所述第一信号线包括位于所述显示区域的第一部分和位于所述非显示区域且与所述第一部分连接的第二部分，所述第一部分整体上沿所述第一方向延伸，所述第二部分与所述第一部分连接；
    在对所述显示面板进行测试前，所述第一信号线与所述测试引线异层设置且彼此绝缘；在对所述显示面板进行测试时，所述测试引线与所述第一信号线的第二部分配置为彼此连接，所述测试电路板配置为通过所述测试焊盘和所述测试引线获取来自所述第一信号线的测试信号。
  2. 根据权利要求1所述的显示面板，其中，在对所述显示面板进行测试前，所述第一信号线的第二部分在所述衬底基板上的正投影与所述测试引线在所述衬底基板上的正投影至少部分重叠；
    在对所述显示面板进行测试时，所述第一信号线的第二部分在所述衬底基板上的正投影与所述测试引线在所述衬底基板上的正投影重叠的部分配置为彼此连接。
  3. 根据权利要求2所述的显示面板，其中，还包括：
    层间绝缘层，其中，在对所述显示面板进行测试前，所述层间绝缘层位于所述第一信号线与所述测试引线之间以使两者绝缘，并且，所述第一信号线、所述层间绝缘层和所述测试引线配置为可被激光在预设位置熔融以使所 述第一信号线和所述测试引线在所述预设位置处电连接，所述预设位置位于所述第一信号线在所述衬底基板上的正投影与所述测试引线在所述衬底基板上的正投影的重叠区域内。
  4. 根据权利要求3所述的显示面板，其中，在对所述显示面板进行测试前，
    所述测试引线位于所述第一信号线的远离所述衬底基板的一侧，所述第一信号线与所述衬底基板之间不设置任何导电层；或者，
    所述测试引线位于所述第一信号线的靠近所述衬底基板的一侧，所述测试引线与所述衬底基板之间不设置任何导电层。
  5. 根据权利要求1-4任一所述的显示面板，其中，所述第一信号线为栅线。
  6. 根据权利要求1-5任一所述的显示面板，其中，所述多个像素行中相邻的像素行之间具有间隙区域，所述移位寄存器和所述时钟信号线位于所述间隙区域内。
  7. 根据权利要求1-6任一所述的显示面板，其中，
    所述多个像素行中的每个像素行包括多条所述第一信号线，所述显示面板包括多个所述测试焊盘和多条所述测试引线，所述多个测试焊盘中的每个与所述多条测试引线中的至少一条测试引线在所述非显示区域电连接；
    在对所述显示面板进行测试前，所述多条测试引线的每条在所述衬底基板上的正投影与所述显示面板的至少一个所述像素行中的多条所述第一信号线的第二部分在所述衬底基板上的正投影至少部分重叠。
  8. 根据权利要求7所述的显示面板，其中，在对所述显示面板进行测试前，
    所述多条测试引线的每条在所述衬底基板上的正投影与所述多个像素行中的同一像素行的多条第一信号线的第二部分在所述衬底基板上的正投影至少部分重叠，或者，
    所述多条测试引线的每条在所述衬底基板上的正投影与所述多个像素行中的相邻的像素行的多条第一信号线的第二部分在所述衬底基板上的正投影至少部分重叠。
  9. 根据权利要求7或8所述的显示面板，其中，所述多条第一信号线中的每条和与其正投影重叠的所述测试引线之间不设置任何开关器件。
  10. 根据权利要求7-9任一所述的显示面板，其中，所述多条测试引线的每条包括：
    主体引线，包括与所述测试焊盘连接的第一端部和远离所述测试焊盘的第二端部，其中，所述第二端部沿第二方向延伸，所述第二方向与所述第一方向基本垂直；以及
    多个子引线，与所述主体引线的第二端部连接，突出于所述第二端部，且与所述多条第一信号线一一对应，其中，在对所述显示面板进行测试前，所述多个子引线的每个在所述衬底基板上的正投影与对应的所述第一信号线的第二部分在所述衬底基板上的正投影至少部分重叠。
  11. 根据权利要求10所述的显示面板，其中，在对所述显示面板进行测试前，
    所述多条第一信号线的每条的第二部分的靠近对应的所述子引线的端部具有第一测试盘，所述第一测试盘在该条第一信号线的线宽方向上的宽度大于该条第一信号线的线宽；
    所述多个子引线的每个的第一端与所述主体引线连接，所述多个子引线的每个的第二端具有第二测试盘，所述第二测试盘在该子引线的线宽方向的宽度大于该子引线的线宽；
    所述第二测试盘在所述衬底基板上的正投影与对应的所述第一信号线的第一测试盘在所述衬底基板上的正投影至少部分重叠。
  12. 根据权利要求11所述的显示面板，其中，
    所述多条第一信号线的第一测试焊盘沿所述第二方向间隔排列，与所述多条第一信号线一一对应的所述多个子引线沿所述第二方向彼此间隔排列，且所述多个子引线的第二测试焊盘沿所述第二方向彼此间隔排列。
  13. 根据权利要求11或12所述的显示面板，其中，所述第二部分包括：
    第一横向部分，沿所述第一方向延伸且与所述第一部分连接，其中，所述第一横向部分的远离所述第一部分的端部包括所述第一测试盘，所述多条第一信号线的第一横向部分沿所述第二方向排列。
  14. 根据权利要求11或12所述的显示面板，其中，所述第二部分包括：
    第一横向部分，沿所述第一方向延伸且与所述第一部分连接；以及
    第一纵向部分，与所述第一横向部分连接且沿所述第二方向延伸；以及
    第二横向部分，与所述第一纵向部分连接且沿所述第一方向延伸，
    其中，所述第二横向部分的远离所述第一纵向部分的端部包括所述第一测试盘，所述多条第一信号线的第一横向部分沿所述第二方向排列，所述多条第一信号线的第二横向部分沿所述第二方向排列，多条第一信号线的第一测试盘非位于同一沿第二方向延伸的直线上。
  15. 根据权利要求7-14任一所述的显示面板，其中，所述像素电路包括发光元件、驱动晶体管、数据写入晶体管和存储电容；所述数据写入晶体管配置为在所述扫描信号的控制下将所述数据信号传输至所述驱动晶体管，所述驱动晶体管配置为根据所述数据信号控制流经所述发光元件的驱动电流的大小；所述存储电容包括第一极板和第二极板，所述第一极板与所述驱动晶体管的栅极电连接，所述第二极板在所述衬底基板上的正投影与所述第一极板在所述衬底基板上的正投影至少部分重叠；
    在对所述显示面板进行测试前，所述第一信号线与所述存储电容的第一极板同层设置，且所述测试引线与所述存储电容的第二极板同层设置，或者，所述第一信号线与所述存储电容的第一极板同层设置，并且，所述显示面板还包括遮光层，所述遮光层位于所述第一信号线的靠近所述衬底基板的一侧，所述驱动晶体管的沟道区在所述衬底基板上的正投影位于所述遮光层在所述衬底基板上的正投影之内，所述测试引线与所述遮光层同层设置。
  16. 根据权利要求15所述的显示面板，还包括多个对位标记，其中，所述多个对位标记的图案彼此不同且与所述多条第一信号线一一对应设置，且分别与对应的所述第一信号线的所述重叠区域间隔开；在对所述显示面板进行测试时，所述多个对位标记配置为分别被对准装置识别以对对应的所述第一信号线的所述重叠区域内的所述预设位置进行定位；
    所述对位标记与所述驱动晶体管的有源层、所述第一信号线和所述测试引线中的任意一者同层设置。
  17. 根据权利要求1-16任一所述的显示面板，其中，所述测试电路板为 覆晶薄膜(COF)，所述多个测试焊盘在所述覆晶薄膜中间隔排列。
  18. 根据权利要求7-17任一所述的显示面板，其中，所述非显示区域包括第一非显示区域、第二非显示区域和第三非显示区域，所述第一非显示区域和所述第二非显示区域分别位于所述显示区域在所述第一方向上的第一侧和第二侧，所述第三非显示区域位于所述显示区域在所述第二方向上的第一侧；所述衬底基板包括靠近所述第一非显示区域且沿所述第二方向延伸的第一边缘、靠近所述第二非显示区域且沿所述第二方向延伸的第二边缘、以及靠近所述第三非显示区域且沿所述第一方向延伸的第三边缘；
    所述多个像素行的第一信号线均从所述显示区域延伸至所述第一非显示区域，所述多个像素行的第一信号线在所述第一非显示区域与所述测试引线连接；
    所述多个测试焊盘位于所述第三非显示区域且沿所述衬底基板的第三边缘排列，或者，所述多个测试焊盘位于所述第一非显示区域且沿所述衬底基板的第一边缘排列。
  19. 根据权利要求7-17任一所述的显示面板，其中，所述非显示区域包括第一非显示区域、第二非显示区域和第三非显示区域，所述第一非显示区域和所述第二非显示区域分别位于所述显示区域在所述第一方向上的第一侧和第二侧，所述第三非显示区域位于所述显示区域在所述第二方向上的第一侧；所述衬底基板包括靠近所述第一非显示区域且沿所述第二方向延伸的第一边缘、靠近所述第二非显示区域且沿所述第二方向延伸的第二边缘、以及靠近所述第三非显示区域且沿所述第一方向延伸的第三边缘；
    所述多个像素行的第一信号线中的第一部分第一信号线从所述显示区域延伸至所述第一非显示区域，所述第一部分第一信号线在所述第一非显示区域与所述测试引线连接；所述多个像素行的第一信号线中的第二部分第一信号线从所述显示区域延伸至所述第二非显示区域，所述第二部分第一信号线在所述第二非显示区域与所述测试引线连接；
    所述多个测试焊盘中的第一部分测试焊盘位于所述第一非显示区域，且沿所述衬底基板的第一边缘排列，所述多个测试焊盘中的第二部分测试焊盘位于所述第二非显示区域，且沿所述衬底基板的第二边缘排列，或者，
    所述第一部分测试焊盘和所述第二部分测试焊盘均位于所述第三非显示区域，且沿所述衬底基板的第三边缘排列。
  20. 一种显示面板，包括：
    衬底基板，包括显示区域和至少部分围绕所述显示区域的非显示区域；
    像素阵列，位于所述衬底基板上的所述显示区域，且包括沿所述第一方向延伸的多个像素行，其中，所述多个像素行的每个像素行包括第一信号线以及子像素，所述子像素包括像素电路，所述第一信号线配置为给其所在的所述像素行中的像素电路提供扫描信号；
    扫描驱动电路，配置为给所述像素电路提供所述扫描信号，且包括位于所述显示区的移位寄存器和时钟信号线；
    测试电路板，位于所述非显示区域，且包括测试焊盘；以及
    测试引线，位于所述非显示区域，与所述测试焊盘电连接，其中，所述第一信号线包括位于所述显示区域的第一部分和位于所述非显示区域且与所述第一部分连接的第二部分，所述第一部分整体上沿所述第一方向延伸，所述第二部分与所述第一部分连接；
    所述第一信号线与所述测试引线异层设置且彼此绝缘，所述第一信号线的第二部分在所述衬底基板上的正投影与所述测试引线在所述衬底基板上的正投影至少部分重叠。
  21. 一种显示装置，包括权利要求1-20任一所述的显示面板。
  22. 一种权利要求1-20任一所述的显示面板的测试方法，包括：
    通过所述测试电路板获取所述第一信号线输出的测试信号以检测所述扫描驱动电路是否正常工作。
  23. 根据权利要求22所述的测试方法，其中，在所述多个像素行中的每个像素行包括多条所述第一信号线，所述显示面板包括多个所述测试焊盘和多条所述测试引线，所述多个测试焊盘中的每个与所述多条测试引线中的至少一条测试引线在所述非显示区域电连接，且在对所述显示面板进行测试前，所述第一信号线与所述测试引线异层设置且通过层间绝缘层彼此绝缘，所述第一信号线的第二部分在所述衬底基板上的正投影与所述测试引线在所述衬底基板上的正投影至少部分重叠的情况下，
    所述测试方法还包括：
    在对所述多条第一信号线中的每条进行测试时，采用激光照射预设位置的所述测试引线、所述层间绝缘层和被测试的所述第一信号线并使所述测试引线、所述层间绝缘层和被测试的所述第一信号线三者熔融且融合，以使融合后的所述测试引线与所述第一信号线在所述预设位置电连接，所述预设位置位于被测试的所述第一信号线与对应的所述测试引线在垂直于衬底基板的方向上的重叠区域内。
  24. 根据权利要求23所述的测试方法，其中，在所述多条测试引线的每条包括主体引线和多个子引线，所述主体引线包括与所述测试焊盘连接的第一端部和远离所述测试焊盘的第二端部，所述多个子引线与所述主体引线的第二端部连接，突出于所述第二端部，且与所述多条第一信号线一一对应，其中，在对所述显示面板进行测试前，所述多个子引线的每个在所述衬底基板上的正投影与对应的所述第一信号线的第二部分在所述衬底基板上的正投影至少部分重叠的情况下，
    所述预设位置位于被测试的所述第一信号线的第二部分的正投影与对应的所述子引线的正投影的重叠区域内。
  25. 根据权利要求24所述的测试方法，其中，所述激光从所述衬底基板的远离所述第一信号线和所述测试引线的一侧入射至所述显示面板的预设位置；
    所述激光依次到达所述衬底基板、所述第一信号线和所述测试引线且不穿过所述第一信号线与所述衬底基板之间的任何导电层；
    或者，所述激光依次到达所述衬底基板、所述测试引线和所述第一信号线且不穿过所述测试引线与所述衬底基板之间的任何导电层。
  26. 根据权利要求22-25任一所述的测试方法，包括：
    依次获取所述多条第一信号线输出的测试信号以依次对所述多条第一信号线进行测试，其中，
    在对所述多条第一信号线中前一条第一信号线测试完成之后，且对所述多条第一信号线中下一条第一信号线进行测试之前，将所述前一条第一信号线切断以在所述前一条第一信号线被切断的位置形成断口，所述断口位于所 述非显示区域；
    所述已完成测试的第一信号线包括被所述断口间隔开的非连接部分和连接部分，所述非连接部分与对应的所述测试引线断开，所述连接部分与对应的所述测试引线连接。
  27. 根据权利要求26所述的测试方法，其中，采用激光将所述前一条第一信号线切断。
  28. 根据权利要求26或27所述的测试方法，其中，多条已完成测试的所述第一信号线的断口在与所述第一方向垂直的第二方向上排列。
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