WO2023048074A1 - 力率改善回路 - Google Patents

力率改善回路 Download PDF

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Publication number
WO2023048074A1
WO2023048074A1 PCT/JP2022/034684 JP2022034684W WO2023048074A1 WO 2023048074 A1 WO2023048074 A1 WO 2023048074A1 JP 2022034684 W JP2022034684 W JP 2022034684W WO 2023048074 A1 WO2023048074 A1 WO 2023048074A1
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WIPO (PCT)
Prior art keywords
control switch
switch
reactor
power factor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/034684
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English (en)
French (fr)
Japanese (ja)
Inventor
明輝 千葉
啓太 石倉
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GS Yuasa International Ltd
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GS Yuasa International Ltd
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Application filed by GS Yuasa International Ltd filed Critical GS Yuasa International Ltd
Priority to US18/694,377 priority Critical patent/US12587092B2/en
Priority to DE112022004498.5T priority patent/DE112022004498T5/de
Priority to JP2023549519A priority patent/JPWO2023048074A1/ja
Priority to CN202280075586.0A priority patent/CN118414776A/zh
Publication of WO2023048074A1 publication Critical patent/WO2023048074A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4266—Arrangements for improving power factor of AC input using passive elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a power factor correction circuit.
  • the choke coil current flowing through the output choke coil flows in both the positive direction and the negative direction within one switching cycle when the output current is equal to or less than the rated value. It is set to a flowing predetermined value. Therefore, the parasitic capacitance of the main switching element can be extracted by turning off the rectifying element while the current of the output choke coil is in the negative direction.
  • Patent Document 1 no consideration is given to the power factor improvement operation of inputting alternating current to improve the power factor, and the amount of reverse excitation is not adjusted during control.
  • FIG. 14 shows a circuit configuration example of the power factor correction circuit of Patent Document 2. As shown in FIG.
  • Patent Document 2 Especially in Patent Document 2, from the following Formula 1 (Formula 7 of Patent Document 2),
  • Equation 2 Equation 9 of Patent Document 2.
  • Equation 2 Since the input voltage Vin is the instantaneous value of the AC input voltage, providing the reverse current Ir of Equation 2 means that at least the instantaneous value of the AC input voltage is always at least the following Equation 3 (see Patent Document 2: Zero voltage switching is possible at any voltage where the input voltage Vin is lower than the output voltage Vo, if the current is reversed by more than the fixed value given by equation 10).
  • JP 2016-220342 A Japanese Patent Application Laid-Open No. 2021-052578
  • the power factor correction circuit of Patent Document 2 is called a critical system. With the power factor correction circuit constants of FIG. 14, the maximum value of the switching frequency with respect to the AC phase angle is about 3.5 times the minimum value as shown in FIG. This is a switching frequency characteristic that is not much different from that of the conventional critical power factor correction circuit, and the switching loss cannot be reduced, and the circulation loss due to charging and discharging of the switch parasitic capacitance cannot be reduced much.
  • One aspect of the present invention provides a power factor correction circuit capable of zero voltage switching of the control switch regardless of the instantaneous value of the input voltage and the value of the output voltage.
  • a power factor correction circuit includes a rectifier circuit that rectifies an input voltage of an AC power supply, and a reactor and a control switch that are connected in series to both ends of the rectifier circuit.
  • a first series circuit a second series circuit in which a synchronous rectification switch and an output capacitor are connected in series to two main terminals of the control switch; a control circuit for alternately turning on and off the control switch and the synchronous rectification switch and controlling the ON time of the control switch so that the peak value of the current flowing through the control switch is proportional to the input voltage; and turning on and off the control switch and the synchronous rectification switch so as to adjust a reverse excitation amount for reversely exciting the reactor by causing the current flowing through the reactor to reversely flow from the output voltage side to the input voltage side, and the reverse excitation amount is
  • the input voltage is adjusted to a second predetermined value regardless of the input voltage.
  • adjustment may be approaching a command value (for example, a fixed value or a calculated value) or approaching a value according to a measured value such as output voltage.
  • FIG. 1 is a circuit configuration diagram of a power factor correction circuit according to the first embodiment.
  • FIG. 3 is a diagram showing an AC input current, a switching reactor current, and a switching reactor current peak value envelope of the power factor correction circuit according to the first embodiment.
  • FIG. 5 is a circuit configuration diagram of a power factor correction circuit according to a modification of the first embodiment.
  • FIG. 1 is a circuit configuration diagram of a power factor correction circuit according to the first embodiment.
  • FIG. 3 is a diagram showing an AC input current, a switching reactor current,
  • FIG. 6 is a diagram showing the relationship between the AC phase angle and the switching frequency of the power factor correction circuit according to the modified example of the first embodiment.
  • FIG. 7 is a diagram showing an AC input current of a power factor correction circuit according to a modification of the first embodiment and a switching reactor current peak value envelope.
  • FIG. 8 is a circuit configuration diagram of a power factor correction circuit according to the second embodiment.
  • 9 is a circuit configuration diagram illustrating the control switch, the parasitic capacitance of the synchronous rectification switch, and the external capacitor of the power factor correction circuit shown in FIG. 10 is a diagram showing a control switch, a synchronous rectification switch, and a polarity changeover switch when the AC input voltage is a positive voltage in the power factor correction circuit shown in FIG. 8.
  • FIG. 8 is a diagram showing the relationship between the AC phase angle and the switching frequency of the power factor correction circuit according to the modified example of the first embodiment.
  • FIG. 7 is a diagram showing an AC input current of a power factor correction circuit according to
  • FIG. 11 is a diagram showing the control switch, the synchronous rectification switch, and the polarity changeover switch when the AC input voltage is a negative voltage in the power factor correction circuit shown in FIG. 8.
  • FIG. FIG. 12 is a circuit configuration diagram of a power factor correction circuit according to the third embodiment.
  • FIG. 13 is a circuit configuration diagram of a power factor correction circuit according to the fourth embodiment.
  • FIG. 14 is a circuit configuration diagram of a conventional power factor correction circuit described in Patent Document 2.
  • FIG. 15 is a diagram showing the relationship between the AC phase angle and the switching frequency of the conventional power factor correction circuit shown in FIG.
  • FIG. 16 is a diagram showing the relationship between the input voltage Vin and the input current Iin of the conventional power factor correction circuit shown in FIG. 14, and the input current discontinuous region.
  • the power factor correction circuit according to the embodiment enables zero voltage switching when the control switch is off at all phase angles of the AC voltage, and enables power factor correction with less distortion.
  • the power factor correction circuit keeps the ON time of the control switch constant even if the load fluctuates by adjusting the amount of reverse excitation, thereby enabling power factor improvement with less distortion. Since the critical type power factor correction circuit according to the embodiment causes the current to flow back to the reactor to perform resonant operation (soft switching), switching loss can be suppressed to a small value even when existing relatively inexpensive FETs are used. When relatively expensive modern or next generation switching devices are used in this critical power factor correction circuit, high efficiency can be maintained without compromising device features.
  • FIG. 1 is a circuit configuration diagram of a power factor correction circuit according to the first embodiment.
  • the power factor correction circuit includes an AC power supply 1 , a full-wave rectifier circuit 2 that performs full-wave rectification of the input voltage of the AC power supply 1 , and an input capacitor C2 connected across the full-wave rectifier circuit 2 .
  • a reactor L and a control switch Q1 consisting of a MOSFET (metal-oxide-semiconductor field-effect transistor) are connected in series to both ends of the full-wave rectifier circuit 2 .
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • a synchronous rectification switch Q2 and an output capacitor C1 are connected in series to the drain terminal and source terminal of the control switch Q1.
  • An output voltage Vo is output from both ends of the output capacitor C1.
  • the control circuit 10 includes an error amplifier 11 , comparators 12 and 17 , RS flip-flop circuits 14 and 18 and a calculator 15 .
  • the error amplifier 11 amplifies the error voltage between the output voltage Vo and the reference voltage Vref and outputs it to the inverting input terminal of the comparator 12 .
  • a current sensor 13 detects a drain current flowing through the control switch Q1.
  • the comparator 12 outputs a low level to the reset terminal R of the RS flip-flop circuit 14 when the error voltage from the error amplifier 11 is equal to or higher than the voltage based on the current detected by the current sensor 13 .
  • the control switch Q1 since a high level is output from the output terminal Q of the RS flip-flop circuit 14, the control switch Q1 is turned on. Since a low level is output from the inverted output terminal of the RS flip-flop circuit 14 to the set terminal S of the RS flip-flop circuit 18, the synchronous rectification switch Q2 is turned off.
  • the comparator 12 outputs a high level to the reset terminal R of the RS flip-flop circuit 14 when the error voltage from the error amplifier 11 is less than the voltage based on the current detected by the current sensor 13 .
  • the control switch Q1 since a low level is output from the output terminal Q of the RS flip-flop circuit 14, the control switch Q1 is turned off. Since a high level is output from the inverted output terminal of the RS flip-flop circuit 14 to the set terminal S of the RS flip-flop circuit 18, the synchronous rectification switch Q2 is turned on.
  • the control switch Q1 and the synchronous rectification switch Q2 it is possible to control the output voltage Vo of the output capacitor C1 to the first predetermined value.
  • the control circuit 10 also controls the ON time of the control switch Q1 so that the peak value of the current flowing through the control switch Q1 is proportional to the input voltage Vin. Therefore, the computing unit 15 operationally amplifies the output voltage Vo, and outputs the operationally amplified output voltage Vo from the inverted output terminal of the RS flip-flop circuit 18 to the set terminal S of the RS flip-flop circuit 14 via the comparator 17.
  • the control switch Q1 is turned on.
  • control circuit 10 controls the control switch Q1 and the synchronous rectification switch Q2 so that the current flowing through the reactor L is reversed from the output voltage Vo side to the input voltage Vin side to adjust the amount of reverse excitation that reversely excites the reactor L. turn off.
  • the synchronous rectification switch Q2 immediately after the excitation energy of the reactor L is released by turning on the synchronous rectification switch Q2, the synchronous rectification switch Q2 continues to be turned on to cause current to flow back from the output capacitor C1 to the input voltage Vin side.
  • the amount of backflow current is determined using at least the output voltage Vo and the inductance value L of the reactor L, the coefficient of the parasitic capacitance value C of the control switch Q1 for boosting.
  • the reactor L stores enough energy to absorb the charge charged in the parasitic capacitance C of the control switch Q1 for boosting.
  • the computing unit 15 operationally amplifies the output voltage Vo and outputs the operationally amplified output voltage Vo to the inverting input terminal of the comparator 17 .
  • the calculator 15 obtains a command value (second predetermined value) of the backflow current Ir regardless of the input voltage Vi as shown in Equation 6 by operationally amplifying the output voltage Vo.
  • ⁇ represents the first term, which is a real number with a magnitude of 1 or more. Since the output voltage Vo is a DC voltage, it takes a constant value (first predetermined value). Therefore, the calculation by Equation 6 has a smaller calculation load than the case where the input voltage Vin whose instantaneous value changes is used for the calculation of the backflow current Ir.
  • the current sensor 16 corresponds to a reverse-excitation current detection unit, and detects the reverse-excitation current that flows when the reactor L is reverse-excited.
  • Comparator 17 corresponds to a zero-voltage switching determination section, and determines that zero-voltage switching of control switch Q1 is possible when the value of reverse excitation current detected by current sensor 16 is equal to or greater than the output from calculator 15.
  • a high level is output to the reset terminal R of the RS flip-flop circuit 18 .
  • the low level of the synchronous rectification switch Q2 is output from the output terminal Q of the RS flip-flop circuit 18, the synchronous rectification switch Q2 is turned off, and the reverse current stops.
  • control switch Q1 and the synchronous rectification switch Q2 are controlled to turn on and off complementarily with a dead time.
  • the backflow current Ir is obtained by multiplying the proportional constant by the instantaneous value of the input voltage Vin.
  • Equation 6 the direct current output voltage Vo (or a higher value Vo ⁇ ) is multiplied by the proportionality constant (Equation 3) to obtain the reverse current Ir. Make it a fixed value.
  • FIG. 3 is a diagram showing an AC input current, a switching reactor current, and a switching reactor current peak value envelope.
  • the peak value (negative peak value) of the switching reactor current at the time of reverse flow, that is, the current envelope on the lower side in FIG. 3 is straight or nearly straight. This means that the reverse excitation amount is adjusted to the second predetermined value regardless of the input voltage.
  • the switching frequency can be lowered by increasing the ON time tonQ2.
  • the parasitic capacitor or the external capacitor C can reach the output voltage Vo during the dead time period before the synchronous rectification switch Q2 turns on later. Therefore, when the synchronous rectification switch Q2 is turned on, reactor excitation energy can be sent to the output side, that is, energy can be sent from the input side to the output side, thereby improving the discontinuity of the input current Iin and improving the power factor. , harmonic distortion can also be reduced.
  • the power factor correction circuit according to the modification shown in FIG. Since other configurations of the power factor correction circuit according to the modification are the same as those of the power factor correction circuit according to the first embodiment, detailed description thereof will be omitted.
  • the backflow current Ir can be set as shown in the following equation 7.
  • the second term ⁇ is a three-fold harmonic component of the AC input voltage Vin alternating with the angular frequency ⁇ .
  • the switching frequency is input as shown in FIG. It becomes a flat shape that is controlled with respect to the phase angle, and by lowering the switching frequency, it is possible to reduce the switching loss. Also, since it does not have various frequencies, it is possible to prevent actual damage such as specific frequency interference to other circuits.
  • FIG. 7 shows the switching current envelope and the input current of the power factor correction circuit according to the modified example of the first embodiment.
  • the backflow current Ir is added with a harmonic that is three times the AC input.
  • a waveform that is adjusted to a second predetermined value appears by adding a harmonic that is three times the AC input to the lower current envelope in FIG.
  • the second term ⁇ may include not only harmonic components that are three times the AC input voltage Vin, but also odd-numbered high-order harmonic components such as five times and seven times the AC input voltage Vin. Since the second term ⁇ includes not only harmonic components of 3 times the AC input voltage Vin, but also higher harmonic components of odd numbers such as 5 times and 7 times the AC input voltage Vin, the switching shown in FIG. The switching loss can be further reduced by making the frequency flatter with respect to the input phase angle and further lowering the switching frequency.
  • the power factor correction circuit of the second embodiment is a totem pole bridgeless power factor correction circuit, and includes an AC power supply, a reactor L, current sensors 13a and 16a, switches Q1-Q4, an output capacitor Co, and a control circuit 10a. Since the full-wave rectifier circuit 2 (see FIGS. 1 and 5) is not used, no loss occurs due to the full-wave rectifier circuit. That is, there is provided a bridgeless critical power factor correction circuit capable of zero voltage switching at all phase angles of AC voltage (all ranges).
  • the switching reactor current peak value envelope in this power factor improvement circuit shows a waveform like an alternating current in which the envelope shown in FIG. .
  • the current sensor 13a is connected in series with the reactor L and detects the current flowing through the reactor L.
  • the switch Q1 and the switch Q2 are connected in series, and one end of the reactor L is connected to the connection end of the switch Q1 and the switch Q2.
  • a series circuit of switches Q3 and Q4 is connected to both ends of the series circuit of switches Q1 and Q2.
  • Both ends of the output capacitor Co are connected to both ends of the series circuit of the switch Q3 and the switch Q4, and the output voltage Vo is obtained from the output capacitor Co.
  • the switch Q1 and the switch Q2 provide a dead time to complementarily turn on and off, and the switch Q3 and the switch Q4 provide a dead time to complementarily switch the polarity.
  • the control circuit 10a includes an error amplifier 11, comparators 12 and 17, RS flip-flop circuits 14a and 18a, a computing unit 15, a polarity discrimination section 19, and polarity switching sections 20-22.
  • the output terminal Q of the RS flip-flop circuit 14 a is connected to one input terminal of the polarity switching section 21 , and the output terminal Q of the RS flip-flop circuit 18 a is connected to the other input terminal of the polarity switching section 21 .
  • the polarity determination unit 19 determines the positive or negative polarity of the input voltage Vin, and outputs the positive or negative polarity to the polarity switching units 20-22.
  • the polarity switching unit 21 switches Q1 to a control switch and Q2 to a synchronous rectification switch.
  • the control switch Q1 is turned on and off by the output from the output terminal Q of the RS flip-flop circuit 14a.
  • the synchronous rectification switch Q2 is turned on and off by the output from the output terminal Q of the RS flip-flop circuit 18a.
  • the polarity switching section 21 switches Q1 to a synchronous rectification switch and Q2 to a control switch.
  • the synchronous rectification switch Q1 is turned on and off by the output from the output terminal Q of the RS flip-flop circuit 14a.
  • the control switch Q2 is turned on and off by the output from the output terminal Q of the RS flip-flop circuit 18a.
  • the polarity switching section 22 switches on the polarity switching switch Q3 and switches off the polarity switching switch Q4.
  • the polarity switching section 22 switches off the polarity switching switch Q3 and switches on the polarity switching switch Q4.
  • FIG. 9 shows the parasitic capacitances (capacitors indicated by dotted lines) of the switches Q1-Q4 and the external capacitors C1-C4 of the power factor correction circuit shown in FIG.
  • the charge of the capacitor C4 is extracted through the first path of C4 ⁇ Q2 ⁇ L ⁇ Vin ⁇ C4. Also, the electric charge of the capacitor C is extracted through the second path of C->L->Vin->Q3->C. Further, a third route of Co ⁇ Q2 ⁇ L ⁇ Vin ⁇ Q3 ⁇ Co is reverse-excited to compensate for the insufficient reverse excitation by the capacitors C and C4.
  • Q1 operates as a synchronous rectification switch
  • Q2 operates as a control switch
  • the polarity changeover switch Q3 is turned off
  • the polarity changeover switch Q4 is turned off. turn on.
  • the charge of the capacitor C3 is extracted through the first path of C3 ⁇ vIN ⁇ L ⁇ Q1 ⁇ C3. Also, the electric charge of the capacitor C is extracted through the second path of C->Q4->Vin->L->C. Further, a third route of Co->Q4->Vin->L->Q1->Co is reverse-excited to compensate for the insufficient reverse-excitation by the capacitors C and C3.
  • the power factor correction circuit according to the second embodiment it is possible to obtain high efficiency by high power factor and zero voltage switching with the same control as the power factor correction circuit according to the first embodiment.
  • the current sensor 16 is provided to detect the reverse excitation current that flows when the reactor L is reversely excited.
  • the power factor correction circuit according to the third embodiment shown in FIG. 12 eliminates the current sensor 16 shown in FIG.
  • the on-time of the control switch Q1 is calculated by digitally adding a fixed value determined using the parasitic capacitance value C to realize zero voltage switching.
  • a reactor L In the power factor correction circuit shown in FIG. 12, a reactor L, a current sensor 13a, and a control switch Q1 consisting of a MOSFET are connected in series across the input voltage Vin.
  • a synchronous rectification switch Q2 and an output capacitor C0 are connected in series to the drain and source terminals of the control switch Q1.
  • a series circuit of resistors R1 and R2 is connected across the output capacitor C0.
  • An output voltage Vo is output from both ends of the output capacitor C0.
  • the control circuit 10 b includes a tonQ1 calculator 31 , a tonQ2 calculator 32 , a multiplier 33 , an adder 34 , a sawtooth wave generation circuit 35 , a comparator 36 and an inverter 37 .
  • the current sensor 13a is connected in series with the reactor L and detects the input current Iin flowing through the reactor L.
  • the on-time tonQ1 of the control switch Q1 is expressed by Equation 10.
  • the tonQ1 calculator 31 calculates the on-time tonQ1 of the control switch Q1 by Equation (10).
  • the first ON time of the control switch Q1 of the conventional critical PFC corresponds to the first term of Equation 10.
  • the second term in Equation 10 is the second ON time determined using the reactor L, the parasitic capacitance C of the control switch Q1, the input voltage Vin, and the output voltage Vo, and represents the amount of reverse excitation shown in Equation 6.
  • the on-time tonQ1 of the switch Q1 of the present invention is obtained by using the inductance value of the reactor L, the parasitic capacitance value C of the control switch Q1, and the output voltage Vo in the first on-time of the control switch Q1 of the conventional critical type PFC. This is the time obtained by adding the determined second ON time.
  • the tonQ1 calculator 31 calculates the first ON time of the control switch Q1 based on the input current Iin and the input voltage Vin detected by the current sensor 13a and the reactance value of the reactor L, and A second on-time determined using the inductance value of L, the parasitic capacitance value C of the control switch Q1, the input voltage Vin, and the output voltage Vo is added to obtain the on-time tonQ1 of the control switch Q1.
  • the reactance value of the reactor L the reactance value of the reactor L, the parasitic capacitance value C of the control switch Q1, the input voltage Vin, and the output voltage Vo are used.
  • the determined predetermined value it is possible to obtain the on-time tonQ1 of the control switch Q1 in consideration of the amount of reverse excitation.
  • the tonQ2 calculator 32 calculates the difference voltage (Vo-Vp) between the input voltage Vin (Vp) and the output voltage Vo, and obtains the division value by dividing the input voltage Vp by the difference voltage (Vo-Vp).
  • the on-time tonQ2 of the switch Q2 is related to the voltage-time product of the reactor L, so the multiplier 33 multiplies the on-time tonQ1 of the control switch Q1 by the division value obtained by the tonQ2 calculator 32 . In other words, the multiplier 33 calculates the on-time tonQ2 of the switch Q2 by Equation (11).
  • the adder 34 obtains the time T by adding the on-time tonQ2 of the switch Q2 from the multiplier 33 to the on-time tonQ1 of the control switch Q1.
  • the time T determines the switching period T.
  • the sawtooth wave generation circuit 35 generates a sawtooth wave signal whose peak value is T based on the time T from the adder 34 .
  • the comparator 36 has an inverting input terminal to which the sawtooth wave signal from the sawtooth wave generating circuit 35 is input, and a non-inverting input terminal to which the on-time tonQ1 of the control switch Q1 is input from the tonQ1 calculator 31 .
  • the comparator 36 applies a high level signal to the gate of the control switch Q1 when the ON time tonQ1 of the control switch Q1 from the tonQ1 calculator 31 is greater than or equal to the value of the sawtooth wave signal from the sawtooth wave generation circuit 35. Turn on the control switch Q1.
  • the comparator 36 inverts the high level signal by the inverter 37 to make it low. A level signal is applied to the gate of switch Q2 to turn switch Q2 off.
  • the comparator 36 applies a low level signal to the gate of the control switch Q1 when the ON time tonQ1 of the control switch Q1 from the tonQ1 calculator 31 is less than the value of the sawtooth wave signal from the sawtooth wave generation circuit 35.
  • the control switch Q1 is turned off.
  • the comparator 36 inverts the low-level signal by the inverter 37 when the on-time tonQ1 of the control switch Q1 from the tonQ1 calculator 31 is less than the value of the sawtooth wave signal from the sawtooth wave generation circuit 35 to make it high.
  • a level signal is applied to the gate of switch Q2 to turn switch Q2 on.
  • the switches Q1 and Q2 are controlled so as to be complementarily turned on and off by the operation of the sawtooth wave generating circuit 35 and the comparator 36 with a dead time.
  • the current sensor 16 is eliminated, and a predetermined value determined using the reactor L and the parasitic capacitance value C is used during the ON time of the conventional critical type PFC. By digitally adding the values, it is possible to calculate the ON time of the switch Q1 and realize zero voltage switching.
  • the power factor correction circuit according to the fourth embodiment shown in FIG. 13 eliminates the current sensor 16a shown in FIG. is digitally controlled to calculate the ON time of the control switch Q1, thereby realizing zero voltage switching.
  • the control circuit 10c includes a full-wave rectifier circuit 2, a polarity discriminator 19, a polarity switcher 20-22, a tonQ1 calculator 31a, a tonQ2 calculator 32, a multiplier 33, an adder 34, a sawtooth wave generation circuit 35, a comparator 36a, It has an inverter 37a.
  • the full-wave rectifying circuit 2, the polarity discriminating section 19, and the polarity switching sections 20-22 have already been described with reference to FIG.
  • the tonQ1 calculator 31a calculates the first ON time of the control switch Q1 based on the input current Iin detected by the current sensor 13a, the input voltage Vin from the full-wave rectifier circuit 2, and the reactance value of the reactor L. A second on-time determined using the inductance value of the reactor L, the parasitic capacitance value C of the control switch Q1, the input voltage Vin, and the output voltage Vo is added to the on-time to obtain the on-time tonQ1 of the control switch Q1.
  • the comparator 36 a outputs a comparator output to the polarity switching section 21 .
  • the inverter 37 a outputs an inverter output to the polarity switching section 21 .
  • the tonQ1 calculator 31a, the tonQ2 calculator 32, the multiplier 33, the adder 34, the sawtooth wave generation circuit 35, the comparator 36a, and the inverter 37a are Since it is provided, an effect similar to that of the power factor correction circuit according to the third embodiment can be obtained.

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  • Engineering & Computer Science (AREA)
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PCT/JP2022/034684 2021-09-22 2022-09-16 力率改善回路 Ceased WO2023048074A1 (ja)

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US18/694,377 US12587092B2 (en) 2021-09-22 2022-09-16 Power factor correction circuit
DE112022004498.5T DE112022004498T5 (de) 2021-09-22 2022-09-16 Leistungsfaktorkorrekturschaltung
JP2023549519A JPWO2023048074A1 (https=) 2021-09-22 2022-09-16
CN202280075586.0A CN118414776A (zh) 2021-09-22 2022-09-16 功率因数改善电路

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