WO2023042450A1 - 半導体装置の製造方法、半導体装置、及び半導体装置用の配線基板 - Google Patents

半導体装置の製造方法、半導体装置、及び半導体装置用の配線基板 Download PDF

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Publication number
WO2023042450A1
WO2023042450A1 PCT/JP2022/013330 JP2022013330W WO2023042450A1 WO 2023042450 A1 WO2023042450 A1 WO 2023042450A1 JP 2022013330 W JP2022013330 W JP 2022013330W WO 2023042450 A1 WO2023042450 A1 WO 2023042450A1
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Prior art keywords
semiconductor
wiring board
semiconductor device
semiconductor chip
chip
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Ceased
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PCT/JP2022/013330
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English (en)
French (fr)
Japanese (ja)
Inventor
大祐 茅野
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Priority to JP2023548112A priority Critical patent/JP7834422B2/ja
Publication of WO2023042450A1 publication Critical patent/WO2023042450A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment

Definitions

  • the present technology (technology according to the present disclosure) relates to a method for manufacturing a semiconductor device, a semiconductor device, and a wiring board for a semiconductor device.
  • the present invention relates to a technique effectively applied to a wiring board for a semiconductor device.
  • a semiconductor chip is formed by singulating a plurality of chip regions set on a semiconductor wafer into individual pieces in the manufacturing process of a semiconductor device.
  • a semiconductor wafer that has been irradiated with a dicing laser is mounted on a dicing tape via an adhesive layer, and then the dicing tape is stretched from the outer circumference. This tension separates the chip regions from each other, resulting in a plurality of singulated semiconductor chips. Then, the separated semiconductor chips are picked up from the dicing tape. The individualized semiconductor chips are then assembled into packages.
  • JP-A-2007-250598 Japanese Patent Application Laid-Open No. 2021-27099 JP 2019-195978 A
  • the process will increase accordingly.
  • the silicon of the semiconductor chip may be exposed.
  • the purpose of this technology is to suppress the occurrence of exposed portions on the surface of the semiconductor chip.
  • a method for manufacturing a semiconductor device includes a semiconductor wafer provided with a plurality of chip regions, which are regions in which constituent elements of a semiconductor chip are formed, and a base material made of an elastic material.
  • the semiconductor wafer is cut so as not to divide the wiring board aggregate, the chip regions are separated into semiconductor chips, and the wiring board aggregate is horizontally extended to form the semiconductor chips. and covering the semiconductor chips with a resin sealing body while maintaining the widened spacing between the semiconductor chips, the resin sealing body and the wiring between the semiconductor chips It includes cutting the substrate assembly to individualize the semiconductor device.
  • a semiconductor device includes a semiconductor chip and a base material made of a stretchable material having an expansion ratio of 200% or more and an elastic modulus of 100 MPa or less, and from one surface of the base material to the other surface.
  • a wiring board having a plurality of electrically connected wirings and superimposed and joined to the bottom surface of the semiconductor chip, and a resin sealing body covering the semiconductor chip.
  • a wiring substrate for a semiconductor device is a substrate that is superimposed and bonded to the bottom surface of a semiconductor chip, and has a base material made of an elastic material having an elastic modulus of 200% or more and an elastic modulus of 100 MPa or less. and a plurality of wirings electrically connected from one surface of the base material to the other surface thereof.
  • FIG. 1 is a plan view schematically showing a semiconductor device according to a first embodiment of the present technology
  • FIG. 1B is a cross-sectional view schematically showing a cross-sectional structure taken along the line AA of FIG. 1A
  • It is a figure which shows the planar structure of a semiconductor wafer.
  • 2B is a diagram showing the configuration of a chip area by enlarging the C area of FIG. 2A
  • FIG. 2 is a diagram showing a configuration of a wiring board area by enlarging a part of the wiring board assembly
  • It is a schematic process sectional view showing a manufacturing method of a semiconductor device concerning a 1st embodiment of this art.
  • FIG. 3B is a schematic process cross-sectional view following FIG.
  • FIG. 3A is a schematic process cross-sectional view following FIG. 3B;
  • FIG. 3C is a schematic process cross-sectional view following FIG. 3C;
  • FIG. 3D is a schematic process cross-sectional view following FIG. 3D;
  • FIG. 3D is a schematic process cross-sectional view following FIG. 3E;
  • FIG. 3F is a schematic process cross-sectional view following FIG. 3F;
  • FIG. 10 is a cross-sectional view schematically showing a schematic configuration of a semiconductor device according to Modification 1-1 of the first embodiment of the present technology; It is a cross-sectional view schematically showing a schematic configuration of a semiconductor device according to Modification 1-2 of the first embodiment of the present technology.
  • FIG. 10 is a plan view schematically showing a schematic configuration of a semiconductor chip included in a semiconductor device according to a second embodiment of the present technology; It is a typical process sectional view showing a manufacturing method of a semiconductor device concerning a 2nd embodiment of this art.
  • FIG. 8B is a schematic process cross-sectional view following FIG. 8A;
  • FIG. 8B is a schematic process cross-sectional view following FIG. 8B;
  • FIG. 8D is a schematic process cross-sectional view following FIG. 8C;
  • FIG. 8D is a schematic process cross-sectional view following FIG. 8D;
  • FIG. 8F is a schematic process cross-sectional view following FIG.
  • FIG. 10 is a cross-sectional view schematically showing a schematic configuration of a semiconductor device according to modification 2-1 of the second embodiment of the present technology; It is a schematic process cross-sectional view showing a method of manufacturing a semiconductor device according to Modification 2-1 of the second embodiment of the present technology.
  • the first direction and the second direction which are orthogonal to each other in the same plane, are the X direction and the Y direction, respectively.
  • a third direction orthogonal to each of the second directions is the Z direction.
  • the thickness direction of a semiconductor device 1A which will be described later, will be described as the Z direction.
  • a semiconductor device 1A according to the first embodiment of the present technology is a semiconductor chip 10 and an interposer called an interposer that is overlapped and joined to a first surface S1 of the semiconductor chip 10.
  • a wiring board 20 is provided.
  • the semiconductor device 1A according to the first embodiment of the present technology further includes a storage body (package) 30 that stores the semiconductor chip 10 .
  • the housing body 30 includes a wiring board 20 and a resin sealing body 31 provided on the fourth surface S4 side, which is the upper surface of the wiring board 20, and sealing the semiconductor chip 10 therein.
  • the semiconductor chip 10 has a rectangular planar shape that intersects with its thickness direction (Z direction).
  • the semiconductor chip 10 mainly includes, but is not limited to, a semiconductor substrate 11 and a plurality of transistors (not shown) provided on an element forming surface (main surface) of the semiconductor substrate 11. and a laminated body (multilayer wiring layer) 12 formed by alternately stacking insulating layers and wiring layers on the element forming surface side of the semiconductor substrate 11 .
  • the semiconductor chip 10 has a first surface S1 and a second surface S2 located opposite to each other.
  • the first surface S1 may be called the bottom surface of the semiconductor chip 10
  • the second surface S2 may be called the top surface of the semiconductor chip 10.
  • the bottom surface of the semiconductor chip 10 is the surface closer to the wiring substrate 20
  • the top surface of the semiconductor chip 10 is the surface opposite to the bottom surface of the semiconductor chip 10 .
  • a third surface S3 shown in FIG. 1B is a side surface of the semiconductor chip 10.
  • the third surface S3 is a surface forming the outer peripheral surface of the semiconductor chip 10, and is a surface connecting the first surface S1 and the second surface S2 in the Z direction.
  • the wiring substrate 20 and the resin sealing body 31 overlap the entire semiconductor chip 10 in plan view. In other words, the contours of the wiring board 20 and the resin sealing body 31 are outside the contour of the semiconductor chip 10 in plan view.
  • the semiconductor substrate 11 shown in FIG. 1B is made of single crystal silicon, for example.
  • the insulating layer of the laminate 12 is composed of, for example, a silicon oxide film.
  • the wiring layer of the laminate 12 is composed of, for example, a copper (Cu) film, an aluminum (Al) film, or an aluminum alloy film in which at least one of silicon (Si) and copper (Cu) is added to Al.
  • Si is added mainly for the purpose of improving electromigration resistance.
  • Cu is added mainly for the purpose of improving alloy spike resistance.
  • the wiring layer of the first embodiment is composed of, for example, an Al alloy film having an Al--Si--Cu composition in which Si and Cu are added to Al.
  • the semiconductor chip 10 contains an integrated circuit.
  • This integrated circuit is mainly composed of transistor elements formed on the semiconductor substrate 11 and wires formed in the wiring layer of the laminate 12 .
  • the semiconductor chip 10 has a plurality of electrode pads 13 provided on the first surface S1 side.
  • the electrode pads 13 are arranged, for example, along four sides in the two-dimensional plane of the semiconductor chip 10 .
  • the electrode pads 13 are formed as components of an integrated circuit and function as external terminals such as signal input/output terminals and power supply terminals.
  • the electrode pads 13 are provided so as to face the first surface S1, and are overlapped and joined to electrode pads 22a of the wiring board 20, which will be described later.
  • the wiring board 20 has a rectangular planar shape that intersects the thickness direction (Z direction), and is, for example, a square in the first embodiment.
  • the wiring board 20 has a fourth surface S4 and a fifth surface S5 located on opposite sides of each other.
  • the fourth surface S4 is sometimes referred to as the top surface of the wiring board 20
  • the fifth surface S5 is sometimes referred to as the bottom surface of the wiring board 20.
  • the top surface of the wiring board 20 is closer to the semiconductor chip 10
  • the bottom surface of the wiring board 20 is the surface opposite to the top surface of the wiring board 20 .
  • the upper surface (fourth surface S4) of the wiring board 20 is joined to the bottom surface (first surface S1) of the semiconductor chip 10.
  • first surface S1 first surface S1
  • the wiring board 20 has a base material 21 and a plurality of wirings 22 provided on the base material 21 .
  • the base material 21 is made of an insulating stretchable material, and can be stretched by applying force.
  • the base material 21 is made of, for example, an elastic material having an expansion ratio of 200% or more and an elastic modulus of 100 MPa or less.
  • Elastic materials include, for example, elastomers.
  • stretchable materials include silicon resin, urethane resin, epoxy resin, acrylic resin, and fluororubber.
  • the elastic material may be the material described in Patent Document 2 or Patent Document 3.
  • the wiring board 20 includes a central portion 20a that overlaps the semiconductor chip 10 in the thickness direction (overlaps in plan view) and a peripheral edge portion 20b that does not overlap the semiconductor chip 10 in the thickness direction (does not overlap in plan view).
  • the peripheral portion 20b is thinner than the central portion 20a. More specifically, the thickness of the peripheral portion 20b becomes thinner as the distance from the central portion 20a increases.
  • the thickness of the central portion 20a is preferably, for example, 200 ⁇ m or more and 300 ⁇ m or less.
  • a plurality of wirings 22 are provided in the central portion 20a of the wiring board 20 between the central portion 20a and the peripheral edge portion 20b. That is, the central portion 20a is a region in which a plurality of wirings 22 are provided. Although not limited to this, a plurality of wirings 22 are provided so as to occupy about 80% of the central portion 20a, for example.
  • the wiring 22 is electrically connected from one surface of the fourth surface S4 and the fifth surface S5 to the other surface. Also, the wiring 22 is electrically connected to the semiconductor chip 10 on one side of the base material 21 .
  • the wiring 22 is an electrode pad 22a provided on the fourth surface S4 side, an electrode pad 22b provided on the fifth surface S5 side, and a connection portion that electrically connects the electrode pad 22a and the electrode pad 22b. 22c.
  • the electrode pads 22 a are arranged at positions corresponding to the electrode pads 13 of the semiconductor chip 10 .
  • the electrode pads 22a face the fourth surface S4 and are overlapped with and joined to the electrode pads 13 of the semiconductor chip 10. As shown in FIG. Thereby, the electrode pad 22 a is electrically connected to the electrode pad 13 .
  • the electrode pads 22b are arranged at positions corresponding to terminals of a mother board (not shown).
  • the configuration of 22c is not limited to the example shown in FIG. 1B, and may have other configurations as long as the electrode pads 22a and 22b are electrically connected.
  • a bump electrode 61 is fixed to the electrode pad 22b and is electrically and mechanically connected.
  • the bump electrode 61 for example, a Pb-free composition solder bump that does not substantially contain Pb is used.
  • the bump electrodes 61 may be provided at positions corresponding to the terminals of the motherboard (not shown), and the positions and number thereof are not limited to those shown in FIG. 1B.
  • the resin sealing body 31 has a square planar shape that intersects the thickness direction (Z direction), and is, for example, a square in the first embodiment.
  • the resin sealing body 31 has the same size as the wiring substrate 20 in plan view.
  • the resin sealing body 31 covers the semiconductor chip 10 . More specifically, as shown in FIG. 1B, the resin sealing body 31 covers the second surface S2 and the third surface S3 of the semiconductor chip 10. As shown in FIG. Also, the resin sealing body 31 covers the peripheral edge portion 20 b of the wiring board 20 . More specifically, the resin sealing body 31 covers the fourth surface S4 of the peripheral portion 20b. With such a configuration, the resin sealing body 31 seals the semiconductor chip 10 .
  • the resin sealing body 31 is made of, for example, an epoxy-based thermosetting resin. As a method for forming the resin sealing body 31, for example, a transfer molding method suitable for mass production is used.
  • the resin sealing body 31 also enters the interior of the gap B, which is slightly formed between the first surface S1 of the semiconductor chip 10 and the fourth surface S4 of the wiring board 20 and has a wedge-shaped cross section.
  • FIG. 2A is a diagram showing the planar configuration of a semiconductor wafer used for manufacturing the semiconductor device 1A
  • FIG. 2B is a diagram showing the configuration of the chip area by enlarging the C area in FIG. 2A
  • FIG. 2C is a diagram showing the configuration of the wiring board area by enlarging a part of the wiring board assembly to be described later.
  • 3A to 3G are schematic cross-sectional views for explaining the manufacturing method of the semiconductor device 1A.
  • a semiconductor wafer 40 and a wiring substrate assembly 50 are prepared.
  • the prepared semiconductor wafer 40 has multiple chip regions 41 .
  • An integrated circuit is fabricated in the chip area 41 . That is, the chip area 41 is an area in which the components of the semiconductor chip 10 have already been formed.
  • the chip regions 41 are partitioned by scribe lines (dicing regions) 42 and arranged repeatedly in the X and Y directions via the scribe lines 42 . That is, a plurality of chip regions 41 are arranged in a matrix.
  • the semiconductor chip 10 on which the integrated circuit is mounted is formed. That is, FIG. 2A is a diagram showing the entire semiconductor substrate in a wafer state before singulation into a plurality of semiconductor chips. Note that the scribe line 42 is not physically formed.
  • an integrated circuit is formed in the chip area 41 shown in FIG. 2B.
  • An integrated circuit is constructed by forming transistor elements on an element forming surface of a semiconductor substrate 11 and then forming a laminate 12 on the element forming surface of the semiconductor substrate 11 .
  • the laminated body 12 is formed by alternately laminating insulating layers and wiring layers on the element forming surface side of the semiconductor substrate 11 .
  • Electrode pads 13 are formed on the uppermost wiring layer of the laminate 12 .
  • the semiconductor substrate 11 is made of single crystal silicon, for example.
  • As the transistor element for example, a p-channel conductivity type MOSFET ((Metal Oxide Semiconductor Field Effect Transistor)) and an n-channel conductivity type MOSFET are used.
  • the integrated circuit has a CMOS (Complementary MOS) circuit configuration.
  • the electrode pads 13 are formed as components of an integrated circuit and function as external terminals such as signal input/output terminals and power supply terminals.
  • the semiconductor wafer 40 shown in FIGS. 2A and 2B is almost completed.
  • components such as transistor elements, laminates 12, integrated circuits, and electrode pads 13 are formed.
  • the wiring board assembly 50 is obtained by providing a plurality of wiring board regions 51 in a base material 21 made of an elastic material.
  • a central portion 20 a having a plurality of wirings 22 is manufactured in the wiring substrate region 51 .
  • the wiring board area 51 is an area in which a plurality of wirings 22 have already been formed.
  • the wiring substrate region 51 is partitioned by regions 52 where no wiring 22 is provided, and the regions 52 are repeatedly arranged in the X direction and the Y direction. That is, a plurality of wiring board regions 51 are arranged in a matrix.
  • the wiring substrate 20 is formed by singulating the plurality of wiring substrate regions 51 individually along the regions 52 .
  • the wiring substrate regions 51 are arranged in a matrix at the same pitch as the chip regions 41 .
  • the wiring board aggregate 50 may be prepared using, for example, MSAP (Modified Semi Additive Process).
  • MSAP Modem Semi Additive Process
  • vias are formed in an elastic material with copper foil by laser, and wiring 22 is formed by photolithography.
  • the next layer of stretchable material with copper foil is laminated thereon by heating while applying pressure, and the same steps are repeated to form a wiring pattern.
  • the MSAP method repeats the process of forming the wiring pattern described above.
  • the dimension (thickness) in the Z direction of the wiring board assembly 50 is preferably, for example, 200 ⁇ m or more and 300 ⁇ m or less.
  • the first surface S1 of the semiconductor wafer 40 and the fourth surface S4 of the wiring substrate assembly 50 shown in FIG. 3A are irradiated with plasma to activate the surfaces.
  • the semiconductor wafer 40 and the wiring substrate assembly 50 are overlapped and bonded.
  • the electrode pad 13 and the electrode pad 22a are overlapped and joined to be electrically connected. After that, heat treatment may be performed.
  • the semiconductor wafer 40 is cut so as not to divide the wiring board assembly 50, and the chip regions 41 are separated into individual semiconductor chips 10. Then, as shown in FIG. More specifically, the semiconductor wafer 40 is cut along the scribe lines 42 shown in FIG. A dicing blade, for example, is used to cut the semiconductor wafer 40 .
  • a gap of about 100 ⁇ m for example, is formed between the semiconductor chips 10, although not limited to this.
  • grooves may be cut out in the wiring board assembly 50 as shown in FIG. 3C.
  • the individualized semiconductor chips 10 are maintained in a state of being joined to the wiring board assembly 50 .
  • the wiring board aggregate 50 (base material 21) is extended in the horizontal direction (direction perpendicular to the Z direction) to widen the space between the semiconductor chips 10.
  • the dimension (thickness) of the wiring board assembly 50 in the Z direction is, for example, 200 ⁇ m or more and 300 ⁇ m or less, it is possible to prevent the wiring substrate assembly 50 from being cut when stretched in the horizontal direction.
  • the gap between the semiconductor chips 10 was about 100 ⁇ m before stretching, the wiring board aggregate 50 is stretched until the gap becomes, for example, about 300 ⁇ m, although it is not limited to this.
  • the extent to which the wiring board assembly 50 is extended may be determined according to the thickness of the resin sealing body 31 to be left on the side surface of the semiconductor chip 10 and the width to be scraped by singulation.
  • a plurality of wirings 22 are provided in the portion of the wiring board assembly 50 that is bonded to the semiconductor chip 10 .
  • the wirings 22 are densely provided in the portion of the wiring substrate aggregate 50 that is joined to the semiconductor chip 10 . Therefore, the portion of the wiring board assembly 50 that is stretched is mainly the portion between the wiring board regions 51 (the region 52 in FIG. 2C). No wiring is provided in the region 52, and grooves are cut out in the region 52 when the semiconductor wafer 40 is cut with a dicing blade. It mainly acts to stretch the base material 21 in the region 52 .
  • the Z-direction dimension of the region 52 after being stretched is not limited to this, but is, for example, about half before being stretched.
  • the thickness of the region 52 after stretching is, for example, 150 ⁇ m.
  • a resin sealing body for sealing the semiconductor chips 10 and the like is placed on the fourth surface S4 side of the wiring substrate 20 while maintaining the state in which the distance between the semiconductor chips 10 is widened. 31 is formed. More specifically, in the state shown in FIG. 3D, the semiconductor chip 10 and the wiring board assembly 50 are placed in a mold (not shown), and the resin sealing body is heated and melted in the mold. Pour in 31. Then, it waits until the temperature of the resin sealing body 31 drops and solidifies. As a result, the semiconductor chip 10 is covered with the resin sealing body 31 as shown in FIG. 3E. More specifically, both the upper surface (second surface S2) and the side surface (third surface S3) of the semiconductor chip 10 are covered with the resin sealing body 31. As shown in FIG.
  • the resin sealing body 31 and the wiring board assembly 50 between the semiconductor chips 10 are cut. More specifically, the resin sealing body 31 between the semiconductor chips 10 and the region 52 of the wiring board assembly 50 are cut together. Thus, the semiconductor device 1A is singulated. Furthermore, a housing body (package) 30 that houses the semiconductor chip 10 including the wiring board 20 and the resin sealing body 31 is formed. More specifically, a housing (package) 30 including a wiring board 20 and a resin sealing body 31 covering both the upper surface (second surface S2) and the side surface (third surface S3) of the semiconductor chip 10. is formed.
  • bump electrodes 61 are formed on the electrode pads 22b. Thereby, the semiconductor device 1A shown in FIGS. 1A and 1B is almost completed.
  • Fan-Out Wafer Level Packaging In order to avoid such exposed silicon, a technology called Fan-Out Wafer Level Packaging (FOWLP) is sometimes used.
  • the fan-out type wafer level package diced semiconductor chips are rearranged on another member with a gap therebetween, and a resin sealing body is formed thereon to form a pseudo wafer. Then, the separate members are removed, and a rewiring layer, bump electrodes, etc. are formed on the surface of the pseudo wafer on which the resin sealing body is not formed, and the wafer is singulated.
  • the resin sealing body is formed between the upper surfaces of the semiconductor chips rearranged with a space therebetween and between the semiconductor chips, it is possible to suppress the occurrence of exposed portions on the surface of the semiconductor chip 10. can.
  • the diced semiconductor chips are rearranged, the number of steps increases and the process becomes complicated.
  • the bottom surface of the semiconductor wafer 40 and the wiring board assembly 50 are overlapped and joined together so that the wiring board assembly 50 is not divided.
  • the semiconductor wafer 40 is cut to separate the chip regions 41 into individual semiconductor chips 10, and the wiring board assembly 50 is extended horizontally to widen the space between the semiconductor chips 10, thereby increasing the space between the semiconductor chips 10.
  • the semiconductor chips 10 are covered with the resin sealing body 31 while keeping the space widened, and the resin sealing body 31 and the wiring board assembly 50 between the semiconductor chips 10 are cut to separate the semiconductor devices 1A. fragmented. Therefore, both the upper surface and side surfaces of the semiconductor chip 10 can be covered with the resin sealing body 31, and the upper surface and side surfaces of the semiconductor chip 10 can be prevented from being exposed. Thereby, chipping of the semiconductor chip 10 can be suppressed.
  • the wiring board assembly includes a base material made of an elastic material and wiring electrically connected from one surface to the other surface of the base material. are provided. Therefore, the wiring board assembly is not a disposable member, but is stretched to widen the space between the semiconductor chips 10, undergoes other processes, is cut into individual wiring boards 20, and is divided into the semiconductor devices 1A. used as part of Therefore, there is no need to rearrange the semiconductor chips 10 , an increase in the number of steps can be suppressed, and complication of the process can be suppressed.
  • the base material 21 is made of a stretchable material having an expansion ratio of 200% or more, and the region 52 includes wiring lines for suppressing expansion and contraction of the base material 21. 22 is not provided, the space between the semiconductor chips 10 can be sufficiently widened. Further, since the base material 21 has an elastic modulus of 100 MPa or less, it is possible to suppress an increase in the force required to stretch the base material 21 .
  • the dimension (thickness) in the Z direction of the wiring board assembly 50 is, for example, 200 ⁇ m or more and 300 ⁇ m or less. Even if it is stretched, it can be prevented from breaking.
  • the material forming the semiconductor device 1A and the material forming the mother board have different coefficients of thermal expansion, so when the temperature reaches normal temperature after the heat treatment, strain may occur between the two. Therefore, the bump electrode may be distorted.
  • the base material 21 included in the wiring board 20 is made of an elastic material. Therefore, the extension of the wiring board 20 can absorb the strain generated between the semiconductor device 1A and the motherboard, so that the application of stress to the bump electrodes 61 can be suppressed. As a result, it is possible to suppress the occurrence of cracks in the bump electrode 61, thereby suppressing the decrease in reliability.
  • the semiconductor device 1A according to the first embodiment of the present technology can absorb the strain generated between the semiconductor device 1A and the mother board due to the extension of the wiring substrate 20 as described above, after mounting on the mother board, It is possible to suppress deterioration in reliability against temperature changes.
  • the semiconductor device 1A was mounted on a mother board and a temperature cycle test was conducted, the experimental results showed improved reliability compared to the conventional redistribution layer (RDL).
  • RDL redistribution layer
  • the experimental results depend on the thickness and stretchability of the wiring board 20, there were cases where the reliability was improved by ten times or more compared to the conventional rewiring layer at a specific thickness and stretchability.
  • the resin sealing body 31 enters the wedge-shaped gap B as shown in FIG. 1B. Therefore, the semiconductor device 1A is suppressed from becoming weak against physical loads and environmental loads.
  • the semiconductor chip 10 and the wiring substrate 20 are bonded by irradiating the bonding surface with plasma, but the present technology is not limited to this.
  • microbumps 14 are formed on the electrode pads 13 of the semiconductor chip 10 (semiconductor wafer 40), and the microbumps 14 and the electrode pads 22a of the wiring board 20 are bonded to form the semiconductor chip 10 (semiconductor wafer 40).
  • the wafer 40) and the wiring substrate 20 (wiring substrate assembly 50) may be bonded.
  • the electrode pads 13 and the electrode pads 22a are electrically connected via the microbumps 14.
  • a sealing body 62 is provided between the semiconductor chip 10 and the wiring board 20 .
  • the sealing body 62 joins the first surface S ⁇ b>1 of the wiring board 20 and the fourth surface S ⁇ b>4 of the wiring board 20 .
  • the encapsulant 62 may be, for example, an underfill made of epoxy resin or the like. The underfill is injected between the bonded semiconductor chip 10 and wiring board 20 and then cured.
  • the sealing body 62 may be an anisotropic conductive material such as an anisotropic conductive film.
  • the anisotropic conductive material is composed of a mixed material of conductive particles responsible for conduction and an adhesive responsible for adhesion. A portion of the anisotropic conductive material located between the microbump 14 and the electrode pad 22a exhibits conductivity when a pressure higher than the surroundings is applied, thereby creating a gap between the microbump 14 and the electrode pad 22a. electrically connected.
  • microbumps 14 are formed on the semiconductor chip 10 (semiconductor wafer 40) side in Modification 1-1 described above, the present technology is not limited to this.
  • microbumps 23 may be formed on the wiring substrate 20 (wiring substrate assembly 50) side. That is, the microbumps 23 may be formed on the electrode pads 22a.
  • the semiconductor chip 10 (semiconductor wafer 40) and the wiring substrate 20 (wiring substrate assembly 50) may be bonded.
  • the electrode pads 13 and the electrode pads 22a are electrically connected via the microbumps 23.
  • the encapsulant 62 has already been described.
  • the semiconductor device 1A according to Modification 1-2 also provides the same effects as the semiconductor device 1A according to the above-described first embodiment.
  • the resin sealing body 31 is made of, for example, an epoxy-based thermosetting resin, and is formed using a transfer molding method.
  • the present technology is not limited to this.
  • the resin is cured.
  • the resin is cured by heat, ultraviolet rays, or the like, for example.
  • the semiconductor chip 10 may be covered with the resin sealing body 31 .
  • the semiconductor device 1A according to the modified example 1-3 can also obtain the same effect as the semiconductor device 1A according to the above-described first embodiment.
  • the resin sealing body 31 according to Modification 1-3 may be applied to Modifications 1-1 and 1-2 described above.
  • a rewiring layer having a thickness in the Z direction approximately equal to that of the wiring board assembly 50 and having an expansion/contraction rate and an elastic modulus approximately equal to those of the wiring board assembly 50 is formed. It may be formed by stacking. Such a rewiring layer is formed by coating a stretchable insulating layer on the first surface S1 of the semiconductor wafer 40, exposing it, and developing it. After that, the semiconductor wafer 40 is cut or half-cut so as not to divide the rewiring layer. Subsequent steps are the same as the steps described in the first embodiment, so description thereof is omitted here.
  • CMOS Complementary Metal Oxide Semiconductor
  • the semiconductor device 1B according to the second embodiment differs from the semiconductor device 1A according to the above-described first embodiment in that it has a semiconductor chip 10B instead of the semiconductor chip 10, and a housing body instead of the housing body 30. 30B, and other than that, the configuration of the semiconductor device 1B is basically the same as that of the semiconductor device 1A of the above-described first embodiment.
  • symbol is attached
  • a semiconductor device 1B includes a semiconductor chip 10B and a housing (package) 30B.
  • the semiconductor chip 10B is equipped with a photodetector.
  • a photodetector for example, image light (incident light) from a subject is taken in via an optical lens, and the amount of light of the incident light formed on the image pickup surface is converted into an electric signal for each pixel, which is then used as a pixel signal.
  • a solid-state image pickup device that emits irradiation light toward an object, detects the reflected light that is reflected by the surface of the object, and receives the reflected light after the irradiation light is emitted.
  • a distance measuring sensor Time of Flight, ToF sensor
  • the photodetector is described as being the solid-state imaging device 70 mounted on the semiconductor chip 10B shown in FIG. 7, but it is not limited to this.
  • the solid-state imaging device 70 (semiconductor chip 10B) according to the second embodiment of the present technology has a square two-dimensional planar shape when viewed in plan.
  • the solid-state imaging device 70 includes a rectangular pixel region 2A provided in the center and a pixel region 2A surrounding the pixel region 2A outside the pixel region 2A on a two-dimensional plane including the X direction and the Y direction that intersect each other. and a peripheral region 2B.
  • the pixel area 2A is a light receiving surface that receives light condensed by, for example, an optical lens (optical system).
  • a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction.
  • the pixels 3 are repeatedly arranged in the X direction and the Y direction that are orthogonal to each other within the two-dimensional plane.
  • a plurality of electrode pads 13B are arranged in the peripheral region 2B.
  • the electrode pads 13B are arranged, for example, along four sides in the two-dimensional plane of the semiconductor chip 10B.
  • the electrode pads 13B are input/output terminals used when electrically connecting the solid-state imaging device 70 to an external device.
  • the solid-state imaging device 70 has logic circuits including a vertical drive circuit, a column signal processing circuit, a horizontal drive circuit, an output circuit, a control circuit, and the like.
  • the logic circuit is composed of, for example, a CMOS (Complementary MOS) circuit.
  • Each pixel 3 of the plurality of pixels 3 has a photoelectric conversion element.
  • a readout circuit is connected to the photoelectric conversion element of each pixel 3 .
  • a photoelectric conversion element is formed for each pixel 3 on the semiconductor substrate 11B shown in FIG. Then, the photoelectric conversion element photoelectrically converts the light into a signal charge corresponding to the amount of received light and holds the signal charge.
  • the semiconductor chip 10B has a first surface S1 and a second surface S2 located on opposite sides in the thickness direction (Z direction).
  • the semiconductor chip 10B includes a semiconductor substrate 11B, a laminate (multilayer wiring layer) 12B formed by alternately stacking insulating layers and wiring layers on the element forming surface side of the semiconductor substrate 11B, and electrode pads 13B. It has
  • a plurality of MOSFETs are configured on the semiconductor substrate 11B as field effect transistors that configure circuits such as the above-described logic circuit and readout circuit.
  • a single crystal silicon substrate for example, can be used as the semiconductor substrate 11B.
  • the laminated body 12B has a laminated structure in which insulating layers and wiring layers are alternately laminated in multiple stages.
  • the electrode pads 13B penetrate through the semiconductor chip 10B.
  • the electrode pad 13B is joined and electrically connected to the electrode pad 22a.
  • the semiconductor chip 10B further includes a flattening film (not shown), a color filter (not shown), and a microlens 15 which are sequentially stacked from the second surface S2 side (light receiving surface side) on the second surface S2 side (light receiving surface side). .
  • the planarizing film planarizes the second surface S2 side.
  • the microlens 15 collects incident light to the semiconductor substrate 11B.
  • the color filter color-separates the incident light to the semiconductor substrate 11B.
  • a color filter and a microlens 15 are provided for each pixel 3, respectively.
  • the color filters and microlenses 15 are made of resin material, for example.
  • the housing body 30B includes the wiring substrate 20, the resin sealing body 31, and the light transmission substrate 32, and seals the semiconductor chip 10B.
  • the semiconductor device 1B has a light transmitting substrate 32 on the light receiving surface side. More specifically, the semiconductor device 1B has a light transmitting substrate 32 on the light receiving surface side of the semiconductor chip 10B.
  • the light-transmitting substrate 32 seals the light-receiving surface side (second surface S2 side) of the semiconductor chip 10B. More specifically, the light-transmitting substrate 32 seals the light-receiving surface side (second surface S2 side) of the semiconductor chip 10B with a gap from the semiconductor chip 10B.
  • the light-transmitting substrate 32 is adhered with a resin 33 to the second surface S2 side of the semiconductor chip 10B.
  • the light-transmitting substrate 32 is configured using a member having light-transmitting properties, and for example, a glass substrate is used, but the present invention is not limited to this.
  • a glass substrate is used, but the present invention is not limited to this.
  • an acrylic resin substrate, a sapphire substrate, or the like may be used as the light transmission substrate 32 .
  • the light transmitted through the light-transmitting substrate 32 is incident on the photoelectric conversion element provided on the semiconductor substrate 11B, and is photoelectrically converted by the photoelectric conversion element into signal charges corresponding to the amount of light.
  • the resin sealing body 31 is provided on the side of the fourth surface S4, which is the upper surface of the wiring board 20, and mainly covers the side surface (third surface S3) of the semiconductor chip 10B.
  • the resin sealant 31 covers the side surface of the light-transmitting substrate 32 (the surface perpendicular to the Z direction) and also enters the gap between the light-transmitting substrate 32 and the semiconductor chip 10B.
  • a semiconductor wafer 40, a wiring board assembly 50, and a light transmissive board 80 are prepared.
  • a solid-state imaging device 70 is manufactured in the chip area 41 of the semiconductor wafer 40 .
  • the light transmissive substrate 80 has the same size as the semiconductor wafer 40 .
  • the semiconductor wafer 40 and the wiring board assembly 50 are overlapped and bonded.
  • the light transmission substrate 80 is adhered to the second surface S2 side of the semiconductor wafer 40 using the resin 33 .
  • the light-transmitting substrate 80 and the semiconductor wafer 40 are cut so as not to divide the wiring substrate assembly 50 .
  • the light-transmitting substrate 80 is singulated into the light-transmitting substrates 32
  • the semiconductor wafer 40 is singulated into the semiconductor chips 10B.
  • the light-transmissive substrate 32 and the semiconductor chip 10B are separated into individual pieces while they are bonded together.
  • the wiring board assembly 50 is extended in the horizontal direction (direction perpendicular to the Z direction) to widen the space between the semiconductor chips 10B. Then, in the state shown in FIG. 8D, the semiconductor chip 10B with the light-transmitting substrate 32 adhered thereto and the wiring board assembly 50 are placed in a mold (not shown), and heated and melted in the mold.
  • the resin sealing body 31 is poured. More specifically, a film is provided on the mold on the side that contacts the light-transmitting substrate 32 so that the resin sealing body 31 does not adhere to the surface of the light-transmitting substrate 32 when the resin sealing body 31 is filled. I'm trying Then, it waits until the temperature of the resin sealing body 31 drops and solidifies.
  • FIG. 8E a resin sealing body 31 covering the side surface of the light-transmitting substrate 32 and the side surface (third surface S3) of the semiconductor chip 10B is formed.
  • FIG. 8F the semiconductor device 1B is separated into individual pieces, and the bump electrodes 61 are provided on the electrode pads 22b as described with reference to FIG. 3G of the first embodiment, thereby completing the semiconductor device 1B shown in FIG.
  • a light transmitting substrate 32 is provided on the light receiving surface side. Therefore, light can enter the semiconductor chip 10B, and the photoelectric conversion element can perform photoelectric conversion. Furthermore, it is possible to prevent the upper surface of the semiconductor chip 10B from being exposed. Moreover, the side surfaces of the semiconductor chip 10B can be mainly covered with the resin sealing body 31, and the side surfaces of the semiconductor chip 10B can be prevented from being exposed. As a result, it is possible to suppress the occurrence of an exposed portion on the surface of the semiconductor chip 10B, and it is possible to suppress chipping of the semiconductor chip 10B.
  • the light transmissive substrate 32 has substantially the same size as the semiconductor chip 10B in plan view, but the present technology is not limited to this.
  • the light transmission substrate 32 may be smaller than the semiconductor chip 10B in plan view. More specifically, it may be smaller than the semiconductor chip 10B as long as it can cover the pixel region 2A shown in FIG. 7 in plan view.
  • the light-transmitting substrate 80 is singulated in advance to prepare the light-transmitting substrate 32. For example, as shown in FIG. The light-transmitting substrate 32 is adhered with the resin 33 . After that, the semiconductor wafer 40 may be singulated. Note that the subsequent steps are the same as those of the second embodiment, so description thereof will be omitted here.
  • the semiconductor device 1B according to the modified example 2-1 can also obtain the same effect as the semiconductor device 1B according to the above-described second embodiment.
  • the semiconductor device 1A according to Modification 1-1 of the first embodiment described above includes the microbump 14, and the semiconductor device 1A according to Modification 1-2 of the first embodiment includes the microbump 23.
  • such a technical idea may be applied to the semiconductor device 1B described in the second embodiment and its modifications.
  • various combinations are possible according to the respective technical ideas, such as applying the rewiring layers according to Modifications 1-4 of the first embodiment to the second embodiment.
  • the semiconductor devices 1A and 1B are provided with the bump electrodes 61 in the above-described embodiments, they may not be provided.
  • the semiconductor devices 1A and 1B can also be referred to as semiconductor devices 1A and 1B after singulation and before forming the bump electrodes 61, as shown in FIGS. 3F and 8F.
  • the present technology may be configured as follows. (1) A semiconductor wafer provided with a plurality of chip regions, which are regions in which components of a semiconductor chip are already formed; preparing a wiring board assembly in which a plurality of wiring board regions, which are already formed regions, are provided; overlapping and bonding the bottom surface of the semiconductor wafer and the wiring board assembly; cutting the semiconductor wafer so as not to divide the wiring board assembly, and singulating the chip regions into semiconductor chips; extending the wiring board assembly in the horizontal direction to widen the space between the semiconductor chips; covering the semiconductor chips with a resin encapsulant while maintaining a state in which the distance between the semiconductor chips is widened; A method of manufacturing a semiconductor device, wherein the resin sealing body and the wiring board assembly between the semiconductor chips are cut to singulate the semiconductor device.
  • a wiring board superimposed and joined to the and a resin sealing body covering the semiconductor chip.
  • the resin sealing body covers at least the side surface out of the upper surface and the side surface of the semiconductor chip.
  • the electrode pads of the semiconductor chip are electrically connected to the wiring of the wiring substrate.
  • (7) Having a light-transmitting substrate on the light-receiving surface side, The semiconductor device according to any one of (4) to (6), wherein the semiconductor chip has a photoelectric conversion element.

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PCT/JP2022/013330 2021-09-14 2022-03-23 半導体装置の製造方法、半導体装置、及び半導体装置用の配線基板 Ceased WO2023042450A1 (ja)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009246174A (ja) * 2008-03-31 2009-10-22 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法、ならびに携帯機器
JP2009267409A (ja) * 2008-04-24 2009-11-12 Mutual-Pak Technology Co Ltd 集積回路デバイス用のパッケージ構造およびパッケージ方法
JP2010114243A (ja) * 2008-11-06 2010-05-20 Toppan Printing Co Ltd 半導体装置
WO2021111716A1 (ja) * 2019-12-04 2021-06-10 ソニーセミコンダクタソリューションズ株式会社 撮像装置および撮像装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005322858A (ja) * 2004-05-11 2005-11-17 Shinko Electric Ind Co Ltd 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009246174A (ja) * 2008-03-31 2009-10-22 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法、ならびに携帯機器
JP2009267409A (ja) * 2008-04-24 2009-11-12 Mutual-Pak Technology Co Ltd 集積回路デバイス用のパッケージ構造およびパッケージ方法
JP2010114243A (ja) * 2008-11-06 2010-05-20 Toppan Printing Co Ltd 半導体装置
WO2021111716A1 (ja) * 2019-12-04 2021-06-10 ソニーセミコンダクタソリューションズ株式会社 撮像装置および撮像装置の製造方法

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