WO2023029705A1 - 信号走线结构及阵列基板 - Google Patents

信号走线结构及阵列基板 Download PDF

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Publication number
WO2023029705A1
WO2023029705A1 PCT/CN2022/102009 CN2022102009W WO2023029705A1 WO 2023029705 A1 WO2023029705 A1 WO 2023029705A1 CN 2022102009 W CN2022102009 W CN 2022102009W WO 2023029705 A1 WO2023029705 A1 WO 2023029705A1
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Prior art keywords
metal
current
layer
current paths
signal
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PCT/CN2022/102009
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English (en)
French (fr)
Inventor
王光加
李伟
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惠科股份有限公司
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Publication of WO2023029705A1 publication Critical patent/WO2023029705A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present application belongs to the field of display technology, and in particular relates to a signal wiring structure and an array substrate.
  • liquid crystal display Liquid Crystal Display, LCD
  • thin film transistor Thin Film Transistor, TFT
  • organic laser display Organic Electroluminesence Display
  • LED Light Emitting Diode
  • Quantum dot light-emitting diode Quantum dot light-emitting diode
  • High-end display panels require high pixel density (Pixels Per Inch, PPI) and a narrow frame, so the width of the metal signal traces in the display panel will be extremely compressed during design, resulting in thinner metal traces, which are prone to problems due to electrostatic discharge (Electro-Static Discharge) discharge, ESD) caused damage to electronic components.
  • PPI Pixel Per Inch
  • ESD electrostatic discharge
  • One of the purposes of the embodiments of the present application is to provide a signal routing structure and an array substrate, by sequentially connecting all metal pads in the signal routing structure, and/or sequentially connecting all conductive units in the signal routing structure,
  • the large current flowing from each metal line into the metal layer can be dispersed into at least two current paths to solve the problem that the thinner metal signal traces in the display panel are prone to damage to electronic components due to electrostatic discharge .
  • the first aspect of the embodiments of the present application provides a signal routing structure, including a plurality of metal lines and a metal layer, a gate insulating layer, a passivation layer and a transparent conductive layer stacked in sequence, and the end of each metal line is a metal pad, the passivation layer is provided with a plurality of first via holes corresponding to the first positions of all the metal pads; the passivation layer and the gate insulating layer are provided with a second position corresponding to the metal layer A plurality of second vias; characterized by:
  • the transparent conductive layer includes a plurality of conductive units, each of the conductive units corresponds to one of the metal pads, one of the first via holes, and one of the second via holes, and each of the metal pads passes through one of the The first via hole is connected to one of the conductive units, each of the conductive units is connected to the metal layer through one of the second via holes; and all the metal pads are connected in sequence, and/or, all The conductive units are connected in sequence.
  • all areas of all the metal pads are sequentially connected.
  • the current of the signal flowing through the metal wire is dispersed into two current paths, one of which is a current path transmitted from the metal wire to the metal layer, and the other current path is a current path from the metal layer to the metal layer.
  • the metal wire transmits a current path to all regions of all the metal pads that are connected in sequence.
  • the i-th regions of all the metal pads are sequentially connected to form the i-th metal pad layer
  • All the metal backing layers are arranged at intervals and have the same minimum size in the row direction;
  • i 1,2,...,m, m ⁇ 2.
  • the current of the signal flowing through the metal wire is dispersed into m+1 current paths, one of which is a current path transmitted from the metal wire to the metal layer, and the remaining m current paths
  • the paths are current paths respectively transmitted from the metal wires to the m metal pad layers, and the currents of the remaining m current paths are equal.
  • the i-th regions of all the metal pads are sequentially connected to form the i-th metal pad layer
  • All the metal backing layers are spaced apart from each other, and at least two of the metal backing layers have different minimum sizes in the row direction;
  • i 1,2,...,m, m ⁇ 2.
  • the current of the signal flowing through the metal wire is dispersed into m+1 current paths, one of which is a current path transmitted from the metal wire to the metal layer, and the remaining m current paths
  • the paths are current paths respectively transmitted from the metal wires to the m metal pad layers, and currents of at least two of the metal pad layers in the remaining m current paths are different.
  • all areas of all the conductive units are sequentially connected.
  • the current of the signal flowing through the metal wire is dispersed into two current paths, one of which is a current path transmitted from the metal wire to the metal layer, and the other current path is a current path from the metal layer to the metal layer.
  • the metal wire is transmitted to a current path of all regions of all the conductive units connected in sequence.
  • the j-th regions of all the conductive units are sequentially connected to form the j-th sub-transparent conductive layer;
  • All the sub-transparent conductive layers are arranged at intervals and have the same minimum size in the row direction;
  • j 1,2,...,n, n ⁇ 2.
  • the current of the signal flowing in through the metal wire is dispersed into n+1 current paths, one of which is a current path transmitted from the metal wire to the metal layer, and the remaining n current paths
  • the paths are current paths respectively transmitted from the metal wires to the n sub-transparent conductive layers, and the currents of the remaining n current paths are equal.
  • the j-th regions of all the conductive units are sequentially connected to form the j-th sub-transparent conductive layer;
  • All the sub-transparent conductive layers are spaced apart from each other, and at least two of the sub-transparent conductive layers have different minimum dimensions in the row direction;
  • j 1,2,...,n, n ⁇ 2.
  • the current of the signal flowing in through the metal wire is dispersed into n+1 current paths, one of which is a current path transmitted from the metal wire to the metal layer, and the remaining n current paths
  • the paths are current paths respectively transmitted from the metal wires to the n sub-transparent conductive layers, and currents of at least two of the sub-transparent conductive layers in the remaining n current paths are different.
  • the metal lines are common voltage signal lines, data signal lines or scanning signal lines.
  • the conductive unit has a thickness ranging from 500 angstroms to 900 angstroms;
  • the metal pad has a thickness ranging from 3000 angstroms to 7000 angstroms.
  • the conductive unit has a thickness of 900 angstroms, and the metal pad has a thickness of 7000 angstroms.
  • the metal pads are used as a transition structure between the metal lines and the metal layer, and all the metal pads are arranged in sequence along the length direction of the metal layer and mutually arranged at intervals, the passivation layer is arranged between the metal layer and all the metal pads.
  • the second aspect of the embodiment of the present application provides an array substrate, including a display area and a non-display area, a pixel array is provided in the display area, and the signal routing provided in the first aspect of the embodiment of the present application is provided in the non-display area.
  • a wire structure, each of the metal wires is electrically connected to a row or a column of pixels of the pixel array.
  • the array substrate is a liquid crystal array substrate, a thin film transistor liquid crystal array substrate, a light emitting diode array substrate or a quantum dot light emitting diode array substrate.
  • the signal routing structure provided in the first aspect of the embodiment of the present application includes a plurality of metal lines and a metal layer, a gate insulating layer, a passivation layer and a transparent conductive layer stacked in sequence, and the end of each metal line is a metal pad,
  • the first position of the passivation layer corresponding to all metal pads is provided with a plurality of first via holes;
  • the second position of the passivation layer and insulating layer corresponding to the metal layer is provided with a plurality of second via holes;
  • the transparent conductive layer includes a plurality of conductive units , each conductive unit corresponds to a metal pad, a first via hole, and a second via hole, each metal pad conducts through a first via hole and a conductive unit, and each conductive unit passes through a second via hole conduction with the metal layer; and all the metal pads are connected in sequence, and/or, all the conductive units are connected in sequence, by connecting all the metal pads and/or all the conductive units in sequence, it
  • FIG. 1 is a perspective view of a first signal wiring structure provided in Embodiment 1 of the present application;
  • FIG. 2 is an A-A cross-sectional view of the first signal wiring structure provided in Embodiment 1 of the present application;
  • Fig. 3 is a B-B cross-sectional view of the first signal wiring structure provided in Embodiment 1 of the present application;
  • FIG. 4 is a schematic diagram of an equivalent circuit of the first signal routing structure provided in Embodiment 1 of the present application;
  • FIG. 5 is a perspective view of a second signal wiring structure provided in Embodiment 1 of the present application.
  • FIG. 6 is an A-A cross-sectional view of the second signal wiring structure provided in Embodiment 1 of the present application.
  • FIG. 7 is a schematic diagram of an equivalent circuit of a second signal routing structure provided in Embodiment 1 of the present application.
  • FIG. 8 is a perspective view of a third signal wiring structure provided in Embodiment 1 of the present application.
  • FIG. 9 is a schematic diagram of a fourth signal wiring structure provided in Embodiment 2 of the present application.
  • FIG. 10 is an A-A cross-sectional view of the fourth signal wiring structure provided in Embodiment 2 of the present application.
  • Fig. 11 is a B-B cross-sectional view of the fourth signal wiring structure provided in Embodiment 2 of the present application;
  • FIG. 12 is a schematic diagram of an equivalent circuit of a fourth signal wiring structure provided in Embodiment 2 of the present application.
  • FIG. 13 is a schematic diagram of a fifth signal routing structure provided in Embodiment 2 of the present application.
  • FIG. 14 is an A-A cross-sectional view of the fifth signal wiring structure provided in Embodiment 2 of the present application.
  • Fig. 15 is a B-B cross-sectional view of the fifth signal wiring structure provided in Embodiment 2 of the present application;
  • FIG. 16 is a schematic diagram of an equivalent circuit of a fifth signal routing structure provided in Embodiment 2 of the present application.
  • FIG. 17 is a schematic diagram of a sixth signal wiring structure provided in Embodiment 2 of the present application.
  • FIG. 18 is a schematic structural diagram of an array substrate provided in Embodiment 3 of the present application.
  • FIG. 19 is a schematic structural diagram of a liquid crystal display panel provided in Embodiment 4 of the present application.
  • Metal line 1; Metal pad: 10; Metal pad: 11 ⁇ 1m; Metal layer: 2; Gate insulation layer: 3; Passivation layer: 4; Transparent conductive layer: 5; Conductive unit: 50; Sub-transparent conductive layer : 51 ⁇ 5n; first via hole: 6; second via hole: 7; display area: 101; non-display area: 102; signal wiring structure: 103; pixel: 104; array substrate: 100; liquid crystal layer: 200 ; Color filter substrate: 300.
  • references to "one embodiment” or “some embodiments” or the like in the specification of the present application means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically stated otherwise.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise. "Multiple” means two or more.
  • Embodiment 1 of the present application provides a signal routing structure of a display panel, which includes a plurality of metal lines 1 arranged at intervals, metal layers 2 stacked in sequence, and gate insulation Layer (Gate Insulator, GI) 3, passivation layer (passivation layer) 4 and transparent conductive layer 5, the end of each metal line 1 is a metal pad 10;
  • a display panel which includes a plurality of metal lines 1 arranged at intervals, metal layers 2 stacked in sequence, and gate insulation Layer (Gate Insulator, GI) 3, passivation layer (passivation layer) 4 and transparent conductive layer 5, the end of each metal line 1 is a metal pad 10;
  • GI Gate Insulator
  • the passivation layer 4 is provided with a plurality of first via holes 6 corresponding to the first positions of all the metal pads 10;
  • the passivation layer 4 and the gate insulating layer 3 are provided with a plurality of second via holes 7 corresponding to the second position of the metal layer 2;
  • the transparent conductive layer 5 includes a plurality of conductive units 50, each conductive unit 50 corresponds to a metal pad 10, a first via hole 6 and a second via hole 7, and each metal pad 10 passes through a first via hole 6 and a second via hole 7.
  • One conductive unit 50 is connected, and each conductive unit 50 is connected to the metal layer 2 through a second via hole 7 ; all metal pads 10 are connected in sequence.
  • metal layers, metal lines and metal pads can be made of any electrically good conductor material, for example, aluminum (Al), copper (Au), silver (Ag), and the like.
  • the metal wire and the terminal are made of the same material, and each metal wire and the metal pad at the end can be an integrally formed structure, and the metal pad serves as a transition structure between the metal wire and the metal layer. All the metal pads are arranged in sequence along the length direction of the metal layer and are spaced apart from each other.
  • the metal line may be a common voltage signal line for transmitting a common voltage (Vcom) signal, a data signal line for transmitting a data (Data) signal, or a scanning signal line for transmitting a scan (Scan) signal.
  • Vcom common voltage
  • Data data
  • Scan scanning signal line
  • the metal layer and the passivation layer are strip structures with a certain width.
  • the passivation layer is arranged between the metal layer and all metal pads, the length of the passivation layer needs to be greater than or equal to the arrangement length of all metal pads in the length direction of the metal layer, and the width of the passivation layer needs to be greater than or equal to that of the metal pads.
  • the width in this way, can fully insulate and protect.
  • the passivation layer may consist of any material that is a poor conductor of electricity, for example, a layer of silicon nitride (SiNx), a layer of silicon oxide (SiOx), or a combination of silicon nitride and silicon oxide.
  • the passivation layer is not only used as a protective layer with a certain strength, but also has an insulating effect.
  • each conductive unit can be realized by a transparent electrode, for example, an indium tin oxide (Indium Tin Oxide, ITO) electrode, an aluminum-doped zinc oxide (AZO) electrode, or a zinc oxide (ZnO) electrode, etc.
  • ITO Indium Tin Oxide
  • AZO aluminum-doped zinc oxide
  • ZnO zinc oxide
  • the first region and the second region of the gate insulating layer and the first region and the second region of the passivation layer are arranged side by side along the width direction of the metal layer, and the lengths of the first region and the second region are both greater than or equal to The length of the metal layer is such that the first region and the second region can completely cover the metal layer after being arranged side by side.
  • a plurality of first via holes are opened in the passivation layer at first positions corresponding to the plurality of metal pads, and the first via holes penetrate the passivation layer along a direction perpendicular to the surface of the metal layer, and the passivation layer and the A plurality of second via holes are provided at the second position corresponding to the metal layer in the gate insulating layer, and the second via holes penetrate the passivation layer and the gate insulating layer in a direction perpendicular to the surface of the metal layer, and all metal pads, all conductive
  • the number of units, all first vias, and all second vias is equal, and each conductive unit corresponds to a metal pad, a first via, and a second via, and each metal pad passes through a first via It is connected to a conductive unit, and each conductive unit is connected to the metal layer through a second via hole, so that the signal flowing in through each metal line can be transmitted to the metal layer through a metal pad and a conductive unit in sequence.
  • the current of the signal flowing in through the metal line can be dispersed into at least two current paths, one of which is the current path transmitted from the metal line to the metal layer, and the other current path
  • the path is the current path that is transmitted from the metal wire to all metal pads that are connected in sequence.
  • Partial areas of all the metal pads are sequentially connected and at least two connected areas have different minimum widths in the row direction.
  • FIG. 1 and FIG. 2 it exemplarily shows the situation that all areas of all metal pads 10 are sequentially connected.
  • the number of the increased current path depends on the number of connected areas of all the metal pads, the more the number of connected areas, the increased the number of current paths The higher the number.
  • the current of the signal flowing through the metal line can be dispersed into two current paths, one of which is the current path transmitted from the metal line to the metal layer, and the other One current path is a current path transmitted from the metal line to all areas of all metal pads connected in sequence.
  • FIG. 4 it exemplarily shows an equivalent circuit schematic diagram corresponding to the first signal wiring structure shown in FIG. 1 , FIG. 2 and FIG. 3 , wherein the resistance R1 and the current I1 are respectively The equivalent resistance and equivalent current corresponding to the metal line 1, the resistance R2 and the current I2 are the equivalent resistance and the equivalent current corresponding to the metal layer 2, respectively, and the resistance R10 and the current I10 are all of the metal pads 10 connected in sequence.
  • the equivalent resistance and equivalent current corresponding to the area the resistance and equivalent current corresponding to the area.
  • Fig. 5 and Fig. 6 it exemplarily shows the situation that the partial regions of all metal pads are connected in sequence and the minimum width of all connected regions in the row direction is the same; wherein, the i-th region of all metal pads 10 is connected in sequence Constitute the i-th metal backing layer;
  • All metal backing layers 11, 12, ..., 1m are arranged at intervals from each other and have the same minimum size in the row direction;
  • i 1,2,...,m, m ⁇ 2.
  • the number of all metal pad layers is equal to the number of increased current paths, and the current of the signal flowing through the metal line can be dispersed as m+1
  • One current path is a current path transmitted from the metal wire to the metal layer, and the remaining m current paths are current paths transmitted from the metal wire to the m metal pad layers respectively, and the currents of the remaining m current paths are equal.
  • FIG. 7 it exemplarily shows an equivalent circuit schematic diagram corresponding to the second signal wiring structure shown in FIG. 5 and FIG.
  • resistance R2 and current I2 are equivalent resistance and equivalent current corresponding to metal layer 2 respectively
  • resistance R11 and current I11 are equivalent resistance corresponding to the first metal pad layer and the equivalent current
  • the resistance R12 and the current I12 are the equivalent resistance and the equivalent current corresponding to the second metal pad layer respectively
  • the resistance R1m and the current I1m are the equivalent resistance corresponding to the mth metal pad layer resistance and equivalent current.
  • FIG. 8 it exemplarily shows the case where the partial regions of all metal pads are connected sequentially and the minimum widths of at least two connected regions in the row direction are different; wherein, the i-th region of all metal pads 10 is connected sequentially. Constitute the i-th metal backing layer;
  • All the metal backing layers 11, 12, ..., 1m are arranged at intervals from each other and the minimum size of at least two metal backing layers in the row direction is different;
  • i 1,2,...,m, m ⁇ 2.
  • the number of all metal pad layers is equal to the number of increased current paths, and the current of the signal flowing through the metal lines can be dispersed into m+1 current paths , one of the current paths is the current path transmitted from the metal wire to the metal layer, and the remaining m current paths are the current paths transmitted from the metal wire to the m metal pad layers respectively, and at least two metals in the current of the remaining m current paths The pad currents are different.
  • the equivalent circuit diagram corresponding to the third signal routing structure shown in FIG. 8 is the same as that in FIG. 7 .
  • Embodiment 2 of the present application provides a signal routing structure of a display panel, which includes a plurality of metal lines 1 arranged at intervals from each other, metal layers 2 stacked in sequence, and gate insulation layer 3, passivation layer 4 and transparent conductive layer 5, each metal line 1 ends with a metal pad 10;
  • the passivation layer 4 is provided with a plurality of first via holes 6 corresponding to the first positions of all the metal pads 10;
  • the passivation layer 4 and the gate insulating layer 3 are provided with a plurality of second via holes 7 corresponding to the second position of the metal layer 2;
  • the transparent conductive layer 5 includes a plurality of conductive units 50, each conductive unit 50 corresponds to a metal pad 10, a first via hole 6 and a second via hole 7, and each metal pad 10 passes through a first via hole 6 and a second via hole 7.
  • One conductive unit 50 is turned on, and each conductive unit 50 is connected to the metal layer 2 through a second via hole 7;
  • All the conductive units 50 are connected in sequence.
  • the current of the signal flowing through the metal wire can be dispersed into at least two current paths, one of which is the current path transmitted from the metal wire to the metal layer, and the other current
  • the path is the current path that is transmitted from the metal wire to all the conductive units that are connected in sequence.
  • Partial areas of all conductive units are sequentially connected and the minimum width of all connected areas in the row direction is the same;
  • Partial areas of all the conductive units are sequentially connected and at least two connected areas have different minimum widths in the row direction.
  • FIG. 9 and FIG. 10 it exemplarily shows the situation that all regions of all conductive units 50 are sequentially connected.
  • the number of the increased current path depends on the number of connected areas of all the conductive units, the more the number of connected areas, the increased current path The higher the number.
  • the current of the signal flowing in through the metal wire can be dispersed into two current paths, one of which is the current path transmitted from the metal wire to the metal layer, and the other A current path is a current path transmitted from the metal wire to all regions of all conductive units connected in sequence.
  • FIG. 12 it exemplarily shows an equivalent circuit diagram corresponding to the fourth signal wiring structure shown in FIG. 9 and FIG.
  • the equivalent resistance and the equivalent current, the resistance R2 and the current I2 are the equivalent resistance and the equivalent current corresponding to the metal layer 2 respectively, and the resistance R50 and the current I50 are the equivalent resistance corresponding to all the areas of all the conductive units 50 connected in turn. resistance and equivalent current.
  • Fig. 13 Fig. 14 and Fig. 15, it exemplarily shows the case that the partial regions of all conductive units are connected sequentially and the minimum width of all connected regions in the row direction is the same; wherein, the jth of all conductive units 50 The regions are sequentially connected to form the jth sub-transparent conductive layer;
  • All the sub-transparent conductive layers 51, 52, ..., 5n are spaced apart from each other and have the same minimum size in the row direction;
  • j 1,2,...,n, n ⁇ 2.
  • the number of all sub-transparent conductive layers is equal to the number of increased current paths, and the current of the signal flowing through the metal line can be dispersed
  • n+1 current paths one of which is the current path transmitted from the metal wire to the metal layer
  • the remaining n current paths are the current paths respectively transmitted from the metal wire to the n sub-transparent conductive layers, and the remaining n current paths currents are equal.
  • the equivalent resistance and equivalent current corresponding to 1 are the equivalent resistance and the equivalent current corresponding to the metal layer 2
  • the resistance R51 and the current I51 are the equivalent resistance corresponding to the first sub-transparent conductive layer
  • Resistance and equivalent current, resistance R52 and current I52 are the equivalent resistance and equivalent current corresponding to the second sub-transparent conductive layer respectively
  • resistance R5n and current I5n are respectively the equivalent resistance corresponding to the nth sub-transparent conductive layer effective resistance and equivalent current.
  • FIG. 17 it exemplarily shows the situation that the partial regions of all conductive units are connected in sequence and the minimum widths of at least two connected regions in the row direction are different; wherein, the jth regions of all conductive units 50 are connected in sequence Constitute the jth sub-transparent conductive layer;
  • All the sub-transparent conductive layers 51, 52, ..., 5n are arranged at intervals from each other, and the minimum dimensions of at least two sub-transparent conductive layers in the row direction are different;
  • j 1,2,...,n, n ⁇ 2.
  • the number of all sub-transparent conductive layers is equal to the number of increased current paths, and the current of the signal flowing in through the metal line can be dispersed into n+1 currents
  • One of the current paths is the current path transmitted from the metal wire to the metal layer, and the remaining n current paths are the current paths transmitted from the metal wire to the n sub-transparent conductive layers respectively, and at least two sub-transparent conductive layers of the current in the remaining n current paths
  • the current of the transparent conductive layer is different.
  • the equivalent circuit diagram corresponding to the sixth signal routing structure shown in FIG. 17 is the same as that in FIG. 16 .
  • connection structure of any metal pad in Embodiment 1 can be combined with the connection structure of any conductive unit in Embodiment 2, that is, all metal pads and all conductive units can be connected at the same time, No more examples and illustrations are given here.
  • the thickness range of the conductive unit can be set to 500 angstroms (A)-900 angstroms, and the thickness range of the metal pad can be set to 3000 angstroms-7000 angstroms. If the thickness allows, the maximum value of the thickness range can be taken, that is, All conductive elements have a thickness of 900 angstroms and the metal pads have a thickness of 7000 angstroms.
  • Embodiment 3 of the present application provides an array substrate, including a display area 101 and a non-display area 102.
  • a pixel array is provided in the display area 101, and an array substrate in Embodiment 1 or 2 is provided in the non-display area 102.
  • Each metal line 1 is used to electrically connect with a column of pixels 104 of the pixel array.
  • FIG. 18 only exemplarily shows a simplified structural diagram of the signal routing structure 103 .
  • each metal line may also be electrically connected to a row of pixels in the pixel array, and FIG. 18 only shows the case where each metal line is connected to a column of pixels in the pixel array.
  • the array substrate can be any type of array substrate that adopts the above-mentioned signal wiring structure to transmit common voltage signals, data signals or scanning signals, for example, liquid crystal array substrates, thin film transistor liquid crystal array substrates, light emitting diode array substrates, quantum dot light emitting diode arrays Substrate etc.
  • Embodiment 4 of the present application provides a liquid crystal display panel, including the array substrate 100 , the liquid crystal layer 200 and the color filter substrate 300 in Embodiment 3 that are sequentially stacked.
  • the liquid crystal display panel may also include an upper polarizer arranged on the side of the color filter substrate away from the array substrate, and a lower polarizer and a backlight module arranged on the side of the array substrate away from the color filter substrate.
  • the module includes a backlight, a light guide plate, and a diffuser plate.
  • the liquid crystal display panel may be a thin film transistor liquid crystal display panel with higher pixel density and narrower frame.
  • FIG. 19 only exemplarily shows a simplified structural diagram of the array substrate 100 .
  • the signal routing structure, the array substrate and the liquid crystal display panel provided by the embodiments of the present application can disperse the large current flowing into the metal layer from each metal line into at least two currents by connecting all the conductive units and/or connecting all the metal pads. path, reducing the magnitude of the current flowing through each current path, thereby reducing the probability of electrostatic discharge, thereby reducing the probability of damage to electronic components.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请适用于显示技术领域，提供一种信号走线结构（103）及阵列基板（100），包括多条金属线（1）以及依次堆叠设置的金属层（2）、栅绝缘层（3）、钝化层（4）和透明导电层（5），每条金属线（1）的末端为金属垫（10），钝化层（4）对应所有金属垫（10）的第一位置设有多个第一过孔（6）；钝化层（4）和栅绝缘层（3）对应金属层（2）的第二位置设有多个第二过孔（7）；透明导电层（5）包括多个导电单元（50），每个金属垫（10）通过一个第一过孔（6）和一个导电单元（50）导通，每个导电单元（50）通过一个第二过孔（7）和金属层（2）导通；所有金属垫（10）依次连通，和/或，所有导电单元（50）依次连通；将从每条金属线（1）流入金属层（2）的大电流分散为多条电流路径，降低每条电流路径的电流大小，从而降低发生静电释放的几率，进而降低电子元器件的损坏几率。

Description

信号走线结构及阵列基板
本申请要求于2021年08月31日在中国国家专利局提交的、申请号为202111009042.8、申请名称为“信号走线结构及阵列基板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于显示技术领域，尤其涉及一种信号走线结构及阵列基板。
 背景技术
随着显示技术的不断发展，液晶显示（Liquid Crystal Display，LCD）面板、薄膜晶体管（Thin Film Transistor，TFT）液晶显示面板，有机电激光显示（Organic Electroluminesence Display）面板、发光二极管（Light Emitting Diode，LED）面板、量子点发光二极管（Quantum Dot Light Emitting Diodes，QLED）面板等各种类型的显示面板层出不穷。高端显示面板要求有具有较高的像素密度（Pixels Per Inch，PPI）和较窄的边框，所以设计的时候会极致压缩显示面板里的金属信号走线的宽度，导致金属走线较细，这样很容易出现由于静电释放（Electro-Static discharge，ESD）而导致的电子元器件损坏。
 技术问题
本申请实施例的目的之一在于：提供一种信号走线结构及阵列基板，通过依次连通信号走线结构中的所有金属垫，和/或，依次连通信号走线结构中的所有导电单元，可以将从每条金属线流入金属层的大电流分散为至少两条电流路径，以解决显示面板里的金属信号走线的较细，很容易出现由于静电释放而导致的电子元器件损坏的问题。
 技术解决方案
为了解决上述技术问题，本申请实施例采用的技术方案是：
本申请实施例的第一方面提供了一种信号走线结构，包括多条金属线以及依次堆叠设置的金属层、栅绝缘层、钝化层和透明导电层，每条所述金属线的末端为金属垫，所述钝化层对应所有所述金属垫的第一位置设有多个第一过孔；所述钝化层和所述栅绝缘层对应所述金属层的第二位置设有多个第二过孔；其特征在于：
所述透明导电层包括多个导电单元，每个所述导电单元和一个所述金属垫、一个所述第一过孔以及一个所述第二过孔对应，每个所述金属垫通过一个所述第一过孔和一个所述导电单元导通，每个所述导电单元通过一个所述第二过孔和所述金属层导通；且所有所述金属垫依次连通，和/或，所有所述导电单元依次连通。
在一个实施例中，所有所述金属垫的全部区域依次连通。
在一个实施例中，经由所述金属线流入的信号的电流被分散为两条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，另一条电流路径为从所述金属线传输至依次连通的所有所述金属垫的全部区域的电流路径。
在一个实施例中，所有所述金属垫的第i个区域依次连通构成第i个金属垫层；
所有所述金属垫层相互间隔设置且在行方向上的最小尺寸相同；
其中，i=1,2,…,m，m≥2。
在一个实施例中，经由所述金属线流入的信号的电流被分散为m+1条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，剩余m条电流路径为从所述金属线分别传输至m个所述金属垫层的电流路径，剩余m条电流路径的电流相等。
在一个实施例中，所有所述金属垫的第i个区域依次连通构成第i个金属垫层；
所有所述金属垫层相互间隔设置且至少两个所述金属垫层在行方向上的最小尺寸相异；
其中，i=1,2,…,m，m≥2。
在一个实施例中，经由所述金属线流入的信号的电流被分散为m+1条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，剩余m条电流路径为从所述金属线分别传输至m个所述金属垫层的电流路径，剩余m条电流路径的电流中至少两个所述金属垫层的电流相异。
在一个实施例中，所有所述导电单元的全部区域依次连通。
在一个实施例中，经由所述金属线流入的信号的电流被分散为两条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，另一条电流路径为从所述金属线传输至依次连通的所有所述导电单元的全部区域的电流路径。
在一个实施例中，所有所述导电单元的第j个区域依次连通构成第j个子透明导电层；
所有所述子透明导电层相互间隔设置且在行方向上的最小尺寸相同；
其中，j=1,2,…,n，n≥2。
在一个实施例中，经由所述金属线流入的信号的电流被分散为n+1条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，剩余n条电流路径为从所述金属线分别传输至n个所述子透明导电层的电流路径，剩余n条电流路径的电流相等。
在一个实施例中，所有所述导电单元的第j个区域依次连通构成第j个子透明导电层；
所有所述子透明导电层相互间隔设置且至少两个所述子透明导电层在行方向上的最小尺寸相异；
其中，j=1,2,…,n，n≥2。
在一个实施例中，经由所述金属线流入的信号的电流被分散为n+1条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，剩余n条电流路径为从所述金属线分别传输至n个所述子透明导电层的电流路径，剩余n条电流路径的电流中至少两个所述子透明导电层的电流相异。
在一个实施例中，所述金属线为公共电压信号线、数据信号线或扫描信号线。
在一个实施例中，所述导电单元的厚度范围为500埃-900埃；
所述金属垫的厚度范围为3000埃-7000埃。
在一个实施例中，所述导电单元的厚度为900埃，所述金属垫的厚度为7000埃。
在一个实施例中，应用于阵列基板，所述金属垫作为所述金属线与所述金属层之间的转接结构，所有所述金属垫沿所述金属层的长度方向依次排布且相互间隔设置，所述钝化层设置于所述金属层与所有所述金属垫之间。
本申请实施例的第二方面提供一种阵列基板，包括显示区和非显示区域，在显示区内设有像素阵列，在非显示区域内设有本申请实施例的第一方面提供的信号走线结构，每条所述金属线与所述像素阵列的一行或一列像素电连接。
在一个实施例中，所述阵列基板为液晶阵列基板、薄膜晶体管液晶阵列基板、发光二极管阵列基板或量子点发光二极管阵列基板。
 有益效果
本申请实施例的第一方面提供的信号走线结构，包括多条金属线以及依次堆叠设置的金属层、栅绝缘层、钝化层和透明导电层，每条金属线的末端为金属垫，钝化层对应所有金属垫的第一位置设有多个第一过孔；钝化层和绝缘层对应金属层的第二位置设有多个第二过孔；透明导电层包括多个导电单元，每个导电单元和一个金属垫、一个第一过孔以及一个第二过孔对应，每个金属垫通过一个第一过孔和一个导电单元导通，每个导电单元通过一个第二过孔和金属层导通；且所有金属垫依次连通，和/或，所有导电单元依次连通，通过依次连通所有金属垫和/或依次连通所有导电单元，可以将从每条金属线流入金属层的大电流分散为至少两条电流路径，降低流经每条电流路径的电流大小，从而降低发生静电释放的几率，进而降低电子元器件的损坏几率。
可以理解的是，上述第二方面的有益效果可以参见上述第一方面中的相关描述，在此不再赘述。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例一提供的第一种信号走线结构的透视图；
图2是本申请实施例一提供的第一种信号走线结构的A-A剖视图；
图3是本申请实施例一提供的第一种信号走线结构的B-B剖视图；
图4是本申请实施例一提供的第一种信号走线结构的等效电路原理图；
图5是本申请实施例一提供的第二种信号走线结构的透视图；
图6是本申请实施例一提供的第二种信号走线结构的A-A剖视图；
图7是本申请实施例一提供的第二种信号走线结构的等效电路原理图；
图8是本申请实施例一提供的第三种信号走线结构的透视图；
图9是本申请实施例二提供的第四种信号走线结构的示意图；
图10是本申请实施例二提供的第四种信号走线结构的A-A剖视图；
图11是本申请实施例二提供的第四种信号走线结构的B-B剖视图；
图12是本申请实施例二提供的第四种信号走线结构的等效电路原理图；
图13是本申请实施例二提供的第五种信号走线结构的示意图；
图14是本申请实施例二提供的第五种信号走线结构的A-A剖视图；
图15是本申请实施例二提供的第五种信号走线结构的B-B剖视图；
图16是本申请实施例二提供的第五种信号走线结构的等效电路原理图；
图17是本申请实施例二提供的第六种信号走线结构的示意图；
图18为本申请实施例三提供的阵列基板的结构示意图；
图19为本申请实施例四提供的液晶显示面板的结构示意图。
附图标号：
金属线：1；金属垫：10；金属垫层：11~1m；金属层：2；栅绝缘层：3；钝化层：4；透明导电层：5；导电单元：50；子透明导电层：51~5n；第一过孔：6；第二过孔：7；显示区：101；非显示区：102；信号走线结构：103；像素：104；阵列基板：100；液晶层：200；彩膜基板：300。
 本发明的实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申请。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
还应当理解，在本申请说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
另外，在本申请说明书和所附权利要求书的描述中，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
在本申请说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。“多个”是指两个及两个以上。
实施例一
如图1、图2或图3所示，本申请实施例一提供一种显示面板的信号走线结构，其包括相互间隔设置的多条金属线1以及依次堆叠设置的金属层2、栅绝缘层（Gate Insulator，GI）3和钝化层（passivation layer）4和透明导电层5，每条金属线1的末端为金属垫10；
钝化层4对应所有金属垫10的第一位置设有多个第一过孔6；
钝化层4和栅绝缘层3对应金属层2的第二位置设有多个第二过孔7；
透明导电层5包括多个导电单元50，每个导电单元50和一个金属垫10、一个第一过孔6以及一个第二过孔7对应，每个金属垫10通过一个第一过孔6和一个导电单元50导通，每个导电单元50通过一个第二过孔7和金属层2导通；所有金属垫10依次连通。
在应用中，金属层、金属线和金属垫可以由任意电的良导体材料构成，例如，铝（Al）、铜（Au）、银（Ag）等。金属线和末端由相同材料构成，每条金属线与其末端的金属垫可以为一体化成型结构，金属垫作为金属线与金属层之间的转接结构。所有金属垫沿金属层的长度方向依次排布且相互间隔设置。
在应用中，金属线可以为用于传输公共电压（Vcom）信号的公共电压信号线、用于传输数据（Data）信号的数据信号线或用于传输扫描（Scan）信号的扫描信号线。
在应用中，金属层和钝化层为具有一定宽度的条状结构。钝化层设置于金属层与所有金属垫之间，钝化层的长度需要大于或等于所有金属垫在金属层的长度方向上的排布长度，钝化层的宽度需要大于或等于金属垫的宽度，如此，才能完全起到绝缘和保护作用。
在应用中，钝化层可以由任意电的不良导体材料构成，例如，氮化硅（SiNx）层、氧化硅（SiOx）层或氮化硅和氧化硅的组合层。钝化层既用于作为具有一定强度的保护层，也具有绝缘作用。
在应用中，每个导电单元都可以通过透明电极实现，例如，氧化铟锡（Indium Tin Oxide，ITO）电极、掺铝氧化锌（AZO）电极或氧化锌（ZnO）电极等。
在应用中，栅绝缘层的第一区域和第二区域以及钝化层的第一区域和第二区域都沿金属层的宽度方向并排设置，第一区域和第二区域的长度都大于或等于金属层的长度，以使得第一区域和第二区域并排设置之后可以完全覆盖金属层。
在应用中，钝化层中与多个金属垫对应的第一位置处开设有多个第一过孔，第一过孔沿垂直于金属层的表面的方向贯穿钝化层，钝化层和栅绝缘层中与金属层对应的第二位置处设有多个第二过孔，第二过孔沿垂直于金属层的表面的方向贯穿钝化层和栅绝缘层，所有金属垫、所有导电单元、所有第一过孔、以及所有第二过孔的数量相等，每个导电单元和一个金属垫、一个第一过孔以及一个第二过孔对应，每个金属垫通过一个第一过孔和一个导电单元导通，每个导电单元通过一个第二过孔和金属层导通，如此，可以将经由每条金属线流入的信号依次通过一个金属垫和一个导电单元传输至金属层。
在应用中，通过将所有金属垫依次连通，使得经由金属线流入的信号的电流可以被分散为至少两条电流路径，其中一条电流路径为从金属线传输至金属层的电流路径，其他条电流路径为从金属线传输至依次连通的所有金属垫的电流路径，如此，可以降低流经每条电流路径的电流大小，从而降低发生静电释放的几率，进而降低电子元器件的损坏几率。
在应用中，所有金属垫依次连通的方式包括如下三种情况：
一、所有金属垫的全部区域依次连通；
二、所有金属垫的部分区域依次连通且所有连通区域在行方向上的最小宽度相同；
三、所有金属垫的部分区域依次连通且至少两个连通区域在行方向上的最小宽度相异。
如图1和图2所示，示例性的示出了所有金属垫10的全部区域依次连通的情况。
在应用中，通过依次连通所有金属垫来增加电流路径时，所增加的电流路径的数量取决于所有金属垫被连通的区域的数量，被连通的区域的数量越多，所增加的电流路径的数量越多。基于图1和图2所示的所有金属垫的连通情况，经由金属线流入的信号的电流可以被分散为两条电流路径，其中一条电流路径为从金属线传输至金属层的电流路径，另一条电流路径为从金属线传输至依次连通的所有金属垫的全部区域的电流路径。
如图4所示，示例性的示出了与图1、图2和图3所示的第一种信号走线结构对应的等效电路原理图，其中，电阻R1和电流I1分别为与一条金属线1对应的等效电阻和等效电流，电阻R2和电流I2分别为与金属层2对应的等效电阻和等效电流，电阻R10和电流I10为与依次连通的所有金属垫10的全部区域对应的等效电阻和等效电流。
如图5和图6所示，示例性的示出了所有金属垫的部分区域依次连通且所有连通区域在行方向上的最小宽度相同的情况；其中，所有金属垫10的第i个区域依次连通构成第i个金属垫层；
所有金属垫层11、12、…、1m相互间隔设置且在行方向上的最小尺寸相同；
其中，i=1,2,…,m，m≥2。
在应用中，基于图5和图6所示的所有金属垫的连通情况，所有金属垫层的数量等于所增加的电流路径的数量，经由金属线流入的信号的电流可以被分散为m+1条电流路径，其中一条电流路径为从金属线传输至金属层的电流路径，剩余m条电流路径为从金属线分别传输至m个金属垫层的电流路径，剩余m条电流路径的电流相等。
如图7所示，示例性的示出了与图5和图6所示的第二种信号走线结构对应的等效电路原理图，其中，电阻R1和电流I1分别为与一条金属线1对应的等效电阻和等效电流，电阻R2和电流I2分别为与金属层2对应的等效电阻和等效电流，电阻R11和电流I11分别为与第1个金属垫层对应的等效电阻和等效电流，电阻R12和电流I12分别为与第2个金属垫层对应的等效电阻和等效电流，……，电阻R1m和电流I1m分别为与第m个金属垫层对应的等效电阻和等效电流。
如图8所示，示例性的示出了所有金属垫的部分区域依次连通且至少两个连通区域在行方向上的最小宽度相异的情况；其中，所有金属垫10的第i个区域依次连通构成第i个金属垫层；
所有金属垫层11、12、…、1m相互间隔设置且至少两个金属垫层在行方向上的最小尺寸相异；
其中，i=1,2,…,m，m≥2。
在应用中，基于图8所示的所有金属垫的连通情况，所有金属垫层的数量等于所增加的电流路径的数量，经由金属线流入的信号的电流可以被分散为m+1条电流路径，其中一条电流路径为从金属线传输至金属层的电流路径，剩余m条电流路径为从金属线分别传输至m个金属垫层的电流路径，剩余m条电流路径的电流中至少两个金属垫层的电流相异。与图8所示的第三种信号走线结构对应的等效电路图与图7相同。
实施例二
如图9、图10或图11所示，本申请实施例二提供一种显示面板的信号走线结构，其包括相互间隔设置的多条金属线1以及依次堆叠设置的金属层2、栅绝缘层3和钝化层4和透明导电层5，每条金属线1的末端为金属垫10；
钝化层4对应所有金属垫10的第一位置设有多个第一过孔6；
钝化层4和栅绝缘层3对应金属层2的第二位置设有多个第二过孔7；
透明导电层5包括多个导电单元50，每个导电单元50和一个金属垫10、一个第一过孔6以及一个第二过孔7对应，每个金属垫10通过一个第一过孔6和一个导电单元50导通，每个导电单元50通过一个第二过孔7和金属层2导通；
所有导电单元50依次连通。
在应用中，通过将所有导电单元依次连通，使得经由金属线流入的信号的电流可以被分散为至少两条电流路径，其中一条电流路径为从金属线传输至金属层的电流路径，其他条电流路径为从金属线传输至依次连通的所有导电单元的电流路径，如此，可以降低流经每条电流路径的电流大小，从而降低发生静电释放的几率，进而降低电子元器件的损坏几率。
在应用中，所有导电单元依次连通的方式包括如下三种情况：
一、所有导电单元的全部区域依次连通；
二、所有导电单元的部分区域依次连通且所有连通区域在行方向上的最小宽度相同；
三、所有导电单元的部分区域依次连通且至少两个连通区域在行方向上的最小宽度相异。
如图9和图10所示，示例性的示出了所有导电单元50的全部区域依次连通的情况。
在应用中，通过依次连通所有导电单元来增加电流路径时，所增加的电流路径的数量取决于所有导电单元被连通的区域的数量，被连通的区域的数量越多，所增加的电流路径的数量越多。基于图9和图10所示的所有导电单元的连通情况，经由金属线流入的信号的电流可以被分散为两条电流路径，其中一条电流路径为从金属线传输至金属层的电流路径，另一条电流路径为从金属线传输至依次连通的所有导电单元的全部区域的电流路径。
如图12所示，示例性的示出了与图9和图10所示的第四种信号走线结构对应的等效电路图，其中，电阻R1和电流I1分别为与一条金属线1对应的等效电阻和等效电流，电阻R2和电流I2分别为与金属层2对应的等效电阻和等效电流，电阻R50和电流I50为与依次连通的所有导电单元50的全部区域对应的等效电阻和等效电流。
如图13、图14和图15所示，示例性的示出了所有导电单元的部分区域依次连通且所有连通区域在行方向上的最小宽度相同的情况；其中，所有导电单元50的第j个区域依次连通构成第j个子透明导电层；
所有子透明导电层51、52、…、5n相互间隔设置且在行方向上的最小尺寸相同；
其中，j=1,2,…,n，n≥2。
在应用中，基于图13、图14和图15所示的所有导电单元的连通情况，所有子透明导电层的数量等于所增加的电流路径的数量，经由金属线流入的信号的电流可以被分散为n+1条电流路径，其中一条电流路径为从金属线传输至金属层的电流路径，剩余n条电流路径为从金属线分别传输至n个子透明导电层的电流路径，剩余n条电流路径的电流相等。
如图16所示，示例性的示出了与图13、图14和图15所示的第五种信号走线结构对应的等效电路图，其中，电阻R1和电流I1分别为与一条金属线1对应的等效电阻和等效电流，电阻R2和电流I2分别为与金属层2对应的等效电阻和等效电流，电阻R51和电流I51分别为与第1个子透明导电层对应的等效电阻和等效电流，电阻R52和电流I52分别为与第2个子透明导电层对应的等效电阻和等效电流，……，电阻R5n和电流I5n分别为与第n个子透明导电层对应的等效电阻和等效电流。
如图17所示，示例性的示出了所有导电单元的部分区域依次连通且至少两个连通区域在行方向上的最小宽度相异的情况；其中，所有导电单元50的第j个区域依次连通构成第j个子透明导电层；
所有子透明导电层51、52、…、5n相互间隔设置且至少两个子透明导电层在行方向上的最小尺寸相异；
其中，j=1,2,…,n，n≥2。
在应用中，基于图17所示的所有导电单元的连通情况，所有子透明导电层的数量等于所增加的电流路径的数量，经由金属线流入的信号的电流可以被分散为n+1条电流路径，其中一条电流路径为从金属线传输至金属层的电流路径，剩余n条电流路径为从金属线分别传输至n个子透明导电层的电流路径，剩余n条电流路径的电流中至少两个子透明导电层的电流相异。与图17所示的第六种信号走线结构对应的等效电路图与图16相同。
在应用中，实施例一中的任一种金属垫的连通结构可以与实施例二中的任一种导电单元的连通结构进行组合设置，也即可以同时连通所有金属垫并连通所有导电单元，此处不再举例和示意。
在应用中，由于显示面板的大小通常是固定的，为了实现窄边框、增大像素密度，有些类型的显示面板（例如，薄膜晶体管液晶显示面板）通常会在压缩金属线的走线宽度的情况，同时也在一定程度上压缩金属层的宽度，因此，为了在保证金属层及堆叠设置于金属层的栅绝缘层、钝化层、导电单元和金属垫的宽度不变的情况下，提高导电能力，可以通过提高导电单元和/或金属垫的厚度来实现，厚度越厚，导电能力越强。例如，导电单元的厚度范围可以设置为500埃（A）-900埃，金属垫的厚度范围可以设置为3000埃-7000埃，在厚度允许的情况下，可以取厚度范围的最大值，也即所有导电单元的厚度为900埃，金属垫的厚度为7000埃。
实施例三
如图18所示，本申请实施三提供一种阵列基板，包括显示区101和非显示区102，在显示区101内设有像素阵列，在非显示区102内设有实施例一或二中的信号走线结构103，每条金属线1用于与像素阵列的一列像素104电连接。
应理解，图18中为了便于示意而仅示例性的示出信号走线结构103的简化结构示意图。
在应用中，每条金属线也可以与像素阵列的一行像素电连接，图18中仅示出每条金属线与像素阵列的一列像素连接的情况。阵列基板可以是任意类型的采用上述信号走线结构来传输公共电压信号、数据信号或扫描信号的阵列基板，例如，液晶阵列基板、薄膜晶体管液晶阵列基板、发光二极管阵列基板、量子点发光二极管阵列基板等。
实施例四
如图19所示，本申请实施例四提供一种液晶显示面板，包括依次层叠设置的实施例三中的阵列基板100、液晶层200和彩膜基板300。
在应用中，液晶显示面板还可以包括设置于彩膜基板远离阵列基板所在的一侧的上偏光板，以及设置于阵列基板远离彩膜基板所在的一侧的下偏光板和背光模组，背光模组包括背光源、导光板、扩散板。液晶显示面板可以是具有较高的像素密度和较窄的边框的薄膜晶体管液晶显示面板。
应理解，图19中为了便于示意而仅示例性的示出阵列基板100的简化结构示意图。
本申请实施例提供的信号走线结构、阵列基板及液晶显示面板，通过连通所有导电单元和/或连通所有金属垫，可以将从每条金属线流入金属层的大电流分散为至少两条电流路径，降低流经每条电流路径的电流大小，从而降低发生静电释放的几率，进而降低电子元器件的损坏几率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种信号走线结构，包括多条金属线以及依次堆叠设置的金属层、栅绝缘层、钝化层和透明导电层，每条所述金属线的末端为金属垫，所述钝化层对应所有所述金属垫的第一位置设有多个第一过孔；所述钝化层和所述栅绝缘层对应所述金属层的第二位置设有多个第二过孔；其特征在于：
    所述透明导电层包括多个导电单元，每个所述导电单元和一个所述金属垫、一个所述第一过孔以及一个所述第二过孔对应，每个所述金属垫通过一个所述第一过孔和一个所述导电单元导通，每个所述导电单元通过一个所述第二过孔和所述金属层导通；且所有所述金属垫依次连通，和/或，所有所述导电单元依次连通。
  2. 如权利要求1所述的信号走线结构，其特征在于，所有所述金属垫的全部区域依次连通。
  3. 如权利要求2所述的信号走线结构，其特征在于，经由所述金属线流入的信号的电流被分散为两条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，另一条电流路径为从所述金属线传输至依次连通的所有所述金属垫的全部区域的电流路径。
  4. 如权利要求1所述的信号走线结构，其特征在于，所有所述金属垫的第i个区域依次连通构成第i个金属垫层；
    所有所述金属垫层相互间隔设置且在行方向上的最小尺寸相同；
    其中，i=1,2,…,m，m≥2。
  5. 如权利要求4所述的信号走线结构，其特征在于，经由所述金属线流入的信号的电流被分散为m+1条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，剩余m条电流路径为从所述金属线分别传输至m个所述金属垫层的电流路径，剩余m条电流路径的电流相等。
  6. 如权利要求1所述的信号走线结构，其特征在于，所有所述金属垫的第i个区域依次连通构成第i个金属垫层；
    所有所述金属垫层相互间隔设置且至少两个所述金属垫层在行方向上的最小尺寸相异；
    其中，i=1,2,…,m，m≥2。
  7. 如权利要求6所述的信号走线结构，其特征在于，经由所述金属线流入的信号的电流被分散为m+1条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，剩余m条电流路径为从所述金属线分别传输至m个所述金属垫层的电流路径，剩余m条电流路径的电流中至少两个所述金属垫层的电流相异。
  8. 如权利要求1所述的信号走线结构，其特征在于，所有所述导电单元的全部区域依次连通。
  9. 如权利要求8所述的信号走线结构，其特征在于，经由所述金属线流入的信号的电流被分散为两条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，另一条电流路径为从所述金属线传输至依次连通的所有所述导电单元的全部区域的电流路径。
  10. 如权利要求1所述的信号走线结构，其特征在于，所有所述导电单元的第j个区域依次连通构成第j个子透明导电层；
    所有所述子透明导电层相互间隔设置且在行方向上的最小尺寸相同；
    其中，j=1,2,…,n，n≥2。
  11. 如权利要求10所述的信号走线结构，其特征在于，经由所述金属线流入的信号的电流被分散为n+1条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，剩余n条电流路径为从所述金属线分别传输至n个所述子透明导电层的电流路径，剩余n条电流路径的电流相等。
  12. 如权利要求1所述的信号走线结构，其特征在于，所有所述导电单元的第j个区域依次连通构成第j个子透明导电层；
    所有所述子透明导电层相互间隔设置且至少两个所述子透明导电层在行方向上的最小尺寸相异；
    其中，j=1,2,…,n，n≥2。
  13. 如权利要求12所述的信号走线结构，其特征在于，经由所述金属线流入的信号的电流被分散为n+1条电流路径，其中一条电流路径为从所述金属线传输至所述金属层的电流路径，剩余n条电流路径为从所述金属线分别传输至n个所述子透明导电层的电流路径，剩余n条电流路径的电流中至少两个所述子透明导电层的电流相异。
  14. 如权利要求1所述的信号走线结构，其特征在于，所述金属线为公共电压信号线、数据信号线或扫描信号线。
  15. 如权利要求1所述的信号走线结构，其特征在于，所述导电单元的厚度范围为500埃-900埃；
    所述金属垫的厚度范围为3000埃-7000埃。
  16. 如权利要求15所述的信号走线结构，其特征在于，所述导电单元的厚度为900埃，所述金属垫的厚度为7000埃。
  17. 如权利要求1所述的信号走线结构，其特征在于，应用于阵列基板，所述金属垫作为所述金属线与所述金属层之间的转接结构，所有所述金属垫沿所述金属层的长度方向依次排布且相互间隔设置，所述钝化层设置于所述金属层与所有所述金属垫之间。
  18. 一种阵列基板，其特征在于，包括显示区和非显示区域，在显示区内设有像素阵列，在非显示区域内设有如权利要求1所述的信号走线结构，每条所述金属线用于与所述像素阵列的一行或一列像素电连接。
  19. 如权利要求18所述的阵列基板，其特征在于，所述阵列基板为液晶阵列基板、薄膜晶体管液晶阵列基板、发光二极管阵列基板或量子点发光二极管阵列基板。
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