WO2023019694A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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WO2023019694A1
WO2023019694A1 PCT/CN2021/121365 CN2021121365W WO2023019694A1 WO 2023019694 A1 WO2023019694 A1 WO 2023019694A1 CN 2021121365 W CN2021121365 W CN 2021121365W WO 2023019694 A1 WO2023019694 A1 WO 2023019694A1
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oxide layer
thermal oxidation
semiconductor structure
oxidation reaction
trench
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French (fr)
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张黎
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长鑫存储技术有限公司
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    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02241—III-V semiconductor

Definitions

  • the present disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
  • the memory includes multiple storage units, and each storage unit includes a MOS transistor and a storage capacitor.
  • the MOS transistor is the abbreviation of Metal-Oxide-Semi-conductor Field Effect Transistor (Metal-Oxide-Semi-conductor Field Effect Transistor).
  • the purpose of the present disclosure is to provide a semiconductor structure and its preparation method to at least solve the problem of reduced yield of existing semiconductor devices due to the short channel effect.
  • a method for preparing a semiconductor structure may include: providing a substrate; forming a trench in the substrate; and performing a first thermal oxidation reaction in an environment with a pressure of 500-800 Torr A first oxide layer is formed on the bottom and sidewalls of the trench, and the thickness of the first oxide layer gradually decreases along a direction close to the bottom.
  • reaction temperature of the first thermal oxidation reaction may be 800-1100 degrees Celsius.
  • the gas in the first thermal oxidation reaction may include: O 2 , H 2 , and N 2 ; wherein, the flow ratio of the H 2 to the N 2 satisfies the following formula :
  • Q H2 is the flow rate of H 2 introduced into the first thermal oxidation reaction
  • Q N2 is the flow rate of N 2 introduced into the first thermal oxidation reaction
  • the gas for the first thermal oxidation reaction may include: O 2 , H 2 , and an inert gas; wherein, the flow ratio of the H 2 to the inert gas satisfies the following formula :
  • Q H2 is the flow rate of the H 2 fed into the first thermal oxidation reaction
  • Q inert is the flow rate of the inert gas fed into the first thermal oxidation reaction
  • the preparation method may further include: annealing the first oxide layer.
  • the preparation method may further include: performing a second thermal oxidation reaction at a preset pressure on the first oxide layer to form a second oxide layer, the preset pressure being less than The reaction pressure of the first thermal oxidation reaction;
  • reaction temperature of the second thermal oxidation reaction may be 800-1100 degrees Celsius.
  • the preset pressure may be 0-20 Torr.
  • the gas for the second thermal oxidation reaction may include oxygen-containing gas and H2.
  • the flow ratio of the H2 to the oxygen-containing gas may satisfy the following formula:
  • Q H2 is the flow rate of the H 2 passed into the second thermal oxidation reaction
  • the Q contains is the flow rate of the oxygen-containing gas passed into the second thermal oxidation reaction.
  • a thickness ratio of the first oxide layer to the second oxide layer may range from 1/4 to 2/3.
  • the preparation method may further include: forming a barrier layer on the surface of the second oxide layer; filling the trench with conductive metal, the conductive metal covering the barrier layer; layer surface.
  • a semiconductor structure which may include: a substrate having a trench; a first oxide layer covering the bottom and sidewalls of the trench, the first oxide layer The thickness of the layer decreases gradually towards the bottom.
  • the semiconductor structure may further include: a second oxide layer covering the surface of the first oxide layer; a barrier layer covering the surface of the second oxide layer; a conductive metal, Filling in the groove, the conductive metal covers the surface of the barrier layer.
  • the first oxide layer and the second oxide layer may serve as gate dielectric layers.
  • the method of the embodiment of the present disclosure provides a substrate, forms a trench in the substrate, and performs a first thermal oxidation reaction under an environment with a pressure of 500-800 Torr to form a first oxide layer on the bottom and sidewall of the trench, the first
  • the thickness of the oxide layer decreases gradually along the direction close to the bottom.
  • the thickness of the oxide layer obtained by this method gradually decreases along the edge of the groove toward the bottom, so that the oxide layer inside the groove is covered in steps.
  • the obtained oxide layer structure in the embodiment of the present disclosure can be used as the gate dielectric layer of the semiconductor storage device, and then can form the gate structure with the barrier layer and the conductive metal, and form the word line structure.
  • the thicker sidewall can reduce gate leakage, and the thinner bottom can strengthen the control ability of the gate. Therefore, this method can improve the reliability of the semiconductor structure and improve the product yield.
  • FIG. 1 is a schematic flow chart of a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure
  • 2-6 are structure change diagrams of the fabrication process of a semiconductor structure according to an exemplary embodiment of the present disclosure
  • FIG. 7 is a schematic flow chart of a method for preparing a semiconductor structure according to another exemplary embodiment of the present disclosure
  • FIGS. 8-9 are structure change diagrams of the fabrication process of a semiconductor structure according to another exemplary embodiment of the present disclosure.
  • 10-12 are schematic diagrams of a semiconductor structure of an exemplary embodiment of the present disclosure.
  • the size of memory devices will become smaller and smaller, and the channel length of field effect transistors will also be shortened.
  • the short channel effect will lead to device failure and lower yield.
  • the groove structure is obtained on the silicon substrate by etching, and then the side wall and bottom of the groove structure are formed with uniform thickness by thermal oxidation process. oxide layer.
  • this method makes the sidewall silicon lattice obtained by etching easy to be damaged, which easily leads to gate leakage, thereby resulting in a decrease in yield.
  • the present disclosure provides a word line structure and a manufacturing method thereof, a semiconductor structure and a manufacturing method thereof to solve this problem.
  • a method for preparing a semiconductor is provided, and the method may include:
  • the oxygen concentration in the region from the top to the bottom of the groove 11 is gradually reduced, and then the concentration of oxygen on the inner wall of the groove 11 is gradually reduced.
  • the thickness of the formed first oxide layer 21 is covered in steps. As shown in FIG. 4, a first oxide layer 21 with different thicknesses is formed on the sidewall and bottom of the trench 11.
  • the first oxide layer 21 at the sidewall has an ideal thickness, which can avoid some defects caused by etching the substrate to obtain the trench 11.
  • the first oxide layer 21 can effectively reduce gate leakage, and the thickness of the first oxide layer 21 at the bottom is relatively thin, which can strengthen the control ability of the gate, improve the reliability of the word line structure, and further improve the semiconductor structure.
  • Product yield is
  • step S110 is implemented: providing a substrate 1 , as shown in FIG. 2 .
  • the material of the substrate 1 in this step includes but is not limited to silicon crystal or germanium crystal, silicon on insulator (Silicon On Insulator, SOI) structure or epitaxial layer structure on silicon, compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium), alloy semiconductors (such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP, or combinations thereof).
  • Step S120 is implemented: forming a trench 11 in the substrate 1 , as shown in FIG. 3 .
  • a mask can be formed on the substrate 1, and a trench 11 is formed on the substrate 1 by photolithography and etching processes.
  • the trench 11 can be a word line trench, so that subsequent steps can be performed in the word line trench.
  • other semiconductor structures may be formed in the substrate 1 , which is not limited herein.
  • an oxide isolation layer is formed on the surface of the substrate 1 , and the oxide isolation layer does not cover the inner surface of the trench 11 , but only covers the upper surface of the substrate 1 .
  • the oxide isolation layer can protect the upper surface of the substrate 1 from being etched in subsequent processes.
  • the buried word line is used to solve the short channel effect.
  • the trench 11 is formed on the substrate 1 by etching.
  • the substrate 1 with the trench 11 is obtained.
  • the substrate of this embodiment is a silicon crystal substrate.
  • the silicon lattice on the sidewall of the trench 11 obtained by etching is easily damaged, and the damage to the silicon lattice easily leads to gate leakage. This further leads to a decrease in the yield of the semiconductor device. Therefore, in order to solve this problem, the next step S130 is introduced.
  • step S130 performing a first thermal oxidation reaction in an environment with a pressure of 500-800 Torr to form a first oxide layer 21 on the bottom and sidewalls of the trench 11, and the thickness of the first oxide layer 21 gradually increases along the direction close to the bottom. decrease, as shown in the partially enlarged area A in Fig. 4.
  • the first oxide layer 21 is formed on the inner wall surface of the trench 11.
  • the first oxide layer 21 can effectively prevent the silicon lattice from being damaged, thereby preventing leakage. happened.
  • Forming the first oxide layer 21 on the surface of the inner wall of the trench 11 can be carried out by performing a first thermal oxidation reaction in an environment with a pressure of 500-800 torr to form the first oxide layer 21 inside the trench 11.
  • the distribution of the reaction gas in the groove 11 is not uniform, the concentration of the reaction gas is higher near the notch of the groove 11, and the bottom of the groove 11
  • the concentration of the reaction gas is relatively low, therefore, during the thermal oxidation reaction process, an oxide layer with a gradient decrease in thickness will be formed on the inner wall of the groove 11, and the thickness of the oxide layer in the groove 11 extends toward the groove 11 along the edge of the groove. The thickness of the oxide layer decreases gradually towards the bottom.
  • the reaction temperature of the first thermal oxidation reaction can be 800-1100 degrees Celsius, for example, the reaction temperature can be 800 degrees Celsius, 850 degrees Celsius, 900 degrees Celsius, 950 degrees Celsius, 1000 degrees Celsius, 1050 degrees Celsius, 1100 degrees Celsius.
  • the oxide layer formed in the range of 800-1100 degrees Celsius is relatively dense, which can effectively prevent leakage.
  • the gas for the first thermal oxidation reaction may include: O 2 , H 2 , and N 2 ; wherein, the flow ratio of H 2 and N 2 satisfies the following formula:
  • Q H2 is the flow rate of H2 for the first thermal oxidation reaction
  • Q N2 is the flow rate of N2 for the first thermal oxidation reaction.
  • This formula can indicate that the flow rate of hydrogen gas is less than the percentage of the total flow rate of hydrogen gas and nitrogen gas.
  • the flow of hydrogen accounts for the percentage of the total flow of hydrogen and nitrogen and can represent the concentration of hydrogen, so this formula can also represent that the concentration of hydrogen is less than 4 percent; the flow ratio of said H and N can be the first to complete
  • the flow ratio of the growth process of the oxide layer 21 is, for example, 2% or 3%.
  • H 2 and N 2 within the above range are intermittently fed into the atmosphere of O 2 , so as to adjust the gradient thickness of the first oxide layer 21 and reduce film defects.
  • the reaction gas of the first thermal oxidation reaction may also include: O 2 , H 2 , and an inert gas; wherein, the flow ratio of the H 2 to the inert gas satisfies the following formula:
  • Q H2 is the flow rate of the first thermal oxidation reaction into the H 2
  • Q is inert is the flow rate of the first thermal oxidation reaction into the inert gas
  • this formula can represent that the flow rate of the hydrogen gas into Three percent of the total flow
  • the percentage of the flow of hydrogen to the total flow of hydrogen and inert gas can represent the concentration of hydrogen, so this formula can also represent that the concentration of hydrogen is less than three percent
  • the ratio may be a flow ratio for completing the growth process of the first oxide layer 21 , for example, 2%, 2.5%.
  • the inert gas can enumerate Ar, Ne, He, adjust and form the gradient thickness of the first oxide layer 21 and reduce film defects.
  • the first thermal oxidation reaction is, for example, an in-situ water vapor oxidation reaction
  • the reaction pressure is carried out under normal pressure conditions, such as 760 Torr
  • the reaction temperature is 900 degrees Celsius
  • the reaction gas includes: H 2 , N 2 and oxidant O 2 , wherein the flow ratio of H 2 and N 2 is 3%.
  • O 2 is fed continuously, and H 2 and N 2 are fed intermittently.
  • a dense oxide dielectric layer is formed on the bottom and sidewalls of the trench 11 in the semiconductor structure, and the thickness of the oxide dielectric layer gradually decreases along the direction close to the bottom. It can effectively reduce the sidewall leakage of the trench 11 and increase the electric field control capability.
  • the first thermal oxidation reaction is an in-situ water vapor oxidation reaction
  • the reaction pressure is carried out under normal pressure conditions, such as 760 Torr, and the reaction temperature of the in-situ water vapor oxidation is 900 degrees Celsius;
  • the reacting gas includes: Ar, H 2 and oxidant O 2 , wherein the flow ratio of H 2 to Ar is 2%.
  • O 2 was fed continuously, and Ar and H 2 were fed intermittently.
  • a dense oxide dielectric layer is formed on the bottom and sidewalls of the trench 11 in the semiconductor structure, and the thickness of the oxide dielectric layer gradually decreases along the direction close to the bottom. It can effectively reduce the sidewall leakage of the trench 11 and increase the electric field control capability.
  • the quality of the first oxide layer 21 is improved, and the preparation of the semiconductor structure
  • the method may also include: annealing the first oxide layer 21 to increase the density of the first oxide layer 21.
  • the annealing temperature is, for example, 800-1100 degrees Celsius, such as 800 degrees Celsius or 850 degrees Celsius.
  • the annealing temperature may be greater than or equal to the second A thermal oxidation reaction temperature ensures the quality of the first oxide layer 21, shields silicon lattice damage defects, and improves the yield of semiconductor devices.
  • the manufacturing method of the semiconductor structure further includes forming a barrier layer 3 in the trench 11 and filling the conductive metal 4, as shown in FIG. 5 and FIG. 6 , the barrier layer 3 covers the surface of the first oxide layer 21, and the conductive metal 4 covers the surface of the barrier layer 3.
  • the first oxide layer 21 is used as the gate dielectric layer 2, and the barrier layer 3 and the conductive metal 4 are used as the gate of the semiconductor device, for example. Pole structure, and word line structure, as shown in Figure 6.
  • a method for preparing a semiconductor structure may include:
  • S740 On the first oxide layer 21, perform a second thermal oxidation reaction at a preset pressure to form the second oxide layer 22, where the preset pressure is lower than the reaction pressure of the first thermal oxidation reaction.
  • the first thermal oxidation layer 21 is not annealed in this embodiment, but the second thermal oxidation process is performed on the surface of the first thermal oxidation layer 21, and the first thermal oxidation A second oxide layer 22 is formed on the surface of the layer 21 , and the first oxide layer 21 and the second oxide layer 22 together serve as the gate dielectric layer 2 .
  • the sidewall of the first oxide layer 21 is thicker, and the bottom is thinner, and then the second oxide layer 22 is continuously formed along the structure of the first oxide layer 21 through the second thermal oxidation reaction, so that the thickness of the entire gate dielectric layer 2 is completed.
  • annealing is performed on the first oxide layer 21 to improve the reliability of the gate dielectric layer 2 and effectively utilize energy, as shown in FIG. 9 .
  • the obtained word line structure can reduce the gate leakage, thereby improving the reliability of the semiconductor device manufactured next.
  • the reaction temperature of the second thermal oxidation reaction may be 800-1100 degrees Celsius.
  • the reaction temperature may be 800 degrees Celsius, 850 degrees Celsius, 900 degrees Celsius, 950 degrees Celsius, 1000 degrees Celsius, 1050 degrees Celsius, 1100 degrees Celsius.
  • the oxide layer formed in the range of 800-1100 degrees Celsius is relatively dense, which can effectively prevent leakage.
  • controlling the reaction temperature of the second thermal oxidation reaction to be consistent with the reaction temperature of the first thermal oxidation reaction can ensure the film quality of the gate dielectric layer 2.
  • the preset pressure is 0-20 Torr, such as 0 Torr, 5 Torr, 10 Torr.
  • the gas under the pressure of 0-20 torr is relatively evenly distributed in the region from the top to the bottom of the trench 11, and the concentration of the gas in the trench 11 is relatively uniform. Therefore, the second thermal oxidation process under the preset pressure
  • the formed second oxide layer 22 has a uniform thickness, and cooperates with the first thermal oxidation process of 500-800 Torr.
  • the first oxide layer 21 is thickened to obtain the gate dielectric layer 2, the thickness of which is The structure of the gate dielectric layer 2 having a step coverage and a thicker sidewall than the bottom prevents leakage caused by sidewall etching defects, and a thinner bottom can enhance the control capability of the gate.
  • the gas for the second thermal oxidation reaction may include oxygen-containing gas and H 2 .
  • oxygen-containing gas the difference from the first thermal oxidation reaction is that the first thermal oxidation process needs to use pure oxygen O 2 to avoid the failure to obtain the first oxide layer 21 with the expected structure, while the second thermal oxidation reaction uses an oxygen-containing gas, namely Yes, there is no particular limitation.
  • the H 2 in this embodiment is fed intermittently to ensure uniform distribution of the oxidizing gas and to make the thickness of the second oxide layer 22 uniform.
  • the gas for the second thermal oxidation reaction may include: oxygen-containing gas and H 2 ;
  • Q H2 is the flow rate of H2 for the second thermal oxidation reaction
  • Q contains the flow rate of oxygen-containing gas for the second thermal oxidation reaction.
  • This formula can indicate that the flow rate of hydrogen gas is less than the total flow rate of hydrogen gas and oxygen-containing gas Thirty percent of the flow of hydrogen; the percentage of the flow of hydrogen to the total flow of hydrogen and oxygen-containing gas can represent the concentration of hydrogen, so this formula can also indicate that the concentration of hydrogen is less than 30 percent; for example, the upper limit of the concentration of hydrogen It can be 18%, 22%, 28%, 30%.
  • H 2 within the above range is intermittently fed into the atmosphere of the oxygen-containing gas to form the second oxide layer 22 and reduce film defects.
  • the H 2 in this embodiment is fed intermittently to ensure uniform distribution of the oxidizing gas and to make the thickness of the gate dielectric layer 2 uniform.
  • the thickness ratio of the first oxide layer 21 to the second oxide layer 22 may range from 1/4 to 2/3.
  • the range of the thickness ratio of the first oxide layer 21 to the second oxide layer 22 may be the range of the average thickness ratio of the first oxide layer 21 to the average thickness of the second oxide layer 22, or the range of the first oxide layer 21 The variation range of the ratio of the thickness of the thinnest part to the thickness of the thickest part and the thickness of the second oxide layer 22 .
  • the ratio of the thickness of the first oxide layer 21 near the bottom of the trench 11 to the thickness of the second oxide layer 22 is 1/4, the thickness of the first oxide layer 21 near the edge of the trench 11 and the thickness of the second oxide layer 22 The ratio is 2/3.
  • the growth thickness of the first oxide layer 21 can be controlled to be 20-40% of the thickness of the gate dielectric layer 2, such as 20%, and the growth thickness of the second oxide layer 22 can be guaranteed to be 60-80% of the thickness of the gate dielectric layer 2. %, such as 80%.
  • an embodiment of the present disclosure also provides a semiconductor structure, which may include:
  • the first oxide layer 21 covers the bottom and sidewalls of the trench 11 , and the thickness of the first oxide layer 21 gradually decreases along the direction close to the bottom.
  • the material of substrate 1 in this embodiment includes but is not limited to silicon crystal or germanium crystal, silicon on insulator (Silicon On Insulator, SOI) structure or epitaxial layer structure on silicon, compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide , indium phosphide, indium arsenide, or indium dysprosium), alloy semiconductors (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof).
  • Oxide layers with different thicknesses are formed on the side walls and bottom of the trench 11 of the semiconductor structure in this embodiment, and the oxide layer can reduce gate leakage and increase the control capability of the gate. Therefore, the reliability of the semiconductor structure is high, and the production is good. The rate is also higher.
  • it may further include: a second oxide layer 22 covering the surface of the first oxide layer 21; a barrier layer 3 covering the surface of the second oxide layer 22; a conductive metal 4 filling the In the trench 11 , the conductive metal 4 covers the surface of the second oxide layer 22 .
  • the barrier layer 3 can be made of, for example, titanium nitride or tantalum nitride, and the material of the conductive metal 4 includes but not limited to metal or metal alloy, such as tungsten, aluminum, copper and their alloys.
  • the conductive material is filled in the groove 11 to form the conductive metal 4 , and the top of the conductive metal 4 may be lower than the upper edge of the groove 11 .
  • the trench 11 is used as a word line trench, and a gate oxide layer is formed in the word line trench, and the gate oxide layer
  • the oxide layer 2 composed of the first thermal oxide layer 21 and/or the second thermal oxide layer 22 in the present disclosure may be used for insulation between the gate and the substrate 1 .
  • the gate dielectric layer 2 can be formed by thermal oxidation.
  • the gate dielectric layer 2 at least covers the inner sidewall of the trench 11 , and the shape of the gate dielectric layer 2 is the same as that of the trench 11 , for example, if the trench 11 is U-shaped, the gate dielectric layer 2 is also U-shaped.
  • the gate dielectric layer 2 also extends outwards to cover the upper surface of the oxide isolation layer.
  • a barrier layer 3 is formed on the gate dielectric layer 2 , and the barrier layer 3 covers at least the inner sidewall of the gate dielectric layer 2 .
  • the shape of the blocking layer 3 is the same as that of the gate dielectric layer 2 , for example, if the shape of the gate dielectric layer 2 is U-shaped, the shape of the blocking layer 3 is also U-shaped.
  • the material of the barrier layer 3 includes but not limited to metal nitride, such as titanium nitride or tantalum nitride. In this specific embodiment, the barrier layer 3 not only covers the inner sidewall of the gate dielectric layer 2 , but also covers the upper surface of the gate dielectric layer 2 .
  • a conductive metal 4 is formed on the barrier layer 3 , and the conductive metal 4 at least fills the trench 11 .
  • Materials of the conductive metal 4 include, but are not limited to, metals or metal alloys, such as tungsten, aluminum, copper and alloys thereof.
  • the conductive metal 4 is formed on the barrier layer 3 , and the conductive metal 4 at least fills the trench 11 , that is, the conductive metal 4 fills the gap formed by the inner sidewall of the barrier layer 3 .
  • the conductive metal 4 not only fills the gap formed by the inner sidewall of the barrier layer 3 but also covers the upper surface of the barrier layer 3 .
  • part of the conductive metal 4 and the barrier layer 3 are removed by etching, and only a part of the conductive metal 4 and the barrier layer 3 in the trench 11 remain.
  • the top of the conductive metal 4 is lower than the upper edge of the trench 11 .
  • the top of the barrier layer 3 is lower than the top of the conductive metal 4 .
  • the top of the barrier layer 3 may also be flush with the top of the conductive metal 4 , or the top of the barrier layer 3 may be higher than the top of the conductive metal 4 .
  • the conductive metal 4 can be carved multiple times, so that the top of the conductive metal 4 is in a stepped configuration with the middle being high and the two sides being low. Specifically, the conductive metal 4 is etched several times along the direction perpendicular to the top of the conductive metal 4, so that the top of the conductive metal 4 is in a stepped configuration with a high center and low sides.
  • One method of making the top of the conductive metal 4 be in a stepped configuration with a high middle and low sides is to etch the conductive metal 4 multiple times along the edge of the top of the conductive layer to the center of the top of the conductive layer, so that the top of the conductive metal 4 It is a stepped configuration with a high middle and low sides.
  • the top of the stepped word line structure is higher than the top of the existing word line structure, which increases the area of the word line structure and reduces the size of the word line structure.
  • the resistance of the gate increases the control ability of the gate to the channel and improves the ability of the transistor to drive current.
  • the highest point of the top and the drain are parallel to the word line The distance in the direction of the top of the structure is not reduced enough to generate leakage current. That is to say, the stepped word line structure can avoid the GIDL effect while reducing the resistance of the word line structure.
  • the semiconductor structure of this embodiment can be used as the word line structure of the semiconductor device finally obtained, and a dense oxide layer is formed on the sidewall and bottom of the trench 11, and the thickness of the gate oxide layer extends from the edge of the word line trench to the word line trench.
  • the direction of the bottom of the trench gradually decreases, so that the gate oxide layer inside the trench of the word line is covered in steps. Because gate oxide layers with different thicknesses are formed on the sidewall and bottom of the word line trench, thicker sidewalls can reduce gate leakage, and thinner bottoms can enhance the control ability of the gate. Therefore, this method can improve the semiconductor structure. reliability and improve product yield.
  • the oxide layer disclosed in the embodiments of the present disclosure can also be used as other dielectric materials, such as the filling material and barrier material of the isolation trench, and any oxide layer formed in the trench should cover within the scope of the present disclosure, the oxide layer of the present disclosure can improve the etching defects of the sidewall of the trench.

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Abstract

本公开公开了一种半导体结构及其制备方法，属于半导体技术领域。半导体结构的制备方法，包括：提供基底；于基底中形成沟槽；在压力为500～800托的环境下，进行第一热氧化反应形成第一氧化层于沟槽的底部及侧壁，第一氧化层的厚度沿靠近底部的方向逐渐减小。该方法得到的氧化层的厚度沿沟槽的边沿向沟槽的底部方向逐渐减小，使得沟槽内部的氧化层呈阶梯覆盖。由于，沟槽的侧壁和底部形成了厚度不同的氧化层，该较厚的侧壁可以降低栅极漏电，较薄的底部可以加强栅极的控制能力，因此，该方法可以提高半导体结构的可靠性，提高产品良率。

Description

半导体结构及其制备方法
交叉引用
本公开基于申请号为202110958168.3、申请日为2021年08月20日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，具体涉及一种半导体结构及其制备方法。
背景技术
存储器中包括多个存储单元，每个存储单元包含一个MOS晶体管和一个存储电容，MOS晶体管是金属氧化物半导体场效应晶体管(Metal-Oxide-Semi-conductor Field Effect Transistor)的简称。
根据摩尔定律，存储器器件尺寸将会越来越小，MOS晶体管的沟道长度也在不断变短，短沟道效应会导致半导体器件失效，导致良率降低。
发明内容
本公开的目的是提供一种半导体结构及其制备方法以至少解决 现有半导体器件由于短沟道效应，导致良率降低的问题。
本公开的技术方案如下：
根据本公开实施例，提供了一种半导体结构的制备方法，该方法可以包括：提供基底；于所述基底中形成沟槽；在压力为500～800托的环境下，进行第一热氧化反应形成第一氧化层于所述沟槽的底部及侧壁，所述第一氧化层的厚度沿靠近所述底部的方向逐渐减小。
在本公开的一些可选实施例中，所述第一热氧化反应的反应温度可以为800-1100摄氏度。
在本公开的一些可选实施例中，所述第一热氧化反应的气体可以包括：O 2、H 2，以及N 2；其中，所述H 2与所述N 2的流量比满足下式：
Q H2＜4％*(Q N2+Q H2)；
其中，Q H2为所述第一热氧化反应通入所述H 2的流量，Q N2为所述第一热氧化反应所述通入N 2的流量。
在本公开的一些可选实施例中，所述第一热氧化反应的气体可以包括：O 2、H 2，以及惰性气体；其中，所述H 2与所述惰性气体的流量比满足下式：
Q H2＜3％*(Q 惰+Q H2)；
其中，Q H2为第一热氧化反应通入所述H 2的流量，Q 惰为第一热氧化反应通入所述惰性气体的流量。
在本公开的一些可选实施例中，所述制备方法还可以包括：对所述第一氧化层进行退火。
在本公开的一些可选实施例中，所述制备方法还可以包括：于所述第一氧化层上，进行预设压力的第二热氧化反应形成第二氧化层，所述预设压力小于第一热氧化反应的反应压力；
在本公开的一些可选实施例中，所述第二热氧化反应的反应温度可以为800-1100摄氏度。
在本公开的一些可选实施例中，所述预设压力可以为0-20托。
在本公开的一些可选实施例中，所述第二热氧化反应的气体可以包括含氧气体和H2。
在本公开的一些可选实施例中，所述H 2与所述含氧气体的流量比可以满足下式：
Q H2＜30％*(Q 含+Q H2)；
其中，Q H2为所述第二热氧化反应通入所述H 2的流量，所述Q 含为所述第二热氧化反应通入所述含氧气体的流量。
在本公开的一些可选实施例中，所述第一氧化层与所述第二氧化层的厚度比的范围可以为1/4至2/3。
在本公开的一些可选实施例中，所述制备方法还可以包括：于所述第二氧化层的表面形成阻挡层；于所述沟槽中填充导电金属，所述导电金属覆盖所述阻挡层的表面。
根据本公开实施例第二方面，还提供了一种半导体结构，该半导体结构可以包括：具有沟槽的基底；第一氧化层，覆盖所述沟槽的底部及侧壁，所述第一氧化层的厚度沿靠近所述底部的方向逐渐减小。
在本公开的一些可选实施例中，所述半导体结构还可以包括：第 二氧化层，覆盖所述第一氧化层的表面；阻挡层，覆盖所述第二氧化层的表面；导电金属，填充于所述沟槽中，所述导电金属覆盖所述阻挡层的表面。
在本公开的一些可选实施例中，所述第一氧化层和第二氧化层可以作为栅介质层。
本公开实施例方法通过提供基底，于基底中形成沟槽，并在压力为500～800托的环境下，进行第一热氧化反应形成第一氧化层于沟槽的底部及侧壁，第一氧化层的厚度沿靠近底部的方向呈梯度降低。该方法得到的氧化层的厚度沿沟槽的边沿向的底部方向逐渐减小，使得沟槽内部的氧化层呈阶梯覆盖。本公开实施例中的获得氧化层结构可以作为半导体存储器件的栅介质层，继而可以与阻挡层、导电金属构成栅极结构，以及形成字线结构，此时，由于沟槽的侧壁和底部形成了厚度不同的氧化层，该较厚的侧壁可以降低栅极漏电，较薄的底部可以加强栅极的控制能力，因此，该方法可以提高半导体结构的可靠性，提高产品良率。
附图说明
图1是本公开一示例性实施例的半导体结构的制备方法流程示意图；
图2-图6是本公开一示例性实施例的半导体结构的制备过程结构变化图；
图7是本公开另一示例性实施例的半导体结构的制备方法流程 示意图
图8-图9是本公开另一示例性实施例的半导体结构的制备过程结构变化图；
图10-图12是本公开一示例性实施例的半导体结构示意图。
具体实施方式
为了使本领域普通人员更好地理解本公开的技术方案，下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本公开的实施例能够以除了在这里图示或描述的那些以外的顺序实施。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
根据摩尔定律，存储器器件尺寸将会越来越小，场效应管的沟道长度也在不断变短，短沟道效应导致器件失效，良率降低。发明人研究发现采用埋入式字线设计可以减少短沟道效应导致器件失效，通过蚀刻的方法在硅基底得到凹槽结构，再通过热氧化工艺在凹槽结构的侧壁和底部形成厚度均匀的氧化层。但是，该方法使得通过蚀刻得到的侧壁硅晶格容易受损，容易导致栅极漏电，从而导致良率降低。为此，本公开提供一种字线结构及其制备方法、半导体结构及其制备方 法以解决该问题。
下面结合附图，通过具体的实施例及其应用场景对本公开实施例提供的字线结构的制备方法进行详细地说明。
如图1所示，在本公开实施例的第一方面，提供了一种半导体的制备方法，该方法可以包括：
S110：提供基底1；
S120：于基底1中形成沟槽11；
S130：在压力为500～800托的环境下，进行第一热氧化反应形成第一氧化层21于沟槽11的底部及侧壁，第一氧化层21的厚度沿靠近底部的方向逐渐减小；
本实施例方法通过控制500～800托的反应压力下，使得在通入O 2进行热氧化时，在沟槽11内顶部向底部的区域的氧气浓度呈逐渐降低，进而使得在沟槽11内壁形成的第一氧化层21的厚度呈阶梯覆盖。如图4所示，沟槽11的侧壁和底部形成了厚度不同的第一氧化层21，侧壁处的第一氧化层21具有理想厚度，可以避免蚀刻基底得到沟槽11而产生一些缺陷的问题，例如该第一氧化层21可以有效地降低栅极漏电，底部处的第一氧化层21厚度较薄，可以加强栅极的控制能力，提高字线结构的可靠性，进而提半导体结构产品的良率。
为了更清楚的描述，接下来对上述方法步骤进行分别描述：
首先实施步骤S110：提供基底1，如图2所示。
本步骤的基底1的材料包括但不限于硅晶体或锗晶体、绝缘缘体上硅(SiliconOnInsulator，SOI)结构或硅上外延层结构、化合物半导体 (例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、或镝化铟)、合金半导体(例如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或者它们的组合)。
实施步骤S120：于基底1中形成沟槽11，如图3所示。
本步骤可以是在基底1上形成掩膜，利用光刻及刻蚀工艺在基底1上形成沟槽11，该沟槽11可以为字线沟槽，从而在该字线沟槽内进行后续的沉积工艺，获得字线结构。所述基底1内除了包括形成埋入式的字线结构之外，可以包括形成其他半导体结构，此处不作限定。
示例性的，在形成沟槽11前，在基底1的表面还形成氧化物隔离层，氧化物隔离层未覆盖沟槽11内表面，而是仅覆盖基底1上表面。氧化物隔离层可在后续工艺中保护基底1的上表面，避免其被刻蚀。
本步骤是为了解决短沟道效应导致半导体器件失效实效的问题，本实施例利用埋入式字线的方式进行解决短沟道效应，首先在基底1上，利用刻蚀手段形成沟槽11，得到了具有沟槽11的基底1，本实施例的基底是硅晶体基底，但是，这样通过蚀刻得到的沟槽11侧壁硅晶格容易受损，硅晶格受损容易导致栅极漏电，进而导致半导体器件良率降低。因此，为了解决这个问题引出下一步骤S130。
实施步骤S130：在压力为500～800托的环境下，进行第一热氧化反应形成第一氧化层21于沟槽11的底部及侧壁，第一氧化层21的厚度沿靠近底部的方向逐渐减小，如图4局部放大区域A所示。
本步骤是为了解决硅晶格受损导致栅极漏电的问题，在沟槽11 内壁表面形成第一氧化层21，该第一氧化层21可以有效的防止硅晶格受损，进而防止了漏电的发生。在沟槽11内壁表面形成第一氧化层21可以是通过在压力为500～800托的环境下，进行第一热氧化反应，在沟槽11内部形成第一氧化层21，在压力为500～800托，例如700托、760托，在此压力的条件下，反应气体在沟槽11内分布并不均匀，在沟槽11的槽口附近反应气体的浓度较高，沟槽11的槽底反应气体的浓度较低，因此，在发生热氧化反应过程中会在沟槽11内壁会形成厚度呈梯度降低趋势的氧化层，沟槽11内氧化层的厚度沿沟槽的边沿向沟槽11的底部方向，氧化层的厚度逐渐减小。
本步骤中，第一热氧化反应的反应温度可以为800-1100摄氏度，例如反应温度可以为800摄氏度、850摄氏度、900摄氏度、950摄氏度、1000摄氏度、1050摄氏度、1100摄氏度。在800-1100摄氏度范围内形成的氧化层较为致密，可以有效防止漏电。
第一热氧化反应的气体可以包括：O 2、H 2，以及N 2；其中，H 2与N 2的流量比满足下式：
Q H2＜4％*(Q N2+Q H2)；
其中，Q H2为第一热氧化反应通入H 2的流量，Q N2为第一热氧化反应通入N 2的流量，该式可以表示通入氢气的流量小于氢气与氮气总流量的百分之四；氢气的流量占氢气与氮气总流量的百分比可以表示氢气的浓度，因此该式也可以表示氢气的浓度小于百分之四；所述H 2与N 2的流量比可以是完成第一氧化层21的生长过程的流量比值，例如为2％、3％。该氧化过程中通入O 2的氛围内间歇性地通入上述 范围内的H 2和N 2，调整形成第一氧化层21的梯度厚度以及降低膜层缺陷。
第一热氧化反应的反应气体也可以包括：O 2、H 2，以及惰性气体；其中，所述H 2与所述惰性气体的流量比满足下式：
Q H2＜3％*(Q 惰+Q H2)；
其中，Q H2为第一热氧化反应通入所述H 2的流量，Q 惰为第一热氧化反应通入所述惰性气体的流量，该式可以表示通入氢气的流量小于氢气与惰性气体总流量的百分之三；氢气的流量占氢气与惰性气体总流量的百分比可以表示氢气的浓度，因此该式也可以表示氢气的浓度小于百分之三；所述H 2与惰性气体的流量比可以是完成第一氧化层21的生长过程的流量比值，例如为2％、2.5％。该氧化过程中通入O 2的氛围内间歇性地通入上述范围内的H 2和惰性气体，所述惰性气体可以列举Ar、Ne、He，调整形成第一氧化层21的梯度厚度以及降低膜层缺陷。
示例性的，该第一热氧化反应例如为原位水汽氧化反应，反应压力是在常压条件进行的，例如为760托，反应温度是900摄氏度，反应气体包括：H 2、N 2及氧化剂O 2，其中，H 2与N 2的流量比为3％。该氧化过程持续通入O 2，H 2和N 2为间歇性地通入。通过该示例性的方法得到半导体结构在沟槽11的底部及侧壁形成致密的氧化介质层，并且该氧化介质层厚度沿靠近底部的方向呈梯度降低。可有以有效降低沟槽11侧壁漏电以及增加电场控制能力。
另一示例性的，该第一热氧化反应为原位水汽氧化反应，反应压 力是在常压条件进行的，例如为760托，该原位水汽氧化的反应温度是900摄氏度；第一热氧化反应的气体包括：Ar、H 2及氧化剂O 2，其中，H 2与Ar的流量比比2％。该氧化过程持续通入O 2，Ar和H 2为间歇性地通入。通过该示例性的方法得到半导体结构在沟槽11的底部及侧壁形成了致密的氧化介质层，并且该氧化介质层厚度沿靠近底部的方向呈梯度降低。可有以有效降低沟槽11侧壁漏电以及增加电场控制能力。
在本公开的一些可选实施例中，在进行第一热氧化反应形成第一氧化层21于沟槽11的底部及侧壁之后，提高第一氧化层21的质量，所述半导体结构的制备方法还可以包括：对第一氧化层21进行退火，提高所述第一氧化层21的致密度，该退火温度例如为800-1100摄氏度，例如800摄氏度、850摄氏度，该退火温度可以大于等于第一热氧化的反应温度，保证第一氧化层21的质量，屏蔽硅晶格受损缺陷，提高半导体器件良率。
在本公开的一些可选实施例中，所述半导体结构的制备方法还包括于所述沟槽11中形成阻挡层3以及填充导电金属4，如图5和图6所示，所述阻挡层3覆盖所述第一氧化层21的表面，所述导电金属4覆盖阻挡层3的表面，该第一氧化层21作为栅介质层2，与阻挡层3、导电金属4作为例如半导体器件的栅极结构，以及字线结构，如图6所示。
如图7所示，在本公开的一些可选实施例中，提供一种半导体结构的制备方法，该方法可以包括：
S710：提供基底1；
S720：于基底1中形成沟槽11；
S730：在压力为500～800托的环境下，进行第一热氧化反应形成第一氧化层21于沟槽11的底部及侧壁，第一氧化层21的厚度沿靠近底部的方向逐渐减小；
S740：于第一氧化层21上，进行预设压力的第二热氧化反应形成第二氧化层22，预设压力小于第一热氧化反应的反应压力。
如图8所示，在本实施例中，在本实施例中对第一热氧化层21不进行退火，而是在第一氧化层21的表面进行第二热氧化工艺，在第一热氧化层21的表面形成第二氧化层22，通过第一氧化层21与第二氧化层22共同作为栅介质层2。其中，第一氧化层21侧壁较厚，而底部得到较薄，再通过第二热氧化反应沿着第一氧化层21结构继续生成第二氧化层22，这样在完成整体栅介质层2厚度增加的同时，对第一氧化层21进行退火，提高栅介质层2的可靠性，也有效地利用了能源，如图9所示。并且，得到的字线结构可以降低栅极漏电，进而提高了接下来制造而成的半导体器件的可靠性。
在本公开的一些可选实施例中，第二热氧化反应的反应温度可以为800-1100摄氏度。示例性的，反应温度可以为800摄氏度、850摄氏度、900摄氏度、950摄氏度、1000摄氏度、1050摄氏度、1100摄氏度。在800-1100摄氏度范围内形成的氧化层较为致密，可以有效防止漏电。
示例性的，控制第二热氧化反应的反应温度与第一热氧化反应的 反应温度保持一致时可以保证栅介质层2的膜层质量。
在本公开的一些可选实施例中，预设压力为0-20托，例如0托、5托、10托。在压力为0-20托条件下的气体在沟槽11内顶部至底部的区域分布较为均匀，在沟槽11内的气体的浓度较为均匀，因此，该预设压力下的第二热氧化工艺形成的第二氧化层22厚度均匀，与500～800托的第一热氧化工艺相互配合，在第一氧化层21的基础上，增厚第一氧化层21，获得栅介质层2，其厚度呈阶梯覆盖，栅介质层2的侧壁比底部更厚的结构，防止侧壁蚀刻缺陷导致漏电，同时较薄的底部可以加强栅极的控制能力。
在本公开的一些可选实施例中，第二热氧化反应的气体可以包括含氧气体和H 2，所述含氧气体可以列举O 2、NO、N 2O，这些为第二热氧化反应提供氧源，与第一热氧化反应中不同的是，第一热氧化过程需要采用纯氧O 2，避免无法获得预期结构的第一氧化层21，而第二热氧化反应使用含氧气体即可，并没有特别的限定。
本实施例中的H 2为间歇性通入，保证氧化性气体均匀分布，可以使第二氧化层22厚度均匀。
在本公开的一些可选实施例中，第二热氧化反应的气体可以包括：含氧气体和H 2；
Q H2＜30％*(Q 含+Q H2)；
其中，Q H2为第二热氧化反应通入H 2的流量，Q 含为第二热氧化反应通入含氧气体的流量，该式可以表示通入氢气的流量小于氢气与含氧气体总流量的百分之三十；氢气的流量占氢气与含氧气体总流量 的百分比可以表示氢气的浓度，因此该式也可以表示氢气的浓度小于百分之三十；例如，氢气的浓度上限值可以为18％、22％、28％、30％。该氧化过程中通入含氧气体的氛围内间歇性地通入上述范围内的H 2，形成第二氧化层22以及降低膜层缺陷。
本实施例中的H 2为间歇性通入，保证氧化性气体均匀分布，可以使栅介质层2厚度均匀。
在本公开的一些可选实施例中，第一氧化层21与第二氧化层22的厚度比的范围可以为1/4至2/3。
本实施例中第一氧化层21与第二氧化层22的厚度比的范围可以为第一氧化层21的平均厚度与第二氧化层22的平均厚度比的范围，也可以是第一氧化层21最薄处的厚度到最厚处的厚度与第二氧化层22的厚度比的变化范围。
示例性的，第一氧化层21靠近沟槽11底部的厚度与第二氧化层22的厚度比为1/4，第一氧化层21靠近沟槽11边沿的厚度与第二氧化层22的厚度比为2/3。
示例性的，可以控制第一氧化层21的生长厚度为栅介质层2厚度的20-40％，例如20％，可以保证第二氧化层22的生长厚度为栅介质层2厚度的60-80％，例如80％。
如图10所示，在本公开实施例的还提供一种半导体结构，该结构可以包括：
具有沟槽11的基底1；
第一氧化层21，覆盖于沟槽11的底部及侧壁，第一氧化层21 的厚度沿靠近底部的方向逐渐减小。
本实施例中基底1的材料包括但不限于硅晶体或锗晶体、绝缘缘体上硅(SiliconOnInsulator，SOI)结构或硅上外延层结构、化合物半导体(例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、或镝化铟)、合金半导体(例如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或者它们的组合)。
本实施例半导体结构的沟槽11侧壁和底部形成了厚度不同的氧化层，该氧化层可以降低栅极漏电以及增加栅极的控制能力，因此，该半导体结构的可靠性较高，生产良率也较高。
在本公开的一些可选实施例中，还可以包括：第二氧化层22，覆盖第一氧化层21的表面；阻挡层3，覆盖所述第二氧化层22的表面；导电金属4，填充于所述沟槽11中，所述导电金属4覆盖所述第二氧化层22的表面。
其中，阻挡层3例如可以采用氮化钛、氮化钽，导电金属4的材料包括但不限于金属或金属合金，例如，钨、铝、铜及其合金等。
在沟槽11内填充导电材料，形成导电金属4，导电金属4的顶端可以低于沟槽11上缘。
如图10所示，在本公开的一些可选实施例中，在形成字线结构中，沟槽11，作为字线沟槽，并在该字线沟槽内形成栅氧化层，栅氧化层可以使用本公开中由第一热氧化层21和/或第二热氧化层22构成的氧化层2，其用于栅极与基底1之间的绝缘。可采用热氧化法形成栅介质层2。栅介质层2至少覆盖沟槽11内侧壁，栅介质层2 与沟槽11的形状相同，例如，沟槽11为U形，则栅介质层2也为U形。在本公开的一些可选实施例中，在本具体实施方式中，栅介质层2还向外延伸覆盖氧化物隔离层的上表面。
如图11所示，在栅介质层2上形成阻挡层3，阻挡层3至少覆盖栅介质层2的内侧壁。阻挡层3的形状与栅介质层2的形状相同，例如，栅介质层2的形状为U形，则阻挡层3的形状也为U形。阻挡层3的材料包括但不限于金属氮化物，例如是氮化钛或氮化钽。在本具体实施方式中，阻挡层3除覆盖栅介质层2的内侧壁外，还覆盖栅介质层2的上表面。
如图11所示，在阻挡层3上形成导电金属4，导电金属4至少充满沟槽11。导电金属4的材料包括但不限于金属或金属合金，例如，钨、铝、铜及其合金。在该步骤实施完毕，导电金属4形成在阻挡层3上，且导电金属4至少充满沟槽11，即导电金属4填充阻挡层3的内侧壁形成的空隙中。在本具体实施方式中，导电金属4不仅填充阻挡层3的内侧壁形成的空隙而且还覆盖阻挡层3的上表面。
如图12所示，刻蚀去除部分导电金属4及阻挡层3，仅保留部分位于沟槽11内的导电金属4及阻挡层3。在执行完该步骤后，导电金属4的顶端低于沟槽11上缘。在本具体实施方式中，阻挡层3的顶端低于导电金属4的顶端。在其他具体实施方式中，阻挡层3的顶端也可与导电金属4的顶端平齐，或者阻挡层3的顶端高于导电金属4的顶端。
在本实施例中，可以分多次刻导电金属4，使导电金属4的顶端 呈中间高两边低的阶梯型构型。具体地说，分多次沿垂直导电金属4顶端的方向刻蚀导电金属4，使导电金属4顶端呈中间高两边低的阶梯型构型。使导电金属4的顶端呈中间高两边低的阶梯型构型的一种方法是沿导电层顶端的边缘向导电层的顶端的中心方向，多次刻蚀导电金属4，使导电金属4的顶端呈中间高两边低的阶梯型构型。相较于现有的字线结构的顶端为平板构型而言，阶梯型字线结构的顶端高于现有的字线结构的顶端，增大了字线结构的面积，降低了字线结构的电阻，增加了栅极对沟道的控制能力，提高晶体管驱动电流的能力。在垂直于字线结构的顶端的方向上，虽然阶梯型字线结构的顶端的最高点距离漏极的距离减小，但是采用台阶构型，其顶端的最高点与漏极在平行于字线结构的顶端的方向上的距离并未减小很多，不足以产生漏电流。也就是说，阶梯型字线结构在降低字线结构的电阻的同时还能够避免产生GIDL效应。
本实施例半导体结构可以作为最终获得的半导体器件的字线结构，在沟槽11的侧壁和底部形成了致密的氧化层，该栅氧化层的厚度沿字线沟槽的边沿向字线沟槽的底部方向逐渐减小，使得字线沟槽内部的栅氧化层呈阶梯覆盖。由于，字线沟槽侧壁和底部形成了厚度不同的栅氧化层，较厚的侧壁可以降低栅极漏电，较薄的底部可以加强栅极的控制能力，因此，该方法可以提高半导体结构的可靠性，提高产品良率。
当然，在其他的一些实施例中，本公开实施例公开的氧化层还可以作为其他电介质材料使用，例如隔离沟槽的填充材料、阻挡材料， 任何在沟槽内形成的氧化层，均应当涵盖在本公开要求保护的范围内，本本公开的氧化层可以改善沟槽侧壁的刻蚀缺陷。
上面结合附图对本公开的实施例进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本公开的保护之内。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供基底；
    于所述基底中形成沟槽；
    在压力为500～800托的环境下，进行第一热氧化反应形成第一氧化层于所述沟槽的底部及侧壁，所述第一氧化层的厚度沿靠近所述底部的方向逐渐减小。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，所述第一热氧化反应的反应温度为800-1100摄氏度。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，所述第一热氧化反应的气体包括：O 2、H 2，以及N 2；
    其中，所述H 2与所述N 2的流量比满足下式：
    Q H2＜4％*(Q N2+Q H2)；
    其中，Q H2为所述第一热氧化反应通入所述H 2的流量，Q N2为所述第一热氧化反应所述通入N 2的流量。
  4. 根据权利要求1所述的半导体结构的制备方法，其中，所述第一热氧化反应的气体包括：O 2、H 2，以及惰性气体；
    其中，所述H 2与所述惰性气体的流量比满足下式：
    Q H2＜3％*(Q 惰+Q H2)；
    其中，Q H2为第一热氧化反应通入所述H 2的流量，Q 惰为第一热氧化反应通入所述惰性气体的流量。
  5. 根据权利要求1所述的半导体结构的制备方法，其中，所述 制备方法还包括：对所述第一氧化层进行退火。
  6. 根据权利要求1-4任一项所述的半导体结构的制备方法，其中，所述制备方法还包括：
    于所述第一氧化层上，进行预设压力的第二热氧化反应形成第二氧化层，所述预设压力小于第一热氧化反应的反应压力；
  7. 根据权利要求6所述的半导体结构的制备方法，其中，所述第二热氧化反应的反应温度为800-1100摄氏度。
  8. 根据权利要求6所述的半导体结构的制备方法，其中，所述预设压力为0-20托。
  9. 根据权利要求6所述的半导体结构的制备方法，其中，所述第二热氧化反应的气体包括含氧气体和H 2。
  10. 根据权利要求9所述的半导体结构的制备方法，其中，所述H 2与所述含氧气体的流量比满足下式：
    Q H2＜30％*(Q 含+Q H2)；
    其中，Q H2为所述第二热氧化反应通入所述H 2的流量，所述Q 含为所述第二热氧化反应通入所述含氧气体的流量。
  11. 根据权利要求6所述的半导体结构的制备方法，其中，所述第一氧化层与所述第二氧化层的厚度比的范围为1/4至2/3。
  12. 根据权利要求6所述的半导体结构的制备方法，其中，所述制备方法还包括：
    于所述第二氧化层的表面形成阻挡层；
    于所述沟槽中填充导电金属，所述导电金属覆盖所述阻挡层的表 面。
  13. 一种半导体结构，包括：
    具有沟槽的基底；
    第一氧化层，覆盖所述沟槽的底部及侧壁，所述第一氧化层的厚度沿靠近所述底部的方向逐渐减小。
  14. 根据权利要求13所述的半导体结构，其中，还包括：
    第二氧化层，覆盖所述第一氧化层的表面；
    阻挡层，覆盖所述第二氧化层的表面；
    导电金属，填充于所述沟槽中，所述导电金属覆盖所述阻挡层的表面。
  15. 根据权利要求14所述的半导体结构，其中，所述第一氧化层和第二氧化层作为栅介质层。
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