WO2023015751A1 - 浅槽隔离结构的制备方法、浅槽隔离结构和半导体结构 - Google Patents

浅槽隔离结构的制备方法、浅槽隔离结构和半导体结构 Download PDF

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WO2023015751A1
WO2023015751A1 PCT/CN2021/129229 CN2021129229W WO2023015751A1 WO 2023015751 A1 WO2023015751 A1 WO 2023015751A1 CN 2021129229 W CN2021129229 W CN 2021129229W WO 2023015751 A1 WO2023015751 A1 WO 2023015751A1
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Prior art keywords
trench
isolation layer
trenches
substrate
shallow trench
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French (fr)
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郑孟晟
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials

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  • the present application relates to the technical field of semiconductor fabrication, and in particular to a method for preparing a shallow trench isolation structure, a shallow trench isolation structure and a semiconductor structure.
  • Shallow Trench Isolation can provide a smaller isolation size and has a planarized surface, and has gradually become the mainstream isolation method in semiconductor manufacturing processes.
  • the cross-sectional width of the trench will gradually decrease as the depth of the trench increases. That is to say, the trench after etching is actually V-shaped, not the desired U-shaped. Therefore, after the trenches are preliminarily formed, subsequent processing steps are required for the trenches, resulting in complicated manufacturing process of the shallow trench isolation structure, and the isolation performance of the finally obtained shallow trench isolation structure is not ideal.
  • Embodiments of the present disclosure provide a method for preparing a shallow trench isolation structure, the shallow trench isolation structure and a semiconductor structure, which can simplify the manufacturing process of the shallow trench isolation structure and improve the insulation performance of the shallow trench isolation structure.
  • the first aspect of the present disclosure provides a method for manufacturing a shallow trench isolation structure, the method including:
  • a continuous first isolation layer is formed on the top of the substrate and inside the plurality of first trenches by a deposition process, and the part of the first isolation layer located in the first trench forms a second trench ; Wherein, the cross-sectional width of the second groove remains constant downward along the vertical direction;
  • a continuous second isolation layer is formed on the surface of the first isolation layer by an ISSG process, and the part of the second isolation layer located in the second trench completely fills the second trench.
  • the maximum cross-sectional width of the upper half of the first trench is less than or equal to the maximum cross-sectional width of the bottom half of the first trench.
  • the forming a plurality of first trenches on the substrate includes:
  • the predetermined etching process includes dry etching and/or wet etching.
  • the etching gas of the predetermined etching process includes at least one of the following: sulfur hexafluoride SF 6 , fluorocarbons CFs, chlorine Cl 2 and argon Ar.
  • the method also includes:
  • the thickness of the first isolation layer is controlled to decrease in the vertical direction downward, so that the cross-sectional width of the second trench is vertically downward. remains unchanged.
  • forming a continuous first isolation layer on the top of the substrate and inside the plurality of first trenches through a deposition process includes:
  • ALD atomic layer deposition
  • the ALD process includes at least one of the following: plasma ALD process, catalytic ALD process and thermal ALD process.
  • the preset step coverage is less than or equal to 80%.
  • the reaction pressure of the ALD process is 0.1-10 Torr
  • the reaction temperature of the ALD process is 300-600 degrees Celsius
  • the reaction gas of the ALD process is oxygen
  • the gas flow rate of the ALD process is 0.1-10 L/min.
  • forming a continuous second isolation layer on the surface of the first isolation layer through an ISSG process includes:
  • the substrate after forming the plurality of second trenches is deposited by the ISSG process until the plurality of second trenches are filled to obtain the second isolation layer.
  • the reaction temperature of the ISSG process is 900-1050 degrees Celsius, and the reaction pressure of the ISSG process is 0.1 Torr-10 Torr.
  • the first isolation layer and the second isolation layer include silicon oxide.
  • the second aspect of the embodiments of the present disclosure provides a shallow trench isolation structure, and the shallow trench isolation structure includes:
  • the base includes a plurality of first grooves, and the cross-sectional width of the first grooves tends to increase downward along the vertical direction;
  • the first isolation layer is located inside the plurality of first trenches and the top of the substrate, and the part of the first isolation layer located in the first trenches forms a second trench, and the cross-sectional width of the second trench is vertically downward constant;
  • the second isolation layer is located on the surface of the first isolation layer, and the part of the second isolation layer located in the second trench completely fills the second trench.
  • the maximum cross-sectional width of the upper half of the first trench is smaller than the maximum cross-sectional width of the bottom half of the first trench.
  • the plurality of first trenches are formed after etching the substrate according to a preset etching process; wherein the preset etching process includes dry etching and/or wet etching.
  • the etching gas of the predetermined etching process includes sulfur hexafluoride SF 6 , fluorocarbons CFs, chlorine Cl 2 , argon Ar one or more.
  • the thickness of the first isolation layer in the first trench decreases vertically downward, so that the cross-sectional width of the correspondingly formed second trench remains constant in the vertical direction.
  • the second isolation layer is formed by depositing the substrate after the formation of the plurality of second trenches through an ISSG process until the plurality of second trenches are filled.
  • the first isolation layer and the second isolation layer include silicon oxide.
  • a third aspect of the embodiments of the present disclosure provides a semiconductor structure, including the shallow trench isolation structure as described in the second aspect.
  • Embodiments of the present disclosure provide a method for preparing a shallow trench isolation structure, a shallow trench isolation structure, and a semiconductor structure.
  • a substrate is provided, and a plurality of first trenches are formed on the substrate, and the cross-sectional width of the first trenches is along the vertical direction.
  • a continuous first isolation layer is formed on the top of the substrate and inside a plurality of first trenches through a deposition process, and the part of the first isolation layer located in the first trench forms a second trench; wherein , the cross-sectional width of the second trench remains constant downward in the vertical direction; a continuous second isolation layer is formed on the surface of the first isolation layer by an ISSG process, and the part of the second isolation layer located in the second trench Two trenches are completely filled.
  • the cross-sectional width of the trenches is controlled to increase downward in the vertical direction, and then the first isolation layer is used to correct the cross-sectional width of the trenches so that it remains constant downward in the vertical direction , and finally fill the trench to obtain the front trench isolation structure, which simplifies the manufacturing process of the shallow trench isolation structure and improves the insulation performance of the shallow trench isolation structure.
  • Fig. 1 is a schematic structural view of a reaction chamber in the related art
  • FIG. 2A is a first schematic diagram of the preparation process of a shallow trench isolation structure in the related art
  • 2B is a second schematic diagram of the preparation process of a shallow trench isolation structure in the related art
  • 2C is a schematic diagram 3 of the preparation process of a shallow trench isolation structure in the related art
  • 2D is a schematic diagram 4 of the preparation process of a shallow trench isolation structure in the related art
  • FIG. 3 is a schematic flowchart of a method for preparing a shallow trench isolation structure provided by an embodiment of the present disclosure
  • FIG. 4A is a first schematic diagram of the preparation process of a shallow trench isolation structure provided by an embodiment of the present disclosure
  • FIG. 4B is a second schematic diagram of the preparation process of a shallow trench isolation structure provided by an embodiment of the present disclosure.
  • FIG. 4C is a third schematic diagram of the preparation process of a shallow trench isolation structure provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a shallow trench isolation structure provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • first ⁇ second ⁇ third involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific ordering of objects. Understandably, “first ⁇ second ⁇ third 3" where permitted, the specific order or sequence may be interchanged such that the embodiments of the disclosure described herein can be practiced in sequences other than those illustrated or described herein.
  • AA Active Area
  • Active area which can be isolated by shallow trenches between active areas.
  • ALD atomic layer deposition
  • ISSG In-Situ Steam Generation
  • DRAM Dynamic Random Access Memory
  • a shallow trench isolation structure (also called a shallow trench isolation structure) is an important isolation structure in semiconductors, and is generally used for isolation between active regions.
  • FIG. 1 shows a schematic structural diagram of a shallow trench isolation structure in the related art.
  • the shallow trench isolation structure includes a base formed of polysilicon, and there are multiple trenches on the base. These trenches are filled with silicon oxide, and the silicon oxide forms a planarized surface on the base, and then silicon nitride is deposited. and other functional structures.
  • the shallow trench isolation structure is an important part in the DRAM manufacturing process. Although there are many methods for preparing the shallow trench isolation structure, all of these methods have the disadvantage of complicated manufacturing process. Specifically, in the current DRAM process, due to the characteristics of the trench, it is impossible to directly form a U-shaped trench. It is necessary to further use polysilicon chemical vapor deposition to form a U-shaped trench first, and then use an oxidation process (such as HQO ALD process, ISSG process) to fill the trenches, and finally obtain a shallow trench isolation structure.
  • an oxidation process such as HQO ALD process, ISSG process
  • FIG. 2 shows a schematic flowchart of a method for preparing a shallow trench isolation structure in the related art.
  • a substrate after the active area (AA) is etched, a plurality of V-shaped grooves are formed; then, as shown in Figure 2B, polysilicon vapor deposition is carried out in the V-shaped grooves, and the The trench is modified into a U-shape to increase the distance between the trenches to avoid short-circuiting the device.
  • the preparation method of the existing shallow trench isolation structure is relatively complicated, and the width of the trench used for filling silicon oxide in the front trench isolation structure will be narrower than expected, which reduces the isolation performance.
  • the manufacturing process of the shallow trench isolation structure is scaled down, the size of the obtained shallow trench isolation structure will also be scaled down accordingly, so the properties of the insulating layer of the shallow trench and the shape of the shallow trench are very important.
  • an embodiment of the present disclosure provides a method for preparing a shallow trench isolation structure.
  • the basic idea is: provide a substrate, and form a plurality of first trenches on the substrate, and the cross-sectional width of the first trenches is along the vertical direction. The bottom tends to increase; a continuous first isolation layer is formed on the top of the substrate and inside a plurality of first trenches through a deposition process, and the part of the first isolation layer located in the first trench forms a second trench; wherein , the cross-sectional width of the second trench remains constant downward in the vertical direction; a continuous second isolation layer is formed on the surface of the first isolation layer by an ISSG process, and the part of the second isolation layer located in the second trench Two trenches are completely filled.
  • the cross-sectional width of the trenches is controlled to increase downward in the vertical direction, and then the first isolation layer is used to correct the cross-sectional width of the trenches so that it remains constant downward in the vertical direction , and finally fill the trench to obtain the front trench isolation structure, which simplifies the manufacturing process of the shallow trench isolation structure and improves the insulation performance of the shallow trench isolation structure.
  • FIG. 3 shows a schematic flowchart of a method for manufacturing a shallow trench isolation structure provided by an embodiment of the present disclosure. As shown in Figure 3, the method may include:
  • S101 Provide a substrate, and form a plurality of first trenches on the substrate, and the cross-sectional width of the first trenches tends to increase downward along a vertical direction.
  • the embodiment of the present disclosure provides a method for preparing a shallow trench isolation structure, which is applied to a semiconductor structure.
  • the substrate needs to be etched to obtain a plurality of first grooves.
  • the first groove it is necessary to widen the lower half of the groove to control the cross-sectional width of the first groove to increase downward along the vertical direction.
  • FIG. 4 it shows a schematic diagram of a manufacturing process of a shallow trench isolation structure provided by an embodiment of the present disclosure.
  • the substrate 201 is formed with a plurality of first grooves.
  • the cross-sectional shape of the upper half is almost constant, but the cross-sectional width of the lower half increases gradually with the depth, that is, The section width at a is smaller than the section width at b.
  • the first trench can be obtained by etching the substrate, and a specific etching process needs to be selected according to an actual application scenario, which is not limited in the embodiments of the present disclosure. Therefore, in some embodiments, forming a plurality of first trenches on the substrate may include:
  • the substrate is etched according to a predetermined etching process to obtain a plurality of first trenches; wherein, the predetermined etching process includes dry etching and/or wet etching.
  • the degree of widening of the first trench can be determined according to actual application requirements.
  • the maximum cross-sectional width of the upper half of the first trench is smaller than the maximum cross-sectional width of the bottom half of the first trench.
  • the maximum cross-sectional width of the upper half of the first groove may also be equal to the maximum cross-sectional width of the lower half of the first groove.
  • the etching gas of the predetermined etching process includes at least one of the following: sulfur hexafluoride SF 6 , fluorocarbons CFs, chlorine Cl 2 and argon Ar .
  • the first groove is V-shaped, and its cross-sectional width gradually decreases downward along the vertical direction; while in the embodiment of the present disclosure, the lower half of the first groove is widened, Therefore, its cross-sectional width tends to increase downward along the vertical direction.
  • S102 Form a continuous first isolation layer on the top of the substrate and inside a plurality of first trenches through a deposition process, and the part of the first isolation layer located in the first trench forms a second trench; wherein, the second trench The cross-sectional width of the groove remains constant down the vertical direction.
  • a first isolation layer is deposited on the substrate by a deposition process, and the part of the first isolation layer inside the first trench forms a second trench, and the second The cross-sectional width of the trench remains constant down the vertical direction.
  • FIG. 4B it shows a second schematic diagram of the preparation process of a shallow trench isolation structure provided by an embodiment of the present disclosure.
  • a first isolation layer 202 is deposited on the top of the substrate and inside the plurality of first trenches.
  • the part of the first isolation layer 202 inside the first trench forms the second trench
  • the second trench is U-shaped, that is, the cross-sectional width of the second trench remains constant downward along the vertical direction.
  • the thickness of the first isolation layer is controlled to decrease vertically downward, so that the second The cross-sectional width of the trench remains constant down the vertical direction.
  • forming a continuous first isolation layer on the top of the substrate and inside the plurality of first trenches through a deposition process may include:
  • ALD atomic layer deposition
  • the ALD process includes at least one of the following: plasma ALD process (PE-ALD process), catalytic ALD process and thermal ALD process (Thermal ALD process).
  • PE-ALD process plasma ALD process
  • catalytic ALD process catalytic ALD process
  • thermal ALD process Thermal ALD process
  • the first isolation layer can be obtained by using an ALD process.
  • the substrate is generally made of polysilicon.
  • oxygen is continuously fed into the substrate, and the substrate is kept at a preset temperature and pressure.
  • the polysilicon on the surface of the substrate will gradually oxidize to silicon oxide, thereby obtaining the first an isolation layer. That is to say, when the first isolation layer is deposited by the ALD process, the oxygen introduced in the ALD process will consume the polysilicon substrate, and it is necessary to further control the ability to consume the substrate by controlling the oxygen flow rate, ionization strength, temperature or pressure.
  • the first isolation layer when forming the first isolation layer, it is necessary to adopt a low step coverage, so that the part of the first isolation layer located at the lower part of the first trench is thicker, and the first isolation layer is located at the upper part of the first trench. The portion is thinner, thereby forming a U-shaped second groove.
  • low step coverage can be obtained by adjusting the flow rate of the ALD process and extending the seed time (Seed Time).
  • the preset step coverage is less than or equal to 80%.
  • the PE-ALD process can be used in some embodiments.
  • the reaction pressure of the ALD process is 0.1-10 Torr
  • the reaction temperature of the ALD process is 300-600 degrees Celsius
  • the reaction gas of the ALD process is oxygen
  • the gas flow rate of the ALD process is 0.1-10 liters/minute.
  • S103 Form a continuous second isolation layer on the surface of the first isolation layer by ISSG process, and the part of the second isolation layer located in the second trench completely fills the second trench.
  • a continuous second isolation layer 203 is continuously formed by the ISSG process to fill up the second trench, thus obtaining a shallow trench isolation structure.
  • the base is mainly composed of polysilicon
  • the first isolation layer and the second isolation layer are mainly composed of silicon oxide, so as to play the role of isolation and insulation.
  • the reaction temperature of the ISSG process is 900-1050 degrees Celsius, and the reaction pressure of the ISSG process is 0.1-10 Torr.
  • the preparation method provided by the embodiment of the present disclosure will be specifically described below by taking one of the feasible solutions as an example.
  • the plasma atomic stack oxidation (PE ALD OX) method is used to form a low step coverage in the trench, so that the AA isolation forms a U shape.
  • the low step coverage is obtained mainly by controlling the different flow rates of PE ALD OX and longer Seed Time, so that a thicker isolation layer is formed at the bottom of the trench.
  • FIG. 4C the shallow trenches are continued to be filled by using the ISSG process, and finally a shallow trench isolation structure is obtained.
  • the trench formed on the substrate 201 is V-shaped, and polysilicon will be further deposited later to shorten the cross-sectional width of the upper half of the trench to obtain a U-shaped trench
  • the groove resulting in a further reduction in the width of the trench actually used to fill the isolation layer (see the circled part in Figure 2D), leading to a decrease in isolation performance.
  • the lower half of the first trench is widened, and the trench width is increased compared with the V-shaped trench, and there is no need to deposit polysilicon again to correct the trench shape, but by direct deposition
  • the isolation layer is used to modify the trench shape, further increasing the trench width (see the circled part in Figure 4C), thereby improving the isolation performance and reducing the leakage current.
  • the embodiments of the present disclosure provide a new method to prepare shallow trench isolation structures.
  • dry etching is used to form AA trenches, and then plasma atomic deposition silicon oxide is used to replace polysilicon and HQO furnace tube process , and then perform the ISSG process to obtain the shallow trench isolation structure.
  • the embodiment of the present disclosure can reduce one process and replace the HQO furnace tube process, so as to better reduce the difference between different wafers, and has better isolation and insulation effect, and can also reduce the generation of leakage current.
  • An embodiment of the present disclosure provides a method for preparing a shallow trench isolation structure.
  • a substrate By providing a substrate, a plurality of first grooves are formed on the substrate, and the cross-sectional width of the first grooves tends to increase downward along the vertical direction;
  • the top of the substrate and the inner sides of the plurality of first trenches form a continuous first isolation layer through a deposition process, and the part of the first isolation layer located in the first trench forms a second trench; wherein, the cross section of the second trench
  • the width remains constant downward in the vertical direction;
  • a continuous second isolation layer is formed on the surface of the first isolation layer by an ISSG process, and the part of the second isolation layer located in the second trench completely fills the second trench.
  • the cross-sectional width of the trenches is controlled to increase downward in the vertical direction, and then the first isolation layer is used to correct the cross-sectional width of the trenches so that it remains constant downward in the vertical direction , and finally fill the trench, which simplifies the manufacturing process of the shallow trench isolation structure and improves the insulation performance of the shallow trench isolation structure.
  • FIG. 5 shows a schematic structural diagram of a shallow trench isolation structure 20 provided by an embodiment of the present disclosure.
  • the shallow trench isolation structure 20 may include:
  • the base 201 includes a plurality of first grooves, the cross-sectional width of the first grooves tends to increase downward along the vertical direction;
  • the first isolation layer 202 is located inside the plurality of first trenches and the top of the substrate 201, and the part of the first isolation layer 202 located in the first trench forms a second trench, so The cross-sectional width of the second groove remains constant downward along the vertical direction;
  • the second isolation layer 203 is located on the surface of the first isolation layer 202 , and the part of the second isolation layer 203 located in the second trench completely fills the second trench.
  • the embodiments of the present disclosure provide a shallow trench isolation structure, which is applied to semiconductors.
  • the shallow trench isolation structure includes a substrate 201 , a first isolation layer 202 and a second isolation layer 203 .
  • a plurality of first grooves are formed on the substrate 201, and the lower half of the first grooves is wider than the upper half, so the cross-sectional width of the first grooves tends to increase vertically; then, The first isolation layer 202 first fills the first groove, and the cross-sectional shape of the first groove is modified to a U shape, so as to obtain a second groove whose cross-sectional width remains constant downward in the vertical direction; finally, the second isolation layer 203 Fill the second trench completely.
  • the trench formed on the substrate 201 is V-shaped, and polysilicon will be further deposited later to shorten the cross-sectional width of the upper half of the trench, so that Modifying the trench into a U-shape leads to a further reduction in the width of the trench actually used to fill the isolation layer (see the circled part in Figure 2D), resulting in a decrease in isolation performance.
  • the lower half of the first trench is widened, and the trench width is increased compared with the V-shaped trench, and there is no need to deposit polysilicon again to correct the trench shape, but by direct deposition
  • the isolation layer is used to modify the trench shape, further increasing the trench width (see the circled part in Figure 4C), thereby improving the isolation performance and reducing the leakage current.
  • the maximum cross-sectional width of the upper half of the first trench is smaller than the maximum cross-sectional width of the bottom half of the first trench.
  • etching when etching the first trench, it is necessary to control the parameters of the etching process, so that the cross-sectional width of the first trench tends to increase downward along the vertical direction.
  • etching can be determined according to actual application scenarios. That is to say, the plurality of first grooves are formed after etching the substrate 201 according to a preset etching process; wherein, the preset etching process includes dry etching and/or wet etching. etched.
  • the etching gas of the preset etching process may include one of sulfur hexafluoride SF 6 , fluorocarbon CFs, chlorine Cl 2 , and argon Ar or more.
  • the thickness of the first isolation layer 202 needs to decrease in the downward direction in the vertical direction, so that the correspondingly formed second trench The section width remains constant in the vertical direction.
  • the U-shaped second trench is obtained by controlling the step coverage of the first isolation layer 202 during the formation process. Therefore, the first isolation layer 202 is formed after depositing the substrate 201 after forming the plurality of first trenches by using an atomic layer deposition (ALD) process based on a preset step coverage; wherein, the ALD process Including at least one of the following: plasma ALD process, catalytic ALD process and thermal ALD process.
  • ALD atomic layer deposition
  • the preset step coverage is less than or equal to 80%.
  • the reaction pressure of the ALD process is 0.1-10 Torr
  • the reaction temperature of the ALD process is 300-600 degrees Celsius
  • the reaction gas of the ALD process is oxygen
  • the gas flow rate of the ALD process is 0.1-10 liters/ minute.
  • the preparation process of the second isolation layer 203 can be selected according to requirements.
  • the second isolation layer 203 is formed by depositing the substrate 201 after forming a plurality of the second trenches through the ISSG process until the plurality of the second trenches are filled. .
  • the reaction temperature of the ISSG process is 900-1050 degrees Celsius, and the reaction pressure of the ISSG process is 0.1-10 Torr.
  • both the first isolation layer 202 and the second isolation layer 203 include silicon oxide to achieve isolation performance.
  • An embodiment of the present disclosure provides a shallow trench isolation structure, which includes: a substrate including a plurality of first trenches, the cross-sectional width of the first trenches tends to increase downward along the vertical direction; An isolation layer, located inside the plurality of first trenches and on the top of the substrate, and the part of the first isolation layer located in the first trenches forms a second trench, the second trench The cross-sectional width of the groove remains constant downward in the vertical direction; the second isolation layer is located on the surface of the first isolation layer, and the part of the second isolation layer located in the second groove divides the second The trench is completely filled.
  • the cross-sectional width of the trenches is controlled to increase downward in the vertical direction, and then the first isolation layer is used to correct the cross-sectional width of the trenches so that it remains constant downward in the vertical direction , and finally fill the trench to obtain the front trench isolation structure, which simplifies the manufacturing process of the shallow trench isolation structure and improves the insulation performance of the shallow trench isolation structure.
  • FIG. 6 shows a semiconductor structure 30 provided by an embodiment of the present disclosure.
  • the semiconductor structure 30 includes the shallow trench isolation structure 20 described in any one of the foregoing embodiments.
  • the semiconductor structure 30 since it includes the shallow trench isolation structure 20, when forming a plurality of first trenches, the cross-sectional width of the control trenches tends to increase downward in the vertical direction, and then the first isolation layer is used to seal the trenches.
  • the cross-sectional width of the trench is corrected to remain constant downward in the vertical direction, and finally the trench is filled to obtain a front trench isolation structure, which simplifies the manufacturing process of the shallow trench isolation structure and improves the insulation performance of the shallow trench isolation structure.
  • a memory which includes the aforementioned semiconductor structure 30 .
  • the cross-sectional width of the control trenches tends to increase downwards in the vertical direction, and then the first isolation layer is used to reduce the cross-sectional width of the trenches.
  • the modification is to keep the vertical direction downward, and finally the trench is filled to obtain the front trench isolation structure, which simplifies the manufacturing process of the shallow trench isolation structure and improves the insulation performance of the shallow trench isolation structure.
  • Embodiments of the present disclosure provide a method for preparing a shallow trench isolation structure, a shallow trench isolation structure, and a semiconductor structure.
  • a substrate is provided, and a plurality of first trenches are formed on the substrate, and the cross-sectional width of the first trenches is along the vertical direction.
  • a continuous first isolation layer is formed on the top of the substrate and inside a plurality of first trenches through a deposition process, and the part of the first isolation layer located in the first trench forms a second trench; wherein , the cross-sectional width of the second trench remains constant downward in the vertical direction; a continuous second isolation layer is formed on the surface of the first isolation layer by an ISSG process, and the part of the second isolation layer located in the second trench Two trenches are completely filled.
  • the cross-sectional width of the trenches is controlled to increase downward in the vertical direction, and then the first isolation layer is used to correct the cross-sectional width of the trenches so that it remains constant downward in the vertical direction , and finally fill the trench to obtain the front trench isolation structure, which simplifies the manufacturing process of the shallow trench isolation structure and improves the insulation performance of the shallow trench isolation structure.

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Abstract

本公开实施例提供了一种浅槽隔离结构的制备方法、浅槽隔离结构和半导体结构，该浅槽隔离结构的制备方法包括：提供基底，于基底上形成多个第一沟槽，且第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；于基底的顶部和多个第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，且第一隔离层位于第一沟槽内的部分形成第二沟槽；第二沟槽的剖面宽度沿垂直方向向下保持不变；于第一隔离层的表面通过ISSG工艺形成连续的第二隔离层，且第二隔离层位于第二沟槽内的部分将第二沟槽完全填满。

Description

浅槽隔离结构的制备方法、浅槽隔离结构和半导体结构
相关申请的交叉引用
本申请基于申请号为202110925394.1、申请日为2021年8月12日、发明名称为“浅槽隔离结构的制备方法、浅槽隔离结构和半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体制作技术领域，尤其涉及一种浅槽隔离结构的制备方法、浅槽隔离结构和半导体结构。
背景技术
浅槽隔离(Shallow Trench Isolation，STI)能够提供较小的隔离尺寸，而且具有平坦化的表面，逐渐成为半导体制造工艺中的主流隔离方法。
然而，对于传统的浅槽隔离工艺，在刻蚀形成沟槽时，随着沟槽深度的增加，沟槽的横截面宽度会逐渐减小。也就是说，刻蚀后的沟槽实际为V形，而不是所希望的U形。因此，在初步形成沟槽后，还需要对沟槽进行后续处理步骤，导致浅槽隔离结构的制程复杂，而且最终获得的浅槽隔离结构的隔离性能也不够理想。
发明内容
本公开实施例提供了一种浅槽隔离结构的制备方法、浅槽隔离结构和半导体结构，能够简化浅槽隔离结构的制程，而且提高浅槽隔离结构的绝缘性能。
根据一些实施例，本公开第一方面提供了一种浅槽隔离结构的制备方法，该方法包括：
提供基底，于所述基底上形成多个第一沟槽，且所述第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；
于所述基底的顶部和多个所述第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，且所述第一隔离层位于所述第一沟槽内的部分形成第二沟槽；其中，所述第二沟槽的剖面宽度沿垂直方向向下保持不变；
于所述第一隔离层的表面通过ISSG工艺形成连续的第二隔离层，且所述第二隔离层位于所述第二沟槽内的部分将所述第二沟槽完全填满。
在一些实施例中，第一沟槽的上半部分的最大剖面宽度小于或等于第一沟槽的下半部分的最大剖面宽度。
在一些实施例中，所述于基底上形成多个第一沟槽，包括：
根据预设刻蚀工艺对基底进行刻蚀处理，得到多个第一沟槽；
其中，预设刻蚀工艺包括干法刻蚀和/或湿法刻蚀。
在一些实施例中，当预设刻蚀工艺为干法刻蚀时，预设刻蚀工艺的刻蚀气体至少包括以下的其中一种：六氟化硫SF 6、碳氟化合物CFs、氯气Cl 2和氩气Ar。
在一些实施例中，该方法还包括：
当第一隔离层位于第一沟槽内的部分形成第二沟槽时，控制第一隔离层的厚度沿垂直方向向下呈减小趋势，以使得第二沟槽的剖面宽度沿垂直方向向下保持不变。
在一些实施例中，所述于基底的顶部和多个第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，包括：
根据预设阶梯覆盖率，利用原子层沉积ALD工艺对形成多个第一沟槽后的基底进行沉积处理，得到第一隔离层；
其中，ALD工艺至少包括以下的其中一种：电浆式ALD工艺、触媒ALD工艺和热型ALD工艺。
在一些实施例中，预设阶梯覆盖率小于或等于80％。
在一些实施例中，ALD工艺的反应压力为0.1～10托，ALD工艺的反应温度为300～600摄氏度，ALD工艺的反应气体为氧气，ALD工艺的气体流速为0.1～10升/分钟。
在一些实施例中，所述于第一隔离层的表面通过ISSG工艺形成连续的第二隔离层，包括：
利用ISSG工艺对形成多个第二沟槽后的基底进行沉积处理，直至填满多个第二沟槽，得到第二隔离层。
在一些实施例中，ISSG工艺的反应温度为900～1050摄氏度，ISSG工艺的反应压力为0.1托～10托。
在一些实施例中，第一隔离层和第二隔离层包括氧化硅。
根据一些实施例，本公开实施例第二方面提供了一种浅槽隔离结构，该浅槽隔离结构包括：
基底，包括多个第一沟槽，第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；
第一隔离层，位于多个第一沟槽的内侧和基底的顶部，且第一隔离层位于第一沟槽内的部分形成第二沟槽，第二沟槽的剖面宽度沿垂直方向向下保持不变；
第二隔离层，位于第一隔离层的表面，且第二隔离层位于第二沟槽内的部分将第二沟槽完全填满。
在一些实施例中，第一沟槽的上半部分的最大剖面宽度小于第一沟槽的下半部分的最大剖面宽度。
在一些实施例中，多个第一沟槽是根据预设刻蚀工艺对基底进行刻蚀处理后形成的；其中，预设刻蚀工艺包括干法刻蚀和/或湿法刻蚀。
在一些实施例中，当预设刻蚀工艺为干法刻蚀时，预设刻蚀工艺的刻 蚀气体包括六氟化硫SF 6、碳氟化合物CFs、氯气Cl 2、氩气Ar中的一种或多种。
在一些实施例中，第一隔离层位于第一沟槽内的厚度沿垂直方向向下呈减小趋势，以使得对应形成的第二沟槽的剖面宽度在垂直方向上保持不变。
在一些实施例中，第二隔离层是通过ISSG工艺对形成多个第二沟槽后的基底进行沉积处理，直至填满多个第二沟槽后形成的。
在一些实施例中，第一隔离层和第二隔离层包括氧化硅。
根据一些实施例，本公开实施例第三方面提供了一种半导体结构，包括如第二方面所述的浅槽隔离结构。
本公开实施例提供了一种浅槽隔离结构的制备方法、浅槽隔离结构和半导体结构，提供基底，于基底上形成多个第一沟槽，且第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；于基底的顶部和多个第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，且第一隔离层位于第一沟槽内的部分形成第二沟槽；其中，第二沟槽的剖面宽度沿垂直方向向下保持不变；于第一隔离层的表面通过ISSG工艺形成连续的第二隔离层，且第二隔离层位于第二沟槽内的部分将第二沟槽完全填满。这样，在形成多个第一沟槽时，控制沟槽的剖面宽度沿垂直方向向下呈增大趋势，然后利用第一隔离层将沟槽的剖面宽度修正为沿垂直方向向下保持不变，最后将沟槽填满以得到前槽隔离结构，简化了浅槽隔离结构的制程，而且提高浅槽隔离结构的绝缘性能。
附图说明
图1为相关技术中的一种反应腔室的结构示意图；
图2A为相关技术中的一种浅槽隔离结构的制备过程示意图一；
图2B为相关技术中的一种浅槽隔离结构的制备过程示意图二；
图2C为相关技术中的一种浅槽隔离结构的制备过程示意图三；
图2D为相关技术中的一种浅槽隔离结构的制备过程示意图四；
图3为本公开实施例提供的一种浅槽隔离结构的制备方法的流程示意图；
图4A为本公开实施例提供的一种浅槽隔离结构的制备过程示意图一；
图4B为本公开实施例提供的一种浅槽隔离结构的制备过程示意图二；
图4C为本公开实施例提供的一种浅槽隔离结构的制备过程示意图三；
图5为本公开实施例提供的一种浅槽隔离结构的结构示意图；
图6为本公开实施例提供的一种半导体结构的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。可以理解的是，此处所描述的具体实施例仅仅用于解释相关申请，而非对该申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与有关申请相关的部分。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本申请。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在不冲突的情况下相互结合。
需要指出，本公开实施例所涉及的术语“第一\第二\第三”仅是用于区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
应理解，为使本公开实施例的目的、技术方案和优点更加清楚，下面 将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
以下为本公开实施例中一些英文名词及英文缩写的含义。
AA(Active Area)：有源区，有源区之间可以利用浅沟槽进行隔离。
ALD(Atomic layer deposition)：原子层沉积
ISSG(In-Situ Steam Generation)：原位水气生成
HQO(High Quality Oxide)：高质量氧化
DRAM(Dynamic Random Access Memory)：动态随机存取存储器
浅槽隔离结构(也称为浅沟槽隔离结构)是半导体中重要的隔离结构，一般用于有源区之间的隔离。参见图1，其示出了相关技术中的一种浅槽隔离结构的结构示意图。如图1所示，浅槽隔离结构包括多晶硅形成的基底，且基底上具有多个沟槽，这些沟槽内被氧化硅填充，氧化硅在基底上方形成平坦化的表面，进而沉积氮化硅以及其他功能结构。
浅槽隔离结构是DRAM制备工艺中的重要部分。虽然浅槽隔离结构的制备方法有许多种，但是这些制备方法均存在制程复杂的缺点。具体地，在当前DRAM工艺中，由于沟槽的特性无法直接形成U形的沟槽，需要进一步使用多晶硅化学气相沉积的方法先形成U形沟槽，然后使用氧化工艺(例如HQO ALD工艺、ISSG工艺)填满沟槽，最终得到浅槽隔离结构。
请参见图2，其示出了相关技术中的一种浅槽隔离结构的制备方法的流程示意图。如图2A所示，针对基底，在进行有源区(AA)刻蚀后，形成了多个V形沟槽；然后，如图2B所示，在V形沟槽中进行多晶硅气相沉积，将沟槽修正为U形，增加沟槽与沟槽之间的距离，避免导致器件短路，另外，在进行多晶硅沉积时，需要采用低阶梯覆盖率，从而在垂直方向上 控制沟槽的剖面宽度相同，得到U形沟槽；之后，如图2C所示，在形成U形沟槽后，利用HQO ALD工艺进行氧化，形成第一层氧化硅层；如图2D所示，在沟槽中继续使用ISSG工艺填满沟槽，进一步让沟槽充满氧化硅薄层，达到隔离的效果。
从以上可以看出，现有的浅槽隔离结构的制备方法较为复杂，且前槽隔离结构中用于填充氧化硅的沟槽宽度会比预想的窄，降低了隔离性能。然而，如果将浅槽隔离结构的制程进行微缩，那么获得的浅槽隔离结构的尺寸也随之微缩，从而浅沟槽的绝缘层性质以及浅沟槽的形状就显得非常重要。
基于此，本公开实施例提供了一种浅槽隔离结构的制备方法，其基本思想是：提供基底，于基底上形成多个第一沟槽，且第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；于基底的顶部和多个第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，且第一隔离层位于第一沟槽内的部分形成第二沟槽；其中，第二沟槽的剖面宽度沿垂直方向向下保持不变；于第一隔离层的表面通过ISSG工艺形成连续的第二隔离层，且第二隔离层位于第二沟槽内的部分将第二沟槽完全填满。这样，在形成多个第一沟槽时，控制沟槽的剖面宽度沿垂直方向向下呈增大趋势，然后利用第一隔离层将沟槽的剖面宽度修正为沿垂直方向向下保持不变，最后将沟槽填满以得到前槽隔离结构，简化了浅槽隔离结构的制程，而且提高浅槽隔离结构的绝缘性能。
下面将结合附图对本申请各实施例进行详细说明。
在本申请的一实施例中，参见图3，其示出了本公开实施例提供的一种浅槽隔离结构的制备方法的流程示意图。如图3所示，该方法可以包括：
S101：提供基底，于基底上形成多个第一沟槽，且第一沟槽的剖面宽度沿垂直方向向下呈增大趋势。
需要说明的是，本公开实施例提供了一种浅槽隔离结构的制备方法，应用于半导体结构。
在本公开实施例中，需要对基底进行刻蚀以得到多个第一沟槽。在形成第一沟槽时，需要将沟槽的下半部分拓宽一些，以控制第一沟槽的剖面宽度沿垂直方向向下呈增大趋势。参见图4，其示出了本公开实施例提供的一种浅槽隔离结构的制备过程示意图。如图4A所示，基底201形成有多个第一沟槽，对于第一沟槽来说，其上半部分的剖面形状几乎不变，但是其下半部分的剖面宽度随深度逐渐增加，即a处的剖面宽度小于b处的剖面宽度。
在这里，第一沟槽可以通过对基底进行刻蚀得到，具体的刻蚀工艺需要根据实际应用场景进行选择，本公开实施例不做限制。因此，在一些实施例中，于基底上形成多个第一沟槽，可以包括：
根据预设刻蚀工艺对基底进行刻蚀处理，得到多个第一沟槽；其中，预设刻蚀工艺包括干法刻蚀和/或湿法刻蚀。
还需要说明的是，在刻蚀得到第一沟槽时，需要控制刻蚀工艺中的具体参数，以使得第一沟槽的剖面宽度沿垂直方向向下呈增大趋势，具体的控制方法需要结合刻蚀设备、刻蚀工艺种类、刻蚀材料等确定，本领域技术人员可以依据本行业的理论知识进行设计。
另外，关于第一沟槽的拓宽程度可以根据实际应用需求进行确定。一般来说，第一沟槽的上半部分的最大剖面宽度小于第一沟槽的下半部分的最大剖面宽度。或者在一些实施例中，第一沟槽的上半部分的最大剖面宽度也可以等于第一沟槽的下半部分的最大剖面宽度。
特别地，在采用干法刻蚀的实施例中，预设刻蚀工艺的刻蚀气体至少包括以下的其中一种：六氟化硫SF 6、碳氟化合物CFs、氯气Cl 2和氩气Ar。
也就是说，在相关技术中，第一沟槽是呈现V形的，其剖面宽度沿垂 直方向向下逐渐减小；而在本公开实施例中，第一沟槽的下半部分被拓宽，所以其剖面宽度沿垂直方向向下呈增大趋势。
S102：于基底的顶部和多个第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，且第一隔离层位于第一沟槽内的部分形成第二沟槽；其中，第二沟槽的剖面宽度沿垂直方向向下保持不变。
需要说明的是，在形成多个第一沟槽后，利用沉积工艺在基底上沉积形成第一隔离层，第一隔离层位于第一沟槽内侧的部分形成了第二沟槽，且第二沟槽的剖面宽度沿垂直方向向下保持不变。
参见图4B，其示出了本公开实施例提供的一种浅槽隔离结构的制备过程示意图二。如图4B所示，在基底的顶部和多个第一沟槽的内侧沉积了第一隔离层202。其中，第一隔离层202在第一沟槽内的部分形成了第二沟槽，且第二沟槽呈现U形，即第二沟槽的剖面宽度沿垂直方向向下保持不变。
进一步地，在一些实施例中，当第一隔离层位于第一沟槽内的部分形成第二沟槽时，控制第一隔离层的厚度沿垂直方向向下呈减小趋势，以使得第二沟槽的剖面宽度沿垂直方向向下保持不变。
还需要说明的是，由于第一沟槽的剖面宽度在下半部分有所增加，所以第一隔离层的厚度也并非是均匀的。在一种具体的实施例中，所述于基底的顶部和多个第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，可以包括：
根据预设阶梯覆盖率，利用原子层沉积ALD工艺对形成多个第一沟槽后的基底进行沉积处理，得到第一隔离层；
其中，ALD工艺至少包括以下的其中一种：电浆式ALD工艺(PE-ALD工艺)、触媒ALD工艺和热型ALD工艺(Thermal ALD工艺)。
需要说明的是，第一隔离层可以利用ALD工艺得到。具体地，基底一般由多晶硅构成，在ALD工艺中，向基底持续通入氧气，且保持基底处于 预设温度和预设压力下，此时基底表面的多晶硅会逐渐氧化为氧化硅，从而得到第一隔离层。也就是说，在利用ALD工艺沉积第一隔离层时，ALD工艺中通入的氧气会消耗多晶硅底材，需要通过控制氧气流量、电离强度、温度或压力来进一步控制消耗底材的能力。
还需要说明的是，在形成第一隔离层时，需要采用低的阶梯覆盖率，从而让第一隔离层位于第一沟槽下部的部分较厚，让第一隔离层位于第一沟槽上部的部分较薄，从而形成U形的第二沟槽。以ALD工艺为例，可以通过调整ALD工艺的流量、延长种子时间(Seed Time)等方法来得到低阶梯覆盖率。
优选地，预设阶梯覆盖率小于或等于80％。
还需要说明的是，在一些实施例中可以采用PE-ALD工艺，此时，ALD工艺的反应压力为0.1～10托，ALD工艺的反应温度为300～600摄氏度，ALD工艺的反应气体为氧气，ALD工艺的气体流速为0.1～10升/分钟。
也就是说，在本公开实施例中，无需在沟槽内沉积多晶硅以修正V形沟槽为U形沟槽，这将导致隔离层的填充空间减小，进而隔离绝缘能力下降；而是直接通过沉积隔离层将V形沟槽修正成U形，此时并不会导致隔离层的填充空间减小，而且第一沟槽的下半部分进行了拓宽，因此还会增加隔离层的填充空间，进而增加隔离绝缘能力。
S103：于第一隔离层的表面通过ISSG工艺形成连续的第二隔离层，且第二隔离层位于第二沟槽内的部分将第二沟槽完全填满。
需要说明的是，如图4C所示，在填充第一隔离层202后，利用ISSG工艺继续形成连续的第二隔离层203，以填满第二沟槽，这样就得到了浅槽隔离结构。
特别地，在浅槽隔离结构中，基底主要由多晶硅构成，第一隔离层和第二隔离层主要由氧化硅构成，以起到隔离绝缘作用。
进一步地，在一些实施例中，ISSG工艺的反应温度为900～1050摄氏度，ISSG工艺的反应压力为0.1～10托。
这样，在本公开实施例中，只需要进行三个步骤就可以获得浅槽隔离结构，简化了浅槽隔离结构的制程，且提高了浅槽隔离结构的隔离效率。
以下仅以其中一种可行方案为例对本公开实施例提供的制备方法进行具体说明。首先，如图4A所示，在AA刻蚀完，将沟槽底部尝试吃宽一点，不需要使用多晶硅沉积达到沟槽所需宽度。其次，如图4B所示，利用电浆式原子堆叠氧化(PE ALD OX)方法在沟槽内形成低阶梯覆盖率，使AA隔离形成U形。在这里，主要通过控制PE ALD OX的不同的流量以及更长Seed Time进行沉积来得到低的阶梯覆盖率，进而让沟槽底部形成较厚的隔离层。最后，如图4C所示，利用ISSG工艺，继续填满浅沟槽，最终得到浅槽隔离结构。
在相关实施例中，由于沟槽的特性以及制备工艺的限制，基底201上形成的沟槽是V形的，而且后续会进一步沉积多晶硅缩短沟槽上半部分的剖面宽度，以得到U形沟槽，导致实际用于填充隔离层的沟槽宽度进一步减小(请参见图2D中的圆圈部分)，导致了隔离性能下降。在本公开实施例中，第一沟槽的下半部分进行了拓宽，较之V形沟槽来说沟槽宽度有所增加，而且无需再次沉积多晶硅来修正沟槽形状，而是通过直接沉积隔离层来修正沟槽形状，进一步增加了沟槽宽度(请参见图4C中的圆圈部分)，从而提高了隔离性能，还可以减少漏电流。
这样，本公开实施例提供了一种新的方法来制备浅沟槽隔离结构，首先采用干法刻蚀的方法形成AA沟槽，然后使用电浆式原子沉积氧化硅取代多晶硅以及HQO炉管制程，再进行ISSG制程即可得到浅槽隔离结构。与相关技术相比，本公开实施例可以减少一道制程，并且取代HQO炉管制程，进而更好的降低不同晶片间的差异，而且隔离绝缘效果更好，还可以 减少漏电流的产生。
本公开实施例提供了一种浅槽隔离结构的制备方法，通过提供基底，于基底上形成多个第一沟槽，且第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；于基底的顶部和多个第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，且第一隔离层位于第一沟槽内的部分形成第二沟槽；其中，第二沟槽的剖面宽度沿垂直方向向下保持不变；于第一隔离层的表面通过ISSG工艺形成连续的第二隔离层，且第二隔离层位于第二沟槽内的部分将第二沟槽完全填满。这样，在形成多个第一沟槽时，控制沟槽的剖面宽度沿垂直方向向下呈增大趋势，然后利用第一隔离层将沟槽的剖面宽度修正为沿垂直方向向下保持不变，最后将沟槽填满即可，简化了浅槽隔离结构的制程，而且提高浅槽隔离结构的绝缘性能。
在本申请的另一实施例中，参见图5，其示出了本公开实施例提供的一种浅槽隔离结构20的结构示意图。如图5所示，浅槽隔离结构20可以包括：
基底201，包括多个第一沟槽，所述第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；
第一隔离层202，位于所述多个第一沟槽的内侧和所述基底201的顶部，且所述第一隔离层202位于所述第一沟槽内的部分形成第二沟槽，所述第二沟槽的剖面宽度沿垂直方向向下保持不变；
第二隔离层203，位于所述第一隔离层202的表面，且所述第二隔离层203位于所述第二沟槽内的部分将所述第二沟槽完全填满。
需要说明的是，本公开实施例提供了一种浅槽隔离结构，应用于半导体。浅槽隔离结构包括基底201、第一隔离层202和第二隔离层203。其中，基底201上形成多个第一沟槽，且第一沟槽的下半部分较之上半部分经过了拓宽，因此第一沟槽的剖面宽度沿垂直方向下呈增大趋势；然后，第一 隔离层202先填充第一沟槽，将第一沟槽的剖面形状修正为U形，以得到剖面宽度沿垂直方向向下保持不变的第二沟槽；最后，第二隔离层203将第二沟槽完全填满。
在这里，在相关实施例中，由于沟槽的特性以及制备工艺的限制，基底201上形成的沟槽是V形的，而且后续会进一步沉积多晶硅以缩短沟槽上半部分的剖面宽度，从而将沟槽修正为U形，导致实际用于填充隔离层的沟槽宽度进一步减小(请参见图2D中的圆圈部分)，导致了隔离性能下降。在本公开实施例中，第一沟槽的下半部分进行了拓宽，较之V形沟槽来说沟槽宽度有所增加，而且无需再次沉积多晶硅来修正沟槽形状，而是通过直接沉积隔离层来修正沟槽形状，进一步增加了沟槽宽度(请参见图4C中的圆圈部分)，从而提高了隔离性能，还可以减少漏电流。
优选地，在一些实施例中，所述第一沟槽的上半部分的最大剖面宽度小于所述第一沟槽的下半部分的最大剖面宽度。
需要说明的是，在本公开实施例中，在刻蚀第一沟槽时，需要控制刻蚀工艺的参数，以使得第一沟槽的剖面宽度沿垂直方向向下呈增大趋势。在这里，刻蚀可以根据实际应用场景确定。也就是说，所述多个第一沟槽是根据预设刻蚀工艺对所述基底201进行刻蚀处理后形成的；其中，所述预设刻蚀工艺包括干法刻蚀和/或湿法刻蚀。
特别的，对于采用干法刻蚀得到第一沟槽时，预设刻蚀工艺的刻蚀气体可以包括六氟化硫SF 6、碳氟化合物CFs、氯气Cl 2、氩气Ar中的一种或多种。
进一步地，由于第一沟槽的剖面宽度沿垂直方向向下呈增大趋势，因此第一隔离层202的厚度需要沿垂直方向向下呈减小趋势，以使得对应形成的第二沟槽的剖面宽度在垂直方向上保持不变。
在一种具体的实施例中，通过控制第一隔离层202在形成过程中的阶 梯覆盖率，从而得到U形的第二沟槽。因此，所述第一隔离层202是基于预设阶梯覆盖率，利用原子层沉积ALD工艺对形成多个所述第一沟槽后的基底201进行沉积处理后形成的；其中，所述ALD工艺至少包括以下的其中一种：电浆式ALD工艺、触媒ALD工艺和热型ALD工艺。
优选地，预设阶梯覆盖率小于或等于80％。以及，对于电浆式ALD工艺，ALD工艺的反应压力为0.1～10托，ALD工艺的反应温度为300～600摄氏度，ALD工艺的反应气体为氧气，ALD工艺的气体流速为0.1～10升/分钟。
需要说明的是，第二隔离层203的制备工艺可以根据需求选用。在一种具体的实施例中，第二隔离层203是通过ISSG工艺对形成多个所述第二沟槽后的基底201进行沉积处理，直至填满多个所述第二沟槽后形成的。
优选地，所述ISSG工艺的反应温度为900～1050摄氏度，所述ISSG工艺的反应压力为0.1～10托。
特别地，第一隔离层202和第二隔离层203均包括氧化硅，以实现隔离性能。
本公开实施例提供了一种浅槽隔离结构，该浅槽隔离结构包括：基底，包括多个第一沟槽，所述第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；第一隔离层，位于所述多个第一沟槽的内侧和所述基底的顶部，且所述第一隔离层位于所述第一沟槽内的部分形成第二沟槽，所述第二沟槽的剖面宽度沿垂直方向向下保持不变；第二隔离层，位于所述第一隔离层的表面，且所述第二隔离层位于所述第二沟槽内的部分将所述第二沟槽完全填满。这样，在形成多个第一沟槽时，控制沟槽的剖面宽度沿垂直方向向下呈增大趋势，然后利用第一隔离层将沟槽的剖面宽度修正为沿垂直方向向下保持不变，最后将沟槽填满以得到前槽隔离结构，简化了浅槽隔离结构的制程，而且提高浅槽隔离结构的绝缘性能。
在又一实施例中，参见图6，其示出了本公开实施例提供的一种半导体结构30。如图6所示，该半导体结构30包括前述实施例任一项所述的浅槽隔离结构20。
对于半导体结构30来说，由于其包括浅槽隔离结构20，在形成多个第一沟槽时，控制沟槽的剖面宽度沿垂直方向向下呈增大趋势，然后利用第一隔离层将沟槽的剖面宽度修正为沿垂直方向向下保持不变，最后将沟槽填满以得到前槽隔离结构，简化了浅槽隔离结构的制程，而且提高浅槽隔离结构的绝缘性能。
在再一实施例中，提供一种存储器，该存储器包括前述的半导体结构30。对于存储器来说，由于其包括半导体结构30，在形成多个第一沟槽时，控制沟槽的剖面宽度沿垂直方向向下呈增大趋势，然后利用第一隔离层将沟槽的剖面宽度修正为沿垂直方向向下保持不变，最后将沟槽填满以得到前槽隔离结构，简化了浅槽隔离结构的制程，而且提高浅槽隔离结构的绝缘性能。
以上，仅为本申请的较佳实施例而已，并非用于限定本申请的保护范围。
需要说明的是，在本申请中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
本申请所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本申请所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或设备实施例。
以上，仅为本公开实施例的具体实施方式，但本公开实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开实施例的保护范围之内。因此，本公开实施例的保护范围应以权利要求的保护范围为准。
工业实用性
本公开实施例提供了一种浅槽隔离结构的制备方法、浅槽隔离结构和半导体结构，提供基底，于基底上形成多个第一沟槽，且第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；于基底的顶部和多个第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，且第一隔离层位于第一沟槽内的部分形成第二沟槽；其中，第二沟槽的剖面宽度沿垂直方向向下保持不变；于第一隔离层的表面通过ISSG工艺形成连续的第二隔离层，且第二隔离层位于第二沟槽内的部分将第二沟槽完全填满。这样，在形成多个第一沟槽时，控制沟槽的剖面宽度沿垂直方向向下呈增大趋势，然后利用第一隔离层将沟槽的剖面宽度修正为沿垂直方向向下保持不变，最后将沟槽填满以得到前槽隔离结构，简化了浅槽隔离结构的制程，而且提高浅槽隔离结构的绝缘性能。

Claims (19)

  1. 一种浅槽隔离结构的制备方法，所述方法包括：
    提供基底，于所述基底上形成多个第一沟槽，且所述第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；
    于所述基底的顶部和多个所述第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，且所述第一隔离层位于所述第一沟槽内的部分形成第二沟槽；其中，所述第二沟槽的剖面宽度沿垂直方向向下保持不变；
    于所述第一隔离层的表面通过ISSG工艺形成连续的第二隔离层，且所述第二隔离层位于所述第二沟槽内的部分将所述第二沟槽完全填满。
  2. 根据权利要求1所述的制备方法，其中，所述第一沟槽的上半部分的最大剖面宽度小于或等于所述第一沟槽的下半部分的最大剖面宽度。
  3. 根据权利要求1所述的制备方法，其中，所述于所述基底上形成多个第一沟槽，包括：
    根据预设刻蚀工艺对所述基底进行刻蚀处理，得到多个所述第一沟槽；
    其中，所述预设刻蚀工艺包括干法刻蚀和/或湿法刻蚀。
  4. 根据权利要求3所述的制备方法，其中，当所述预设刻蚀工艺为干法刻蚀时，所述预设刻蚀工艺的刻蚀气体至少包括以下的其中一种：六氟化硫SF 6、碳氟化合物CFs、氯气Cl 2和氩气Ar。
  5. 根据权利要求1所述的制备方法，其中，所述方法还包括：
    当所述第一隔离层位于所述第一沟槽内的部分形成第二沟槽时，控制所述第一隔离层的厚度沿垂直方向向下呈减小趋势，以使得所述第二沟槽的剖面宽度沿垂直方向向下保持不变。
  6. 根据权利要求5所述的制备方法，其中，所述于所述基底的顶部 和多个所述第一沟槽的内侧通过沉积工艺形成连续的第一隔离层，包括：
    根据预设阶梯覆盖率，利用原子层沉积ALD工艺对形成多个所述第一沟槽后的基底进行沉积处理，得到所述第一隔离层；
    其中，所述ALD工艺至少包括以下的其中一种：电浆式ALD工艺、触媒ALD工艺和热型ALD工艺。
  7. 根据权利要求6所述的制备方法，其中，所述预设阶梯覆盖率小于或等于80％。
  8. 根据权利要求6所述的制备方法，其中，所述ALD工艺的反应压力为0.1～10托，所述ALD工艺的反应温度为300～600摄氏度，所述ALD工艺的反应气体为氧气，所述ALD工艺的气体流速为0.1～10升/分钟。
  9. 根据权利要求1所述的制备方法，其中，所述于所述第一隔离层的表面通过ISSG工艺形成连续的第二隔离层，包括：
    利用ISSG工艺对形成多个所述第二沟槽后的基底进行沉积处理，直至填满多个所述第二沟槽，得到所述第二隔离层。
  10. 根据权利要求9所述的制备方法，其中，
    所述ISSG工艺的反应温度为900～1050摄氏度，所述ISSG工艺的反应压力为0.1托～10托。
  11. 根据权利要求1至10任一项所述的制备方法，其中，所述第一隔离层和所述第二隔离层包括氧化硅。
  12. 一种浅槽隔离结构，包括：
    基底，包括多个第一沟槽，所述第一沟槽的剖面宽度沿垂直方向向下呈增大趋势；
    第一隔离层，位于所述多个第一沟槽的内侧和所述基底的顶部，且所述第一隔离层位于所述第一沟槽内的部分形成第二沟槽，所述第二沟 槽的剖面宽度沿垂直方向向下保持不变；
    第二隔离层，位于所述第一隔离层的表面，且所述第二隔离层位于所述第二沟槽内的部分将所述第二沟槽完全填满。
  13. 根据权利要求12所述的浅槽隔离结构，其中，所述第一沟槽的上半部分的最大剖面宽度小于所述第一沟槽的下半部分的最大剖面宽度。
  14. 根据权利要求12所述的浅槽隔离结构，其中，所述多个第一沟槽是根据预设刻蚀工艺对所述基底进行刻蚀处理后形成的；其中，所述预设刻蚀工艺包括干法刻蚀和/或湿法刻蚀。
  15. 根据权利要求14所述的浅槽隔离结构，其中，当所述预设刻蚀工艺为干法刻蚀时，所述预设刻蚀工艺的刻蚀气体包括六氟化硫SF 6、碳氟化合物CFs、氯气Cl 2、氩气Ar中的一种或多种。
  16. 根据权利要求12所述的浅槽隔离结构，其中，
    所述第一隔离层位于所述第一沟槽内的厚度沿垂直方向向下呈减小趋势，以使得对应形成的第二沟槽的剖面宽度在垂直方向上保持不变。
  17. 根据权利要求12所述的浅槽隔离结构，其中，所述第二隔离层是通过ISSG工艺对形成多个所述第二沟槽后的基底进行沉积处理，直至填满多个所述第二沟槽后形成的。
  18. 根据权利要求12至17任一项所述的浅槽隔离结构，其中，所述第一隔离层和所述第二隔离层包括氧化硅。
  19. 一种半导体结构，包括如权利要求12至18任一项所述的浅槽隔离结构。
PCT/CN2021/129229 2021-08-12 2021-11-08 浅槽隔离结构的制备方法、浅槽隔离结构和半导体结构 Ceased WO2023015751A1 (zh)

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