WO2023004875A1 - 薄膜晶体管及显示面板 - Google Patents

薄膜晶体管及显示面板 Download PDF

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Publication number
WO2023004875A1
WO2023004875A1 PCT/CN2021/111220 CN2021111220W WO2023004875A1 WO 2023004875 A1 WO2023004875 A1 WO 2023004875A1 CN 2021111220 W CN2021111220 W CN 2021111220W WO 2023004875 A1 WO2023004875 A1 WO 2023004875A1
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Prior art keywords
thin film
film transistor
gate
heavily doped
size
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Ceased
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PCT/CN2021/111220
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English (en)
French (fr)
Inventor
程洪
田超
管延庆
刘广辉
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US17/598,275 priority Critical patent/US12132120B2/en
Publication of WO2023004875A1 publication Critical patent/WO2023004875A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present application relates to the field of display technology, in particular to a thin film transistor and a display panel.
  • the thin film transistor with double channels will fail when continuously subjected to bias stress, which is not conducive to the stability of the thin film transistor with double channels.
  • the purpose of the present application is to provide a thin film transistor and a display panel, so as to solve the problem that the double channel thin film transistor fails continuously due to bias stress.
  • a thin film transistor comprising:
  • a gate pattern including a first gate and a second gate which are arranged at intervals and are electrically connected to each other;
  • Active patterns including:
  • the first transfer portion has a first size
  • the second transmission portion is electrically connected to the heavily doped drain portion and at least partially overlaps the second gate, in a direction in which the second transmission portion points to the heavily doped drain portion, the second transfer portion has a second size;
  • both the first transmission part and the second transmission part are located between the source heavily doped part and the drain heavily doped part, and the first transmission part and the second transmission part
  • the parts are arranged at intervals, and the first size is different from the second size.
  • a kind of thin film transistor, described thin film transistor comprises:
  • a gate pattern including a first gate and a second gate which are arranged at intervals and are electrically connected to each other;
  • Active patterns including:
  • the first transfer portion has a first size
  • the second transmission portion is electrically connected to the heavily doped drain portion and at least partially overlaps the second gate, in a direction in which the second transmission portion points to the heavily doped drain portion, the second transfer portion has a second size;
  • both the first transmission part and the second transmission part are located between the source heavily doped part and the drain heavily doped part, and the first transmission part and the second transmission part Partial interval setting;
  • the electric field intensity applied to the carriers transported by the first transport part is different from the electric field intensity applied to the carriers transported by the second transport part.
  • a display panel the display panel includes the above-mentioned thin film transistor.
  • the present application provides a thin film transistor and a display panel, by making the first size of the first transfer part electrically connected to the heavily doped source part and the first size of the second transfer part electrically connected to the heavily doped drain part
  • the two sizes are different, wherein the first size is the size of the first transfer part in the direction of the first transfer part pointing to the source heavily doped part, and the second size is the second transfer part pointing to the drain heavily doped part
  • the size in the direction of the portion so that the transmission portion corresponding to the larger one of the first size or the second size receives a small electric field intensity on the carriers transported when the thin film transistor is turned on, reducing the impact of the carriers on the source. Or the bombardment of the drain, improve the damage of the bias stress to the source or the drain, and improve the stability of the thin film transistor.
  • FIG. 1 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present application
  • FIG. 2 is a schematic plan view of the thin film transistor shown in FIG. 1;
  • FIG. 3 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present application.
  • FIG. 4 is a schematic plan view of the thin film transistor shown in FIG. 3;
  • FIG. 5 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 6 is a structural diagram of a gate driving circuit of the display panel shown in FIG. 5;
  • FIG. 7 is a schematic circuit diagram of the gate driving circuit shown in FIG. 6 .
  • FIG. 1 is a schematic cross-sectional view of the thin film transistor of the embodiment of the present application
  • FIG. 2 is a schematic plan view of the thin film transistor shown in FIG. 1
  • the thin film transistor is an N-type thin film transistor
  • the thin film transistor 100 includes an active pattern 10 , a gate insulating layer 20 , a gate pattern 30 , an interlayer insulating layer 40 and a source-drain electrode lead 50 .
  • the thin film transistor may also be a P-type thin film transistor.
  • the active pattern 10 is strip-shaped, and the active pattern 10 is linear.
  • the preparation material of the active pattern 10 is low temperature polysilicon.
  • the active pattern 10 may also be made of metal oxide semiconductor material, such as InGaZnO.
  • the active pattern 10 includes a heavily doped source portion 101 , a first transfer portion 102 , a heavily doped drain portion 103 , a second transfer portion 104 and an intermediate connection portion 105 .
  • the first transmission part 102 is adjacent to and electrically connected to the source heavily doped part 101
  • the second transmission part 104 is adjacent to and electrically connected to the drain heavily doped part 103.
  • the first transmission part 102 and the second transmission part 104 are located between the heavily doped source portion 101 and the heavily doped drain portion 103, the first transfer portion 102 and the second transfer portion 104 are spaced apart, and the second transfer portion 104 and the first transfer portion 102 are respectively connected to opposite sides of the middle connecting portion 105 .
  • Both the first transmission part 102 and the second transmission part 104 are used to transmit carriers.
  • the intermediate connection 105 is also used to transport charge carriers.
  • the first transmission part 102 includes a first channel 1021 and at least one first lightly doped part 1022, the first channel 1021 has not undergone ion implantation treatment, the first lightly doped part 1022 and the source
  • the extremely heavily doped portion 101 is obtained by ion implantation of semiconductors, and the ion implantation dose of the first lightly doped portion 1022 is smaller than the ion implantation dose of the source heavily doped portion 101
  • the second transmission portion 104 includes a first Two channels 1041 and at least one second lightly doped portion 1042, the second channel 1041 has not undergone ion implantation treatment, the second lightly doped portion 1042 and the drain heavily doped portion 103 are obtained by semiconductor ion implantation , the ion implantation dose of the second lightly doped part 1042 is the same as the ion implantation dose of the first lightly doped part 1022, the ion implantation dose of the source heavily doped part 101 is the same as the ion implantation dose of the drain heavily doped part 103
  • the ion implantation dose of the source heavily doped portion 101 and the ion implantation dose of the drain heavily doped portion 103 are both 10 14 ions per cubic centimeter, and the ion implantation dose of the second lightly doped portion 1042
  • the ion implantation dose of the first lightly doped portion 1022 is 10 13 ions per cubic centimeter.
  • the first transmission part 102 includes two first lightly doped parts 1022 and a first channel 1021, the two first lightly doped parts 1022 are connected to opposite sides of the first channel 1021, and one first lightly doped part 1021
  • the doped part 1022 is connected between the heavily doped source part 101 and the first channel 1021, and the other first lightly doped part 1022 is connected to the side of the first channel 1021 away from the heavily doped source part 101.
  • the two first lightly doped parts 1022 are the same;
  • the second transmission part 104 includes two second lightly doped parts 1042 and a second channel 1041, and the two second lightly doped parts 1042 are connected to opposite sides of the second channel 1041.
  • first transmission part 102 may also include only one first lightly doped part 1022 and the first lightly doped part 1022 is disposed between the first channel 1021 and the source heavily doped part 101
  • second transmission portion 104 may also include only one second lightly doped portion 1042 and the second lightly doped portion 1042 is disposed between the second channel 1041 and the heavily doped drain portion 103 .
  • the first transfer portion 102 in the direction where the first transfer portion 102 points to the heavily doped source portion 101 , the first transfer portion 102 has a first dimension D1; in the direction where the second transfer portion 104 points to the heavily doped drain portion 103 direction, the second transmission part 104 has a second dimension D2, and the first dimension D1 is different from the second dimension D2, so that the electric field strength applied to the carrier transported by the first transmission part 102 when the thin film transistor is turned on is the same as that applied to the first transmission part 102.
  • the electric field strengths of the carriers transported by the two transport parts 104 are different, and the transport part corresponding to the larger one of the first dimension D1 or the second dimension D2 receives a smaller electric field intensity when the thin film transistor is turned on. , reduce the bombardment effect of carriers on the source or drain, improve the damage of bias stress to the source or drain, and improve the stability of the thin film transistor.
  • the first dimension D1 is smaller than the second dimension D2, so that the electric field strength applied to the carriers during the carrier transport process of the second transport part 104 is small, and the bombardment effect of the carriers on the drain is small, which is beneficial to solve
  • the drain of the thin film transistor is subject to a large bias stress.
  • the first dimension D1 may also be larger than the second dimension D2, so as to reduce the bombardment effect of the carriers on the source.
  • the first channel 1021 is a part of the first transmission part 102 that overlaps with the first gate 301 in the thickness direction of the thin film transistor, and the first transmission part 102 points to the heavily doped source part 101 In the direction of , the first channel 1021 has a third dimension D3, and the two first lightly doped parts 1022 have a fifth dimension 2 ⁇ D5;
  • the second channel 1041 is the In the overlapping part in the thickness direction of the thin film transistor, in the direction in which the second transmission part 104 points to the drain heavily doped part 103, the second channel 1041 has a fourth dimension D4, and the two second lightly doped parts 1042 Has a sixth size 2 ⁇ D6;
  • the fifth size 2 ⁇ D5 is equal to the sixth size 2 ⁇ D6,
  • the third size D3 is smaller than the fourth size D4, so that the first size D1 of the first transmission part 102 is smaller than the second transmission part 104
  • the third dimension D3 is greater than 0 micrometers and less than or equal to 200 micrometers
  • the fourth dimension D4 is greater than 0 micrometers and less than or equal to 400 micrometers.
  • the third dimension D3 is 80 microns, 100 microns, 120 microns or 180 microns
  • the fourth dimension D4 is 100 microns, 140 microns, 180 microns, 200 microns, 250 microns, 300 microns, 400 microns.
  • D5 and D6 are greater than 0 microns and less than or equal to 25 microns, for example, 10 microns, 15 microns, 20 microns or 25 microns.
  • the gate insulating layer 20 covers the active pattern 10 .
  • the preparation material of the gate insulating layer 20 is at least one of silicon nitride or silicon oxide.
  • the thickness of the gate insulating layer 20 is 1000 ⁇ -2000 ⁇ .
  • the gate pattern 30 is interdigitated, and the gate pattern 30 is disposed on the gate insulating layer 20.
  • the gate pattern 30 includes a first gate 301, a second gate 302, a connecting segment 303, a second gate An extension section 304 and a second extension section 305, the two ends of the connection section 303 are respectively connected to the first grid 301 and the second grid 302, the first grid 301 and the second grid 302 are located on the same side of the connection section 303,
  • the first extension section 304 is connected to a side of the first grid 301 away from the connection section 303
  • the second extension section 305 is connected to a side of the second grid 302 away from the connection section 303 .
  • the first gate 301 is a part of the gate pattern 30 that overlaps the active pattern 10 and is close to the source heavily doped portion 101
  • the second gate 302 is a part of the gate pattern 30 that overlaps the active pattern 10 and is close to the drain. Part of the heavily doped portion 103 .
  • the size of the first gate 301 in the direction in which the first transmission part 102 points to the source heavily doped part 101 is equal to the third dimension D3 of the first channel 1021
  • the second gate 302 points to the drain in the second transmission part 104
  • the direction dimension of the heavily doped portion 103 is equal to the fourth dimension D4 of the second channel 1041 .
  • the gate pattern 30 is made of at least one material selected from molybdenum, aluminum, titanium, copper and silver.
  • the interlayer insulating layer 40 covers the gate pattern 30 and the gate insulating layer 20 .
  • the thickness of the interlayer insulating layer 40 is 5000 ⁇ -6000 ⁇ , and the material for making the interlayer insulating layer 40 is selected from at least one of silicon nitride and silicon oxide.
  • the source-drain electrode lead 50 includes a source lead 501 and a drain lead 502, and the source lead 501 passes through the first via hole 100a penetrating through the interlayer insulating layer 40 and the gate insulating layer 20 to be heavily doped with the source.
  • the doped portion 101 is connected, and the drain lead 502 is connected to the heavily doped drain portion 103 through the second via hole 100 b penetrating through the interlayer insulating layer 40 and the gate insulating layer 20 .
  • the source-drain electrode leads 50 are made of at least one material selected from molybdenum, aluminum, titanium, copper and silver.
  • the source lead 501 and the source heavily doped part 101 form a source
  • the drain lead 502 and the drain heavily doped part 103 form a drain.
  • the thin film transistor in this embodiment reduces the transmission of the second transmission part by making the fourth dimension D4 of the second transmission part close to the heavily doped drain part larger than the third dimension D3 of the first transmission part close to the heavily doped source part.
  • the electric field applied to the carriers during the carrier process reduces the bombardment of the carriers on the drain and avoids the failure of the thin film transistor.
  • the technical solution in this embodiment can also be applied to a P-type thin film transistor, and the P-type thin film transistor may not have a lightly doped portion.
  • FIG. 3 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present application
  • FIG. 4 is a schematic plan view of the thin film transistor shown in FIG. 3
  • the thin film transistor shown in FIG. 3 is basically similar to the thin film transistor shown in FIG. 1, except that the third dimension D3 is equal to the fourth dimension D4, the fifth dimension 2 ⁇ D5 is smaller than the sixth dimension 2 ⁇ D6, and D5 is smaller than D6, So that the first size D1 of the first transmission part 102 is smaller than the second size D2 of the second transmission part 104 .
  • D5 is greater than 0 microns and less than or equal to 20 microns
  • D6 is greater than 0 microns and less than or equal to 30 microns. For example, D5 is 15 microns and D6 is 25 microns.
  • FIG. 5 is a schematic diagram of the display panel of the embodiment of the present application
  • FIG. 6 is a structural diagram of the gate drive circuit of the display panel shown in FIG. 5
  • FIG. 7 is a schematic diagram of the gate drive circuit shown in FIG. Circuit schematic.
  • the display panel 200 is a liquid crystal display panel, and the liquid crystal display panel is applied in a vehicle.
  • the display panel 200 may also be an OLED display panel.
  • the display panel 200 has a display area 200a and a peripheral area 200b.
  • the display panel 200 includes scan lines 202 , data lines 203 and a plurality of gate driving units 60 .
  • a plurality of scanning lines 202 and a plurality of data lines 203 are arranged in the display area 200a of the display panel 200, and a plurality of gate driving units 60 are arranged in the peripheral area 200b of the display panel 200 and are located on opposite sides of the display area 200a.
  • Line 202 is connected to two opposing gate drive units 60 .
  • the gate drive unit 60 includes the above-mentioned thin film transistors to meet the requirements of the vehicle display on the stability of the gate drive circuit due to factors such as complex use environment and long working hours.
  • the nth level gate driving unit 60 includes an input module 601 , a pull-up module 602 , a pull-down module 603 , a pull-down control module 604 , a feedback module 605 and a function module 606 .
  • the input module 601 is used to receive the forward scanning signal U2D, the reverse scanning signal D2U, the (n-2)th level scanning signal G(n-2) and the (n+2)th level scanning signal G (n+2), adjusting the potential of the first node Q in response to the (n ⁇ 2)th level scan signal G(n ⁇ 2) and the (n+2)th level scan signal G(n+2).
  • the input module 601 includes a first thin film transistor NT1 and a second thin film transistor NT2.
  • the gate of the first thin film transistor NT1 receives the (n-2)th level scanning signal G(n-2), the first pole of the first thin film transistor NT1 receives the forward scanning signal U2D, and the second pole of the first thin film transistor NT1 Connect with the first node Q.
  • the gate of the second thin film transistor NT2 receives the (n+2)th level scanning signal G(n+2), the first pole of the second thin film transistor NT2 receives the reverse scanning signal D2U, and the second pole of the second thin film transistor NT2 Connect with the first node Q.
  • the pull-up module 602 is used for pulling up the nth-level scan signal G(n) according to the voltage of the first node Q.
  • the pull-up module 602 includes a seventh thin film transistor NT7 and a ninth thin film transistor NT9.
  • the gate of the seventh thin film transistor NT7 receives the constant-voltage high-level signal VGH, the first pole of the seventh thin film transistor NT7 is connected to the first node Q, the second pole of the seventh thin film transistor NT7 is connected to the gate of the ninth thin film transistor NT9 connected, the first pole of the ninth thin film transistor NT9 receives the first clock signal CK(n), and the second pole of the ninth thin film transistor NT9 outputs the pulled-up n-th level scan signal G(n).
  • the pull-down module 603 is used to pull down the nth-level scan signal G(n) according to the voltage of the second node P.
  • the pull-down module 603 includes a tenth thin film transistor NT10, the gate of the tenth thin film transistor NT10 is connected to the second node P, the first electrode of the tenth thin film transistor NT10 receives the constant-voltage low-level signal VGL, and the tenth thin film transistor NT10
  • the second pole of NT10 is connected to the second pole of the ninth thin film transistor NT9 to output the pulled-down n-th level scan signal G(n).
  • the pull-down control module 604 is used to receive the forward scan signal U2D, the reverse scan signal D2U, the second clock signal CK(n+1) and the third clock signal CK(n-1) to adjust the second The potential of node P.
  • the pull-down control module 604 includes a third thin film transistor NT3 , a fourth thin film transistor NT4 and an eighth thin film transistor NT8 .
  • the gate of the third thin film transistor NT3 receives the forward scanning signal U2D
  • the first pole of the third thin film transistor NT3 receives the second clock signal CK (n+1)
  • the gate of the fourth thin film transistor NT4 receives the reverse scanning signal D2U, the first pole of the fourth thin film transistor NT4 receives the third clock signal CK (n-1), the second pole of the fourth thin film transistor NT4 and the eighth thin film transistor Gate connection for NT8.
  • the first pole of the eighth thin film transistor NT8 is connected to the constant voltage high level VGH, and the second pole of the eighth thin film transistor NT8 is connected to the second node P.
  • the feedback module 605 is connected to the first node Q and the second node P, and the feedback module 605 is used to adjust the potential of the second node P according to the potential of the first node Q and adjust the potential of the second node P according to the potential of the second node P.
  • the feedback module 605 includes a sixth thin film transistor NT6 and a fifth thin film transistor NT5.
  • the gate of the fifth TFT NT5 is connected to the second node P, the first electrode of the fifth TFT NT5 receives the constant voltage low level signal VGL, and the second electrode of the fifth TFT NT5 is connected to the first node Q.
  • the gate of the sixth thin film transistor NT6 is connected to the first node Q, the first electrode of the sixth thin film transistor NT6 receives the constant voltage low level signal VGL, and the second electrode of the sixth thin film transistor NT6 is connected to the second node P.
  • the function module 606 is used to pull up the nth scan signal G(n) when the display panel is abnormally powered off, and is also used to pull down the nth scan signal G(n) when the display panel is touched.
  • the functional module 606 includes an eleventh thin film transistor NT11 , a twelfth thin film transistor NT12 and a thirteenth thin film transistor NT13 .
  • the gate of the twelfth thin film transistor NT12 receives the first global control signal GAS1
  • the first pole of the twelfth thin film transistor NT12 receives the constant voltage low level signal VGL
  • the second pole of the twelfth thin film transistor NT12 is connected to the second node P connection.
  • the gate of the eleventh thin film transistor NT11 receives the first global control signal GAS1, the first pole of the eleventh thin film transistor NT11 is connected to the gate of the eleventh thin film transistor NT11, the second pole of the eleventh thin film transistor NT11 is connected to the The second pole of the nine thin film transistor NT9 is connected.
  • the gate of the thirteenth thin film transistor NT13 is connected to the second global control signal GAS2, the first pole of the thirteenth thin film transistor NT13 receives a constant voltage low-level signal, and the second pole of the thirteenth thin film transistor NT13 is connected to the ninth thin film transistor NT13.
  • the second pole of transistor NT9 is connected.
  • the first global control signal GAS1 is a constant-voltage low-level signal; when the display panel is abnormally powered off, the first global control signal GAS1 is a constant-voltage high-level signal, so that the gate The driving unit outputs the nth-level scanning signal G(n) pulled high.
  • the second global control signal GAS2 is a constant-voltage high-level signal, so that the n-th gate driving unit outputs the n-th scan signal G(n) pulled down.
  • the first thin film transistor NT1 to the thirteenth thin film transistor NT13 of the gate driving circuit are all N-type low temperature polysilicon thin film transistors.
  • the first thin film transistor NT1 to the thirteenth thin film transistor NT13 can be the above thin film transistors with the first channel 1021 and the second channel 1041, so as to improve the application of the low temperature polysilicon thin film transistor with double channels to the gate drive circuit.
  • the channel of the thin film transistor close to the drain is subjected to a large bias stress, and the stability of the gate drive circuit is improved.
  • the fifth thin film transistor NT5 is continuously subjected to bias stress, being the above thin film transistor is more conducive to improving the stability of the gate driving circuit.

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Abstract

本申请提供一种薄膜晶体管及显示面板，通过使与源极重掺杂部电性连接的第一传输部的第一尺寸和与漏极重掺杂部电性连接的第二传输部的第二尺寸不同，以使第一尺寸或第二尺寸中较大的一者对应的传输部在薄膜晶体管导通时传输的载流子所受的电场强度小，降低载流子对源极或漏极的轰击作用提高薄膜晶体管的稳定性。

Description

薄膜晶体管及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种薄膜晶体管及显示面板。
 背景技术
目前，具有双沟道的薄膜晶体管持续受偏压应力作用会出现失效问题，不利于具有双沟道的薄膜晶体管工作的稳定性。
因此，有必要提出一种技术方案以解决具有双沟道的薄膜晶体管持续受偏压应力而失效的问题。
 技术问题
本申请的目的在于提供一种薄膜晶体管及显示面板，以解决具有双沟道的薄膜晶体管持续受偏压应力而失效的问题。
 技术解决方案
一种薄膜晶体管，包括：
栅极图案，包括间隔设置且相互电性连接的第一栅极和第二栅极；以及
有源图案，包括：
源极重掺杂部；
第一传输部，与所述源极重掺杂部电性连接且与所述第一栅极至少部分交叠，在所述第一传输部指向所述源极重掺杂部的方向上，所述第一传输部具有第一尺寸；
漏极重掺杂部；以及
第二传输部，与所述漏极重掺杂部电性连接且与所述第二栅极至少部分交叠，在所述第二传输部指向所述漏极重掺杂部的方向上，所述第二传输部具有第二尺寸；
其中，所述第一传输部和所述第二传输部均位于所述源极重掺杂部和所述漏极重掺杂部之间，且所述第一传输部与所述第二传输部间隔设置，所述第一尺寸与所述第二尺寸不同。
一种薄膜晶体管，所述薄膜晶体管包括：
栅极图案，包括间隔设置且相互电性连接的第一栅极和第二栅极；以及
有源图案，包括：
源极重掺杂部；
第一传输部，与所述源极重掺杂部电性连接且与所述第一栅极至少部分交叠，在所述第一传输部指向所述源极重掺杂部的方向上，所述第一传输部具有第一尺寸；
漏极重掺杂部；以及
第二传输部，与所述漏极重掺杂部电性连接且与所述第二栅极至少部分交叠，在所述第二传输部指向所述漏极重掺杂部的方向上，所述第二传输部具有第二尺寸；
其中，所述第一传输部和所述第二传输部均位于所述源极重掺杂部和所述漏极重掺杂部之间，且所述第一传输部与所述第二传输部间隔设置；
所述薄膜晶体管导通时，施加于所述第一传输部传输的载流子的电场强度与施加于所述第二传输部传输的载流子的电场强度不同。
一种显示面板，所述显示面板包括上述薄膜晶体管。
 有益效果
本申请提供一种薄膜晶体管及显示面板，通过使与源极重掺杂部电性连接的第一传输部的第一尺寸和与漏极重掺杂部电性连接的第二传输部的第二尺寸不同，其中，第一尺寸为第一传输部在第一传输部指向源极重掺杂部方向上的尺寸，第二尺寸为第二传输部在第二传输部指向漏极重掺杂部方向上的尺寸，以使得第一尺寸或第二尺寸中较大的一者对应的传输部在薄膜晶体管导通时传输的载流子所受的电场强度小，降低载流子对源极或漏极的轰击作用，改善偏压应力对源极或漏极的损伤，提高薄膜晶体管的稳定性。
 附图说明
图1为本申请实施例薄膜晶体管的截面示意图；
图2为图1所示薄膜晶体管的平面示意图；
图3为本申请另一实施例的薄膜晶体管的截面示意图；
图4为图3所示薄膜晶体管的平面示意图；
图5为本申请实施例显示面板的示意图；
图6为图5所示显示面板的栅极驱动电路的架构图；
图7为图6所示栅极驱动电路的电路示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1及图2，图1为本申请实施例薄膜晶体管的截面示意图，图2为图1所示薄膜晶体管的平面示意图。该薄膜晶体管为N型薄膜晶体管，薄膜晶体管100包括有源图案10、栅极绝缘层20、栅极图案30、层间绝缘层40以及源漏电极引线50。可以理解的是，该薄膜晶体管也可以为P型薄膜晶体管。
在本实施例中，有源图案10为条状，且有源图案10呈直线形。有源图案10的制备材料为低温多晶硅。在其他实施例中，有源图案10的制备材料也可以为金属氧化物半导体材料，例如氧化铟镓锌。
在本实施例中，有源图案10包括源极重掺杂部101、第一传输部102、漏极重掺杂部103、第二传输部104以及中间连接部105。第一传输部102与源极重掺杂部101相邻且电性连接，第二传输部104与漏极重掺杂部103相邻且电性连接，第一传输部102和第二传输部104均位于源极重掺杂部101和漏极重掺杂部103之间，第一传输部102与第二传输部104间隔设置，且第二传输部104与第一传输部102分别连接于中间连接部105的相对两侧。第一传输部102与第二传输部104均用于传输载流子。中间连接部105也用于传输载流子。
在本实施例中，第一传输部102包括一个第一沟道1021和至少一个第一轻掺杂部1022，第一沟道1021未经过离子植入处理，第一轻掺杂部1022和源极重掺杂部101均是半导体经过离子植入处理得到，第一轻掺杂部1022的离子植入剂量小于源极重掺杂部101的离子植入剂量；第二传输部104包括一个第二沟道1041和至少一个第二轻掺杂部1042，第二沟道1041未经过离子植入处理，第二轻掺杂部1042与漏极重掺杂部103均是半导体经过离子植入得到，第二轻掺杂部1042的离子植入剂量与第一轻掺杂部1022的离子植入剂量相同，源极重掺杂部101的离子植入剂量与漏极重掺杂部103的离子植入剂量相同。例如，源极重掺杂部101的离子植入剂量与漏极重掺杂部103的离子植入剂量均为每立方厘米有10 14个离子，第二轻掺杂部1042的离子植入剂量与第一轻掺杂部1022的离子植入剂量均为每立方厘米有10 13个离子。
具体地，第一传输部102包括两个第一轻掺杂部1022和第一沟道1021，两个第一轻掺杂部1022连接于第一沟道1021的相对两侧，一个第一轻掺杂部1022连接在源极重掺杂部101和第一沟道1021之间，另一个第一轻掺杂部1022连接第一沟道1021远离源极重掺杂部101的一侧，两个第一轻掺杂部1022相同；第二传输部104包括两个第二轻掺杂部1042和第二沟道1041，两个第二轻掺杂部1042连接于第二沟道1041的相对两侧，一个第二轻掺杂部1042连接在漏极重掺杂部103和第二沟道1041之间，另一个第二轻掺杂部1042连接第二沟道1041远离漏极重掺杂部103的一侧，两个第二轻掺杂部1042相同。可以理解的是，第一传输部102也可以只包括一个第一轻掺杂部1022且该第一轻掺杂部1022设置于第一沟道1021和源极重掺杂部101之间，第二传输部104也可以只包括一个第二轻掺杂部1042且该第二轻掺杂部1042设置于第二沟道1041和漏极重掺杂部103之间。
在本实施例中，在第一传输部102指向源极重掺杂部101的方向上，第一传输部102具有第一尺寸D1；在第二传输部104指向漏极重掺杂部103的方向上，第二传输部104具有第二尺寸D2，第一尺寸D1与第二尺寸D2不同，使得薄膜晶体管导通时施加于第一传输部102传输的载流子的电场强度与施加于第二传输部104传输的载流子的电场强度不同，第一尺寸D1或第二尺寸D2中较大的一者对应的传输部在薄膜晶体管导通时传输的载流子所受的电场强度小，降低载流子对源极或漏极的轰击作用，改善偏压应力对源极或漏极的损伤，提高薄膜晶体管的稳定性。
具体地，第一尺寸D1小于第二尺寸D2，以使得第二传输部104传输载流子过程中施加于载流子的电场强度小，载流子对漏极的轰击作用小，有利于解决N型低温多晶硅薄膜晶体管应用于栅极驱动电路时薄膜晶体管的漏极受到偏压应力大的问题。可以理解的是，也可以第一尺寸D1大于第二尺寸D2，减小载流子对源极的轰击作用。
在本实施例中，第一沟道1021为第一传输部102中与第一栅极301在薄膜晶体管的厚度方向上交叠的部分，在第一传输部102指向源极重掺杂部101的方向上，第一沟道1021具有第三尺寸D3，两个第一轻掺杂部1022具有第五尺寸2×D5；第二沟道1041为第二传输部104中与第二栅极302在薄膜晶体管的厚度方向上交叠的部分，在第二传输部104指向漏极重掺杂部103的方向上，第二沟道1041具有第四尺寸D4，两个第二轻掺杂部1042具有第六尺寸2×D6；第五尺寸2×D5等于第六尺寸2×D6，第三尺寸D3小于第四尺寸D4，以使得第一传输部102的第一尺寸D1小于第二传输部104的第二尺寸D2。具体地，第三尺寸D3大于0微米且小于或等于200微米，第四尺寸D4大于0微米且小于或等于400微米。例如，第三尺寸D3为80微米、100微米、120微米或者180微米；第四尺寸D4为100微米、140微米、180微米、200微米、250微米、300微米、400微米。D5和D6大于0微米且小于或等于25微米，例如为10微米、15微米、20微米或者25微米。
在本实施例中，栅极绝缘层20覆盖有源图案10。栅极绝缘层20的制备材料为氮化硅或氧化硅中的至少一种。栅极绝缘层20的厚度为1000埃-2000埃。
在本实施例中，栅极图案30呈叉指形，栅极图案30设置于栅极绝缘层20上，栅极图案30包括第一栅极301、第二栅极302、连接段303、第一延伸段304以及第二延伸段305，连接段303的两端分别连接第一栅极301和第二栅极302，第一栅极301和第二栅极302位于连接段303的同一侧，第一延伸段304连接第一栅极301远离连接段303的一侧，第二延伸段305连接第二栅极302远离连接段303的一侧。第一栅极301为栅极图案30中与有源图案10重叠且靠近源极重掺杂部101的部分，第二栅极302为栅极图案30中与有源图案10重叠且靠近漏极重掺杂部103的部分。第一栅极301在第一传输部102指向源极重掺杂部101的方向上的尺寸等于第一沟道1021的第三尺寸D3，第二栅极302在第二传输部104指向漏极重掺杂部103的方向上的尺寸等于第二沟道1041的第四尺寸D4。栅极图案30的制备材料选自钼、铝、钛、铜以及银中的至少一种。
在本实施例中，层间绝缘层40覆盖栅极图案30和栅极绝缘层20。层间绝缘层40的厚度为5000埃-6000埃，层间绝缘层40的制备材料选自氮化硅或氧化硅中的至少一种。
在本实施例中，源漏电极引线50包括源极引线501和漏极引线502，源极引线501通过贯穿层间绝缘层40及栅极绝缘层20的第一过孔100a与源极重掺杂部101连接，漏极引线502通过贯穿层间绝缘层40及栅极绝缘层20的第二过孔100b与漏极重掺杂部103连接。源漏电极引线50的制备材料选自钼、铝、钛、铜以及银中的至少一种。源极引线501与源极重掺杂部101组成源极，漏极引线502与漏极重掺杂部103组成漏极。
本实施例薄膜晶体管通过使靠近漏极重掺杂部的第二传输部的第四尺寸D4大于靠近源极重掺杂部的第一传输部的第三尺寸D3，以降低第二传输部传输载流子过程中施加于载流子的电场，减小载流子对漏极的轰击，避免薄膜晶体管失效。
需要说明的是，本实施例中的技术方案也可以应用于P型薄膜晶体管，该P型薄膜晶体管可以不具有轻掺杂部。
请参阅图3及图4，图3为本申请另一实施例的薄膜晶体管的截面示意图，图4为图3所示薄膜晶体管的平面示意图。图3所示薄膜晶体管与图1所示薄膜晶体管基本相似，不同之处在于，第三尺寸D3等于第四尺寸D4，第五尺寸2×D5小于第六尺寸2×D6，且D5小于D6，以使得第一传输部102的第一尺寸D1小于第二传输部104的第二尺寸D2。D5大于0微米且小于或等于20微米，D6大于0微米且小于或等于30微米。例如，D5为15微米，D6为25微米。
需要说明的是，图1和图3所示的方案也可以进行组合，例如，调整第三尺寸D3和第四尺寸D4不同的同时，使得第五尺寸2×D5与第六尺寸2×D6也不同，以使得第一传输部102的第一尺寸D1与第二传输部104的第二尺寸D2不同。
请参阅图5-图7，图5为本申请实施例显示面板的示意图，图6为图5所示显示面板的栅极驱动电路的架构图，图7为图6所示栅极驱动电路的电路示意图。
在本实施例中，显示面板200为液晶显示面板，该液晶显示面板应用于车载。显示面板200也可以为有机发光二极管显示面板。显示面板200具有显示区200a和外围区200b。显示面板200包括扫描线202、数据线203以及多个栅极驱动单元60。多条扫描线202及多条数据线203设置于显示面板200的显示区200a，多个栅极驱动单元60设置于显示面板200的外围区200b且位于显示区200a的相对两侧，每条扫描线202与两个相对的栅极驱动单元60连接。栅极驱动单元60包括上述薄膜晶体管，以满足车载显示由于使用环境复杂和工作时间长等因素对栅极驱动电路工作稳定性的要求。
在本实施例中，第n级栅极驱动单元60包括输入模块601、上拉模块602、下拉模块603、下拉控制模块604、反馈模块605以及功能模块606。
在本实施例中，输入模块601用于接收正向扫描信号U2D、反向扫描信号D2U、第(n-2)级扫描信号G(n-2)以及第（n+2）级扫描信号G（n+2），响应于第(n-2)级扫描信号G(n-2)以及第（n+2）级扫描信号G（n+2）以调整第一节点Q的电势。具体地，输入模块601包括第一薄膜晶体管NT1和第二薄膜晶体管NT2。第一薄膜晶体管NT1的栅极接收第(n-2)级扫描信号G(n-2)，第一薄膜晶体管NT1的第一极接收正向扫描信号U2D，第一薄膜晶体管NT1的第二极与第一节点Q连接。第二薄膜晶体管NT2的栅极接收第(n+2)级扫描信号G(n+2)，第二薄膜晶体管NT2的第一极接收反向扫描信号D2U，第二薄膜晶体管NT2的第二极与第一节点Q连接。
在本实施例中，上拉模块602用于根据第一节点Q的电压上拉第n级扫描信号G(n)。具体地，上拉模块602包括第七薄膜晶体管NT7和第九薄膜晶体管NT9。第七薄膜晶体管NT7的栅极接收恒压高电平信号VGH，第七薄膜晶体管NT7的第一极连接第一节点Q，第七薄膜晶体管NT7的第二极与第九薄膜晶体管NT9的栅极连接，第九薄膜晶体管NT9的第一极接收第一时钟信号CK（n），第九薄膜晶体管NT9的第二极输出上拉的第n级扫描信号G(n)。
在本实施例中，下拉模块603用于根据第二节点P的电压下拉第n级扫描信号G(n)。具体地，下拉模块603包括第十薄膜晶体管NT10，第十薄膜晶体管NT10的栅极与第二节点P连接，第十薄膜晶体管NT10的第一极接收恒压低电平信号VGL，第十薄膜晶体管NT10的第二极与第九薄膜晶体管NT9的第二极连接，以输出下拉的第n级扫描信号G(n)。
在本实施例中，下拉控制模块604用于接收正向扫描信号U2D、反向扫描信号D2U、第二时钟信号CK（n+1）以及第三时钟信号CK（n-1）以调节第二节点P的电位。具体地，下拉控制模块604包括第三薄膜晶体管NT3、第四薄膜晶体管NT4以及第八薄膜晶体管NT8。第三薄膜晶体管NT3的栅极接收正向扫描信号U2D，第三薄膜晶体管NT3的第一极接收第二时钟信号CK（n+1），第三薄膜晶体管NT3的第二极与第八薄膜晶体管NT8的栅极连接。第四薄膜晶体管NT4的栅极接收反向扫描信号D2U，第四薄膜晶体管NT4的第一极接收第三时钟信号CK（n-1），第四薄膜晶体管NT4的第二极与第八薄膜晶体管NT8的栅极连接。第八薄膜晶体管NT8的第一极与恒压高电平VGH连接，第八薄膜晶体管NT8的第二极与第二节点P连接。
在本实施例中，反馈模块605与第一节点Q和第二节点P连接，反馈模块605用于根据第一节点Q的电势调整第二节点P的电势且根据第二节点P的电势调整第一节点Q的电势。具体地，反馈模块605包括第六薄膜晶体管NT6和第五薄膜晶体管NT5。第五薄膜晶体管NT5的栅极与第二节点P连接，第五薄膜晶体管NT5的第一极接收恒压低电平信号VGL，第五薄膜晶体管NT5的第二极与第一节点Q连接。第六薄膜晶体管NT6的栅极与第一节点Q连接，第六薄膜晶体管NT6的第一极接收恒压低电平信号VGL，第六薄膜晶体管NT6的第二极与第二节点P连接。
在本实施例中，功能模块606用于在显示面板异常断电时上拉第n级扫描信号G(n)，还用于在显示面板进行触控时下拉第n级扫描信号G(n)。功能模块606包括第十一薄膜晶体管NT11、第十二薄膜晶体管NT12以及第十三薄膜晶体管NT13。第十二薄膜晶体管NT12的栅极接收第一全局控制信号GAS1，第十二薄膜晶体管NT12的第一极接收恒压低电平信号VGL，第十二薄膜晶体管NT12的第二极与第二节点P连接。第十一薄膜晶体管NT11的栅极接收第一全局控制信号GAS1，第十一薄膜晶体管NT11的第一极连接第十一薄膜晶体管NT11的栅极，第十一薄膜晶体管NT11的第二极与第九薄膜晶体管NT9的第二极连接。第十三薄膜晶体管NT13的栅极与第二全局控制信号GAS2连接，第十三薄膜晶体管NT13的第一极接收恒压低电平信号，第十三薄膜晶体管NT13的第二极与第九薄膜晶体管NT9的第二极连接。在显示面板正常显示时，第一全局控制信号GAS1为恒压低电平信号；在显示面板异常断电时，第一全局控制信号GAS1为恒压高电平信号，以使第n级栅极驱动单元输出拉高的第n级扫描信号G(n)。在显示面板进行触控驱动时，第二全局控制信号GAS2为恒压高电平信号，以使第n级栅极驱动单元输出拉低的第n级扫描信号G(n)。
在本实施例中，栅极驱动电路的第一薄膜晶体管NT1至第十三薄膜晶体管NT13均为N型低温多晶硅薄膜晶体管。第一薄膜晶体管NT1至第十三薄膜晶体管NT13均可以为上述具有第一沟道1021和第二沟道1041的薄膜晶体管，以改善具有双沟道的低温多晶硅薄膜晶体管应用于栅极驱动电路时，薄膜晶体管靠近漏极的沟道受的偏压应力大的问题，提高栅极驱动电路的稳定性。特别地，第五薄膜晶体管NT5由于持续受偏压应力作用，其为上述薄膜晶体管更能有利于提高栅极驱动电路的稳定性。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (17)

  1. 一种薄膜晶体管，其中，包括：
    栅极图案，包括间隔设置且相互电性连接的第一栅极和第二栅极；以及
    有源图案，包括：
    源极重掺杂部；
    第一传输部，与所述源极重掺杂部电性连接且与所述第一栅极至少部分交叠，在所述第一传输部指向所述源极重掺杂部的方向上，所述第一传输部具有第一尺寸；
    漏极重掺杂部；以及
    第二传输部，与所述漏极重掺杂部电性连接且与所述第二栅极至少部分交叠，在所述第二传输部指向所述漏极重掺杂部的方向上，所述第二传输部具有第二尺寸；
    其中，所述第一传输部和所述第二传输部均位于所述源极重掺杂部和所述漏极重掺杂部之间，且所述第一传输部与所述第二传输部间隔设置，所述第一尺寸与所述第二尺寸不同。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第一尺寸小于所述第二尺寸。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述第一传输部包括第一沟道，所述第一沟道为所述第一传输部中与所述第一栅极交叠的部分，在所述第一传输部指向所述源极重掺杂部的方向上，所述第一沟道具有第三尺寸；
    所述第二传输部包括第二沟道，所述第二沟道为所述第二传输部中与所述第二栅极交叠的部分，在所述第二传输部指向所述漏极重掺杂部的方向上，所述第二沟道具有第四尺寸；
    其中，所述第三尺寸小于所述第四尺寸。
  4. 根据权利要求2所述的薄膜晶体管，其中，所述第一传输部包括至少一个第一轻掺杂部，在所述第一传输部指向所述源极重掺杂部的方向上，至少一个所述第一轻掺杂部具有第五尺寸；
    所述第二传输部包括至少一个第二轻掺杂部，在所述第二传输部指向所述漏极重掺杂部的方向上，至少一个所述第二轻掺杂部具有第六尺寸；
    其中，所述第五尺寸小于所述第六尺寸。
  5. 根据权利要求4所述的薄膜晶体管，其中，所述第一传输部包括两个所述第一轻掺杂部和第一沟道，两个所述第一轻掺杂部分别连接于所述第一沟道的相对两侧；
    所述第二传输部包括两个所述第二轻掺杂部和第二沟道，两个所述第二轻掺杂部分别连接于所述第二沟道的相对两侧；
    所述有源图案还包括中间连接部，所述第一传输部和所述第二传输部分别连接在所述中间连接部的相对两侧。
  6. 根据权利要求1所述的薄膜晶体管，其中，所述有源图案呈直线形。
  7. 根据权利要求1所述的薄膜晶体管，其中，所述栅极图案还包括连接段，所述连接段的两端分别连接所述第一栅极和所述第二栅极，所述第一栅极和所述第二栅极位于所述连接段的同一侧。
  8. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    栅极图案，包括间隔设置且相互电性连接的第一栅极和第二栅极；以及
    有源图案，包括：
    源极重掺杂部；
    第一传输部，与所述源极重掺杂部电性连接且与所述第一栅极至少部分交叠；
    漏极重掺杂部；以及
    第二传输部，与所述漏极重掺杂部电性连接且与所述第二栅极至少部分交叠；
    其中，所述第一传输部和所述第二传输部均位于所述源极重掺杂部和所述漏极重掺杂部之间，且所述第一传输部与所述第二传输部间隔设置；
    所述薄膜晶体管导通时，施加于所述第一传输部传输的载流子的电场强度与施加于所述第二传输部传输的载流子的电场强度不同。
  9. 根据权利要求8所述的薄膜晶体管，其中，在所述第一传输部指向所述源极重掺杂部的方向上，所述第一传输部具有第一尺寸；
    在所述第二传输部指向所述漏极重掺杂部的方向上，所述第二传输部具有第二尺寸；
    其中，所述第一尺寸与所述第二尺寸不同。
  10. 根据权利要求9所述的薄膜晶体管，其中，所述第一尺寸小于所述第二尺寸。
  11. 根据权利要求10所述的薄膜晶体管，其中，所述第一传输部包括第一沟道，所述第一沟道为所述第一传输部中与所述第一栅极交叠的部分，在所述第一传输部指向所述源极重掺杂部的方向上，所述第一沟道具有第三尺寸；
    所述第二传输部包括第二沟道，所述第二沟道为所述第二传输部中与所述第二栅极交叠的部分，在所述第二传输部指向所述漏极重掺杂部的方向上，所述第二沟道具有第四尺寸；
    其中，所述第三尺寸小于所述第四尺寸。
  12. 根据权利要求10所述的薄膜晶体管，其中，所述第一传输部包括至少一个第一轻掺杂部，在所述第一传输部指向所述源极重掺杂部的方向上，至少一个所述第一轻掺杂部具有第五尺寸；
    所述第二传输部包括至少一个第二轻掺杂部，在所述第二传输部指向所述漏极重掺杂部的方向上，至少一个所述第二轻掺杂部具有第六尺寸；
    其中，所述第五尺寸小于所述第六尺寸。
  13. 根据权利要求12所述的薄膜晶体管，其中，所述第一传输部包括两个所述第一轻掺杂部和第一沟道，两个所述第一轻掺杂部分别连接于所述第一沟道的相对两侧；
    所述第二传输部包括两个所述第二轻掺杂部和第二沟道，两个所述第二轻掺杂部分别连接于所述第二沟道的相对两侧；
    所述有源图案还包括中间连接部，所述第一传输部和所述第二传输部分别连接在所述中间连接部的相对两侧。
  14. 根据权利要求8所述的薄膜晶体管，其中，所述有源图案呈直线形。
  15. 根据权利要求8所述的薄膜晶体管，其中，所述栅极图案还包括连接段，所述连接段的两端分别连接所述第一栅极和所述第二栅极，所述第一栅极和所述第二栅极位于所述连接段的同一侧。
  16. 一种显示面板，其中，所述显示面板包括如权利要求1所述薄膜晶体管。
  17. 根据权利要求16所述的显示面板，其中，所述显示面板包括栅极驱动电路，所述栅极驱动电路包括所述薄膜晶体管。
PCT/CN2021/111220 2021-07-27 2021-08-06 薄膜晶体管及显示面板 Ceased WO2023004875A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025607A (en) * 1996-05-08 2000-02-15 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistor and liquid crystal display device
US20040089862A1 (en) * 2002-07-10 2004-05-13 Seiko Epson Corporation Thin-film transistor, switching circuit, active element substrate, electro-optical device, electronic apparatus, thermal head, droplet ejecting head, printer, and thin-film-transistor driving and light-emitting display device
CN1719508A (zh) * 2005-08-10 2006-01-11 友达光电股份有限公司 显示器的像素电路
CN105206216A (zh) * 2015-10-23 2015-12-30 武汉华星光电技术有限公司 显示装置及其应用在栅极驱动电路中的移位寄存电路
CN111710728A (zh) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 阵列基板、显示面板及显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070051956A1 (en) * 2005-08-31 2007-03-08 Chih-Jen Shih Thin film transistor
TWI384628B (zh) * 2008-06-27 2013-02-01 Au Optronics Corp 薄膜電晶體

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025607A (en) * 1996-05-08 2000-02-15 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistor and liquid crystal display device
US20040089862A1 (en) * 2002-07-10 2004-05-13 Seiko Epson Corporation Thin-film transistor, switching circuit, active element substrate, electro-optical device, electronic apparatus, thermal head, droplet ejecting head, printer, and thin-film-transistor driving and light-emitting display device
CN1719508A (zh) * 2005-08-10 2006-01-11 友达光电股份有限公司 显示器的像素电路
CN105206216A (zh) * 2015-10-23 2015-12-30 武汉华星光电技术有限公司 显示装置及其应用在栅极驱动电路中的移位寄存电路
CN111710728A (zh) * 2020-06-30 2020-09-25 厦门天马微电子有限公司 阵列基板、显示面板及显示装置

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