WO2024093195A1 - 像素驱动电路、像素驱动方法和显示面板 - Google Patents

像素驱动电路、像素驱动方法和显示面板 Download PDF

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Publication number
WO2024093195A1
WO2024093195A1 PCT/CN2023/094619 CN2023094619W WO2024093195A1 WO 2024093195 A1 WO2024093195 A1 WO 2024093195A1 CN 2023094619 W CN2023094619 W CN 2023094619W WO 2024093195 A1 WO2024093195 A1 WO 2024093195A1
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Prior art keywords
thin film
film transistor
power supply
supply voltage
node
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PCT/CN2023/094619
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English (en)
French (fr)
Inventor
樊涛
袁海江
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惠科股份有限公司
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Priority to EP23884137.3A priority Critical patent/EP4439537A1/en
Publication of WO2024093195A1 publication Critical patent/WO2024093195A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present application relates to the field of pixel driving technology, and in particular to a pixel driving circuit, a pixel driving method and a display panel.
  • each light-emitting device needs to be equipped with a pixel driving circuit.
  • each existing pixel driving circuit often needs to use 6 or even more thin-film transistors to achieve threshold voltage compensation for the driving thin-film transistor, which affects the transmittance of the display panel.
  • the main purpose of the present application is to provide a pixel driving circuit, aiming to solve the problem of low transmittance of a self-luminous display panel.
  • the pixel driving circuit proposed in the present application is applied to a display panel, wherein the display panel is provided with a pixel array, wherein the pixel array includes a first light-emitting device and a second light-emitting device adjacent to each other in the same column, wherein the anode of the first light-emitting device is connected to a first node, and the cathode is connected to a first power supply voltage; the anode of the second light-emitting device is connected to a third node, and the cathode is connected to a second power supply voltage;
  • the pixel driving circuit comprises: a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor and a capacitor;
  • the controlled end of the first thin film transistor is connected to the first control signal, the first end is connected to the first power supply voltage, and the second end is connected to the first node;
  • the controlled end of the second thin film transistor receives the second control signal, the first end is connected to the fourth node, and the second end is connected to the second end of the first thin film transistor;
  • the controlled end of the second thin film transistor is connected to the scanning signal, the first end is connected to the data signal, and the second end is connected to the second node;
  • the fourth thin film transistor has a controlled end connected to the fourth node, a first end connected to the first node, and a second end connected to the third node;
  • the controlled end of the fifth thin film transistor is connected to the third control signal, the first end is connected to the fourth node, and the second end is connected to the third node;
  • the controlled end of the sixth thin film transistor is connected to the fourth control signal, the first end is connected to the second end of the fifth thin film transistor, and the second end is connected to the second power supply voltage;
  • One end of the capacitor is connected to the second node, and the other end is connected to the fourth node.
  • the present application also proposes a pixel driving method, which is applied to the above-mentioned pixel driving circuit, and the pixel driving method includes:
  • controlling the second thin film transistor to turn on controlling the first thin film transistor, the fifth thin film transistor and the sixth thin film transistor to turn off, controlling the third thin film transistor to turn on in a preset sub-phase, controlling the third thin film transistor to turn off outside the preset sub-phase, and controlling the data signal
  • the first power supply voltage and the second power supply voltage are high potentials, so that the potential of the fourth node is the sum of the difference between the second power supply voltage and the absolute value of the threshold voltage of the fourth thin film transistor and the data signal
  • controlling the sixth thin film transistor to be turned on controlling the first thin film transistor, the second thin film transistor, the third thin film transistor and the fifth thin film transistor to be turned off, controlling the first power supply voltage to be a negative potential, controlling the second power supply voltage to be a high potential, and controlling the data signal to be a low potential, so that the first light-emitting device emits light;
  • controlling the fifth thin film transistor to be turned on controlling the first thin film transistor, the second thin film transistor and the sixth thin film transistor to be turned off, controlling the third thin film transistor to be turned on in a preset sub-phase, and controlling the third thin film transistor to be turned off outside the preset sub-phase, and controlling the data signal, the first power supply voltage and the second power supply voltage to be high potentials, so that the fourth node potential is the sum of the difference between the first power supply voltage and the absolute value of the threshold voltage of the fourth thin film transistor and the data signal;
  • the first thin film transistor is controlled to be turned on, and the second thin film transistor, the third thin film transistor, the fifth thin film transistor and the sixth thin film transistor are controlled to be turned off, and the first power supply voltage is controlled to be a high potential, and the second power supply voltage is controlled to be a negative potential, and the data signal is controlled to be a low potential, so that the second light-emitting device emits light.
  • the present application also provides a display panel, the display panel comprising:
  • the pixel array comprising a first light emitting device and a second light emitting device adjacent to each other in the same column;
  • the pixel driving circuit is connected to the first light emitting device and the second light emitting device.
  • the technical solution of the present application adopts a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor and a capacitor to form a pixel driving circuit of a 3T0.5C circuit structure, so that two adjacent light-emitting devices on the same column can share a pixel driving circuit, and the threshold voltage of the driving thin film transistor and the voltage drop of the power supply voltage can be compensated, thereby eliminating the influence of the threshold voltage defect of the driving thin film transistor and the voltage drop of the power supply voltage on the current flowing through the light-emitting device, which is beneficial to improving the display uniformity of the self-luminous display panel.
  • the pixel driving circuit of the present application can also make the first light-emitting device and the second light-emitting device in a reverse bias state to reduce the aging speed of the light-emitting device, which is beneficial to prolonging the service life of the self-luminous display panel.
  • FIG1 is a circuit diagram of a pixel driving circuit according to an embodiment of the present application.
  • FIG2 is a timing diagram of a pixel driving circuit according to an embodiment of the present application.
  • FIG3 is a schematic diagram of a path of a pixel driving circuit in a first sampling phase according to an embodiment of the present application
  • FIG4 is a schematic diagram of a path of a pixel driving circuit in a first data phase according to an embodiment of the present application
  • FIG. 5 is a schematic diagram of a path of a pixel driving circuit in a first light-emitting writing stage according to an embodiment of the present application
  • FIG6 is a schematic diagram of a path of a pixel driving circuit in a second sampling phase according to an embodiment of the present application
  • FIG7 is a schematic diagram of a path of a pixel driving circuit in a second data phase according to an embodiment of the present application.
  • FIG8 is a schematic diagram of a path of a pixel driving circuit in a second light emitting stage according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of the steps of a pixel driving method according to a second embodiment of the present application.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the present application provides a pixel driving circuit which can be applied to a display panel.
  • the display panel may include a pixel layer, a light-emitting layer, a driving circuit layer and an array substrate stacked in sequence.
  • the driving circuit layer is disposed on the array substrate.
  • the pixel layer may include a plurality of pixels arranged in an array, and the light-emitting layer may include a light-emitting device corresponding to each pixel.
  • the driving circuit layer may include a plurality of pixel driving circuits, each pixel driving circuit being connected to a light-emitting device, and each pixel driving circuit being used to drive the light-emitting device of the corresponding pixel to emit light, thereby realizing the self-luminous display of the display panel.
  • the light-emitting device may be an organic light-emitting diode (OLED), a mini light-emitting diode (MINI-LED) or a micro light-emitting diode (MICRO-LED), which is not limited here; the embodiment of the present application is described by taking the light-emitting device as an organic light-emitting diode as an example.
  • OLED organic light-emitting diode
  • MINI-LED mini light-emitting diode
  • MICRO-LED micro light-emitting diode
  • a driving thin film transistor for controlling the current flowing through the light-emitting device may be provided in the pixel driving circuit, and the threshold voltage of the driving thin film transistor has a non-uniformity problem, and the threshold voltage will also drift with the increase of working time, so as to cause the display panel to produce uneven brightness moire.
  • the prior art usually increases the number of thin film transistors and adds a storage capacitor C, so that the number of thin film transistors in each pixel driving circuit is 6 or more.
  • the pixel driving circuit also needs to access the power supply voltage through the power line to drive the corresponding light-emitting device.
  • the power line itself has a certain degree of internal resistance, so the power supply voltage actually transmitted to the light-emitting device has a voltage drop, and because the power supply voltage drops of different display devices are different, the light-emitting brightness of each light-emitting device will be uneven, and the light-emitting device in the pixel driving circuit will also age faster because it is in a forward bias state, so that the service life of the self-luminous display panel is relatively low.
  • the present application proposes a pixel driving circuit for driving two adjacent light-emitting devices on the same column in a pixel array, wherein the first light-emitting device D1 may be a light-emitting device on an odd row, and the second light-emitting device D2 may be a light-emitting device on an even row.
  • the pixel driving circuit of the present application includes a first thin film transistor M1, a second thin film transistor M2, a third thin film transistor M3, a fourth thin film transistor M4, a fifth thin film transistor M5, a sixth thin film transistor M6 and a capacitor C.
  • the first thin film transistor M1 and the second thin film transistor M2 are used to control the first light emitting device D1 to emit light and the charge of the first node A1 to be cleared.
  • the third thin film transistor M3 is a data writing thin film transistor.
  • the fourth thin film transistor M4 also serves as a driving thin film transistor for the first light emitting device D1 and the second light emitting device D2.
  • the fifth thin film transistor M5 and the sixth thin film transistor M6 are used to control the second light emitting device D2 to emit light and the charge of the third node A3 to be cleared.
  • the capacitor C may be a storage capacitor C.
  • the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5, and the sixth thin film transistor M6 may all be oxide semiconductor thin film transistors, low temperature polycrystalline silicon thin film transistors or
  • the thin film transistors T1 to T7 are amorphous silicon thin film transistors, that is, the types of thin film transistors T1 to T7 can all be indium gallium zinc oxide (IGZO), low temperature polysilicon (LTPS) or amorphous silicon (A-Si) types.
  • the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5, and the sixth thin film transistor M6 can all be P-type thin film transistors.
  • the controlled end of the thin film transistor can be a gate, one of the first end and the second end can be a source, and the other end can be a drain; the thin film transistor can connect the first end and the second end when it is turned on, and disconnect the connection between the first end and the second end when it is turned off.
  • the first thin film transistor M1 has a controlled end connected to a first control signal Ctr1, a first end connected to a first power supply voltage Vss1, and a second end connected to a first node A1;
  • the controlled end of the second thin film transistor M2 is connected to the second control signal Ctr2, the first end is connected to the fourth node A4, and the second end is connected to the second end of the first thin film transistor M1;
  • the controlled end of the second thin film transistor M2 is connected to the scan signal Scan, the first end is connected to the data signal Data, and the second end is connected to the second node A2;
  • the fourth thin film transistor M4 has a controlled end connected to the fourth node A4, a first end connected to the first node A1, and a second end connected to the third node A3;
  • the controlled end of the fifth thin film transistor M5 is connected to the third control signal Ctr3, the first end is connected to the fourth node A4, and the second end is connected to the third node A3;
  • the sixth thin film transistor M6 has a controlled end connected to the fourth control signal Ctr4, a first end connected to the second end of the fifth thin film transistor M5, and a second end connected to the second power supply voltage Vss2;
  • One end of the capacitor C is connected to the second node A2, and the other end is connected to the fourth node A4.
  • the anode of the first light emitting device D1 is connected to the first node A1, and the cathode is connected to the first power supply voltage Vss1;
  • the anode of the second light emitting device D2 is connected to the third node A3, and the cathode is connected to the second power supply voltage Vss2;
  • the first reset stage T1, the first sampling stage T2, the first data writing stage T3, the first light-emitting stage T4, the second reset stage, the second sampling stage T6, the second data writing stage T7, and the second light-emitting stage T8 are respectively controlled to have the scanning signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2, and the data signal Data at different potentials, so that the pixel driving circuit of the present application can successively drive the first light-emitting device D1 and the second light-emitting device D2 to emit light.
  • the pixel driving circuit of the present application can be regarded as a 3T0.5C circuit structure.
  • first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the scan signal Scan and the data signal Data can all be output by an external timing controller, and the first power supply voltage Vss1 and the second power supply voltage Vss2 can be output by an external common voltage generating circuit.
  • two adjacent light-emitting devices in the same column can share a pixel driving circuit, and the threshold voltage of the fourth thin-film transistor M4 and the voltage drop of the power supply voltage can be compensated, thereby eliminating the influence of the threshold voltage defect of the driving thin-film transistor and the voltage drop of the power supply voltage on the current flowing through the light-emitting device, which is beneficial to improving the display uniformity of the self-luminous display panel.
  • the number of thin-film transistors is greatly reduced, thereby greatly improving the transmittance of the panel.
  • the pixel driving circuit of the present application can also make the first light-emitting device D1 and the second light-emitting device D2 in a reverse bias state to reduce the aging speed of the light-emitting device, which is beneficial to prolonging the service life of the self-luminous display panel.
  • the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2, the scan signal Scan and the data signal Data are combined to correspond to the first reset stage T1, the first sampling stage T2, the first data writing stage T3, the first light-emitting stage T4, the second reset stage T5, the second sampling stage T6, the second data writing stage T7, and the second light-emitting stage T8; wherein, in the first light-emitting stage T4, the first light-emitting device D1 emits light; and in the second light-emitting stage T8, the second light-emitting device D2 emits light.
  • FIG. 1 can also be a diagram of the pixel driving circuit of the present application under the driving timing shown in FIG. 2.
  • the scan signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2 and the data signal Data are all at a low potential to control the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5 and the sixth thin film transistor M6 to be turned on.
  • the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 are at a low potential; it should be noted that in the present application, the low potential of the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 is 0V, so that the pixel driving circuit clears the residual charge to reset the terminal voltage of the capacitor C and the potential value of the controlled end of the fourth thin film transistor M4 to 0 level.
  • Figure 3 is a schematic diagram of the path of the pixel driving circuit of the present application in the first sampling stage T2 under the driving timing shown in Figure 2.
  • the second control signal Ctr2 and the fourth control signal Ctr4 are both at a low potential to control the second thin film transistor M2 and the sixth thin film transistor M6 to be turned on.
  • the first control signal Ctr1, the scan signal Scan, and the third control signal Ctr3 are all at a high potential to control the first thin film transistor M1, the third thin film transistor M3, and the fifth thin film transistor M5 to be turned off.
  • the data signal Data is at a low potential
  • the first power supply voltage Vss1 and the second power supply voltage Vss2 are at a high potential
  • the terminal voltage of the capacitor C is still 0V
  • the potential value of the first node A1 is less than the high potential of the first power supply voltage Vss1, so that the first light emitting device D1 is in a reverse bias state, thereby improving the aging process of the first light emitting device D1.
  • FIG. 4 is a schematic diagram of the path of the first data writing stage T3 of the pixel driving circuit of the present application under the driving timing shown in FIG. 2 .
  • the second control signal Ctr2 is at a low potential to control the second thin film transistor M2 to turn on.
  • the first control signal Ctr1 , the third control signal Ctr3 , and the fourth control signal Ctr4 are all at a high potential to control the first thin film transistor M1 , the fifth thin film transistor M5 , and the sixth thin film transistor M6 to turn off.
  • the scan signal Scan is at a low potential in the preset sub-stage T31 to control the third thin film transistor M3 to turn on in the preset sub-stage T31; the scan signal Scan is at a high potential during the duration of the first data writing stage T3 except the preset sub-stage T31 to control the third thin film transistor M3 to turn off outside the preset sub-stage T31.
  • the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 are all at a high potential, so that the data signal Data is written into the second node A2 through the third thin film transistor M3.
  • the rising edge (signal edge from low potential to high potential) of the scan signal Scan(n) of the first light-emitting device D1 at the end of its preset sub-stage T31 corresponds to the falling edge (signal edge from high potential to low potential) of the scan signal Scan(n+2) of the subsequent light-emitting device at the beginning of its preset sub-stage T32.
  • FIG. 5 is a schematic diagram of the path of the first light-emitting stage T4 of the pixel driving circuit of the present application under the driving timing shown in FIG. 2.
  • the fourth control signal Ctr4 is at a low potential to control the sixth thin film transistor M6 to turn on.
  • the first control signal Ctr1, the second control signal Ctr2, the scan signal Scan and the third control signal Ctr3 are all at a high potential to control the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3 and the fifth thin film transistor M5 to turn off.
  • the first power supply voltage Vss1 is a negative potential
  • the second power supply voltage Vss2 is a high potential
  • the data signal Data is a low potential
  • the negative potential of the first power supply voltage Vss1 is less than its low potential.
  • the potential of the third node A3 can be pulled up to the high potential of the second power supply voltage Vss2, and the fourth thin film transistor M4 is turned on to generate a current flowing through the first light-emitting device D1, so as to achieve driving the first light-emitting device D1 to emit light.
  • the expression of the current flowing through the first light-emitting device D1 can be:
  • ⁇ is the carrier mobility of the fourth thin film transistor M4
  • W is the channel width of the fourth thin film transistor M4
  • L is the channel length of the fourth thin film transistor M4
  • C GI is the gate capacitance C of the fourth thin film transistor M4.
  • FIG. 1 is also a schematic diagram of the path of the pixel driving circuit of the present application in the second light-emitting stage T5 under the driving timing shown in FIG. 2 .
  • the scan signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2 and the data signal Data are all at a low potential to control the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5 and the sixth thin film transistor M6 to be turned on.
  • the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 are at a low potential so that the pixel driving circuit clears the residual charge to reset the terminal voltage of the capacitor C and the potential value of the controlled terminal of the fourth thin film transistor M4 to the 0 level again.
  • FIG. 6 is a schematic diagram of the path of the pixel driving circuit of the present application in the second sampling stage T6 under the driving timing shown in FIG. 2 .
  • the first control signal Ctr1 , the scan signal Scan , and the third control signal Ctr3 are all at a low potential to control the first thin film transistor M1 , the third thin film transistor M3 , and the fifth thin film transistor M5 to turn on.
  • the second control signal Ctr2 and the fourth control signal Ctr4 are both at a high potential to control the second thin film transistor M2 and the sixth thin film transistor M6 to turn off.
  • the data signal Data is at a low potential
  • the first power supply voltage Vss1 and the second power supply voltage Vss2 are at a high potential
  • the terminal voltage of the capacitor C is still 0V
  • the potential value of the third node A3 is lower than the high potential of the second power supply voltage Vss2, so that the second light emitting device D2 is in a reverse bias state, thereby improving the aging process of the second light emitting device D2.
  • FIG. 7 is a schematic diagram of the path of the pixel driving circuit of the present application in the second data writing stage T7 under the driving timing shown in FIG. 2 .
  • the third control signal Ctr3 is at a low potential to control the fifth thin film transistor M5 to turn on.
  • the first control signal Ctr1 , the second control signal Ctr2 , and the fourth control signal Ctr4 are all at a high potential to control the first thin film transistor M1 , the second thin film transistor M2 , and the sixth thin film transistor M6 to turn off.
  • the scan signal Scan is at a low potential in the preset sub-stage T71 to control the third thin film transistor M3 to turn on in the preset sub-stage T71; the scan signal Scan is at a high potential during the duration of the first data writing stage T3 except the preset sub-stage T71 to control the third thin film transistor M3 to turn off outside the preset sub-stage T71.
  • the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 are all at a high potential, so that the data signal Data is written into the second node A2 through the third thin film transistor M3.
  • the rising edge (signal edge from low potential to high potential) of the scan signal Scan(n+1) of the first light-emitting second light-emitting device D2 at the end of its preset sub-stage T71 corresponds to the falling edge (signal edge from high potential to low potential) of the scan signal Scan(n+3) of the second light-emitting device D2 at the beginning of its preset sub-stage T72.
  • FIG. 8 is a second light emitting pixel driving circuit of the present application under the driving timing shown in FIG. 2.
  • the first control signal Ctr1 is at a low potential to control the first thin film transistor M1 to turn on.
  • the second control signal Ctr2, the fourth control signal Ctr4, the third control signal Ctr3 and the scan signal Scan are all at a high potential to control the second thin film transistor M2, the sixth thin film transistor M6, the fifth thin film transistor M5 and the third thin film transistor M3 to turn off.
  • the first power supply voltage Vss1 is a high potential
  • the second power supply voltage Vss2 is a negative potential
  • the data signal Data is a low potential
  • the negative potential of the second power supply voltage Vss2 is less than its low potential.
  • the potential of the first node A1 can be pulled up to a high potential of the first power supply voltage Vss1
  • the fourth thin film transistor M4 is turned on to generate a current flowing through the second light-emitting device D2, so as to drive the second light-emitting device D2 to emit light.
  • the expression of the current flowing through the second light-emitting device D2 can be:
  • the current flowing through the second light-emitting device D2 when it emits light is also only related to the data signal Data, and has nothing to do with the threshold voltage of the fourth thin-film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, that is, it does not change with the changes in the threshold voltage of the fourth thin-film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, thereby eliminating the influence of the threshold voltage defect of the fourth thin-film transistor M4 and the power supply voltage drop on the current flowing through the second light-emitting device D2.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the present application further proposes a pixel driving method, which can be applied to a pixel driving circuit.
  • the specific structure of the pixel driving circuit refers to the above-mentioned embodiment 1. Since the present pixel driving method adopts all the technical solutions of the above-mentioned embodiment 1, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiment 1, which will not be described one by one here.
  • the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the scan signal Scan and the data signal Data are combined to correspond successively to the first reset stage T1, the first sampling stage T2, the first data writing stage T3, the first light-emitting stage T4, the second reset stage T5, the second sampling stage T6, the second data writing stage T7, and the second light-emitting stage T8.
  • the pixel driving method includes:
  • Step S1 enter the first reset stage T1, control the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5 and the sixth thin film transistor M6 to turn on, and control the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 to be low potential.
  • the scan signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2 and the data signal Data are all at a low potential.
  • the pixel driving circuit can clear the residual charge to reset the terminal voltage of the capacitor C and the potential value of the controlled end of the fourth thin film transistor M4 to 0 level.
  • Step S2 entering the first sampling stage T2, controlling the second thin film transistor M2 and the sixth thin film transistor M6 to turn on, controlling the first thin film transistor M1, the third thin film transistor M3, and the fifth thin film transistor M5 to turn off, and controlling the data signal Data to be low potential, the first power supply voltage Vss1 and the second power supply voltage Vss2 to be high potential, so that the potential of the fourth node A4 is the difference between the second power supply voltage Vss2 and the absolute value of the threshold voltage of the fourth thin film transistor M4.
  • the second control signal Ctr2 and the fourth control signal Ctr4 are both at a low potential; the first control signal Ctr1, the scan signal Scan, and the third control signal Ctr3 are all at a high potential.
  • Step S3 entering the first data writing stage T3, controlling the second thin film transistor M2 to turn on, controlling the first thin film transistor M1, the fifth thin film transistor M5 and the sixth thin film transistor M6 to turn off, controlling the third thin film transistor M3 to turn on in the preset sub-stage T31, and controlling the third thin film transistor M3 to turn off outside the preset sub-stage T31, and controlling the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 to be high potential, so that the potential of the fourth node A4 is the sum of the difference between the second power supply voltage Vss2 and the absolute value of the threshold voltage of the fourth thin film transistor M4 and the data signal Data.
  • the second control signal Ctr2 is at a low potential; the first control signal Ctr1, the third control signal Ctr3 and the fourth control signal Ctr4 are all at a high potential; the scan signal Scan is at a low potential in the preset sub-stage T31, and is at a high potential during the duration of the first data writing stage T3 except the preset sub-stage T31.
  • Step S4 enter the first light-emitting stage T4, control the sixth thin film transistor M6 to turn on, and control the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3 and the fifth thin film transistor M5 to turn off, and control the first power supply voltage Vss1 to be a negative potential, and control the second power supply voltage Vss2 to be a high potential, and control the data signal Data to be a low potential, so that the first light-emitting device D1 emits light.
  • the fourth control signal Ctr4 is at a low potential
  • the first control signal Ctr1, the second control signal Ctr2, the scan signal Scan and the third control signal Ctr3 are all at a high potential.
  • the potential of the third node A3 can be pulled up to the high potential of the second power supply voltage Vss2, and the fourth thin film transistor M4 is turned on to generate a current flowing through the first light-emitting device D1, so as to achieve driving the first light-emitting device D1 to emit light.
  • the current flowing through the first light-emitting device D1 that the current flowing through the first light-emitting device D1 when emitting light is only related to the data signal Data, and has nothing to do with the threshold voltage of the fourth thin film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, that is, it does not change with the changes in the threshold voltage of the fourth thin film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, thereby eliminating the influence of the threshold voltage defect of the fourth thin film transistor M4 and the power supply voltage drop on the current flowing through the first light-emitting device D1.
  • Step S5 entering the second reset stage T5, controlling the first thin film transistor M1, the second thin film transistor M2, the third thin film transistor M3, the fourth thin film transistor M4, the fifth thin film transistor M5 and the sixth thin film transistor M6 to turn on, and controlling the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 to be low potential.
  • the scan signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2 and the data signal Data are all at low potential.
  • the pixel driving circuit clears the residual charge, so as to reset the terminal voltage of the capacitor C and the potential value of the controlled terminal of the fourth thin film transistor M4 to 0 level again.
  • Step S6 entering the second sampling stage T6, controlling the first thin film transistor M1, the third thin film transistor M3, and the fifth thin film transistor M5 to be turned on, controlling the second thin film transistor M2 and the sixth thin film transistor M6 to be turned off, controlling the data signal Data to be low potential, and controlling the first power supply voltage Vss1 and the second power supply voltage Vss2 to be high potential, so that the potential of the fourth node A4 is the difference between the absolute value of the first power supply voltage Vss1 and the threshold voltage of the fourth thin film transistor M4.
  • the first control signal Ctr1, the scan signal Scan, and the third control signal Ctr3 are all at a low potential
  • the second control signal Ctr2 and the fourth control signal Ctr4 are all at a high potential.
  • Step S7 entering the second data writing stage T7, controlling the fifth thin film transistor M5 to turn on, controlling the first thin film transistor M1, the second thin film transistor M2 and the sixth thin film transistor M6 to turn off, controlling the third thin film transistor M3 to turn on in the preset sub-stage T71, and controlling the third thin film transistor M3 to turn off outside the preset sub-stage T71, and controlling the data signal Data, the first power supply voltage Vss1 and the second power supply voltage Vss2 to be high potentials, so that the potential of the fourth node A4 is the difference between the absolute value of the first power supply voltage Vss1 and the threshold voltage of the fourth thin film transistor M4 and the data signal
  • the third control signal Ctr3 is at a low potential
  • the first control signal Ctr1, the second control signal Ctr2, and the fourth control signal Ctr4 are all at a high potential
  • the scan signal Scan is at a low potential in the preset sub-stage T71, and is at a high potential in the first data
  • Step S8 entering the second light-emitting stage T8, controlling the first thin film transistor M1 to turn on, controlling the second thin film transistor M2, the third thin film transistor M3, the fifth thin film transistor M5 and the sixth thin film transistor M6 to turn off, controlling the first power supply voltage Vss1 to be a high potential, controlling the second power supply voltage Vss2 to be a negative potential, and controlling the data signal Data to be a low potential, so that the second light-emitting device D2 emits light.
  • the first control signal Ctr1 is at a low potential
  • the second control signal Ctr2, the fourth control signal Ctr4, the third control signal Ctr3 and the scan signal Scan are all at a high potential.
  • the potential of the first node A1 can be pulled up to a high potential of the first power supply voltage Vss1, and the fourth thin film transistor M4 is turned on to generate a current flowing through the second light-emitting device D2, thereby driving the second light-emitting device D2 to emit light.
  • the current flowing through the second light-emitting device D2 when emitting light is also only related to the data signal Data, and has nothing to do with the threshold voltage of the fourth thin film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, that is, it does not change with the changes in the threshold voltage of the fourth thin film transistor M4, the first power supply voltage Vss1 and the second power supply voltage Vss2, thereby eliminating the influence of the threshold voltage defect of the fourth thin film transistor M4 and the power supply voltage drop on the current flowing through the second light-emitting device D2.
  • the present application also proposes a display panel, which includes a pixel array and a pixel driving circuit.
  • the specific structure of the pixel driving circuit refers to the above-mentioned embodiment 1. Since the pixel driving method adopts all the technical solutions of the above-mentioned embodiment 1, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiment 1, which will not be repeated here one by one.
  • the pixel array includes a first light emitting device D1 and a second light emitting device D2 adjacent to each other in the same column.
  • the pixel driving circuit is connected to the first light emitting device D1 and the second light emitting device D2, and is used to drive the first light emitting device D1 and the second light emitting device D2 to emit light in sequence according to the input scanning signal Scan, the first control signal Ctr1, the second control signal Ctr2, the third control signal Ctr3, the fourth control signal Ctr4, the first power supply voltage Vss1, the second power supply voltage Vss2 and the potential of the data signal Data.

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Abstract

一种像素驱动电路、像素驱动方法和显示面板，其中，像素驱动电路包括第一薄膜晶体管(M1)、第二薄膜晶体管(M2)、第三薄膜晶体管(M3)、第四薄膜晶体管(M4)、第五薄膜晶体管(M5)、第六薄膜晶体管(M6)和电容(C)。列上相邻的第一发光器件（D1）和第二发光器件（D2）可共用一个像素驱动电路，且可对第四薄膜晶体管(M4)的阈值电压以及电源电压(Vss1,Vss2)的压降进行补偿。

Description

像素驱动电路、像素驱动方法和显示面板
相关申请
本申请要求于2022年11月2日申请的、申请号为202211359796.0的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及像素驱动技术领域，特别涉及一种像素驱动电路、像素驱动方法和显示面板。
背景技术
目前，对于采用发光器件来作为像素的显示面板而言，每一发光器件都需要配备一像素驱动电路，但每一现有像素驱动电路为实现对驱动薄膜晶体管的阈值电压补偿，往往需要采用6个甚至更多的薄膜晶体管，从而影响显示面板的透过率。
发明内容
本申请的主要目的是提供一种像素驱动电路，旨在解决自发光显示面板透过率较低的问题。
为实现上述目的，本申请提出的像素驱动电路，应用于显示面板，所述显示面板设有像素阵列，所述像素阵列包括位于同列上相邻的第一发光器件和第二发光器件，所述第一发光器件的阳极连接于第一节点，阴极接入第一电源电压；第二发光器件的阳极连接于第三节点，阴极接入第二电源电压；
所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管和电容；
所述第一薄膜晶体管的受控端接入第一控制信号，第一端接入第一电源电压，第二端连接于第一节点；
所述第二薄膜晶体管的受控端接入第二控制信号，第一端连接于第四节点，第二端连接于所述第一薄膜晶体管的第二端；
所述第二薄膜晶体管的受控端接入扫描信号，第一端连接于数据信号，第二端连接于第二节点；
所述第四薄膜晶体管的受控端连接于第四节点，第一端连接于第一节点，第二端连接于第三节点；
所述第五薄膜晶体管的受控端接入第三控制信号，第一端连接于第四节点，第二端连接于第三节点；
所述第六薄膜晶体管的受控端接入第四控制信号，第一端连接于所述第五薄膜晶体管的第二端，第二端接入第二电源电压；
所述电容的一端连接于第二节点，另一端连接于第四节点。
本申请还提出一种像素驱动方法，应用于如上述的像素驱动电路，所述像素驱动方法包括：
进入第一复位阶段，控制所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管开启，以及控制所述数据信号、所述第一电源电压以及所述第二电源电压为低电位；
进入第一采样阶段，控制所述第二薄膜晶体管和所述第六薄膜晶体管开启，以及控制所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管关闭，以及控制所述数据信号为低电位，所述第一电源电压以及所述第二电源电压为高电位，以使所述第四节点电位为第二电源电压与所述第四薄膜晶体管阈值电压的绝对值之差；
进入第一数据写入阶段，控制所述第二薄膜晶体管开启，以及控制所述第一薄膜晶体管、所述第五薄膜晶体管和所述第六薄膜晶体管关闭，以及控制所述第三薄膜晶体管在预设子阶段开启，以及控制所述第三薄膜晶体管在预设子阶段之外关闭，以及控制所述数据 信号、所述第一电源电压以及所述第二电源电压为高电位，以使所述第四节点电位为第二电源电压与所述第四薄膜晶体管阈值电压的绝对值的差值与数据信号之和；
进入第一发光阶段，控制所述第六薄膜晶体管开启，以及控制所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管和所述第五薄膜晶体管关闭，以及控制所述第一电源电压为负电位，以及控制所述第二电源电压为高电位，以及控制所述数据信号为低电位，以使所述第一发光器件发光；
进入第二复位阶段，控制所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管开启，以及控制所述数据信号、所述第一电源电压以及所述第二电源电压为低电位；
进入第二采样阶段，控制所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管开启，以及控制所述第二薄膜晶体管和所述第六薄膜晶体管关闭，以及控制所述数据信号为低电位，以及控制所述第一电源电压以及所述第二电源电压为高电位，以使所述第四节点电位为第一电源电压与所述第四薄膜晶体管阈值电压的绝对值之差；
进入第二数据写入阶段，控制所述第五薄膜晶体管开启，以及控制所述第一薄膜晶体管、所述第二薄膜晶体管和所述第六薄膜晶体管关闭，以及控制所述第三薄膜晶体管在预设子阶段开启，以及控制所述第三薄膜晶体管在预设子阶段之外关闭，以及控制所述数据信号、所述第一电源电压以及所述第二电源电压为高电位，以使所述第四节点电位为第一电源电压与所述第四薄膜晶体管阈值电压的绝对值的差值与数据信号之和；
进入第二发光阶段，控制所述第一薄膜晶体管开启，以及控制所述第二薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管和所述第六薄膜晶体管关闭，以及控制所述第一电源电压为高电位，以及控制所述第二电源电压为负电位，以及控制所述数据信号为低电位，以使所述第二发光器件发光。
本申请还提出一种显示面板，所述显示面板包括：
像素阵列，所述像素阵列包括位于同列上相邻的第一发光器件和第二发光器件；以及，
如上述的像素驱动电路，所述像素驱动电路与所述第一发光器件和所述第二发光器件连接。
本申请技术方案通过采用第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管和电容，以构成3T0.5C电路结构的像素驱动电路，以使同列上相邻两发光器件可共用一个像素驱动电路，且可对驱动薄膜晶体管的阈值电压以及电源电压的压降进行补偿，因而可消除驱动薄膜晶体管的阈值电压缺陷和电源电压压降对发光器件流经电流的影响，有利于提高自发光显示面板的显示均匀性，相较于分别设置两路像素驱动电路所需的至少12个薄膜晶体管而言，极大降低了薄膜晶体管的数量，从而可极大改善面板的透过率。此外，本申请像素驱动电路还可使得第一发光器件和第二发光器件处于反向偏置状态，以降低发光器件的老化速度，有利于延长自发光显示面板的使用寿命。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请实施例一像素驱动电路的电路示意图；
图2为本申请实施例一像素驱动电路的时序示意图；
图3为本申请实施例一像素驱动电路在第一采样阶段的通路示意图；
图4为本申请实施例一像素驱动电路在第一数据阶段的通路示意图；
图5为本申请实施例一像素驱动电路在第一发光写入阶段的通路示意图；
图6为本申请实施例一像素驱动电路在第二采样阶段的通路示意图；
图7为本申请实施例一像素驱动电路在第二数据阶段的通路示意图；
图8为本申请实施例一像素驱动电路在第二发光阶段的通路示意图；
图9为本申请实施例二像素驱动方法的步骤示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
另外，在本申请中如涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
实施例一：
本申请提出一种像素驱动电路，可应用于显示面板。
显示面板可以包括依次叠设的像素层、发光层、驱动电路层和阵列基板。驱动电路层设置于阵列基板上。像素层可以包括多个呈阵列排布的像素，发光层对应每一像素设置有一发光器件。驱动电路层可以包括多个像素驱动电路，每一像素驱动电路连接有一发光器件，每一像素驱动电路用于驱动对应像素的发光器件的发光，从而以实现显示面板的自发光显示。发光器件可以是有机发光二极管(OLED)、迷你发光二极管(MINI-LED)或者是微发光二极管(MICRO-LED)，在此不做限定；本申请实施例以发光器件为有机发光二极管为例进行说明。
在实际应用中，像素驱动电路中可设有一个用于控制发光器件流经电流的驱动薄膜晶体管，而驱动薄膜晶体管的阀值电压存在非均匀性问题，且该阈值电压还会随着工作时间的增加而发生漂移，以导致显示面板产生亮度不均的云纹。现有技术为解决阈值电压所存在的上述缺陷，通常会增加的薄膜晶体管的数量和增设存储电容C，以导致每一像素驱动电路中的薄膜晶体管数量为6个及以上，由像素驱动电路所在驱动电路层在显示面板的位置可知，每一像素驱动电路中的薄膜晶体管数量越多，发光层经驱动电路层透出的光线也就越少，显示面板的透过率也就越低。其次，像素驱动电路还需要经电源线接入电源电压来驱动对应的发光器件，电源线本身存在一定程度的内阻，因而实际传递到发光器件的电源电压存在压降，且由于不同显示器件的电源电压压降不同，因而会导致各发光器件的发光亮度不均，并且像素驱动电路中的发光器件由于处于正向偏置状态，还会使得发光器件的老化速度较快，以导致自发光显示面板的使用寿命较低。
针对上述问题，本申请提出一种像素驱动电路，用于驱动像素阵列中同一列上相邻的两发光器件，其中第一发光器件D1可为奇数行上的发光器件，第二发光器件D2可为偶数行的发光器件。
参照图1，本申请的像素驱动电路包括第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6和电容C。第一薄膜晶体管M1和第二薄膜晶体管M2用于控制第一发光器件D1发光以及第一节点A1的电荷清空。第三薄膜晶体管M3为数据写入薄膜晶体管。第四薄膜晶体管M4同时作为第一发光器件D1和第二发光器件D2的驱动薄膜晶体管。第五薄膜晶体管M5和第六薄膜晶体管M6用于控制第二发光器件D2发光以及第三节点A3的电荷清空。电容C可为存储电容C。其中，第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6可均为氧化物半导体薄膜晶体管、低温多晶硅薄膜晶体管或 者非晶硅薄膜晶体管，也即薄膜晶体管T1至T7的类型均可以为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、低温多晶硅(Low Temperature Poly-silicon，LTPS)或者非晶硅(A-Si)类型。当然，也可以对薄膜晶体管M1至M6分别采用不同类型的薄膜晶体管，组合方式有多种，在此不再赘述。本实施例中，第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5、第六薄膜晶体管M6均可为P型薄膜晶体管。可以理解的是，薄膜晶体管的受控端可为栅极，第一端和第二端中的一者可为源极，另一端可为漏极；薄膜晶体管可在开启时使第一端和第二端连接，在关闭时使第一端和第二端的连接断开。
第一薄膜晶体管M1的受控端接入第一控制信号Ctr1，第一端接入第一电源电压Vss1，第二端连接于第一节点A1；
第二薄膜晶体管M2的受控端接入第二控制信号Ctr2，第一端连接于第四节点A4，第二端连接于第一薄膜晶体管M1的第二端；
第二薄膜晶体管M2的受控端接入扫描信号Scan，第一端连接于数据信号Data，第二端连接于第二节点A2；
第四薄膜晶体管M4的受控端连接于第四节点A4，第一端连接于第一节点A1，第二端连接于第三节点A3；
第五薄膜晶体管M5的受控端接入第三控制信号Ctr3，第一端连接于第四节点A4，第二端连接于第三节点A3；
第六薄膜晶体管M6的受控端接入第四控制信号Ctr4，第一端连接于第五薄膜晶体管M5的第二端，第二端接入第二电源电压Vss2；
电容C的一端连接于第二节点A2，另一端连接于第四节点A4。
第一发光器件D1的阳极连接于第一节点A1，阴极接入第一电源电压Vss1；第二发光器件D2的阳极连接于第三节点A3，阴极接入第二电源电压Vss2；
对第一复位阶段T1、第一采样阶段T2、第一数据写入阶段T3、第一发光阶段T4、第二复位阶段、第二采样阶段T6、第二数据写入阶段T7、第二发光阶段T8分别控制扫描信号Scan、第一控制信号Ctr1、第二控制信号Ctr2、第三控制信号Ctr3、第四控制信号Ctr4、第一电源电压Vss1、第二电源电压Vss2和数据信号Data处于不同的电位，从而可以使得本申请像素驱动电路先后驱动第一发光器件D1和第二发光器件D2发光。换而言之，本申请像素驱动电路可视为3T0.5C的电路结构。
需要说明的是，第一控制信号Ctr1、第二控制信号Ctr2、第三控制信号Ctr3、第四控制信号Ctr4、扫描信号Scan和数据信号Data均可由外部时序控制器输出得到，第一电源电压Vss1和第二电源电压Vss2可由外部公共电压产生电路输出得到。
如此，以使同列上相邻两发光器件可共用一个像素驱动电路，且可对第四薄膜晶体管M4的阈值电压以及电源电压的压降进行补偿，因而可消除驱动薄膜晶体管的阈值电压缺陷和电源电压压降对发光器件流经电流的影响，有利于提高自发光显示面板的显示均匀性，相较于分别设置两路像素驱动电路所需的至少12个薄膜晶体管而言，极大降低了薄膜晶体管的数量，从而可极大改善面板的透过率。此外，本申请像素驱动电路还可使得第一发光器件D1和第二发光器件D2中处于反向偏置状态，以降低发光器件的老化速度，有利于延长自发光显示面板的使用寿命。
在一实施例中，第一控制信号Ctr1、第二控制信号Ctr2、第三控制信号Ctr3、第四控制信号Ctr4、所述第一电源电压Vss1、所述第二电源电压Vss2、扫描信号Scan以及数据信号Data相组合先后对应于第一复位阶段T1、第一采样阶段T2、第一数据写入阶段T3、第一发光阶段T4、第二复位阶段T5、第二采样阶段T6、第二数据写入阶段T7、第二发光阶段T8；其中，在第一发光阶段T4，第一发光器件D1发光；在第二发光阶段T8，第二发光器件D2发光。
参照图1和图2，图1同时也可为本申请像素驱动电路在图2所示的驱动时序下的第 一复位阶段T1的通路示意图。在第一复位阶段T1，扫描信号Scan、第一控制信号Ctr1、第二控制信号Ctr2、第三控制信号Ctr3、第四控制信号Ctr4、第一电源电压Vss1、第二电源电压Vss2和数据信号Data均处于低电位，以控制第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5以及第六薄膜晶体管M6均开启。此时，数据信号Data、第一电源电压Vss1以及第二电源电压Vss2为低电位；需要说明的是，本申请中数据信号Data、第一电源电压Vss1、第二电源电压Vss2的低电位为0V，从而以使像素驱动电路清空残留电荷，以将电容C的端电压和第四薄膜晶体管M4受控端的电位值复位至0准位。
参照图1、图2和图3，图3为本申请像素驱动电路在图2所示的驱动时序下的第一采样阶段T2的通路示意图。在第一采样阶段T2，第二控制信号Ctr2和第四控制信号Ctr4均处于低电位，以控制第二薄膜晶体管M2和第六薄膜晶体管M6开启。第一控制信号Ctr1、扫描信号Scan、第三控制信号Ctr3均处于高电位，以控制第一薄膜晶体管M1、第三薄膜晶体管M3、第五薄膜晶体管M5关闭。此时，数据信号Data为低电位，第一电源电压Vss1以及第二电源电压Vss2为高电位，由于电容C的耦合作用，因而电容C的端电压依然为0V，而第四薄膜晶体管M4的受控端电位，即第四节点A4电位可被充电至第二电源电压Vss2与第四薄膜晶体管M4阈值电压的绝对值之差，用公式表示即为VG＝VS2-|VTH|，其中：VG为第四薄膜晶体管M4受控端的电位值，VS2为第二电源电压Vss2的电位值，VTH为第四薄膜晶体管M4阈值电压。其次，此时第一节点A1的电位值小于第一电源电压Vss1的高电位，以使第一发光器件D1处于反向偏置状态，从而以实现改善第一发光器件D1的老化进程。
参照图1、图2和图4，图4为本申请像素驱动电路在图2所示的驱动时序下的第一数据写入阶段T3的通路示意图。在第一数据写入阶段T3，第二控制信号Ctr2处于低电位，以控制第二薄膜晶体管M2开启。第一控制信号Ctr1、第三控制信号Ctr3、第四控制信号Ctr4均处于高电位，以控制第一薄膜晶体管M1、第五薄膜晶体管M5和第六薄膜晶体管M6关闭。扫描信号Scan在预设子阶段T31中处于低电位，以控制第三薄膜晶体管M3在预设子阶段T31开启；扫描信号Scan在第一数据写入阶段T3除预设子阶段T31之外的时长中处于高电位，以控制第三薄膜晶体管M3在预设子阶段T31之外关闭。此时，数据信号Data、第一电源电压Vss1以及第二电源电压Vss2均处于为高电位，以使数据信号Data经第三薄膜晶体管M3写入第二节点A2，由于电容C的耦合作用，第四节点A4电位为第二电源电压Vss2与第四薄膜晶体管M4阈值电压的绝对值的差值与数据信号Data之和，用公式表示即为VG＝VS2-|VTH|+VDATA；其中，VDATA为数据信号Data的电位。需要说明的是，对于同列上距离最近的两第一发光器件D1而言，先发光第一发光器件D1在其预设子阶段T31结束时扫描信号Scan(n)的上升沿(由低电位转为高电位的信号边沿)与后发光器件在其预设子阶段T32开始时扫描信号Scan(n+2)的下升沿(由高电位转为低电位的信号边沿)相对应。
参照图1、图2和图5，图5为本申请像素驱动电路在图2所示的驱动时序下的第一发光阶段T4的通路示意图。在第一发光阶段T4，第四控制信号Ctr4处于低电位，以控制第六薄膜晶体管M6开启。第一控制信号Ctr1、第二控制信号Ctr2、扫描信号Scan和第三控制信号Ctr3均处于高电位，以控制第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3和第五薄膜晶体管M5关闭。此时，第一电源电压Vss1为负电位，第二电源电压Vss2为高电位，数据信号Data为低电位；需要说明的是，第一电源电压Vss1的负电位小于其低电位。如此，第三节点A3电位可上拉至第二电源电压Vss2的高电位，且第四薄膜晶体管M4开启，以产生第一发光器件D1的流经电流，从而以实现驱动第一发光器件D1发光，第一发光器件D1流经电流的表达式可为：
其中：μ为第四薄膜晶体管M4的载流子迁移率，W为第四薄膜晶体管M4的沟道宽度，L为第四薄膜晶体管M4的沟道长度，CGI为第四薄膜晶体管M4的栅极电容C。由此可见，第一发光器件D1发光时的流经电流只与数据信号Data相关，而与第四薄膜晶体管M4的阈值电压、第一电源电压Vss1和第二电源电压Vss2无关，也即为不随第四薄膜晶体管M4的阈值电压、第一电源电压Vss1和第二电源电压Vss2的变化而变化，从而以消除第四薄膜晶体管M4的阈值电压缺陷和电源电压压降对第一发光器件D1流经电流的影响。
参照图1和图2，图1同时还可为本申请像素驱动电路在图2所示的驱动时序下的第二发光阶段T5的通路示意图。在第二复位阶段T5，扫描信号Scan、第一控制信号Ctr1、第二控制信号Ctr2、第三控制信号Ctr3、第四控制信号Ctr4、第一电源电压Vss1、第二电源电压Vss2和数据信号Data均处于低电位，以控制第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5以及第六薄膜晶体管M6均开启。此时，数据信号Data、第一电源电压Vss1以及第二电源电压Vss2为低电位，以使像素驱动电路清空残留电荷，以将电容C的端电压和第四薄膜晶体管M4受控端的电位值再次复位至0准位。
参照图1、图2和图6，图6为本申请像素驱动电路在图2所示的驱动时序下的第二采样阶段T6的通路示意图。在第二采样阶段T6，第一控制信号Ctr1、扫描信号Scan、第三控制信号Ctr3均处于低电位，以控制第一薄膜晶体管M1、第三薄膜晶体管M3、第五薄膜晶体管M5开启。第二控制信号Ctr2和第四控制信号Ctr4均处于高电位，以控制第二薄膜晶体管M2和第六薄膜晶体管M6关闭。此时，数据信号Data为低电位，第一电源电压Vss1以及第二电源电压Vss2为高电位，由于电容C的耦合作用，因而电容C的端电压依然为0V，而第四薄膜晶体管M4的受控端电位，即第四节点A4电位可被充电至第一电源电压Vss1与第四薄膜晶体管M4阈值电压的绝对值之差，用公式表示即为VG＝VS1-|VTH|，其中：VS1为第一电源电压Vss1的电位值。其次，此时第三节点A3的电位值小于第二电源电压Vss2的高电位，以使第二发光器件D2处于反向偏置状态，从而以实现改善第二发光器件D2的老化进程。
参照图1、图2和图7，图7为本申请像素驱动电路在图2所示的驱动时序下的第二数据写入阶段T7的通路示意图。在第二数据写入阶段T7，第三控制信号Ctr3处于低电位，以控制第五薄膜晶体管M5开启。第一控制信号Ctr1、第二控制信号Ctr2、第四控制信号Ctr4均处于高电位，以控制第一薄膜晶体管M1、第二薄膜晶体管M2和第六薄膜晶体管M6关闭。扫描信号Scan在预设子阶段T71中处于低电位，以控制第三薄膜晶体管M3在预设子阶段T71开启；扫描信号Scan在第一数据写入阶段T3除预设子阶段T71之外的时长中处于高电位，以控制第三薄膜晶体管M3在预设子阶段T71之外关闭。此时，数据信号Data、第一电源电压Vss1以及第二电源电压Vss2均处于为高电位，以使数据信号Data经第三薄膜晶体管M3写入第二节点A2，由于电容C的耦合作用，第四节点A4电位为第一电源电压Vss1与第四薄膜晶体管M4阈值电压的绝对值的差值与数据信号Data之和，用公式表示即为VG＝VS1-|VTH|+VDATA。需要说明的是，对于同列上距离最近的两第二发光器件D2而言，先发光第二发光器件D2在其预设子阶段T71结束时扫描信号Scan(n+1)的上升沿(由低电位转为高电位的信号边沿)与后发光器件在其预设子阶段T72开始时扫描信号Scan(n+3)的下升沿(由高电位转为低电位的信号边沿)相对应。
参照图1、图2和图8，图8为本申请像素驱动电路在图2所示的驱动时序下的第二发光 阶段T8的通路示意图。在第二发光阶段T8，第一控制信号Ctr1处于低电位，以控制第一薄膜晶体管M1开启。第二控制信号Ctr2、第四控制信号Ctr4、第三控制信号Ctr3和扫描信号Scan均处于高电位，以控制第二薄膜晶体管M2、第六薄膜晶体管M6、第五薄膜晶体管M5和第三薄膜晶体管M3关闭。此时，第一电源电压Vss1为高电位，第二电源电压Vss2为负电位，数据信号Data为低电位；需要说明的是，第二电源电压Vss2的负电位小于其低电位。如此，第一节点A1电位可上拉至为第一电源电压Vss1的高电位，且第四薄膜晶体管M4开启，以产生第二发光器件D2的流经电流，从而以实现驱动第二发光器件D2发光，第二发光器件D2流经电流的表达式可为：
由此可见，第二发光器件D2发光时的流经电流同样只与数据信号Data相关，而与第四薄膜晶体管M4的阈值电压、第一电源电压Vss1和第二电源电压Vss2无关，也即为不随第四薄膜晶体管M4的阈值电压、第一电源电压Vss1和第二电源电压Vss2的变化而变化，从而以消除第四薄膜晶体管M4的阈值电压缺陷和电源电压压降对第二发光器件D2流经电流的影响。
实施例二：
参照图9，本申请还提出一种像素驱动方法，该像素驱动方法可应用于像素驱动电路，该像素驱动电路的具体结构参照上述实施例一，由于本像素驱动方法采用了上述实施例一的全部技术方案，因此至少具有上述实施例一的技术方案所带来的所有有益效果，在此不再一一赘述。
第一控制信号Ctr1、第二控制信号Ctr2、第三控制信号Ctr3、第四控制信号Ctr4、扫描信号Scan以及数据信号Data相组合先后对应于第一复位阶段T1、第一采样阶段T2、第一数据写入阶段T3、第一发光阶段T4、第二复位阶段T5、第二采样阶段T6、第二数据写入阶段T7、第二发光阶段T8。
其中，像素驱动方法包括：
步骤S1、进入第一复位阶段T1，控制第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5以及第六薄膜晶体管M6开启，以及控制数据信号Data、第一电源电压Vss1以及第二电源电压Vss2为低电位。该阶段中，扫描信号Scan、第一控制信号Ctr1、第二控制信号Ctr2、第三控制信号Ctr3、第四控制信号Ctr4、第一电源电压Vss1、第二电源电压Vss2和数据信号Data均处于低电位。如此，以使得像素驱动电路可清空残留电荷，以将电容C的端电压和第四薄膜晶体管M4受控端的电位值复位至0准位。
步骤S2、进入第一采样阶段T2，控制第二薄膜晶体管M2和第六薄膜晶体管M6开启，以及控制第一薄膜晶体管M1、第三薄膜晶体管M3、第五薄膜晶体管M5关闭，以及控制数据信号Data为低电位，第一电源电压Vss1以及第二电源电压Vss2为高电位，以使第四节点A4电位为第二电源电压Vss2与第四薄膜晶体管M4阈值电压的绝对值之差。该阶段中，第二控制信号Ctr2和第四控制信号Ctr4均处于低电位；第一控制信号Ctr1、扫描信号Scan、第三控制信号Ctr3均处于高电位。如此，以使得第四薄膜晶体管M4的受控端电位，即第四节点A4电位可被充电至第二电源电压Vss2与第四薄膜晶体管M4阈值电压的绝对值之差，用公式表示即为VG＝VS2-|VTH|，并且此时第一节点A1的电位值小于第一电源电压Vss1的高电位，以使第一发光器件D1处于反向偏置状态，从而以实现改善第一发光 器件D1的老化进程。
步骤S3、进入第一数据写入阶段T3，控制第二薄膜晶体管M2开启，以及控制第一薄膜晶体管M1、第五薄膜晶体管M5和第六薄膜晶体管M6关闭，以及控制第三薄膜晶体管M3在预设子阶段T31开启，以及控制第三薄膜晶体管M3在预设子阶段T31之外关闭，以及控制数据信号Data、第一电源电压Vss1以及第二电源电压Vss2为高电位，以使第四节点A4电位为第二电源电压Vss2与第四薄膜晶体管M4阈值电压的绝对值的差值与数据信号Data之和。该阶段中，第二控制信号Ctr2处于低电位；第一控制信号Ctr1、第三控制信号Ctr3、第四控制信号Ctr4均处于高电位；扫描信号Scan在预设子阶段T31中处于低电位，而在第一数据写入阶段T3除预设子阶段T31之外的时长中处于高电位。如此，以使得数据信号Data可经第三薄膜晶体管M3写入第二节点A2，并由于电容C的耦合作用，还使得第四节点A4电位为第二电源电压Vss2与第四薄膜晶体管M4阈值电压的绝对值的差值与数据信号Data之和，用公式表示即为VG＝VS2-|VTH|+VDATA。
步骤S4、进入第一发光阶段T4，控制第六薄膜晶体管M6开启，以及控制第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3和第五薄膜晶体管M5关闭，以及控制第一电源电压Vss1为负电位，以及控制第二电源电压Vss2为高电位，以及控制数据信号Data为低电位，以使第一发光器件D1发光。该阶段中，第四控制信号Ctr4处于低电位，第一控制信号Ctr1、第二控制信号Ctr2、扫描信号Scan和第三控制信号Ctr3均处于高电位。如此，以使得第三节点A3电位可上拉至第二电源电压Vss2的高电位，且使得第四薄膜晶体管M4开启，以产生第一发光器件D1的流经电流，从而以实现驱动第一发光器件D1发光。此外，由第一发光器件D1流经电流的表达式可知，第一发光器件D1发光时的流经电流只与数据信号Data相关，而与第四薄膜晶体管M4的阈值电压、第一电源电压Vss1和第二电源电压Vss2无关，也即为不随第四薄膜晶体管M4的阈值电压、第一电源电压Vss1和第二电源电压Vss2的变化而变化，从而以消除第四薄膜晶体管M4的阈值电压缺陷和电源电压压降对第一发光器件D1流经电流的影响。
步骤S5、进入第二复位阶段T5，控制第一薄膜晶体管M1、第二薄膜晶体管M2、第三薄膜晶体管M3、第四薄膜晶体管M4、第五薄膜晶体管M5以及第六薄膜晶体管M6开启，以及控制数据信号Data、第一电源电压Vss1以及第二电源电压Vss2为低电位。该阶段中，扫描信号Scan、第一控制信号Ctr1、第二控制信号Ctr2、第三控制信号Ctr3、第四控制信号Ctr4、第一电源电压Vss1、第二电源电压Vss2和数据信号Data均处于低电位。如此，以使得像素驱动电路清空残留电荷，以将电容C的端电压和第四薄膜晶体管M4受控端的电位值再次复位至0准位。
步骤S6、进入第二采样阶段T6，控制第一薄膜晶体管M1、第三薄膜晶体管M3、第五薄膜晶体管M5开启，以及控制第二薄膜晶体管M2和第六薄膜晶体管M6关闭，以及控制数据信号Data为低电位，以及控制第一电源电压Vss1以及第二电源电压Vss2为高电位，以使第四节点A4电位为第一电源电压Vss1与第四薄膜晶体管M4阈值电压的绝对值之差。该阶段中，第一控制信号Ctr1、扫描信号Scan、第三控制信号Ctr3均处于低电位，第二控制信号Ctr2和第四控制信号Ctr4均处于高电位。如此，以第四薄膜晶体管M4的受控端电位，即第四节点A4电位可被充电至第一电源电压Vss1与第四薄膜晶体管M4阈值电压的绝对值之差，用公式表示即为VG＝VS1-|VTH|，并且此时第三节点A3的电位值小于第二电源电压Vss2的高电位，以使第二发光器件D2处于反向偏置状态，从而以实现改善第二发光器件D2的老化进程。
步骤S7、进入第二数据写入阶段T7，控制第五薄膜晶体管M5开启，以及控制第一薄膜晶体管M1、第二薄膜晶体管M2和第六薄膜晶体管M6关闭，以及控制第三薄膜晶体管M3在预设子阶段T71开启，以及控制第三薄膜晶体管M3在预设子阶段T71之外关闭，以及控制数据信号Data、第一电源电压Vss1以及第二电源电压Vss2为高电位，以使第四节点A4电位为第一电源电压Vss1与第四薄膜晶体管M4阈值电压的绝对值的差值与数据信 号Data之和。本阶段中，第三控制信号Ctr3处于低电位；第一控制信号Ctr1、第二控制信号Ctr2、第四控制信号Ctr4均处于高电位；扫描信号Scan在预设子阶段T71中处于低电位，在第一数据写入阶段T3除预设子阶段T71之外的时长中处于高电位。如此，以使得数据信号Data经第三薄膜晶体管M3写入第二节点A2，并由于电容C的耦合作用，还使得使第四节点A4电位为第一电源电压Vss1与第四薄膜晶体管M4阈值电压的绝对值的差值与数据信号Data之和，用公式表示即为VG＝VS1-|VTH|+VDATA。
步骤S8、进入第二发光阶段T8，控制第一薄膜晶体管M1开启，以及控制第二薄膜晶体管M2、第三薄膜晶体管M3、第五薄膜晶体管M5和第六薄膜晶体管M6关闭，以及控制第一电源电压Vss1为高电位，以及控制第二电源电压Vss2为负电位，以及控制数据信号Data为低电位，以使第二发光器件D2发光。本阶段中，第一控制信号Ctr1处于低电位，第二控制信号Ctr2、第四控制信号Ctr4、第三控制信号Ctr3和扫描信号Scan均处于高电位。如此，以使得第一节点A1电位可上拉至为第一电源电压Vss1的高电位，且第四薄膜晶体管M4开启，以产生第二发光器件D2的流经电流，从而以实现驱动第二发光器件D2发光。此外，由第二发光器件D2的电流表达式可知，第二发光器件D2发光时的流经电流同样只与数据信号Data相关，而与第四薄膜晶体管M4的阈值电压、第一电源电压Vss1和第二电源电压Vss2无关，也即为不随第四薄膜晶体管M4的阈值电压、第一电源电压Vss1和第二电源电压Vss2的变化而变化，从而以消除第四薄膜晶体管M4的阈值电压缺陷和电源电压压降对第二发光器件D2流经电流的影响。
实施例三：
本申请还提出一种显示面板，该显示面板包括像素阵列以及像素驱动电路，该像素驱动电路的具体结构参照上述实施例一，由于本像素驱动方法采用了上述实施例一的全部技术方案，因此至少具有上述实施例一的技术方案所带来的所有有益效果，在此不再一一赘述。
其中，像素阵列包括位于同列上相邻的第一发光器件D1和第二发光器件D2。像素驱动电路与第一发光器件D1和第二发光器件D2连接，用于根据接入的扫描信号Scan、第一控制信号Ctr1、第二控制信号Ctr2、第三控制信号Ctr3、第四控制信号Ctr4、第一电源电压Vss1、第二电源电压Vss2和数据信号Data所处电位，先后驱动第一发光器件D1和第二发光器件D2发光。
以上所述仅为本申请的一些实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (15)

  1. 一种像素驱动电路，应用于显示面板，所述显示面板设有像素阵列，所述像素阵列包括位于同列上相邻的第一发光器件(D1)和第二发光器件(D2)，其中，所述第一发光器件(D1)的阳极连接于第一节点(A1)，阴极接入第一电源电压；第二发光器件(D2)的阳极连接于第三节点(A3)，阴极接入第二电源电压；
    所述像素驱动电路包括：第一薄膜晶体管(M1)、第二薄膜晶体管(M2)、第三薄膜晶体管(M3)、第四薄膜晶体管(M4)、第五薄膜晶体管(M5)、第六薄膜晶体管(M6)和电容(C)；
    所述第一薄膜晶体管(M1)的受控端接入第一控制信号(Ctr1)，第一端接入第一电源电压，第二端连接于第一节点(A1)；
    所述第二薄膜晶体管(M2)的受控端接入第二控制信号(Ctr2)，第一端连接于第四节点(A4)，第二端连接于所述第一薄膜晶体管(M1)的第二端；
    所述第二薄膜晶体管(M2)的受控端接入扫描信号(Scan)，第一端连接于数据信号(Data)，第二端连接于第二节点(A2)；
    所述第四薄膜晶体管(M4)的受控端连接于第四节点(A4)，第一端连接于第一节点(A1)，第二端连接于第三节点(A3)；
    所述第五薄膜晶体管(M5)的受控端接入第三控制信号(Ctr3)，第一端连接于第四节点(A4)，第二端连接于第三节点(A3)；
    所述第六薄膜晶体管(M6)的受控端接入第四控制信号(Ctr4)，第一端连接于所述第五薄膜晶体管(M5)的第二端，第二端接入第二电源电压；
    所述电容(C)的一端连接于第二节点(A2)，另一端连接于第四节点(A4)。
  2. 如权利要求1所述的像素驱动电路，其中：
    所述第一薄膜晶体管(M1)和所述第二薄膜晶体管(M2)用于控制所述第一发光器件(D1)发光以及所述第一节点(A1)的电荷清空；
    所述第三薄膜晶体管(M3)为数据写入薄膜晶体管；
    所述第四薄膜晶体管(M4)同时作为所述第一发光器件(D1)和所述第二发光器件(D2)的驱动薄膜晶体管；
    所述第五薄膜晶体管(M5)和所述第六薄膜晶体管(M6)用于控制所述第二发光器件(D2)发光以及所述第三节点(A3)的电荷清空；以及
    所述电容(C)为存储电容。
  3. 如权利要求1所述的像素驱动电路，其中，所述第一薄膜晶体管(M1)、所述第二薄膜晶体管(M2)、所述第三薄膜晶体管(M3)、所述第四薄膜晶体管(M4)、所述第五薄膜晶体管(M5)和所述第六薄膜晶体管(M6)的受控端均为栅极。
  4. 如权利要求1所述的像素驱动电路，其中，所述第一控制信号(Ctr1)、所述第二控制信号(Ctr2)、所述第三控制信号(Ctr3)、所述第四控制信号(Ctr4)、所述扫描信号(Scan)和所述数据信号(Data)均由外部时序控制器输出得到，第一电源电压(Vss1)和所述第二电源电压(Vss2)由外部公共电压产生电路输出得到。
  5. 如权利要求1所述的像素驱动电路，其中，所述第一控制信号(Ctr1)、所述第二控制信号(Ctr2)、所述第三控制信号(Ctr3)、所述第四控制信号(Ctr4)、所述第一电源电压、所述第二电源电压、所述扫描信号(Scan)以及所述数据信号(Data)相组合先后对应于第一复位阶段(T1)、第一采样阶段(T2)、第一数据写入阶段(T3)、第一发光阶段(T4)、第二复位阶段(T5)、第二采样阶段(T6)、第二数据写入阶段(T7)、第二发光阶段(T8)；
    其中，在所述第一发光阶段(T4)，所述第一发光器件(D1)发光；在所述第二发光阶段(T8)，所述第二发光器件(D2)发光。
  6. 如权利要求5所述的像素驱动电路，其中，在所述第一复位阶段(T1)和所述第 二复位阶段(T5)，所述第一薄膜晶体管(M1)、所述第二薄膜晶体管(M2)、所述第三薄膜晶体管(M3)、所述第四薄膜晶体管(M4)、所述第五薄膜晶体管(M5)以及所述第六薄膜晶体管(M6)开启；
    所述数据信号(Data)、所述第一电源电压以及所述第二电源电压为低电位。
  7. 如权利要求5所述的像素驱动电路，其中，在所述第一采样阶段(T2)，所述第二薄膜晶体管(M2)和所述第六薄膜晶体管(M6)开启，所述第一薄膜晶体管(M1)、所述第三薄膜晶体管(M3)、所述第五薄膜晶体管(M5)关闭，所述数据信号(Data)为低电位，所述第一电源电压以及所述第二电源电压为高电位，所述第四节点(A4)电位为第二电源电压与所述第四薄膜晶体管(M4)阈值电压的绝对值之差；
    在所述第二采样阶段(T6)，所述第一薄膜晶体管(M1)、所述第三薄膜晶体管(M3)、所述第五薄膜晶体管(M5)开启，所述第二薄膜晶体管(M2)和所述第六薄膜晶体管(M6)关闭，所述数据信号(Data)为低电位，所述第一电源电压以及所述第二电源电压为高电位，所述第四节点(A4)电位为第一电源电压与所述第四薄膜晶体管(M4)阈值电压的绝对值之差。
  8. 如权利要求7所述的像素驱动电路，其中，在所述第一采样阶段(T2)，所述第一发光器件(D1)处于反向偏置状态；
    在所述第二采样阶段(T6)，所述第二发光器件(D2)处于反向偏置状态。
  9. 如权利要求5所述的像素驱动电路，其中，在所述第一数据写入阶段(T3)，所述第二薄膜晶体管(M2)开启，所述第一薄膜晶体管(M1)、所述第五薄膜晶体管(M5)和所述第六薄膜晶体管(M6)关闭，所述第三薄膜晶体管(M3)在预设子阶段开启，所述第三薄膜晶体管(M3)在预设子阶段之外关闭，所述数据信号(Data)、所述第一电源电压以及所述第二电源电压为高电位，所述第四节点(A4)电位为第二电源电压与所述第四薄膜晶体管(M4)阈值电压的绝对值的差值与数据信号(Data)之和；
    在所述第二数据写入阶段(T7)，所述第五薄膜晶体管(M5)开启，所述第一薄膜晶体管(M1)、所述第二薄膜晶体管(M2)和所述第六薄膜晶体管(M6)关闭，所述第三薄膜晶体管(M3)在预设子阶段开启，所述第三薄膜晶体管(M3)在预设子阶段之外关闭，所述数据信号(Data)、所述第一电源电压以及所述第二电源电压为高电位，所述第四节点(A4)电位为第一电源电压与所述第四薄膜晶体管(M4)阈值电压的绝对值的差值与数据信号(Data)之和。
  10. 如权利要求5所述的像素驱动电路，其中，在所述第一发光阶段(T4)，所述第六薄膜晶体管(M6)开启，所述第一薄膜晶体管(M1)、所述第二薄膜晶体管(M2)、所述第三薄膜晶体管(M3)和所述第五薄膜晶体管(M5)关闭，所述第一电源电压为负电位，所述第二电源电压为高电位，所述数据信号(Data)为低电位；
    在所述第二发光阶段(T8)，所述第一薄膜晶体管(M1)开启，所述第二薄膜晶体管(M2)、所述第三薄膜晶体管(M3)、所述第五薄膜晶体管(M5)和所述第六薄膜晶体管(M6)关闭，所述第一电源电压为高电位，所述第二电源电压为负电位，所述数据信号(Data)为低电位。
  11. 如权利要求10所述的像素驱动电路，其中，所述第一发光器件(D1)和所述第二发光器件(D2)在发光时的流经电流，不随所述第四薄膜晶体管(M4)的阈值电压的变化而变化。
  12. 一种像素驱动方法，其中，应用于一种像素驱动电路，其中所述像素驱动电路应用于显示面板，所述显示面板设有像素阵列，所述像素阵列包括位于同列上相邻的第一发光器件和第二发光器件，其中，所述第一发光器件的阳极连接于第一节点，阴极接入第一电源电压；第二发光器件的阳极连接于第三节点，阴极接入第二电源电压；
    所述像素驱动电路包括：第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管和电容；
    所述第一薄膜晶体管的受控端接入第一控制信号，第一端接入第一电源电压，第二端连接于第一节点；
    所述第二薄膜晶体管的受控端接入第二控制信号，第一端连接于第四节点，第二端连接于所述第一薄膜晶体管的第二端；
    所述第二薄膜晶体管的受控端接入扫描信号，第一端连接于数据信号，第二端连接于第二节点；
    所述第四薄膜晶体管的受控端连接于第四节点，第一端连接于第一节点，第二端连接于第三节点；
    所述第五薄膜晶体管的受控端接入第三控制信号，第一端连接于第四节点，第二端连接于第三节点；
    所述第六薄膜晶体管的受控端接入第四控制信号，第一端连接于所述第五薄膜晶体管的第二端，第二端接入第二电源电压；
    所述电容的一端连接于第二节点，另一端连接于第四节点；
    所述像素驱动方法包括：
    (S1)，进入第一复位阶段，控制所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管开启，以及控制所述数据信号、所述第一电源电压以及所述第二电源电压为低电位；
    (S2)，进入第一采样阶段，控制所述第二薄膜晶体管和所述第六薄膜晶体管开启，以及控制所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管关闭，以及控制所述数据信号为低电位，所述第一电源电压以及所述第二电源电压为高电位，以使所述第四节点电位为第二电源电压与所述第四薄膜晶体管阈值电压的绝对值之差；
    (S3)，进入第一数据写入阶段，控制所述第二薄膜晶体管开启，以及控制所述第一薄膜晶体管、所述第五薄膜晶体管和所述第六薄膜晶体管关闭，以及控制所述第三薄膜晶体管在预设子阶段开启，以及控制所述第三薄膜晶体管在预设子阶段之外关闭，以及控制所述数据信号、所述第一电源电压以及所述第二电源电压为高电位，以使所述第四节点电位为第二电源电压与所述第四薄膜晶体管阈值电压的绝对值的差值与数据信号之和；
    (S4)，进入第一发光阶段，控制所述第六薄膜晶体管开启，以及控制所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管和所述第五薄膜晶体管关闭，以及控制所述第一电源电压为负电位，以及控制所述第二电源电压为高电位，以及控制所述数据信号为低电位，以使所述第一发光器件发光；
    (S5)，进入第二复位阶段，控制所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管、所述第四薄膜晶体管、所述第五薄膜晶体管以及所述第六薄膜晶体管开启，以及控制所述数据信号、所述第一电源电压以及所述第二电源电压为低电位；
    (S6)，进入第二采样阶段，控制所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管开启，以及控制所述第二薄膜晶体管和所述第六薄膜晶体管关闭，以及控制所述数据信号为低电位，以及控制所述第一电源电压以及所述第二电源电压为高电位，以使所述第四节点电位为第一电源电压与所述第四薄膜晶体管阈值电压的绝对值之差；
    (S7)，进入第二数据写入阶段，控制所述第五薄膜晶体管开启，以及控制所述第一薄膜晶体管、所述第二薄膜晶体管和所述第六薄膜晶体管关闭，以及控制所述第三薄膜晶体管在预设子阶段开启，以及控制所述第三薄膜晶体管在预设子阶段之外关闭，以及控制所述数据信号、所述第一电源电压以及所述第二电源电压为高电位，以使所述第四节点电位为第一电源电压与所述第四薄膜晶体管阈值电压的绝对值的差值与数据信号之和；以及
    (S8)，进入第二发光阶段，控制所述第一薄膜晶体管开启，以及控制所述第二薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管和所述第六薄膜晶体管关闭，以及控制所述第一电源电压为高电位，以及控制所述第二电源电压为负电位，以及控制所述数据信号为低电位，以使所述第二发光器件发光。
  13. 如权利要求12所述的像素驱动方法，其中，所述(S2)，进入所述第一采样阶段，控制所述第二薄膜晶体管和所述第六薄膜晶体管开启，以及控制所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管关闭，以及控制所述数据信号为低电位，所述第一电源电压以及所述第二电源电压为高电位，以使所述第四节点电位为第二电源电压与所述第四薄膜晶体管阈值电压的绝对值之差，包括：
    所述第二控制信号和第四控制信号均处于低电位，所述第一控制信号、所述扫描信号、所述第三控制信号均处于高电位，所述第一节点的电位值小于所述第一电源电压的高电位。
  14. 如权利要求12所述的像素驱动方法，其中，所述(S4)，进入所述第一发光阶段，控制所述第六薄膜晶体管开启，以及控制所述第一薄膜晶体管、所述第二薄膜晶体管、所述第三薄膜晶体管和所述第五薄膜晶体管关闭，以及控制所述第一电源电压为负电位，以及控制所述第二电源电压为高电位，以及控制所述数据信号为低电位，以使所述第一发光器件发光，包括：
    所述第四控制信号处于低电位，所述第一控制信号、所述第二控制信号、所述扫描信号和所述第三控制信号均处于高电位。
  15. 一种显示面板，其中，所述显示面板包括：
    像素阵列，所述像素阵列包括位于同列上相邻的第一发光器件(D1)和第二发光器件(D2)；以及
    像素驱动电路，所述第一发光器件(D1)的阳极连接于第一节点(A1)，阴极接入第一电源电压；第二发光器件(D2)的阳极连接于第三节点(A3)，阴极接入第二电源电压；
    所述像素驱动电路包括：第一薄膜晶体管(M1)、第二薄膜晶体管(M2)、第三薄膜晶体管(M3)、第四薄膜晶体管(M4)、第五薄膜晶体管(M5)、第六薄膜晶体管(M6)和电容(C)；
    所述第一薄膜晶体管(M1)的受控端接入第一控制信号(Ctr1)，第一端接入第一电源电压，第二端连接于第一节点(A1)；
    所述第二薄膜晶体管(M2)的受控端接入第二控制信号(Ctr2)，第一端连接于第四节点(A4)，第二端连接于所述第一薄膜晶体管(M1)的第二端；
    所述第二薄膜晶体管(M2)的受控端接入扫描信号(Scan)，第一端连接于数据信号(Data)，第二端连接于第二节点(A2)；
    所述第四薄膜晶体管(M4)的受控端连接于第四节点(A4)，第一端连接于第一节点(A1)，第二端连接于第三节点(A3)；
    所述第五薄膜晶体管(M5)的受控端接入第三控制信号(Ctr3)，第一端连接于第四节点(A4)，第二端连接于第三节点(A3)；
    所述第六薄膜晶体管(M6)的受控端接入第四控制信号(Ctr4)，第一端连接于所述第五薄膜晶体管(M5)的第二端，第二端接入第二电源电压；
    所述电容(C)的一端连接于第二节点(A2)，另一端连接于第四节点(A4)；
    所述像素驱动电路与所述第一发光器件(D1)和所述第二发光器件(D2)连接。
PCT/CN2023/094619 2022-11-02 2023-05-16 像素驱动电路、像素驱动方法和显示面板 WO2024093195A1 (zh)

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