WO2023226408A1 - 像素电路、像素驱动方法及显示装置 - Google Patents

像素电路、像素驱动方法及显示装置 Download PDF

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Publication number
WO2023226408A1
WO2023226408A1 PCT/CN2022/140951 CN2022140951W WO2023226408A1 WO 2023226408 A1 WO2023226408 A1 WO 2023226408A1 CN 2022140951 W CN2022140951 W CN 2022140951W WO 2023226408 A1 WO2023226408 A1 WO 2023226408A1
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Prior art keywords
transistor
signal
scanning signal
switching element
terminal
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PCT/CN2022/140951
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English (en)
French (fr)
Inventor
周仁杰
袁海江
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惠科股份有限公司
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Priority to EP22930148.6A priority Critical patent/EP4303861A1/en
Publication of WO2023226408A1 publication Critical patent/WO2023226408A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • the present application belongs to the field of display technology, and specifically relates to a pixel circuit, a pixel driving method and a display device.
  • the pixel circuits are affected by process and other reasons. There are differences in the characteristics of the driving transistors that drive the light-emitting elements to emit light. The threshold voltage of the driving transistors drifts, resulting in uneven display in the OLED display.
  • the present disclosure provides a pixel circuit, a pixel circuit driving method and a display device, which can compensate the threshold voltage of a driving transistor, thereby improving display uniformity.
  • a first aspect of the present disclosure discloses a pixel circuit, including a light-emitting element, a capacitor structure, a driving transistor, a first switching element, a second switching element, a third switching element and a fourth switching element,
  • the first switching element is configured to respond to a first scan signal to connect a data line for providing a data signal to a first end of the capacitive structure
  • the second switching element is used to respond to the second scan signal to connect the first end of the driving transistor to the control end of the driving transistor and the second end of the capacitor structure respectively;
  • the third switching element is used to respond to a third scan signal to connect the second end of the driving transistor to the first end of the light-emitting element;
  • the fourth switching element is used to respond to the fourth scan signal to connect the first power signal terminal to the first terminal of the driving transistor;
  • the second end of the light-emitting element is connected to the second end of the driving transistor, and the first end of the light-emitting element is connected to the ground end.
  • a second aspect of the present disclosure discloses a pixel driving method for driving a pixel circuit.
  • the pixel driving method includes:
  • the first, second, and fourth scanning signals are used to turn on the first switching element, the second switching element, and the fourth switching element, and at the same time, the third scanning signal is used to turn off The third switching element;
  • the first, second, and third scanning signals are used to turn on the first switching element, the second switching element, and the third switching element, and at the same time, the fourth scanning signal is used to turn off the fourth switching element;
  • the first scanning signal is used to turn on the first switching element, and at the same time, the second scanning signal, the third scanning signal and the fourth scanning signal are used to close the second switching element and the third switch. component and the fourth switching component;
  • the fourth scanning signal is used to turn on the fourth switching element, and at the same time, the first scanning signal, the second scanning signal, and the third scanning signal are used to close the first switching element and the second switch. component and the third switching component.
  • a third aspect of the present disclosure also discloses a display device, including a pixel unit and the pixel circuit, and the pixel circuit corresponds to the pixel unit one-to-one.
  • the pixel circuit, pixel circuit driving method and display device of the present disclosure can be used to realize pixel compensation.
  • the pixel circuit may include a light-emitting element, a capacitor structure, a driving transistor and first to fourth switching elements.
  • the scanning signal is used to control the opening or closing of the four switching elements and the driving transistor.
  • the pixel circuit may be in the second stage and the third stage. Using the form of autonomous discharge, a voltage containing the threshold voltage is generated at the gate of the driving transistor, thereby offsetting the threshold voltage of the driving transistor itself during the light-emitting phase, thereby compensating for the threshold voltage drift of the driving transistor, thereby improving display uniformity.
  • FIG. 1 shows a schematic diagram of module connections of the pixel circuit according to Embodiment 1 of the present disclosure.
  • FIG. 2 shows a schematic diagram of the pixel circuit according to Embodiment 1 of the present disclosure.
  • FIG. 3 shows a schematic diagram of a pixel circuit with a fifth switching element according to Embodiment 1 of the present disclosure.
  • FIG. 4 shows a schematic diagram of the pixel circuit according to Embodiment 1 of the present disclosure.
  • FIG. 5 shows a driving timing diagram of the pixel circuit according to Embodiment 2 of the present disclosure.
  • FIG. 6 shows a flow chart of the pixel driving method according to Embodiment 2 of the present disclosure.
  • Figure 7 shows the equivalent circuit diagram of the first stage in Figure 3.
  • Figure 8 shows the equivalent circuit diagram of the second stage in Figure 3.
  • Figure 9 shows the equivalent circuit diagram of the third stage in Figure 3.
  • FIG. 10 shows the equivalent circuit diagram of the fourth stage in FIG. 3 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • Embodiments of the present disclosure provide a pixel circuit for implementing pixel compensation.
  • the pixel circuit may include a light-emitting element L, a capacitor structure C, a driving transistor DT, a first switching element 11 , a second switching element 12 , a third switching element 13 , and a fourth switching element 14 .
  • both the light-emitting element L and the capacitor structure C have a first terminal and a second terminal, and the driving transistor DT not only has the first terminal and the second terminal, it also has a control terminal; wherein, the first to fourth switching elements
  • the relationship between 14, the light-emitting element L, the capacitor structure C, and the driving transistor DT is as follows.
  • the first switch unit may be configured to respond to the first scan signal Sn to connect the data line 21 for providing the data signal Data to the first end of the capacitor structure C.
  • the second switch element 12 can be used to respond to the second scan signal Sn+1 to connect the first terminal of the driving transistor DT to the control terminal of the driving transistor DT and the second terminal of the capacitor structure C respectively.
  • the third switching element 13 can be used to respond to the third scan signal Sn+2 to connect the second terminal of the driving transistor DT to the first terminal of the light-emitting element L, and the second terminal of the light-emitting element L is connected to the third terminal of the driving transistor DT. Two ends are connected, and the first end of the light-emitting element L is connected to the ground end.
  • the common ground voltage provided by the ground terminal can be 0 or other reference voltage.
  • the fourth switching element 14 can be used to respond to the fourth scanning signal Sn+3 to connect the first power signal terminal to the first terminal of the driving transistor DT.
  • four switching elements and the driving transistor DT are controlled to turn on or off through four scanning signals, thereby realizing charging, discharging, compensation and lighting of the circuit; during the compensation phase, the pixel circuit can switch on or off the driving transistor DT.
  • the gate generates a voltage that includes the DT threshold voltage of the driving transistor, thereby eliminating the influence of the DT threshold voltage of the driving transistor during the light-emitting phase, thus improving display uniformity.
  • the pixel circuit further includes a fifth switching element.
  • the fifth switching element can be used to respond to the fifth scanning signal Sn+4 to connect the second end of the driving transistor DT and the second end of the light-emitting element L.
  • By arranging the fifth switching element it can effectively avoid causing the light-emitting element L to emit light when the circuit is charging in the first, second and third stages. This ensures that the light-emitting element L only emits light during the light-emitting stage to avoid flickering. Phenomenon.
  • the first scanning signal Sn is provided by the Nth row scanning line
  • the second scanning signal Sn+1 is provided by the N+1th row scanning signal line
  • the third scanning signal Sn+2 is provided by the N+2th row scanning signal line.
  • the fourth scanning signal Sn+3 is provided by the N+3th row scanning signal line
  • the fifth scanning signal Sn+4 is provided by the N+4th row scanning signal line, wherein the scanning direction of this embodiment is from the 1st to the last line, that is to say, the first scan signal Sn precedes the second scan signal Sn+1, the second scan signal Sn+1 precedes the third scan signal Sn+2, and the third scan line precedes the fourth scan signal.
  • the fourth scanning signal Sn+3 precedes the fifth scanning signal Sn+4.
  • the circuit structure can be simplified. Designed to reduce the number of control signal wiring, thereby increasing the pixel aperture ratio.
  • N is a positive integer greater than or equal to 1.
  • the first switching element 11 includes a first transistor T1
  • the second switching element 12 includes a second transistor T2
  • the third switching element 13 includes a third transistor T3
  • the fourth switching element 14 The fourth transistor T4 is included
  • the fifth switching element includes a fifth transistor T5.
  • first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are the same as the driving transistor DT, and all have a first terminal, a second terminal and a control terminal.
  • the control terminal of each transistor corresponds to the gate of the transistor, one of the first terminal and the second terminal corresponds to the source of the transistor, and the other corresponds to the drain of the transistor.
  • the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 in the embodiment of the present disclosure may all be oxide thin film transistors, that is, each transistor has
  • the material of the source layer can be an oxide.
  • metal oxide materials such as IGZO (Indium Gallium Zinc Oxide) can be used.
  • IGZO thin film transistors Compared with a-Si (amorphous silicon) thin film transistors, IGZO thin film transistors have better performance than a-Si (amorphous silicon) thin film transistors. It has three main advantages, namely high precision, low power consumption and high touch performance. Its main supply targets are electronic display products such as tablet computers and ultrabooks.
  • IGZO thin film transistors do not require laser irradiation to crystallize the semiconductor layer. Therefore, the size of the glass substrate can be easily increased. Because the IGZO thin film transistor process is different from the a-Si thin film transistor process. The process similarity is extremely high, coupled with IZGO's high electron mobility, it can be applied and produced in LCD (Liquid Crystal Display, liquid crystal display device) and OLED display devices.
  • LCD Liquid Crystal Display, liquid crystal display device
  • OLED display devices Liquid Crystal Display, liquid crystal display device
  • each transistor can be a bottom-gate type, that is, the gate electrode of the transistor is located below the active layer (close to the side of the glass substrate), so that the product can be appropriately thinned.
  • each transistor can also be a bottom-gate type.
  • Top grid type depending on the specific situation.
  • each transistor may be an enhancement mode or a depletion mode transistor, which is not specifically limited in the embodiments of the present disclosure.
  • all transistors in the pixel circuit may be N-type thin film transistors, that is, the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may all be N-type thin film transistors.
  • the driving voltage of each transistor corresponds to a high-level voltage.
  • the first power signal Vdd provided by the first power signal terminal can be a DC high-level signal.
  • each transistor in the pixel circuit is not limited to the aforementioned N-type thin film transistor, and may also be a P-type thin film transistor.
  • the driving voltage of each transistor can be a corresponding low-level voltage.
  • the first power supply signal Vdd can be a DC low-level signal.
  • the light-emitting element L can be a current-driven light-emitting element L, which is controlled to emit light by the current flowing through the driving transistor DT.
  • the light-emitting element L can be an organic light-emitting diode (OLED). This pixel circuit can be applied to OLED display. device.
  • the first terminal of the light-emitting element L is the cathode of the OLED, and the second terminal of the light-emitting element L is the anode of the OLED.
  • the first terminal of the light-emitting element L is the anode of the OLED, and the second terminal of the light-emitting element L is the cathode of the OLED.
  • each transistor is an N-type thin film transistor
  • the first power signal Vdd is a DC high level signal
  • the first end of the light-emitting element L is the cathode of the OLED
  • the second end of the light-emitting element L is the anode of the OLED.
  • the control end of the first transistor T1 is connected to the first scan signal line 16 for providing the first scan signal Sn, the first end of the first transistor T1 is connected to the data line 21, and the second end of the first transistor T1 is connected to the capacitor structure C. First end connection.
  • the control terminal of the second transistor T2 is connected to the second scanning signal line 17 for providing the second scanning signal Sn+1, the first terminal of the second transistor T2 is connected to the first node A, and the second terminal of the second transistor T2 is connected to the second scanning signal line 17 .
  • the control terminal of the third transistor T3 is connected to the third scanning signal line 18 for providing the third scanning signal Sn+2.
  • the first terminal of the third transistor T3 is connected to the second terminal of the driving transistor DT.
  • the second terminal of the third transistor T3 The terminal is connected to the first terminal of the light-emitting element L.
  • the control terminal of the fourth transistor T4 is connected to the fourth scanning signal line 19 for providing the fourth scanning signal Sn+3, the first terminal of the fourth transistor T4 is connected to the first power signal terminal, and the first power signal terminal provides the first power supply.
  • Signal Vdd the second terminal of the fourth transistor T4 is connected to the second node B.
  • the control terminal of the fifth transistor T5 is connected to the fifth scanning signal line 20 for providing the fifth scanning signal Sn+4, the first terminal of the fifth transistor T5 is connected to the second terminal of the driving transistor DT, and the second terminal of the fifth transistor T5 The terminal is connected to the second terminal of the light-emitting element L.
  • the control terminal of the driving transistor DT and the second terminal of the capacitor structure C are both connected to the first node A, and the first terminal of the driving transistor DT is connected to the second node B.
  • the first end of the light-emitting element L is connected to the ground end; specifically, the cathode of the organic light-emitting diode is connected to the ground end, and the anode of the organic light-emitting diode is connected to the second end of the fifth transistor T5.
  • the pixel circuit of the embodiment of the present disclosure also includes a voltage comparator U1, an AND gate circuit U2, and a current limiting resistor R.
  • the function of the voltage comparator U1 is to compare the magnitude of the two input voltages and output a high level or a low level according to the comparison result;
  • the AND gate circuit U2 is a basic logic gate circuit that performs AND calculations and has multiple inputs. terminal and an output terminal. When all inputs are high level at the same time, the output is high level, otherwise the output is low level.
  • the voltage comparator U1 and the AND gate circuit U2 both have a first input terminal, a second input terminal and an output terminal, and the current limiting resistor has a first terminal and a second terminal.
  • the first input terminal of the voltage comparator U1 is connected to the reference signal terminal for providing the reference signal Vref
  • the second input terminal of the voltage comparator U1 is connected to the first terminal of the current limiting resistor
  • the output terminal of the voltage comparator U1 is connected to
  • the first input terminal of the AND gate circuit U2 and the second terminal of the current limiting resistor are connected to the second terminal of the driving transistor DT
  • the second input terminal of the AND gate circuit U2 is connected to the fourth scanning signal line 19 and the output of the AND gate circuit U2 terminal is connected to the control terminal of the fourth transistor T4.
  • the first input terminal of the voltage comparator U1 is the non-inverting terminal of the voltage comparator U1
  • the second input terminal of the voltage comparator U1 is the inverse terminal of the voltage comparator U1.
  • the voltage comparison Device U1 outputs high level.
  • the voltage at the second input terminal increases.
  • the output terminal of the voltage comparator U1 outputs a low level.
  • the fourth scanning signal Sn+3 is a high level or Low level
  • the fourth transistor T4 is always turned off, and the circuit is disconnected and there is no current, thereby protecting the circuit.
  • the pixel circuit of the embodiment of the present disclosure adopts a 5T1C structure to realize the charging, discharging, compensation and lighting of the circuit in the first to fourth stages, so that a voltage that protects the threshold voltage can be generated at the gate of the driving transistor DT before lighting. , thereby compensating the threshold voltage of the driving transistor DT when the light-emitting element L emits light in the fourth stage, avoiding the occurrence of threshold voltage drift, thereby improving display uniformity.
  • Embodiment 2 of the present disclosure also provides a pixel driving method.
  • the pixel driving method may include:
  • Step S100 in the first stage, the first switching element 11, the second switching element 12 and the fourth switching element 14 are turned on using the first scanning signal Sn, the second scanning signal Sn+1 and the fourth scanning signal Sn+3. , using the third scanning signal Sn+2 and the fifth scanning signal Sn+4 to turn off the third switching element 13 and the fifth switching element;
  • Step S200 in the second stage, use the first scanning signal Sn, the second scanning signal Sn+1, and the third scanning signal Sn+2 to turn on the first switching element 11, the second switching element 12, and the third switching element 13.
  • Step S200 using the fourth scanning signal Sn+3 and the fifth scanning signal Sn+4 to turn off the fourth switching element 14 and the fifth scanning signal Sn+4;
  • Step S300 in the third stage, the first scanning signal Sn is used to turn on the first switching element 11, and at the same time, the second scanning signal Sn+1, the third scanning signal Sn+2, the fourth scanning signal Sn+3 and the fifth scanning signal are used to turn on the first switching element 11.
  • the scanning signal Sn+4 turns off the second switching element 12, the third switching element 13, the fourth switching element 14 and the fifth switching element;
  • Step S400 in the fourth stage, use the fourth scanning signal Sn+3 and the fifth scanning signal Sn+4 to turn on the fourth switching element 14 and the fifth switching element, and at the same time, use the first scanning signal Sn and the second scanning signal Sn +1.
  • the third scanning signal Sn+2 turns off the first switching element 11, the second switching element 12 and the third switching element 13.
  • the pixel driving method corresponding to the pixel circuit in FIG. 2 will be described in detail below in conjunction with the operation timing diagram of the pixel circuit shown in FIG. 5 .
  • the operation timing diagram of the pixel circuit shown in FIG. 5 shows the first scanning signal Sn, the second scanning signal Sn+1, the third scanning signal Sn+2, the fourth scanning signal Sn+3, and the fifth scanning signal Sn+. 4 and the level states of the data signal Data in the four stages.
  • the capacitor structure is charged.
  • the first scanning signal Sn, the second scanning signal Sn+1 and the fourth scanning signal Sn+3 are high level
  • the fifth scanning signal Sn+4 and the data signal Data are low level, so that the first transistor T1, the second transistor T2 and the fourth transistor T4 are in an open state, and the third transistor T3 and the fourth transistor T4 are turned on.
  • Five transistors T5 are in a closed state.
  • the data signal Data inputs a low level to the first end of the capacitor structure C, and the first power signal Vdd is applied to the first node A through the fourth transistor T4 and the second transistor T2 to charge the capacitor structure C, that is, The first node A writes the first power signal.
  • VA Vdd
  • VA is the voltage at the first node A.
  • the circuit in the second stage, the circuit is discharged.
  • the first scanning signal Sn, the second scanning signal Sn+1 and the third scanning signal Sn+2 are high level, and the fourth scanning signal Sn+3 and the fifth scanning signal Sn+2 are at high level.
  • the scanning signal Sn+4 and the data signal Data are at a low level, so that the first transistor T1, the second transistor T2, and the third transistor T3 are in an open state, and the fourth transistor T4 and the fifth transistor T5 are in a closed state.
  • the first scan signal Sn and the data signal Data are at high level, and the second scan signal Sn+1 to the fifth scan signal Sn+4 are all at low level, so that the first transistor T1 is in an open state, and the second transistor T2 to the fifth transistor T5 are all in a closed state.
  • the data signal Data charges the capacitor structure C through the first transistor T1, and the capacitor structure C charges VData.
  • the fourth scanning signal Sn+3 and the fifth scanning signal Sn+4 are high level
  • the first scanning signal Sn to the third scanning signal Sn+2 are low level
  • the data signal Data It can be either a high level or a low level, so that the fourth transistor T4 and the fifth transistor T5 and the driving transistor DT are in an open state, and the first to third transistors T1 to T3 are all in an off state, so that the light-emitting element L emits light.
  • the voltage VA of the first node A VData + Vth, that is, the gate voltage of the driving transistor DT is equal to the voltage of the first node A, and already contains Vth, the threshold voltage Vth of the driving transistor DT is changed. compensation, the drift of the threshold voltage of the driving transistor DT will not affect the driving current of the light-emitting element L, ensuring the uniformity and stability of the driving current. Therefore, the brightness of the display device can be made more uniform, the generation of afterimages can be reduced, and the display effect can be enhanced. .
  • the third embodiment further provides a display device, which may be an OLED display device.
  • the display device may include a pixel unit and a pixel circuit in the embodiment, and the pixel circuit corresponds to the pixel unit one-to-one. Since this embodiment has the pixel circuit shown in Embodiment 1, the display device has all the beneficial effects of the pixel circuit in Embodiment 1, which will not be described again.
  • the display device of the embodiment of the present disclosure can be an AMOLED (Active-matrix organic light-emitting diode) display, which has many advantages such as thin body, power saving, bright colors, and high image quality. a wide range of applications. For example: OLED TVs, mobile phones, laptop screens, etc., are gradually taking a dominant position in the field of flat panel display.
  • AMOLED Active-matrix organic light-emitting diode
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • plurality means two or more than two, unless otherwise explicitly and specifically limited.
  • connection in this application, unless otherwise clearly stated and limited, the terms “assembly”, “connection” and other terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection. A connection can also be an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interaction between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

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Abstract

本公开涉及一种像素电路、像素电路驱动方法及显示装置。像素电路包括发光元件、电容结构、驱动晶体管及第一至第四开关元件，所述第一开关元件用于响应第一扫描信号，以将用于提供数据信号的数据线与所述电容结构的第一端连接；所述第二开关元件用于响应第二扫描信号，以将所述驱动晶体管的第一端分别与所述驱动晶体管的控制端及所述电容结构的第二端连接；所述第三开关元件用于响应第三扫描信号，以将所述驱动晶体管的第二端与所述发光元件的第一端连接；所述第四开关元件用于响应第四扫描信号，以将第一电源信号端与所述驱动晶体管的第一端连接。

Description

像素电路、像素驱动方法及显示装置
本申请要求于2022年5月26日提交中国专利局，申请号为CN 202210581578.5，申请名称为“像素电路、像素驱动方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于显示技术领域，具体涉及一种像素电路、像素驱动方法及显示装置。
背景技术
目前，在OLED显示器面板中，其像素电路受到工艺等原因影响，驱动发光元件发光的驱动晶体管的特性存在差异，驱动晶体管的阈值电压存在漂移，从而使得OLED显示器出现显示不均匀的情况。
申请内容
本公开提供一种像素电路、像素电路驱动方法及显示装置，能够对驱动晶体管的阈值电压进行补偿，从而提高显示均匀性。
本公开第一方面公开了一种像素电路，包括发光元件、电容结构、驱动晶体管、第一开关元件、第二开关元件、第三开关元件及第四开关元件，
所述第一开关元件用于响应第一扫描信号，以将用于提供数据信号的数据线与所述电容结构的第一端连接；
所述第二开关元件用于响应第二扫描信号，以将所述驱动晶体管的第一端分别与所述驱动晶体管的控制端及所述电容结构的第二端连接；
所述第三开关元件用于响应第三扫描信号，以将所述驱动晶体管的第二端与所述发光元件的第一端连接；
所述第四开关元件用于响应第四扫描信号，以将第一电源信号端与所述驱动晶体管的第一端连接；
所述发光元件的第二端与所述驱动晶体管的第二端连接，所述发光元件的第一端连接接地端。
本公开第二方面公开了一种像素驱动方法，用于驱动像素电路，所述像素驱动方法包括：
在第一阶段，利用所述第一扫描信号、第二扫描信号、第四扫描信号打开所述第一开关元件、第二开关元件和第四开关元件，同时，利用所述第三扫描信号关闭所述第三开关元件；
在第二阶段，利用所述第一扫描信号、第二扫描信号、第三扫描信号打开所述第一开关元件、第二开关元件、第三开关元件，同时，利用所述第四扫描信号关闭所述第四开关元件；
在第三阶段，利用所述第一扫描信号打开所述第一开关元件，同时，利用所述第二扫描信号、第三扫描信号及第四扫描信号关闭所述第二开关元件、第三开关元件及第四开关元件；
在第四阶段，利用所述第四扫描信号打开所述第四开关元件，同时，利用所述第一扫描信号、第二扫描信号、第三扫描信号关闭所述第一开关元件、第二开关元件及第三开关元件。
本公开第三方面还公开了一种显示装置，包括像素单元和所述的像素电路，所述像素电路与所述像素单元一一对应。
本公开方案的像素电路、像素电路驱动方法及显示装置，可用于实现像素补偿。该像素电路可包括发光元件、电容结构、驱动晶体管及第一至第四开关元件，通过扫描信号控制四个开关元件及驱动晶体管的打开或关闭，此像素电路可以在第二阶段和第三阶段利用自主放电的形式，在驱动晶体管的栅极生产包含阈值电压的电压，从而在发光阶段，以抵消驱动晶体管自身的阈值电压，从而对驱动晶体管的阈值电压漂移进行补偿，进而提高显示均匀性。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并于说明书一起用于解释本申请的原理。
为了使本公开的内容更容易被清楚的理解，下面根据本公开的具体实施例并结合附图，对本公开作进一步详细的说明，其中：
图1示出了本公开实施例一所述的像素电路的模块连接示意图。
图2示出了本公开实施例一所述的像素电路的示意图。
图3示出了本公开实施例一所述的具有第五开关元件的像素电路示意图。
图4示出了本公开实施例一所述的像素电路的示意图。
图5示出了本公开实施例二所述的像素电路的驱动时序图。
图6示出了本公开实施例二所述的像素驱动方法的流程图。
图7示出了图3中第一阶段的等效电路图。
图8示出了图3中第二阶段的等效电路图。
图9示出了图3中第三阶段的等效电路图。
图10示出了图3中第四阶段的等效电路图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本申请将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本申请的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本申请的技术方案而没有特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知方法、装置、实现或者操作以避免模糊本申请的各方面。
下面结合附图和具体实施例对本申请作进一步详述。在此需要说明的是，下面所描述的本申请各个实施例中所涉及的技术特征只要彼此之间未构成冲突就可以相互组合。下面通过参考附图描述的实施例是示例性的，旨在用于解释本申请，而不能理解为对本申请的限制。
实施例一
本公开实施例提供了一种像素电路，用于实现像素补偿。如图1及图2所示，像素电路可包括发光元件L、电容结构C、驱动晶体管DT、第一开关元件11、第二开关元件12、第三开关元件13、第四开关元件14。
应当理解的是，发光元件L和电容结构C均具有第一端和第二端，驱动晶体管DT除了具有第一端和第二端，其还具有控制端；其中，第一至第四开关元件14与发光元件L、电容结构C、驱动晶体管DT之间的关系如下所示。
第一开关单元，可用于响应第一扫描信号Sn，以将用于提供数据信号Data的数据线21与电容结构C的第一端连接。
第二开关元件12，可用于响应第二扫描信号Sn+1，以将驱动晶体管DT的第一端分别与驱动晶体管DT的控制端和电容结构C的第二端连接。
第三开关元件13，可用于响应第三扫描信号Sn+2，以将驱动晶体管DT的第二端与发光元件L的第一端连接，而发光元件L的第二端与驱动晶体管DT的第二端连接，发光元件L的第一端连接接地端。该接地端提供的公共接地端电压可以是0，也可是其它参考电压。
第四开关元件14，可用于响应第四扫描信号Sn+3，以将第一电源信号端与驱动晶体管DT的第一端连接。
在本公开实施例中，通过四个扫描信号控制四个开关元件及驱动晶体管DT打开或关闭，从而可实现电路的充电、放电、补偿及发光；此像素电路在补偿阶段可在驱动晶体管DT的栅极生产一个包含驱动晶体管DT阈值电压的电压，从而可以在发光阶段消除驱动晶体管DT阈值电压的影响，进而提高了显示均匀性。
进一步的，参见图3，像素电路还包括第五开关元件，第五开关元件可用于响应第五扫描信号Sn+4，以将驱动晶体管DT的第二端和发光元件L的第二端连接。通过设置第五开关元件，可以有效避免在电路在第一阶段、第二阶段和第三阶段进行充电的时候，使发光元件L发光，可保证发光元件L只在发光阶段进行发光，避免发生闪烁现象。
示例的，第一扫描信号Sn由第N行扫描线提供，第二扫描信号Sn+1由第N+1行扫描信号线提供，第三扫描信号Sn+2由第N+2行扫描信号线提供，第四扫描信号Sn+3由第N+3行扫描信号线提供，第五扫描信号Sn+4由第N+4行扫描信号线提供，其中，本实施例的扫描方向为从第1行至最后一行，也就是说，第一扫描信号Sn先于第二扫描信号Sn+1，第二扫描信号Sn+1先于第三扫描信号Sn+2，第三扫描线先于第四扫描信号Sn+3，第四扫描信号Sn+3先于第五扫描信号Sn+4，通过利用五个相邻的扫描信号线分别对应提供第一至第五扫描信号Sn+4，可以简化电路结构设计，减少控制信号的布线数量，从而增加像素开口率。
其中，应当理解的是，N为大于或等于1的正整数。
示例的，结合图1至图3所示，第一开关元件11包括第一晶体管T1，第二开关元件12包括第二晶体管T2，第三开关元件13包括第三晶体管T3，第四开关元件14包括第四晶体管T4，第五开关元件包括第五晶体管T5。
应当理解的是，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5与驱动晶体管DT相同，均具有第一端、第二端和控制端。各晶体管的控制端对应晶体管的栅极，第一端和第二端中的一者对应为晶体管的源极，另 一者对应为晶体管的漏极。
示例的，本公开实施例的驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4及第五晶体管T5可均为氧化物薄膜晶体管，即：各晶体管的有源层的材料可为氧化物，例如，可采用IGZO(Indium Gallium Zinc Oxide，铟锌氧化物)等金属氧化物材料，相比a-Si(非晶硅)薄膜晶体管，IGZO薄膜晶体管在性能上主要有3大优势，分别是高精度、低功耗与高触控性能，主要的供货目标是平板电脑、超级本这些电子显示产品。
此外，IGZO薄膜晶体管相比于低温多晶硅(LTPS)薄膜晶体管，无需通过照射激光使半导体层结晶，因此具有可轻松加大玻璃基板尺寸的特点，由于IGZO薄膜晶体管制程工艺与a-Si薄膜晶体管制程工艺相似度极高，加上IZGO的电子迁移率高，可以应用与生产LCD(Liquid Crystal Display，液晶显示装置)以及OLED显示装置。
举例而言，各晶体管可为底栅型，即：晶体管的栅极位于有源层的下方(靠近玻璃基板的一侧)，以能够适当减薄产品，但不限于此，各晶体管也可为顶栅型，视具体情况而定。
此外，各晶体管可为增强型或耗尽型晶体管，本公开实施例对此不做具体限定。
示例的，像素电路中的所有晶体管可均为N型薄膜晶体管，即：驱动晶体管DT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5可均为N型薄膜晶体管，则各个晶体管的驱动电压对应为高电平电压，基于此，前述第一电源信号端提供的第一电源信号Vdd可为直流高电平信号。
应当理解的是，像素电路中各晶体管不限于前述提到的N型薄膜晶体管，也可以为P型薄膜晶体管。在各晶体管均为P型薄膜晶体管时，各晶体管的驱动电压可对应的为低电平电压，基于此，第一电源信号Vdd可为直流低电平信号。
示例的，发光元件L可为电流驱动型发光元件L，由流经驱动晶体管DT的电流控制其进行发光，例如，发光元件L可以为有机发光二极管(OLED)，此像素电路可应用于OLED显示装置。
在像素电路中，各晶体管均为N型薄膜晶体管时，发光元件L的第一端为OLED的阴极，发光元件L的第二端为OLED的阳极。在像素电路中，各晶体管均为P型薄膜晶体管时，发光元件L的第一端为OLED的阳极，发光元件L的第二端为OLED的阴极。
下面结合图3并以各晶体管均为N型薄膜晶体管、第一电源信号Vdd为直流高 电平信号、发光元件L的第一端为OLED的阴极、发光元件L的第二端为OLED的阳极为例对像素电路中各结构的连接关系进行详细说明。
第一晶体管T1的控制端连接用于提供第一扫描信号Sn的第一扫描信号线16，第一晶体管T1的第一端连接数据线21，第一晶体管T1的第二端与电容结构C的第一端连接。
第二晶体管T2的控制端连接用于提供第二扫描信号Sn+1的第二扫描信号线17，第二晶体管T2的第一端连接第一节点A，第二晶体管T2的第二端连接第二节点B。
第三晶体管T3的控制端连接用于提供第三扫描信号Sn+2的第三扫描信号线18，第三晶体管T3的第一端连接驱动晶体管DT的第二端，第三晶体管T3的第二端连接发光元件L的第一端。
第四晶体管T4的控制端连接用于提供第四扫描信号Sn+3的第四扫描信号线19，第四晶体管T4的第一端连接第一电源信号端，第一电源信号端提供第一电源信号Vdd，第四晶体管T4的第二端连接第二节点B。
第五晶体管T5的控制端连接用于提供第五扫描信号Sn+4的第五扫描信号线20，第五晶体管T5的第一端连接驱动晶体管DT的第二端，第五晶体管T5的第二端连接发光元件L的第二端。
驱动晶体管DT的控制端和电容结构C的第二端均与第一节点A连接，驱动晶体管DT的第一端连接第二节点B。
发光元件L的第一端连接接地端；具体的，有机发光二极管的阴极连接接地端，有机发光二极管的阳极连接第五晶体管T5的第二端。
进一步的，参见图4，本公开实施例的像素电路还包括电压比较器U1、与门电路U2和限流电阻R。其中，电压比较器U1的功能是对两个输入电压的大小进行比较，并根据比较结果输出高电平或低电平；与门电路U2是执行与计算的基本逻辑门电路，有多个输入端和一个输出端，当所有的输入同时为高电平时，输出才为高电平，否则输出为低电平。应当理解的是，在本实施例中，电压比较器U1和与门电路U2均具有第一输入端、第二输入端和输出端，限流电阻具有第一端和第二端。
其中，电压比较器U1的第一输入端连接用于提供参考信号Vref的参考信号端，电压比较器U1的第二输入端与限流电阻的第一端连接，电压比较器U1的输出端连接与门电路U2的第一输入端，限流电阻的第二端连接驱动晶体管DT的第二端；与门电路U2的第二输入端与第四扫描信号线19连接，与门电路U2的输出端和第四晶 体管T4的控制端连接。
在本实施例中，电压比较器U1的第一输入端为电压比较器U1的同向端，电压比较器U1的第二输入端为电压比较器U1的反向端，默认状态下，电压比较器U1输出高电平。当出现大电流的时候，第二输入端的电压增高，当其大于参考电压的时候，电压比较器U1的输出端输出低电平，此时，无论第四扫描信号Sn+3为高电平还是低电平，第四晶体管T4始终截止，电路断开没有电流，从而保护电路。
基于此，本公开实施例的像素电路采用5T1C结构来实现电路在第一至第四阶段的充电、放电、补偿及发光，这样可以在发光前在驱动晶体管DT的栅极生产保护阈值电压的电压，从而在第四阶段发光元件L发光时对驱动晶体管DT的阈值电压进行补偿，避免了阈值电压漂移情况的发生，从而提高了显示均匀性。
实施例二
基于实施例一提到的像素电路，本公开实施例二还提供了一种像素驱动方法，结合图3、图5及图6所示，像素驱动方法可包括：
步骤S100，在第一阶段，利用第一扫描信号Sn、第二扫描信号Sn+1、第四扫描信号Sn+3打开第一开关元件11、第二开关元件12和第四开关元件14，同时，利用第三扫描信号Sn+2和第五扫描信号Sn+4关闭第三开关元件13和第五开关元件；
步骤S200，在第二阶段，利用第一扫描信号Sn、第二扫描信号Sn+1、第三扫描信号Sn+2打开第一开关元件11、第二开关元件12、第三开关元件13，同时，利用第四扫描信号Sn+3和第五扫描信号Sn+4关闭第四开关元件14和第五扫描信号Sn+4；
步骤S300，在第三阶段，利用第一扫描信号Sn打开第一开关元件11，同时，利用第二扫描信号Sn+1、第三扫描信号Sn+2、第四扫描信号Sn+3及第五扫描信号Sn+4关闭第二开关元件12、第三开关元件13及第四开关元件14及第五开关元件；
步骤S400，在第四阶段，利用第四扫描信号Sn+3和第五扫描信号Sn+4打开第四开关元件14及第五开关元件，同时，利用第一扫描信号Sn、第二扫描信号Sn+1、第三扫描信号Sn+2关闭第一开关元件11、第二开关元件12及第三开关元件13。
下面结合图5所示的像素电路的工作时序图对图2中的像素电路对应的像素驱动方法进行详细说明。
图5所示的像素电路的工作时序图绘示了第一扫描信号Sn、第二扫描信号Sn+1、第三扫描信号Sn+2、第四扫描信号Sn+3、第五扫描信号Sn+4及数据信号Data在四 个阶段的电平状态。
参见图7，在第一阶段，对电容结构进行充电，参考图5和图6所示，第一扫描信号Sn、第二扫描信号Sn+1及第四扫描信号Sn+3为高电平，第三扫描信号Sn+2、第五扫描信号Sn+4及数据信号Data为低电平，以使第一晶体管T1、第二晶体管T2及第四晶体管T4呈打开状态，第三晶体管T3和第五晶体管T5呈闭合状态。基于此，数据信号Data输入一个低电平至电容结构C的第一端，第一电源信号Vdd通过第四晶体管T4和第二晶体管T2施加至第一节点A，对电容结构C进行充电，即第一节点A写入第一电源信号，此时VA＝Vdd，VA为第一节点A处的电压。
参见图8，在第二阶段，对电路进行放电，第一扫描信号Sn、第二扫描信号Sn+1及第三扫描信号Sn+2为高电平，第四扫描信号Sn+3、第五扫描信号Sn+4及数据信号Data为低电平，以使得第一晶体管T1、第二晶体管T2及第三晶体管T3呈打开状态，第四晶体管T4及第五晶体管T5呈闭合状态。基于此，数据信号Data继续输入一个低电平至电容结构C的第一端，驱动晶体管DT的第二端由于第三晶体管T3的导通而接地，第一节点A的电压沿第二晶体管T2、驱动晶体管DT和第三晶体管T3进行放电，由于放电路径经过驱动晶体管DT，直到第一节点A的电压放电至VGS＝Vth的时候就不会再放电，同时由于电容结构C稳压的作用，第一节点A的电压VA-VS＝VGS＝Vth，此时VS＝0，即VA＝Vth保持不变，VS为驱动晶体管的第二端的电压，Vth为驱动晶体管的阈值电压。
参见图9，在第三阶段，第一扫描信号Sn及数据信号Data为高电平，第二扫描信号Sn+1至第五扫描信号Sn+4均为低电平，以使得第一晶体管T1呈打开状态，第二晶体管T2至第五晶体管T5均呈关闭状态。基于此，数据信号Data通过第一晶体管T1对电容结构C充电，电容结构C充电VData，此时，第一节点A的电压VA＝VData+Vth，由于电容结构C稳压的作用，VA＝VData+Vth保持不变，在驱动晶体管栅极生产包含驱动晶体管阈值电压的电压，以对驱动晶体管进行阈值电压补偿。
参见图10，在第四阶段，第四扫描信号Sn+3和第五扫描信号Sn+4为高电平，第一扫描信号Sn至第三扫描信号Sn+2为低电平，数据信号Data为高电平或低电平均可，以使得第四晶体管T4和第五晶体管T5及驱动晶体管DT呈打开状态，第一晶体管T1至第三晶体管T3均呈关闭状态，发光元件L从而进行发光，由于在第三阶段最后第一节点A的电压VA＝VData+Vth，即驱动晶体管DT的栅极电压等于第一节点A的电压，且已经包含Vth，从而对驱动晶体管DT的阈值电压Vth进行了补偿， 则驱动晶体管DT阈值电压的漂移不会对发光元件L的驱动电流产生影响，保证了驱动电流的均匀性和稳定性，因此可以使显示装置亮度更加均匀，降低残影产生，增强显示效果。
实施例三
基于前述实施例一的内容，本实施例三还提供了一种显示装置，其可为OLED显示装置。其中，显示装置可包括像素单元和实施例中的像素电路，像素电路与像素单元一一对应。由于本实施例具有实施例一所示的像素电路，因此本显示装置具有实施例一中像素电路的所有有益效果，在此不再赘述。
本公开实施例的显示装置可为AMOLED(Active-matrix organic light-emitting diode，有源矩阵有机发光二极体)显示，具有机身薄、省电、色彩鲜艳，画质强等众多优点，得到了广泛的应用。如：OLED电视、移动电话、笔记本电脑屏幕等，在平板显示领域中逐渐占主导地位。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，除非另有明确的规定和限定，术语“装配”、“连接”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对 上述实施例进行变化、修改、替换和变型，故但凡依本申请的权利要求和说明书所做的变化或修饰，皆应属于本申请专利涵盖的范围之内。

Claims (20)

  1. 一种像素电路，包括发光元件、电容结构、驱动晶体管、第一开关元件、第二开关元件、第三开关元件及第四开关元件，其中，
    所述第一开关元件用于响应第一扫描信号，以将用于提供数据信号的数据线与所述电容结构的第一端连接；
    所述第二开关元件用于响应第二扫描信号，以将所述驱动晶体管的第一端分别与所述驱动晶体管的控制端及所述电容结构的第二端连接；
    所述第三开关元件用于响应第三扫描信号，以将所述驱动晶体管的第二端与所述发光元件的第一端连接；
    所述第四开关元件用于响应第四扫描信号，以将第一电源信号端与所述驱动晶体管的第一端连接；
    所述发光元件的第二端与所述驱动晶体管的第二端连接，所述发光元件的第一端连接接地端。
  2. 根据权利要求1所述的像素电路，其中，
    所述像素电路还包括第五开关元件，所述第五开关元件用于响应第五扫描信号，以将所述驱动晶体管的第二端和所述发光元件的第二端连接。
  3. 根据权利要求2所述的像素电路，其中，
    所述第一至第五开关元件分别对应包括第一至第五晶体管；其中，
    所述第一晶体管的控制端连接用于提供所述第一扫描信号的第一扫描信号线，所述第一晶体管的第一端连接所述数据线，所述第一晶体管的第二端与所述电容结构的第一端连接；
    所述第二晶体管的控制端连接用于提供所述第二扫描信号的第二扫描信号线，所述第二晶体管的第一端连接第一节点，所述第二晶体管的第二端连接第二节点；
    所述第三晶体管的控制端连接用于提供所述第三扫描信号的第三扫描信号线，所述第三晶体管的第一端连接所述驱动晶体管的第二端，所述第三晶体管的第二端连接所述发光元件的第一端；
    所述第四晶体管的控制端连接用于提供所述第四扫描信号的第四扫描信号线，所述第四晶体管的第一端连接所述第一电源信号端，所述第四晶体管的第二端连接所述第二节点；
    所述第五晶体管的控制端连接用于提供所述第五扫描信号的第五扫描信号线，所述第五晶体管的第一端连接所述驱动晶体管的第二端，所述第五晶体管的第二端连接所述发光元件的第二端。
    所述驱动晶体管的控制端和所述电容结构的第二端均与所述第一节点连接，所述驱动晶体管的第一端连接所述第二节点。
  4. 根据权利要求3所述的像素电路，其中，
    所述驱动晶体管及所述第一晶体管至所述第五晶体管均为N型薄膜晶体管；
    其中，所述第一电源信号端提供的第一电源信号为直流高电平信号。
  5. 根据权利要求3所述的像素电路，其中，所述像素电路还包括电压比较器、与门电路及限流电阻；
    所述电压比较器的第一输入端连接用于提供参考信号的参考信号端，所述电压比较器的第二输入端与所述限流电阻的第一端连接，所述电压比较器的输出端连接所述与门电路的第一输入端，所述限流电阻的第二端连接所述驱动晶体管的第二端；
    所述与门电路的第二输入端与所述第四扫描信号线连接，所述与门电路的输出端与所述第四晶体管的控制端连接。
  6. 根据权利要求5所述的像素电路，其中，所述电压比较器的第一输入端为所述电压比较器的同向端，所述电压比较器的第二输入端为所述电压比较器的反向端。
  7. 根据权利要求3所述的像素电路，其中，各所述晶体管可为底栅型。
  8. 根据权利要求3所述的像素电路，其中，各所述晶体管同为N型薄膜晶体管或P型薄膜晶体管.
  9. 根据权利要求2所述的像素电路，其中，
    所述第一扫描信号由第N行扫描信号线提供，所述第二扫描信号由第N+1行扫描信号线提供，所述第三扫描信号由第N+2行扫描信号线提供，所述第四扫描信号由第N+3行扫描信号线提供，所述第五扫描信号由第N+4行扫描信号线提供，其中，N为大于或等于1的正整数；其中，
    所述像素电路的扫描方向为从第1行至最后一行。
  10. 一种像素驱动方法，用于驱动像素电路，其中，所述像素驱动方法包括：
    在第一阶段，利用第一扫描信号、第二扫描信号、第四扫描信号打开第一开关元件、第二开关元件和第四开关元件，同时，利用第三扫描信号关闭第三开关元件；
    在第二阶段，利用所述第一扫描信号、第二扫描信号、第三扫描信号打开所述第一开关元件、第二开关元件、第三开关元件，同时，利用所述第四扫描信号关闭所述第四开关元件；
    在第三阶段，利用所述第一扫描信号打开所述第一开关元件，同时，利用所述第二扫描信号、第三扫描信号及第四扫描信号关闭所述第二开关元件、第三开关元件及第四开关元件；
    在第四阶段，利用所述第四扫描信号打开所述第四开关元件，同时，利用所述第一扫描信号、第二扫描信号、第三扫描信号关闭所述第一开关元件、第二开关元件及第三开关元件。
  11. 根据权利要求10所述的像素驱动方法，其中，所述像素电路还包括第五开关元件，所述第五开关元件用于响应第五扫描信号，以将驱动晶体管的第二端和所述 发光元件的第二端连接；
    在所述第一阶段至所述第三阶段，利用所述第五扫描信号关闭所述第五开关元件；
    在所述第四阶段，利用所述第五扫描信号打开所述第五开关元件。
  12. 根据权利要求11所述的像素驱动方法，其中，第一电源信号端提供的第一电源信号为直流高电平信号；其中，
    在所述第一阶段，所述第一扫描信号、第二扫描信号及第四扫描信号为高电平，所述第三扫描信号、所述第五扫描信号及所述数据信号为低电平；
    在所述第二阶段，所述第一扫描信号、第二扫描信号及第三扫描信号为高电平，所述第四扫描信号、第五扫描信号及数据信号为低电平；
    在所述第三阶段，所述第一扫描信号及数据信号为高电平，所述第二扫描信号、第三扫描信号、第四扫描信号及第五扫描信号为低电平；
    在所述第四阶段，所述数据信号、第四扫描信号及第五扫描信号为高电平，所述第一扫描信号、第二扫描信号及第三扫描信号为低电平。
  13. 一种显示装置，包括像素单元和像素电路，所述像素电路与所述像素单元一一对应,所述像素电路包括发光元件、电容结构、驱动晶体管、第一开关元件、第二开关元件、第三开关元件及第四开关元件，
    所述第一开关元件用于响应第一扫描信号，以将用于提供数据信号的数据线与所述电容结构的第一端连接；
    所述第二开关元件用于响应第二扫描信号，以将所述驱动晶体管的第一端分别与所述驱动晶体管的控制端及所述电容结构的第二端连接；
    所述第三开关元件用于响应第三扫描信号，以将所述驱动晶体管的第二端与所述发光元件的第一端连接；
    所述第四开关元件用于响应第四扫描信号，以将第一电源信号端与所述驱动晶体管的第一端连接；
    所述发光元件的第二端与所述驱动晶体管的第二端连接，所述发光元件的第一端连接接地端。
  14. 根据权利要求13所述的显示装置，其中，
    所述像素电路还包括第五开关元件，所述第五开关元件用于响应第五扫描信号，以将所述驱动晶体管的第二端和所述发光元件的第二端连接。
  15. 根据权利要求14所述的显示装置，其中，
    所述第一至第五开关元件分别对应包括第一至第五晶体管；其中，
    所述第一晶体管的控制端连接用于提供所述第一扫描信号的第一扫描信号线，所述第一晶体管的第一端连接所述数据线，所述第一晶体管的第二端与所述电容结构的 第一端连接；
    所述第二晶体管的控制端连接用于提供所述第二扫描信号的第二扫描信号线，所述第二晶体管的第一端连接第一节点，所述第二晶体管的第二端连接第二节点；
    所述第三晶体管的控制端连接用于提供所述第三扫描信号的第三扫描信号线，所述第三晶体管的第一端连接所述驱动晶体管的第二端，所述第三晶体管的第二端连接所述发光元件的第一端；
    所述第四晶体管的控制端连接用于提供所述第四扫描信号的第四扫描信号线，所述第四晶体管的第一端连接所述第一电源信号端，所述第四晶体管的第二端连接所述第二节点；
    所述第五晶体管的控制端连接用于提供所述第五扫描信号的第五扫描信号线，所述第五晶体管的第一端连接所述驱动晶体管的第二端，所述第五晶体管的第二端连接所述发光元件的第二端。
    所述驱动晶体管的控制端和所述电容结构的第二端均与所述第一节点连接，所述驱动晶体管的第一端连接所述第二节点。
  16. 根据权利要求15所述的显示装置，其中，
    所述驱动晶体管及所述第一晶体管至所述第五晶体管均为N型薄膜晶体管；
    其中，所述第一电源信号端提供的第一电源信号为直流高电平信号。
  17. 根据权利要求15所述的显示装置，其中，所述像素电路还包括电压比较器、与门电路及限流电阻；
    所述电压比较器的第一输入端连接用于提供参考信号的参考信号端，所述电压比较器的第二输入端与所述限流电阻的第一端连接，所述电压比较器的输出端连接所述与门电路的第一输入端，所述限流电阻的第二端连接所述驱动晶体管的第二端；
    所述与门电路的第二输入端与所述第四扫描信号线连接，所述与门电路的输出端与所述第四晶体管的控制端连接。
  18. 根据权利要求17所述的显示装置，其中，所述电压比较器的第一输入端为所述电压比较器的同向端，所述电压比较器的第二输入端为所述电压比较器的反向端。
  19. 根据权利要求15所述的显示装置，其中，各所述晶体管可为底栅型。
  20. 根据权利要求14所述的显示装置，其中，
    所述第一扫描信号由第N行扫描信号线提供，所述第二扫描信号由第N+1行扫描信号线提供，所述第三扫描信号由第N+2行扫描信号线提供，所述第四扫描信号由第N+3行扫描信号线提供，所述第五扫描信号由第N+4行扫描信号线提供，其中，N为大于或等于1的正整数；其中，
    所述像素电路的扫描方向为从第1行至最后一行。
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