WO2023000409A1 - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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Publication number
WO2023000409A1
WO2023000409A1 PCT/CN2021/111831 CN2021111831W WO2023000409A1 WO 2023000409 A1 WO2023000409 A1 WO 2023000409A1 CN 2021111831 W CN2021111831 W CN 2021111831W WO 2023000409 A1 WO2023000409 A1 WO 2023000409A1
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Prior art keywords
layer
metal
sub
drain
source
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English (en)
French (fr)
Inventor
李恭檀
李珊
徐铉植
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Huizhou China Star Optoelectronics Display Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Huizhou China Star Optoelectronics Display Co Ltd
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Priority to US17/608,755 priority Critical patent/US12396258B2/en
Publication of WO2023000409A1 publication Critical patent/WO2023000409A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate and a preparation method thereof.
  • oxide thin film transistor indium gallium zinc oxide, IGZO for short
  • IGZO indium gallium zinc oxide
  • oxide TFT technology is characterized by higher mobility ( ⁇ >10 cm2/Vs), large area uniformity and low production cost.
  • BCE Back channel Etch
  • the traditional etch-stop structure oxide thin film transistor adopts SiOx insulating film layer to block the damage, but this requires an additional SiOx film-forming process and a photomask , increasing the production process and cost.
  • the embodiment of the present application provides an array substrate and a preparation method thereof, which are used to solve the problem of the existing back-channel etched oxide thin film transistors. Technical issues that lead to reduced device stability.
  • an array substrate including:
  • a main gate located on the substrate
  • the source electrode and the drain electrode partially cover the etching barrier layer, the region of the etching barrier layer not covered by the source electrode and the drain electrode is configured as an oxide metal layer, and the oxide The metal layer is arranged opposite to the active layer and the main gate.
  • a metal connection layer is disposed on the source and the drain, and the drain is connected to a pixel through the metal connection layer.
  • the material of the metal connection layer includes any one of Mo, MoTi and MoNi.
  • a passivation layer is further disposed on the substrate, and the passivation layer covers at least the metal oxide layer and the metal connection layer on the source and the drain. ;
  • a through hole is formed in the passivation layer, and the through hole is arranged opposite to the metal connection layer on the drain.
  • the passivation layer includes a first sub-passivation layer and a second sub-passivation layer stacked, the first sub-passivation layer is partially in contact with the metal oxide layer, and the The material of the first sub-passivation layer includes silicon oxide.
  • the oxide thin film transistor further includes an auxiliary gate, the auxiliary gate is located on the metal oxide layer, and is arranged opposite to the metal oxide layer; the auxiliary gate is arranged between the first sub-passivation layer and the second sub-passivation layer.
  • the material of the etching barrier layer includes Ti, and the film thickness of the etching barrier layer is 5 nm ⁇ 10 nm.
  • the thickness of the film layer where the source electrode and the drain electrode are located is 3 to 5 times the thickness of the film layer of the etching barrier layer or the metal connection layer.
  • a method for preparing the array substrate includes the steps of:
  • the step S30 includes:
  • the material of the metal connection layer includes any one of Mo, MoTi and MoNi.
  • the material of the etching barrier layer includes Ti;
  • step S40 "oxidizing the region of the etch stop layer not covered by the source and the drain" includes:
  • O2 plasma is used to oxidize the etching barrier layer, wherein the oxidized region of the etching barrier layer reacts to form a TiOx oxide metal layer.
  • the film thickness of the etching stopper layer is 5 nm ⁇ 10 nm.
  • the thickness of the film layer where the source electrode and the drain electrode are located is 3 to 5 times the thickness of the film layer of the etching barrier layer or the metal connection layer.
  • the step S50 includes:
  • the step S50 also includes:
  • S504 Form a connected via hole in the first sub-passivation layer and the second sub-passivation layer, wherein the via hole is connected to the metal connection layer on the source or the metal on the drain Connection layer alignment settings.
  • the material of the first sub-passivation layer includes silicon oxide.
  • the array substrate and its preparation method provided by the present invention form a metal film layer on the active layer of the oxide thin film transistor, and the metal film layer is formed in the subsequent source/drain pattern During chemical treatment, the active layer is protected from the damage of etching solution or dry etching process, and the part of the subsequent metal film layer corresponding to the channel of the active layer is oxidized to form an oxide layer to maintain the functional characteristics of the active layer; on the array substrate During the entire manufacturing process, the active layer is not damaged by the subsequent manufacturing process, and the stability of the device is maintained.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by the present invention.
  • FIGS. 2a to 2g are schematic structural diagrams of the fabrication process of the array substrate provided by the present invention.
  • FIG. 3 is a flow chart of the method for preparing an array substrate provided by the present invention.
  • An embodiment of the present application provides an array substrate, which will be described in detail below with reference to FIG. 1 .
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • the array substrate provided by the present invention includes a base 101 on which a main gate 102 is prepared, and the main gate 102 is covered with There is a gate insulating layer 103, an active layer 104 is formed on the gate insulating layer 103, the active layer 104 is arranged opposite to the main gate 102, and the active layer 104 and the gate insulating layer 103 are formed with
  • the first layer of metal is used as the etching barrier layer 105 of the active layer 104, and the second layer of metal is formed on the etching barrier layer 105, as the source electrode 1061 and the drain electrode 1062, and the source electrode 1061 and the
  • a third layer of metal is formed on the drain electrodes 1062, as the metal connection layer 107 connecting the drain electrodes 1062 to the pixel, and a passivation layer is formed on the film layer stack formed above, which constitutes the oxide layer in the array substrate provided by the present invention.
  • the etch barrier layer 105 is disposed covering the active layer 104, the etch barrier layer 105 includes an oxidized metal region corresponding to the middle part of the active layer 104, and non-oxidized regions relatively located at both ends of the oxidized metal region
  • the metal oxide region of the etch barrier layer 105 can be configured as a metal oxide layer, and can be used as the channel 108 of the active layer 104 .
  • the source electrode 1061 and the drain electrode 1062 partially cover the etching barrier layer 105, and the part of the source electrode 1061 and the drain electrode 1062 covering the etching barrier layer 105 is the etching barrier layer 105 in the non-oxidizing region.
  • the portion of the etch barrier layer 105 not covered by the source electrode 1061 and the drain electrode 1062 is the metal oxide region of the etch barrier layer 105 .
  • the source electrode 1061 and the drain electrode 1062 overlap the two ends of the active layer 104 through the non-oxidized region of the etching stopper layer 105, the source electrode 1061 is separated from the drain electrode 1062 and Avoid the arrangement of the metal oxide region; further, the source 1061 and the drain 1062 are both non-planar structures and both are symmetrically arranged with respect to the active layer 104, and the source 1061 is taken as an example below
  • the source electrode 1061 includes a first-dimensional metal layer (that is, a metal layer arranged horizontally) and a second-dimensional metal layer (that is, a metal layer that is vertically arranged), and the first-dimensional metal layer and the second-dimensional metal layer The metal layers are connected and arranged at the junction, wherein the first-dimensional metal layer is arranged on the active layer 104 and is in electrical contact with the active layer 104 through the etching barrier layer 105.
  • the end of the one-dimensional metal layer ends at the edge of the metal oxide region; the second-dimensional metal layer is disposed on the gate insulating layer 103, and the side of the second-dimensional metal layer passes through the etching barrier
  • the layer 105 is in electrical contact with the end surface of the active layer 104 ; the structure of the drain 1062 is symmetrical to that of the source 1061 , and will not be repeated here.
  • the array substrate includes at least one layer of the passivation layer, the surface of the passivation layer will be provided with the pixel electrodes of the display panel in the subsequent process, and a through hole is formed in the passivation layer, and the through hole is connected with the
  • the drain 1062 is arranged oppositely, and the pixel electrode extends into the through hole and is in electrical contact with the source 1061 or the metal connection layer 107 on the drain 1062 .
  • the array substrate includes two passivation layers, that is, a first sub-passivation layer 110 and a second sub-passivation layer 111 located on the first sub-passivation layer 110, the first sub-passivation layer
  • the passivation layer 110 and the second sub-passivation layer 111 are laminated, and the first sub-passivation layer 110 and the second sub-passivation layer 111 are formed with opposite through holes 113.
  • a pixel electrode 114 will be formed on the surface of the sub-passivation layer 111, and the pixel electrode 114 extends into the through hole 113 and is in electrical contact with the metal connection layer 107 on the source electrode 1061 or the drain electrode 1062. .
  • the array substrate further includes an auxiliary gate 115, which is arranged in alignment with the metal oxide region of the active layer 104, and in the thickness direction of the array substrate, the auxiliary gate 115 and the The main gate 102 is relatively located on both sides of the active layer 104, and the auxiliary gate 115 is located between the first sub-passivation layer 110 and the second sub-passivation layer 111, for example, the The auxiliary gate 115 is located on the surface of the first sub-passivation layer 110, and for another example, the auxiliary gate 115 is formed in the first sub-passivation layer 110, and the surface of the auxiliary gate 115 and the first sub-passivation layer The surface of a sub-passivation layer 110 is arranged evenly, and the double-gate structure is used to enhance the stability of the oxide thin film transistor.
  • the first sub-passivation layer 110 and the second sub-passivation layer 111 are made of different materials, for example, the first sub-passivation layer 110 is closer to the second sub-passivation layer 111
  • the active layer 104 is set, and the first sub-passivation layer 110 covers the metal connection layer 107 on the source electrode 1061 and the drain electrode 1062, and covers the oxide metal region of the active layer 104, so the The first sub-passivation layer 110 is also made of an oxide insulating material to continue the inductive effect between the oxide metal region of the active layer 104 and the auxiliary gate 115, while the second sub-passivation layer 111 is Materials different from the first sub-passivation layer 110 may be used.
  • the first sub-passivation layer 110 is made of SiOx material
  • the second sub-passivation layer 111 is made of SiNx material.
  • the array substrate provided by the present invention includes an etching stopper layer 105, a layer where the source electrode 1061/drain electrode 1062 is located, and a composite metal layer of the metal connection layer 107.
  • the etch stopper layer 105 covers the gate insulating layer 103 and The active layer 104 , and the etch barrier layer 105 covers the end of the active layer 104 sideways.
  • the layer where the source electrode 1061/drain electrode 1062 is located is disposed between the etching barrier layer 105 and the metal connection layer 107, and the film thickness of the etching barrier layer 105 and the metal connection layer 107 is Similarly, the film thickness of the etching barrier layer 105 and the metal connection layer 107 is 5 nm to 10 nm, and the film thickness of the layer where the source electrode 1061/drain electrode 1062 is located is the same as the etching barrier layer 105 or the film thickness of the metal connection layer 107.
  • the film thickness of the layer where the source electrode 1061/drain electrode 1062 is located refers to the overall thickness of the first-dimensional metal layer and the second-dimensional metal layer,
  • the layer where the source electrode 1061/drain electrode 1062 is located adopts a sunken setting and overlaps one side of the active layer 104, and the part of the layer where the source electrode 1061/drain electrode 1062 is located beyond the active layer 104 is smaller than the Therefore, the composite metal layer does not increase the overall thickness of the display panel.
  • the preparation material of the etching barrier layer 105 is Ti
  • the metal connection layer 107 is made of any material of Mo, MoTi and MoNi
  • the layer where the source electrode 1061/drain electrode 1062 is located is made of Cu material
  • the preparation material of the etching stopper layer 105 and the metal connection layer 107 are interchangeable.
  • the present invention also provides a preparation process of the array substrate, please refer to Fig. 2a to Fig. 2g, Fig. 2a to Fig. 2g are schematic structural diagrams of the preparation process of the array substrate provided by the present invention.
  • a substrate is provided, a main gate 102 is formed on the substrate, a gate insulating layer 103 is formed on the substrate and the main gate 102, and a pattern is formed on the gate insulating layer 103
  • the active layer 104 is an oxide semiconductor layer.
  • a first metal layer that is, an etch barrier layer 105, is provided on the film layer structure of FIG. Surface: the first metal layer fully covers the active layer 104 .
  • the material of the first metal layer is preferably Ti, and the thickness of the first metal layer is 5 nm ⁇ 10 nm.
  • a second metal layer 109 that is, the metal layers of the source and drain electrodes, is provided on the film structure of FIG. 2b, and the second metal layer 109 is provided on the surface of the first metal layer, so
  • the second metal layer 109 is made of different materials from the first metal layer, and its thickness is greater than that of the second metal layer 109; preferably, the second metal layer 109 is made of Cu material, and the second metal layer
  • the thickness of the layer 109 is 3-5 times of the thickness of the first metal layer.
  • a third metal layer 116 is provided on the film layer structure of Figure 2c, the third metal layer 116 is provided on the surface of the second metal layer 109, the third metal layer 116 and The materials of the second metal layer 109 and the first metal layer are different; preferably, the third metal layer 116 is made of any material of Mo, MoTi and MoNi, and the thickness of the third metal layer 116 is Much smaller than the thickness of the second metal layer 109 , the thickness of the third metal layer 116 is the same as that of the first metal layer.
  • the second metal layer 109 and the third metal layer 116 are patterned, for example, using a yellow light process on the second metal layer 109 and the third metal layer 116.
  • the third metal layer 116 is etched to form opposite source electrodes 1061 and drain electrodes 1062, and a metal connection layer 107 located on the source electrodes 1061 and the drain electrodes 1062, and the first metal layer serves as the
  • the etch barrier layer 105 of the active layer 104 is retained when the source electrode 1061 and the drain electrode 1062 are formed, and avoids wrong etching of the active layer 104 by the yellow light process.
  • the etched regions of the second metal layer 109 and the third metal layer 116 are arranged opposite to the active layer 104, and the source 1061 and the drain 1062 are connected to the active layer 104 .
  • O2 plasma treatment is performed on the part of the first metal layer exposed in the etched region to form an oxide metal region as the trench of the active layer 104. Road 108. So far, the main part of the oxide thin film transistor has been formed, and the subsequent process will form the auxiliary part structure of the oxide thin film transistor.
  • a first sub-passivation layer 110 is formed, and the first sub-passivation layer 110 is arranged in a paved manner, and fills the second metal layer 109 and the first sub-passivation layer.
  • An auxiliary gate 115 is formed on the first sub-passivation layer 110, the auxiliary gate 115 is arranged opposite to the main gate 102, and the auxiliary gate 115 is at least connected to the trench of the active layer 104 Track 108 alignment setting.
  • a second sub-passivation layer 111 is formed on the first sub-passivation layer 110, the second sub-passivation layer 111 is made of different materials from the first sub-passivation layer 110, further, the first sub-passivation layer
  • the passivation layer 110 is disposed relatively close to the metal oxide region of the first metal layer, and the first sub-passivation layer 110 is made of an oxide material, such as the first sub-passivation layer 110 is made of SiOx material, the The second sub-passivation layer 111 is made of SiNx material.
  • a through hole 113 is formed in the first sub-passivation layer 110 and the second sub-passivation layer 111 corresponding to the source electrode 1061 or the drain electrode 1062, and the through hole 113 is filled with A metal layer, one end of the metal layer is connected to the metal connection layer 107 on the source electrode 1061 or the drain electrode 1062 , and the opposite end is connected to the pixel electrode 114 of the display panel.
  • the metal connection layer 107 can block the impact of the dry etching or etching process on the source electrode 1061 or the drain electrode 1062, ensuring that the The integrity of the source 1061 and the drain 1062, while the metal connection layer 107 also serves as an auxiliary connection layer for the source 1061 and the drain 1062, the source 1061 and the drain 1062 Stability of connection to the pixel electrode 114 is maintained.
  • FIG. 3 is a flow chart of the method for preparing an array substrate provided by the present invention. According to the array substrate provided by the present invention, a method for preparing the array substrate is further proposed. The method includes steps:
  • the step S30 includes:
  • the source electrode 1061 and the drain electrode 1062 opposite to each other are formed on the second metal layer 109 and the third metal layer 116 by wet etching, and the The metal connection layer 107 on the source electrode 1061 and the drain electrode 1062, the first metal layer is used as the etching barrier layer 105 of the active layer 104, and is retained when the source electrode 1061 and the drain electrode 1062 are formed, and Misetching of the active layer 104 by the yellow light process is avoided.
  • the etched regions of the second metal layer 109 and the third metal layer 116 are arranged opposite to the active layer 104, and the source 1061 and the drain 1062 are connected to the active layer 104 .
  • the preparation material of the etching stopper layer is Ti, and in the step S40, "oxidize the region of the etching stopper layer not covered by the source and the drain" , in order to use O2 plasma to oxidize the etching barrier layer, the oxidized region of the etching barrier layer reacts to form a TiOx oxide metal layer.
  • the step S50 includes:
  • the step S50 further includes: S504 forming a via hole communicating with the first sub-passivation layer and the second sub-passivation layer, wherein the via hole is connected to the source
  • the metal connection layer on the drain electrode or the metal connection layer on the drain electrode is arranged in opposite positions.
  • the composite metal layer includes a first metal layer, a second metal layer 109 and a third metal layer 116 that are stacked.
  • the first metal layer is an etch barrier layer 105, and the first metal layer covers the surface, the end surface and the surface of the gate insulating layer 103 of the active layer 104; the first metal layer completely covers the active layer 104 .
  • the material of the first metal layer is preferably Ti, and the thickness of the first metal layer is 5 nm ⁇ 10 nm.
  • the second metal layer 109 is a metal layer used for etching to form the source and drain.
  • the second metal layer 109 is disposed on the surface of the first metal layer, the second metal layer 109 and the first metal layer are made of different materials, and the thickness is greater than that of the second metal layer 109; preferably , the second metal layer 109 is made of Cu material, and the thickness of the second metal layer 109 is 3-5 times of the thickness of the first metal layer.
  • the third metal layer 116 is a metal connection layer, the third metal layer 116 is arranged on the surface of the second metal layer 109, the third metal layer 116 is connected with the second metal layer 109, the first metal layer
  • the materials of the layers are all different; preferably, the third metal layer 116 is made of any material of Mo, MoTi and MoNi, and the thickness of the third metal layer 116 is much smaller than the thickness of the second metal layer 109 , the thickness of the third metal layer 116 is the same as the thickness of the first metal layer.
  • a metal film layer is formed on the active layer of the array substrate, and the metal film layer protects the active layer from etching during the subsequent source/drain patterning process. Due to the damage of the liquid or dry etching process, the part of the subsequent metal film layer corresponding to the active layer channel is oxidized to form an oxide layer to maintain the functional characteristics of the active layer; in the entire process of the array substrate, the active layer is not affected by the subsequent process. damage, the stability of the device is maintained.

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Abstract

本发明提供一种阵列基板及其制备方法，在阵列基板的主动层之上形成有金属膜层，金属膜层在源/漏极图案化处理时保护所述主动层免受刻蚀液或干刻制程的损害，后续金属膜层对应在主动层沟道处的部分被氧化处理形成氧化层，保持主动层的功能特性；在阵列基板的整个制程中，主动层没有受到后续制程的损害，器件稳定性得以保持。

Description

阵列基板及其制备方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
 背景技术
氧化物薄膜晶体管(indium gallium zinc oxide，简称IGZO)技术被认为是有希望取代非晶硅薄膜晶体管技术，成为下一代显示驱动背板的主流技术。与非晶硅薄膜晶体管技术相比，氧化物薄膜晶体管技术的特点是迁移率较高（μ>10 cm2/Vs）、大面积均匀性好和生产成本较低。
 技术问题
由于氧化物薄膜晶体管的稳定性仍然存在一定的问题，特别是采用背沟道刻蚀（Back channel Etch，简称BCE）结构的氧化物薄膜晶体管，现有技术的BCE结构的氧化物薄膜晶体管在制备过程中，氧化物沟道处裸露会直接受到源/漏极金属刻蚀液或者干刻蚀制程的影响，导致器件稳定性不佳，传统刻蚀阻挡型结构氧化物薄膜晶体管为防止氧化物沟道被损坏，采用SiOx绝缘膜层阻挡损坏，但这需要增加一次SiOx成膜制程和一道光罩，增加了生产工序和成本。
因此，改善氧化物薄膜晶体管的稳定性，特别是改善BCE结构的氧化物薄膜晶体管稳定性成为亟待解决的技术问题。
 技术解决方案
本申请实施例提供一种阵列基板及其制备方法，用于解决现有背沟道刻蚀型氧化物薄膜晶体管，制备过程中氧化物沟道在后续制程裸露易被误刻蚀受损，进而导致器件稳定性降低的技术问题。
为解决上述技术问题，本发明提供一种阵列基板，包括：
基底；
主栅极，位于所述基底之上；
主动层，位于主栅极之上；
刻蚀阻挡层，位于所述主动层之上；以及
源极和漏极，位于所述刻蚀阻挡层之上；
其中，所述源极和所述漏极部分覆盖所述刻蚀阻挡层，所述刻蚀阻挡层未被所述源极和所述漏极覆盖的区域配置成氧化金属层，且所述氧化金属层与所述主动层、所述主栅极对位设置。
根据本发明一实施例，所述源极和所述漏极之上均设置有金属连接层，所述漏极通过所述金属连接层连接至像素。
根据本发明一实施例，所述金属连接层的材料包括Mo、MoTi以及MoNi中的任意一种。
根据本发明一实施例，所述基底之上还设置有钝化层，所述钝化层至少覆盖所述氧化金属层以及位于所述源极和所述漏极之上的所述金属连接层；
所述钝化层形成有通孔，所述通孔与位于所述漏极之上的所述金属连接层对位设置。
根据本发明一实施例，所述钝化层包括层叠设置的第一子钝化层和第二子钝化层，所述第一子钝化层与所述氧化金属层部分接触，且所述第一子钝化层的材料包括硅氧化物。
根据本发明一实施例，所述氧化物薄膜晶体管还包括辅栅极，所述辅栅极位于所述氧化金属层之上，且与所述氧化金属层对位设置；所述辅栅极设置于所述第一子钝化层与所述第二子钝化层之间。
根据本发明一实施例，所述刻蚀阻挡层的材料包括Ti，且所述刻蚀阻挡层的膜层厚度为5nm~10nm。
根据本发明一实施例，所述源极和所述漏极所在的膜层的厚度为所述刻蚀阻挡层或所述金属连接层的膜层厚度的3至5倍。
依据本发明提供的阵列基板，进一步提出该阵列基板的制备方法，所述方法包括步骤：
S10、提供基底，并在所述基底上形成主栅极、栅绝缘层以及主动层；
S20、在所述主动层之上形成复合金属层，所述复合金属层包括层叠设置的刻蚀阻挡层、源漏金属层以及金属连接层；
S30、对所述复合金属层中刻蚀阻挡层之外的金属层进行图案化处理，形成位于所述刻蚀阻挡层上的源极和漏极，以及位于所述源极和所述漏极上的金属连接层；
S40、对所述刻蚀阻挡层未被所述源极和所述漏极覆盖的区域进行氧化处理，形成氧化金属层，其中，所述氧化金属层与所述主动层对位设置；
S50、在所述步骤S40形成的膜层之上制备钝化层。
根据本发明一实施例，所述步骤S30包括：
通过湿法刻蚀对所述金属连接层和所述源漏金属层进行图案化处理，形成所述源极和所述漏极、以及位于所述源极和所述漏极上的金属连接层。
根据本发明一实施例，所述金属连接层的材料包括Mo、MoTi以及MoNi中的任意一种。
根据本发明一实施例，所述刻蚀阻挡层的材料包括Ti；
所述步骤S40中“对所述刻蚀阻挡层未被所述源极和所述漏极覆盖的区域进行氧化处理”包括：
为采用O2等离子体对所述刻蚀阻挡层进行氧化处理，其中，所述刻蚀阻挡层被氧化处理的区域反应形成TiOx氧化金属层。
根据本发明一实施例，所述刻蚀阻挡层的膜层厚度为5nm~10nm。
根据本发明一实施例，所述源极和所述漏极所在的膜层的厚度为所述刻蚀阻挡层或所述金属连接层的膜层厚度的3至5倍。
根据本发明一实施例，所述步骤S50包括：
S501，在所述步骤S40形成的膜层之上制备第一子钝化层；
S502，在所述第一子钝化层之上形成辅栅极，其中，所述辅栅极与所述氧化金属层对位设置；
S503，在所述第一子钝化层之上制备第二子钝化层，其中，所述第二子钝化层覆盖所述辅栅极。
根据本发明一实施例，所述步骤S50还包括：
S504：在所述第一子钝化层和所述第二子钝化层形成连通的通孔，其中，所述通孔与所述源极上的金属连接层或所述漏极上的金属连接层对位设置。
根据本发明一实施例，所述第一子钝化层的材料包括硅氧化物。
 有益效果
本揭示实施例的有益效果：相比现有技术，本发明提供的阵列基板及其制备方法，在氧化物薄膜晶体管的主动层之上形成金属膜层，金属膜层在后续源/漏极图案化处理时保护所述主动层免受刻蚀液或干刻制程的损害，后续金属膜层对应在主动层沟道处的部分被氧化处理形成氧化层，保持主动层的功能特性；在阵列基板的整个制程中，主动层没有受到后续制程的损害，器件稳定性得以保持。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的阵列基板结构示意图。
图2a至图2g为本发明提供的阵列基板制备流程结构示意图。
图3为本发明提供的阵列基板制备方法流程图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
本申请实施例提供一种阵列基板，下面结合图1进行详细说明。
请参照图1，图1为本申请实施例提供的阵列基板结构示意图，本发明提供的阵列基板，包括基底101，所述基底101上制备有主栅极102，所述主栅极102上覆盖有栅绝缘层103，所述栅绝缘层103上形成有主动层104，所述主动层104与所述主栅极102对位设置，所述主动层104与所述栅绝缘层103上形成有第一层金属，作为所述主动层104的刻蚀阻挡层105，所述刻蚀阻挡层105上形成有第二层金属，作为源极1061和漏极1062，所述源极1061和所述漏极1062上均形成有第三层金属，作为所述漏极1062连接至像素的金属连接层107，以上形成的膜层叠构上形成有钝化层，构成本发明提供的阵列基板中的氧化物薄膜晶体管。
所述刻蚀阻挡层105覆盖所述主动层104设置，所述刻蚀阻挡层105包括对应于所述主动层104中间部的氧化金属区域，以及相对位于所述氧化金属区域两端的非氧化区域，所述刻蚀阻挡层105的金属氧化区域可以配置成氧化金属层，并且可以作为所述主动层104的沟道108。所述源极1061和所述漏极1062部分覆盖所述刻蚀阻挡层105，所述源极1061和所述漏极1062覆盖所述刻蚀阻挡层105的部分即为所述刻蚀阻挡层105的非氧化区域。所述刻蚀阻挡层105未被所述源极1061和所述漏极1062覆盖的部分即为所述刻蚀阻挡层105的氧化金属区域。
所述源极1061和所述漏极1062各通过所述刻蚀阻挡层105的非氧化区域搭接在所述主动层104的两端，所述源极1061与所述漏极1062相分离且避开所述氧化金属区域设置；进一步，所述源极1061和所述漏极1062均为非平面结构且两者相对于所述主动层104为对称设置，下面以所述源极1061为例进行说明，所述源极1061包括第一维度金属层（即水平设置的金属层）以及第二维度金属层（即垂直设置的金属层），所述第一维度金属层与所述第二维度金属层在交汇处相连接设置，其中，所述第一维度金属层设置于所述主动层104之上，且通过所述刻蚀阻挡层105与所述主动层104电性接触，所述第一维度金属层的端部止于所述氧化金属区域边缘；所述第二维度金属层设置于所述栅绝缘层103之上，且所述第二维度金属层的侧面通过所述刻蚀阻挡层105与所述主动层104的端面电性接触；所述漏极1062的结构与所述源极1061为对称设置，此处不再进行赘述。
所述阵列基板包括至少一层所述钝化层，所述钝化层表面在后续制程将会设置显示面板的像素电极，所述钝化层内形成有通孔，所述通孔与所述漏极1062对位设置，所述像素电极延伸至所述通孔内，并与所述源极1061或所述漏极1062上的金属连接层107电性接触。
例如，所述阵列基板包括两层所述钝化层，即第一子钝化层110和位于所述第一子钝化层110之上的第二子钝化层111，所述第一子钝化层110与所述第二子钝化层111层叠设置，所述第一子钝化层110与所述第二子钝化层111上形成有相对位的通孔113，所述第二子钝化层111表面将会形成像素电极114，且所述像素电极114延伸至所述通孔113内，并与所述源极1061或所述漏极1062上的金属连接层107电性接触。
进一步，所述阵列基板还包括辅栅极115，所述辅栅极115与所述主动层104的氧化金属区域对位设置，在所述阵列基板的厚度方向上，所述辅栅极115与所述主栅极102相对位于所述主动层104两侧，且所述辅栅极115位于所述第一子钝化层110与所述第二子钝化层111之间，例如，所述辅栅极115位于所述第一子钝化层110表面，又如，所述辅栅极115形成在所述第一子钝化层110内，且所述辅栅极115表面与所述第一子钝化层110表面平齐设置，双栅结构用以增强氧化物薄膜晶体管的稳定性。
进一步，所述第一子钝化层110与所述第二子钝化层111采用不同材料制备，例如，所述第一子钝化层110相对于所述第二子钝化层111靠近所述主动层104设置，且所述第一子钝化层110覆盖所述源极1061和所述漏极1062上的金属连接层107，以及覆盖所述主动层104的氧化金属区域，因此所述第一子钝化层110也采用氧化物绝缘材料制备，以延续所述主动层104的氧化金属区域与所述辅栅极115之间的电感作用，而所述第二子钝化层111则可以采用不同于所述第一子钝化层110的材料，优选的，所述第一子钝化层110采用SiOx材料制备，所述第二子钝化层111采用SiNx材料制备。
本发明提供的阵列基板包括刻蚀阻挡层105、源极1061/漏极1062所在层、以及金属连接层107三者的复合金属层，所述刻蚀阻挡层105覆盖所述栅绝缘层103以及所述主动层104，并且所述刻蚀阻挡层105侧面覆盖所述主动层104的端部。
进一步，所述源极1061/漏极1062所在层设置于所述刻蚀阻挡层105与所述金属连接层107之间，所述刻蚀阻挡层105与所述金属连接层107的膜层厚度相同，所述刻蚀阻挡层105与所述金属连接层107的膜层厚度为5nm~10nm，所述源极1061/漏极1062所在层的膜层厚度为所述刻蚀阻挡层105或所述金属连接层107膜层厚度的3～5倍；优选的，前述所述源极1061/漏极1062所在层的膜层厚度是指第一维度金属层与第二维度金属层的整体厚度，所述源极1061/漏极1062所在层采用下沉设置并搭接在所述主动层104的一侧，所述源极1061/漏极1062所在层超出所述主动层104的部分小于所述源极1061/漏极1062所在层的整体厚度，因此所述复合金属层没有增加显示面板的整体厚度。
例如，所述刻蚀阻挡层105的制备材料为Ti，所述金属连接层107采用Mo、MoTi以及MoNi的任意一种材料制备，所述源极1061/漏极1062所在层采用Cu材料制备；又如，所述刻蚀阻挡层105的制备材料与所述金属连接层107可互换。
依据本发明提供的阵列基板，本发明还提供了该阵列基板的制备流程，请参照图2a至图2g，图2a至图2g为本发明提供的阵列基板制备流程结构示意图。
如图2a所示，提供一基板，在所述基板上形成主栅极102，在所述基板和所述主栅极102之上形成栅绝缘层103，在所述栅绝缘层103上形成图案化的主动层104，所述主动层104为氧化物半导体层。
如图2b所示，在图2a的膜层结构上设置第一金属层，即刻蚀阻挡层105，所述第一金属层覆盖所述主动层104的表面、端面以及所述栅绝缘层103的表面；所述第一金属层全覆盖所述主动层104。所述第一金属层的材料优选为Ti，所述第一金属层的厚度为5nm~10nm。
如图2c所示，在图2b的膜层结构上设置第二金属层109，即源极和漏极的金属层，所述第二金属层109设置于所述第一金属层的表面，所述第二金属层109与所述第一金属层采用不同材料制备，且厚度大于所述第二金属层109；优选的，所述第二金属层109采用Cu材料制备，且所述第二金属层109的厚度为所述第一金属层厚度的3～5倍。
如图2d所示，在图2c的膜层结构上设置第三金属层116，所述第三金属层116设置于所述第二金属层109的表面，所述第三金属层116与所述第二金属层109、所述第一金属层的材料均不同；优选的，所述第三金属层116采用Mo、MoTi以及MoNi的任意一种材料制备，且所述第三金属层116的厚度远小于所述第二金属层109的厚度，所述第三金属层116的厚度与所述第一金属层的厚度相同。
如图2e所示，在图2d的膜层结构上，对所述第二金属层109和所述第三金属层116进行图案化处理，例如采用黄光工艺在所述第二金属层109与所述第三金属层116上刻蚀形成相对的源极1061和漏极1062，以及位于所述源极1061和所述漏极1062上的金属连接层107，所述第一金属层作为所述主动层104的刻蚀阻挡层105，在形成源极1061和漏极1062时得以保留，且避免黄光工艺对所述主动层104的误刻蚀。所述第二金属层109与所述第三金属层116的刻蚀区域与所述主动层104对位设置，所述源极1061与所述漏极1062通过所述第一金属层连接所述主动层104。
如图2f所示，在图2e的膜层结构上，对所述第一金属层裸露在所述刻蚀区域的部分进行O2等离子体处理，形成氧化金属区，作为所述主动层104的沟道108。至此，所述氧化物薄膜晶体管的主体部分已形成，后续制程将形成所述氧化物薄膜晶体管的辅助部分结构。
如图2g所示，在2f的膜层结构上，形成第一子钝化层110，所述第一子钝化层110呈铺设式设置，并填充所述第二金属层109和所述第三金属层116上的刻蚀区域。在所述第一子钝化层110上形成辅栅极115，所述辅栅极115与所述主栅极102对位设置，且所述辅栅极115至少与所述主动层104的沟道108对位设置。所述第一子钝化层110上形成有第二子钝化层111，所述第二子钝化层111与所述第一子钝化层110采用不同材料，进一步，所述第一子钝化层110相对靠近所述第一金属层的氧化金属区设置，所述第一子钝化层110则采用氧化物材料，如所述第一子钝化层110采用SiOx材料制备，所述第二子钝化层111采用SiNx材料制备。进一步，所述第一子钝化层110与所述第二子钝化层111对应于所述源极1061或所述漏极1062的位置形成有通孔113，所述通孔113内填充有金属层，所述金属层一端连接所述源极1061或所述漏极1062上的金属连接层107，相对另一端连接显示面板的像素电极114。形成完整的氧化物薄膜晶体管；在形成所述通孔113时，所述金属连接层107一方面可以阻挡干刻或蚀刻制程对所述源极1061或所述漏极1062造成的影响，保证所述源极1061和所述漏极1062的完整性，同时所述金属连接层107还作为所述源极1061和所述漏极1062的辅助连接层，所述源极1061和所述漏极1062连接至像素电极114的稳定性得以保持。
参照图3，图3为本发明提供的阵列基板制备方法流程图，依据本发明提供的阵列基板，进一步提出该阵列基板的制备方法，所述方法包括步骤：
S10、提供基底，并在所述基底上形成主栅极、栅绝缘层以及主动层；
S20、在所述主动层之上形成复合金属层，所述复合金属层包括层叠设置的刻蚀阻挡层、源漏金属层以及金属连接层；
S30、对所述复合金属层中刻蚀阻挡层之外的金属层进行图案化处理，形成位于所述刻蚀阻挡层上的源极和漏极，以及位于所述源极和所述漏极上的金属连接层；
S40、对所述刻蚀阻挡层未被所述源极和所述漏极覆盖的区域进行氧化处理，形成氧化金属层，其中，所述氧化金属层与所述主动层对位设置；
S50、在所述步骤S40形成的膜层之上制备钝化层。
根据本发明一实施例，所述步骤S30包括：
通过湿法刻蚀对所述金属连接层和所述源漏金属层进行图案化处理，形成所述源极和所述漏极、以及位于所述源极和所述漏极上的金属连接层。
如图2e所示，所述步骤S30中，通过湿法刻蚀在所述第二金属层109与所述第三金属层116上刻蚀形成相对的源极1061和漏极1062，以及位于所述源极1061和所述漏极1062上的金属连接层107，所述第一金属层作为所述主动层104的刻蚀阻挡层105，在形成源极1061和漏极1062时得以保留，且避免黄光工艺对所述主动层104的误刻蚀。所述第二金属层109与所述第三金属层116的刻蚀区域与所述主动层104对位设置，所述源极1061与所述漏极1062通过所述第一金属层连接所述主动层104。
根据本发明一实施例，所述刻蚀阻挡层的制备材料为Ti，所述步骤S40中“对所述刻蚀阻挡层未被所述源极和所述漏极覆盖的区域进行氧化处理”，为采用O2等离子体对所述刻蚀阻挡层进行氧化处理，所述刻蚀阻挡层被氧化处理的区域反应形成TiOx氧化金属层。
根据本发明一实施例，所述步骤S50包括：
S501，在所述步骤S40形成的膜层之上制备第一子钝化层；
S502，在所述第一子钝化层之上形成辅栅极，其中，所述辅栅极与所述氧化金属层对位设置；
S503，在所述第一子钝化层之上制备第二子钝化层，其中，所述第二子钝化层覆盖所述辅栅极。
根据本发明一实施例，所述步骤S50还包括：S504在所述第一子钝化层和所述第二子钝化层形成连通的通孔，其中，所述通孔与所述源极上的金属连接层或所述漏极上的金属连接层对位设置。
如图2b至2d所示，所述步骤S20中，复合金属层包括层叠设置的第一金属层、第二金属层109和第三金属层116。第一金属层为刻蚀阻挡层105，所述第一金属层覆盖所述主动层104的表面、端面以及所述栅绝缘层103的表面；所述第一金属层全覆盖所述主动层104。所述第一金属层的材料优选为Ti，所述第一金属层的厚度为5nm~10nm。
第二金属层109为用于刻蚀形成所述源极和漏极的金属层。所述第二金属层109设置于所述第一金属层的表面，所述第二金属层109与所述第一金属层采用不同材料制备，且厚度大于所述第二金属层109；优选的，所述第二金属层109采用Cu材料制备，且所述第二金属层109的厚度为所述第一金属层厚度的3～5倍。
第三金属层116为金属连接层，所述第三金属层116设置于所述第二金属层109的表面，所述第三金属层116与所述第二金属层109、所述第一金属层的材料均不同；优选的，所述第三金属层116采用Mo、MoTi以及MoNi的任意一种材料制备，且所述第三金属层116的厚度远小于所述第二金属层109的厚度，所述第三金属层116的厚度与所述第一金属层的厚度相同。
相比现有技术，本发明实施例提供的阵列基板，在阵列基板的主动层之上形成金属膜层，金属膜层在后续源/漏极图案化处理时保护所述主动层免受刻蚀液或干刻制程的损害，后续金属膜层对应在主动层沟道处的部分被氧化处理形成氧化层，保持主动层的功能特性；在阵列基板的整个制程中，主动层没有受到后续制程的损害，器件稳定性得以保持。
综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。

Claims (17)

  1. 一种阵列基板，包括：
    基底；
    主栅极，位于所述基底之上；
    主动层，位于主栅极之上；
    刻蚀阻挡层，位于所述主动层之上；以及
    源极和漏极，位于所述刻蚀阻挡层之上；
    其中，所述源极和所述漏极部分覆盖所述刻蚀阻挡层，所述刻蚀阻挡层未被所述源极和所述漏极覆盖的区域配置成氧化金属层，且所述氧化金属层与所述主动层、所述主栅极对位设置。
  2. 根据权利要求1所述的阵列基板，其中，所述源极和所述漏极之上均设置有金属连接层，所述漏极通过所述金属连接层连接至像素。
  3. 根据权利要求2所述的阵列基板，其中，所述金属连接层的材料包括Mo、MoTi以及MoNi中的任意一种。
  4. 根据权利要求2所述的阵列基板，其中，所述基底之上还设置有钝化层，所述钝化层至少覆盖所述氧化金属层以及位于所述源极和所述漏极之上的所述金属连接层；
    所述钝化层形成有通孔，所述通孔与位于所述漏极之上的所述金属连接层对位设置。
  5. 根据权利要求4所述的阵列基板，其中，所述钝化层包括层叠设置的第一子钝化层和第二子钝化层，所述第一子钝化层与所述氧化金属层部分接触，且所述第一子钝化层的材料包括硅氧化物。
  6. 根据权利要求5所述的阵列基板，其中，所述氧化物薄膜晶体管还包括辅栅极，所述辅栅极位于所述氧化金属层之上，且与所述氧化金属层对位设置；
    其中，所述辅栅极设置于所述第一子钝化层与所述第二子钝化层之间。
  7. 根据权利要求1所述的阵列基板，其中，所述刻蚀阻挡层的材料包括Ti，且所述刻蚀阻挡层的膜层厚度为5nm~10nm。
  8. 如权利要求1所述的阵列基板，其中，所述源极和所述漏极所在的膜层的厚度为所述刻蚀阻挡层或所述金属连接层的膜层厚度的3至5倍。
  9. 一种阵列基板的制备方法，包括步骤：
    S10、提供基底，并在所述基底上形成主栅极、栅绝缘层以及主动层；
    S20、在所述主动层之上形成复合金属层，所述复合金属层包括层叠设置的刻蚀阻挡层、源漏金属层以及金属连接层；
    S30、对所述复合金属层中刻蚀阻挡层之外的金属层进行图案化处理，形成位于所述刻蚀阻挡层上的源极和漏极，以及位于所述源极和所述漏极上的金属连接层；
    S40、对所述刻蚀阻挡层未被所述源极和所述漏极覆盖的区域进行氧化处理，形成氧化金属层，其中，所述氧化金属层与所述主动层对位设置；
    S50、在所述步骤S40形成的膜层之上制备钝化层。
  10. 根据权利要求9所述的制备方法，其中，所述步骤S30包括：
    通过湿法刻蚀对所述金属连接层和所述源漏金属层进行图案化处理，形成所述源极和所述漏极、以及位于所述源极和所述漏极上的金属连接层。
  11. 如权利要求9所述的制备方法，其中，所述金属连接层的材料包括Mo、MoTi以及MoNi中的任意一种。
  12. 根据权利要求9所述的制备方法，其中，所述刻蚀阻挡层的材料包括Ti；
    所述步骤S40中“对所述刻蚀阻挡层未被所述源极和所述漏极覆盖的区域进行氧化处理”包括：
    采用O2等离子体对所述刻蚀阻挡层进行氧化处理，其中，所述刻蚀阻挡层被氧化处理的区域反应形成TiOx氧化金属层。
  13. 如权利要求9所述的制备方法，其中，所述刻蚀阻挡层的膜层厚度为5nm~10nm。
  14. 如权利要求9所述的制备方法，其中，所述源极和所述漏极所在的膜层的厚度为所述刻蚀阻挡层或所述金属连接层的膜层厚度的3至5倍。
  15. 根据权利要求9所述的制备方法，其中，所述步骤S50包括：
    S501，在所述步骤S40形成的膜层之上制备第一子钝化层；
    S502，在所述第一子钝化层之上形成辅栅极，其中，所述辅栅极与所述氧化金属层对位设置；
    S503，在所述第一子钝化层之上制备第二子钝化层，其中，所述第二子钝化层覆盖所述辅栅极。
  16. 根据权利要求15所述的制备方法，其中，所述步骤S50还包括：
    S504：在所述第一子钝化层和所述第二子钝化层形成连通的通孔，其中，所述通孔与所述源极上的金属连接层或所述漏极上的金属连接层对位设置。
  17. 如权利要求15所述的制备方法，其中，所述第一子钝化层的材料包括硅氧化物。
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