WO2022270654A1 - 프리 몰드 기판 및 프리 몰드 기판의 제조 방법 - Google Patents
프리 몰드 기판 및 프리 몰드 기판의 제조 방법 Download PDFInfo
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- WO2022270654A1 WO2022270654A1 PCT/KR2021/007958 KR2021007958W WO2022270654A1 WO 2022270654 A1 WO2022270654 A1 WO 2022270654A1 KR 2021007958 W KR2021007958 W KR 2021007958W WO 2022270654 A1 WO2022270654 A1 WO 2022270654A1
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- Prior art keywords
- mold
- base member
- resin
- mold resin
- groove
- Prior art date
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- 239000000758 substrate Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 238000000034 method Methods 0.000 title description 30
- 229920005989 resin Polymers 0.000 claims abstract description 92
- 239000011347 resin Substances 0.000 claims abstract description 92
- 239000000463 material Substances 0.000 claims description 20
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 239000006071 cream Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 description 15
- 238000000465 moulding Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000003892 spreading Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 230000001680 brushing effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910017518 Cu Zn Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910017755 Cu-Sn Inorganic materials 0.000 description 1
- 229910017752 Cu-Zn Inorganic materials 0.000 description 1
- 229910017827 Cu—Fe Inorganic materials 0.000 description 1
- 229910017927 Cu—Sn Inorganic materials 0.000 description 1
- 229910017943 Cu—Zn Inorganic materials 0.000 description 1
- 229910017985 Cu—Zr Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- TVZPLCNGKSPOJA-UHFFFAOYSA-N copper zinc Chemical compound [Cu].[Zn] TVZPLCNGKSPOJA-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
Definitions
- the present invention relates to a pre-mold substrate.
- the substrates or lead frames there is a pre-molded substrate or a pre-molded lead frame on which a part of the mold resin is disposed.
- a part of the mold resin is disposed in advance before mounting the semiconductor chip, and thus the semiconductor package manufacturing process. has the advantage of shortening
- Korean Patent Laid-open Publication No. 10-2016-0021304 discloses a method for manufacturing a lead frame in which a pre-mold resin is disposed on the lower surface.
- a main object is to provide an improved pre-mold substrate and a manufacturing method of the pre-mold substrate.
- a first pre-mold groove is formed on a lower surface
- a second pre-mold groove is formed on an upper surface
- an electrically conductive base member constituting a circuit pattern and disposed in the first pre-mold groove.
- a pre-mold substrate comprising a first pre-mold resin; and a second pre-mold resin disposed in the second pre-mold groove.
- the first and second pre-molding resins are disposed on the lower and upper surfaces of the base member, respectively, there is an effect of preventing the pre-molding substrate from bending.
- FIG. 1 is a cross-sectional view of a pre-mold substrate according to an embodiment of the present invention.
- 2 to 8 are schematic cross-sectional views sequentially illustrating a process of manufacturing a pre-mold substrate according to an embodiment of the present invention.
- FIG. 9 is a schematic cross-sectional view illustrating a semiconductor package to which a pre-molded substrate according to an embodiment of the present invention is applied.
- FIG. 10 is a schematic flowchart illustrating a process of manufacturing a pre-mold substrate according to an embodiment of the present invention.
- a first pre-mold groove is formed on a lower surface
- a second pre-mold groove is formed on an upper surface
- an electrically conductive base member constituting a circuit pattern and disposed in the first pre-mold groove.
- a pre-mold substrate comprising a first pre-mold resin; and a second pre-mold resin disposed in the second pre-mold groove.
- first pre-mold resin and the second pre-mold resin may be made of the same type of resin.
- solder cream may be disposed on at least a portion of a portion of the base member that is not covered by the first pre-mold resin and the second pre-mold resin and is exposed.
- first pre-mold resin and the second pre-mold resin may be made of the same type of resin.
- the step of processing the lower surface of the base member to form the first pre-mold groove may be performed using etching.
- the etching may be performed by disposing a dry film resist of a photosensitive material on the lower surface of the base member and forming a resist pattern with the dry film resist.
- the step of processing the upper surface of the base member to form the second pre-mold groove may be performed using etching.
- the etching may be performed by disposing a dry film resist of a photosensitive material on the lower surface of the base member and forming a resist pattern with the dry film resist.
- the method may further include disposing solder cream on at least a portion of the portion of the base member that is not covered by the first pre-molding resin and the second pre-molding resin and is exposed.
- FIG. 1 is a cross-sectional view of a pre-mold substrate according to an embodiment of the present invention.
- a pre-mold substrate 100 includes a base member 110, a first pre-mold resin 120, and a second pre-mold resin 130. .
- the base member 110 forms a part of the pre-molded substrate 100 and forms a circuit pattern after processing.
- the base member 110 may be made of an electrically conductive material, and there are no other special limitations.
- the material of the base member 110 may be made of a single material such as Cu or Fe, a copper alloy such as Cu-Sn, Cu-Zr, Cu-Fe, or Cu-Zn, Fe-Ni, Fe- It may be made of various materials such as iron alloys such as Ni-Co.
- a commercially available lead frame material may be applied as the material of the base member 110 .
- a first pre-molding groove 111 is formed on the lower surface of the base member 110
- a second pre-molding groove 112 is formed on the upper surface of the base member 110 .
- the exposed portion S1 ( S2) serves as a terminal for electrical connection with a semiconductor chip or an external circuit board.
- the first pre-mold resin 120 is disposed in the first pre-mold groove 111 .
- the first pre-molded resin 120 forms the pre-molded substrate 100 together with the base member 110 and protects the base member 110 .
- the first pre-mold resin 120 is an electrically insulating resin.
- the first pre-mold resin 120 may be a thermoplastic resin or a thermosetting resin, and preferably contains 80 to 90% or more of silica to minimize thermal expansion.
- the filling of the first pre-mold resin 120 may be performed using a liquid resin material or a solid tape containing a resin component.
- the first pre-mold resin 120 is composed of an appropriate material for preventing the solder cream disposed in the exposed portions S1 and S2 of the base member 110 from spreading, but the present invention is not necessarily limited thereto. don't
- the second pre-mold resin 130 is disposed in the second pre-mold groove 112 .
- the second pre-mold resin 130 is an electrically insulating resin.
- the second pre-mold resin 130 may be a thermoplastic resin or a thermosetting resin, and preferably contains 80 to 90% or more of silica to minimize thermal expansion.
- the filling of the second pre-mold resin 130 may be performed using a liquid resin material or a solid tape containing a resin component.
- the second pre-mold resin 130 is made of an appropriate material for preventing the solder cream disposed in the exposed portions S1 and S2 of the base member 110 from spreading, but the present invention is not necessarily limited thereto. don't
- the first pre-mold resin 120 and the second pre-mold resin 130 are made of the same type of resin.
- the resin disposed on both sides of the base member 110 is made of the same type, there is no difference in the coefficient of thermal expansion between the both sides of the pre-molded substrate 100, and thus the warping of the pre-molded substrate 100 is more effective. It can be prevented.
- the first pre-mold resin 120 and the second pre-mold resin 130 are made of the same type of resin, but the present invention is not limited thereto. That is, according to the present invention, the first pre-mold resin 120 and the second pre-mold resin 130 may be made of different types of resins.
- FIG. 2 to 8 are schematic cross-sectional views sequentially illustrating a process of manufacturing a pre-mold substrate according to an embodiment of the present invention
- FIG. 9 is a semiconductor package to which a pre-mold substrate according to an embodiment of the present invention is applied.
- 10 is a schematic flowchart illustrating a process of manufacturing a pre-mold substrate according to an embodiment of the present invention.
- the base member 110 is prepared (step S1).
- the base member 110 is made of an electrically conductive material and includes a lower surface 110a and an upper surface 110b.
- Step S2 the lower surface 110a of the base member 100 is processed to form the first pre-mold groove 111 as shown in FIG. 3 (Step S2).
- a method of processing the lower surface 110a of the base member 100 may use an etching method.
- the etching method wet etching, dry etching, or the like may be applied.
- a dry film resist made of photosensitive material is disposed on the lower surface 110a of the base member 100, and the dry film resist is exposed and developed to form a resist pattern with the dry film resist. Subsequently, etching may be performed using the formed resist pattern to form the first pre-mold groove 111 .
- step S3 the first pre-mold resin 120 is applied and placed in the first pre-mold groove 111.
- the first pre-mold resin 120 has a portion 120b located in the first pre-mold groove 111 as well as a portion 120b covering a portion of the lower surface 110a.
- the exposed portion S1 may be formed by exposing the lower surface 110a of the base member 100 through a brushing process, a polishing process, an etching process, or the like, as shown in FIG. 5 .
- step S4 the upper surface 110b of the base member 110 is processed to form the second pre-mold groove 112 (step S4).
- a method of processing the upper surface 110b of the base member 100 may use an etching method.
- the etching method wet etching, dry etching, or the like may be applied.
- a dry film resist of a photosensitive material is disposed on the upper surface 110b of the base member 100, and the dry film resist is exposed and developed to form a resist pattern R with the dry film resist, as shown in FIG. do.
- etching is performed using the formed resist pattern R to form second pre-mold grooves 112 as shown in FIG. 6 .
- the second pre-mold resin 130 is applied and placed in the second pre-mold groove 112 (step S5).
- the second pre-mold resin 130 has a portion 130b located in the second pre-mold groove 112 as well as a portion 130b covering a portion of the upper surface 110b.
- the exposed portion S2 may be formed by exposing the upper surface 110b of the base member 100 as shown in FIG. 1 through a brushing process, a polishing process, an etching process, or the like.
- exposed parts (S1) and (S2) that are not covered by the first pre-mold resin 120 and the second pre-mold resin 130 are electrically connected to the semiconductor chip or the external circuit board. It performs the function of the terminal for Accordingly, an additional process may be performed on the exposed portions S1 and S2. For example, at least a portion of the exposed portions S1 and S2 may be plated with Au, Pd, or the like, or organic solderability preservative (OSP) coating may be performed to increase solder adhesion in a subsequent process.
- OSP organic solderability preservative
- the manufacturing of the pre-mold substrate 100 is completed with the structure shown in FIG. 1, and the manufactured pre-mold substrate 100 is transferred to a semiconductor package manufacturing process to manufacture a semiconductor package.
- the process may proceed, but the present invention is not limited thereto. That is, according to the present invention, in the manufacturing process of the pre-mold substrate 100, at least some of the exposed portions S1 and S2 of the base member 110 shown in FIG. 1, as shown in FIG. 8, A process of disposing solder cream (K) may be added. That is, the process of disposing the solder cream (K) is generally performed in the semiconductor packaging process, but as described above, the exposed portions (S1) (S2) of the base member 110 function as terminals for electrical connection.
- the solder cream K may be previously disposed on at least a part of the exposed portions S1 and S2. In that case, even if the shape of the solder cream K is flexible, it does not deviate from the exposed portions S1 and S2, which is because the materials of the base member 110 and the first and second pre-mold resins 120 and 130 are different. This is because the surface of the first and second pre-mold resins 120 and 130 pushes the solder cream K out of the material, so that the spread of the solder cream K is prevented.
- solder cream K After the solder cream K is disposed, electrical connection between the electrode P of the semiconductor chip C and the base member 110 is performed using the solder cream K in a semiconductor package manufacturing process. Subsequently, encapsulation is performed using a mold resin (G) such as an epoxy material or a urethane-based material to realize the structure of the semiconductor package 200 as shown in FIG. 9 .
- G mold resin
- the electrode P of the semiconductor chip C is electrically connected to the base member 110 by directly using the solder cream K, but the present invention is not limited thereto. That is, according to the present invention, electrical connection with the chip C may be performed by forming bumps using solder cream K.
- the second pre-mold groove 112 is formed and the second pre-mold resin 130 is disposed, but the present invention is not limited thereto. That is, in the manufacturing process of the pre-mold substrate according to the present invention, the second pre-mold groove 112 is formed, the second pre-mold resin 130 is placed, and then the first pre-mold groove 111 is formed. 1 may proceed in the order of disposing the pre-mold resin 120 .
- the first and second pre-mold grooves may be formed first, and then the first and second pre-mold resins may be disposed.
- the process of pre-mold substrate 100 described above is performed in units of flat plates, the present invention is not limited thereto. That is, according to the present invention, the process of pre-mold substrate 100 described above can be continuously performed as a roll-to-roll process.
- the first pre-molding grooves 111 are formed on the lower surface 110a of the base member 110, and the second pre-molding grooves are formed on the upper surface 110b. 112 is formed, the first pre-mold resin 120 is disposed in the first pre-mold groove 111, and the second pre-mold resin 130 is disposed in the second pre-mold groove 112, so that the base A pre-mold resin is disposed on both the lower surface side and the upper surface side of the member 110 .
- the first pre-mold resin 120 and the second pre-mold resin 130 are made of the same type of resin, so that warping of the substrate can be more effectively prevented.
- the solder cream K is placed on the exposed portions S1 and S2 of the base member 110.
- the materials of the base member 110 and the first and second pre-molded resins 120 and 130 are different, spreading of the solder cream K is naturally prevented, and thus the quality of the semiconductor package is improved.
- the pre-mold substrate and the method for manufacturing the pre-mold substrate according to the present embodiment can be applied to industries that manufacture pre-mold substrates.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
Claims (10)
- 하면에 제1 프리 몰드 홈이 형성되고, 상면에 제2 프리 몰드 홈이 형성되며, 회로 패턴을 이루는 전기 전도성의 베이스 부재;상기 제1 프리 몰드 홈에 배치된 제1 프리 몰드 수지; 및상기 제2 프리 몰드 홈에 배치된 제2 프리 몰드 수지를 포함하는, 프리 몰드 기판.
- 제1항에 있어서,상기 제1 프리 몰드 수지와 상기 제2 프리 몰드 수지는 동일한 종류의 수지로 이루어지는, 프리 몰드 기판.
- 제1항에 있어서,상기 베이스 부재의 부분 중 상기 제1 프리 몰드 수지와 상기 제2 프리 몰드 수지로 덮이지 않아 노출되는 부분의 적어도 일부에는, 솔더 크림이 배치되는, 프리 몰드 기판.
- 전기 전도성의 베이스 부재를 준비하는 단계;상기 베이스 부재의 하면을 가공하여 제1 프리 몰드 홈을 형성하는 단계;상기 형성된 제1 프리 몰드 홈에 제1 프리 몰드 수지를 배치하는 단계;상기 베이스 부재의 상면을 가공하여 제2 프리 몰드 홈을 형성하는 단계; 및상기 형성된 제2 프리 몰드 홈에 제2 프리 몰드 수지를 배치하는 단계를 포함하는, 프리 몰드 기판의 제조 방법.
- 제4항에 있어서,상기 제1 프리 몰드 수지와 상기 제2 프리 몰드 수지는 동일한 종류의 수지로 이루어지는, 프리 몰드 기판의 제조 방법.
- 제4항에 있어서,상기 제1 프리 몰드 홈을 형성하기 위해 상기 베이스 부재의 하면을 가공하는 단계는, 에칭을 이용하여 이루어지는, 프리 몰드 기판의 제조 방법.
- 제6항에 있어서,상기 에칭은, 감광성 소재의 드라이 필름 레지스트를 상기 베이스 부재의 하면에 배치하고, 상기 드라이 필름 레지스트로 레지스트 패턴을 형성하여 수행하는, 프리 몰드 기판의 제조 방법.
- 제4항에 있어서,상기 제2 프리 몰드 홈을 형성하기 위해 상기 베이스 부재의 상면을 가공하는 단계는, 에칭을 이용하여 이루어지는, 프리 몰드 기판의 제조 방법.
- 제8항에 있어서,상기 에칭은, 감광성 소재의 드라이 필름 레지스트를 상기 베이스 부재의 하면에 배치하고, 상기 드라이 필름 레지스트로 레지스트 패턴을 형성하여 수행하는, 프리 몰드 기판의 제조 방법.
- 제4항에 있어서,상기 베이스 부재의 부분 중 상기 제1 프리 몰드 수지와 상기 제2 프리 몰드 수지로 덮이지 않아 노출되는 부분의 적어도 일부에는, 솔더 크림을 배치하는 공정을 더 포함하는, 프리 몰드 기판의 제조 방법.
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US17/428,258 US20240038652A1 (en) | 2021-06-21 | 2021-06-24 | Pre-mold substrate and method of manufacturing pre-mold substrate |
CN202180002167.XA CN115715427A (zh) | 2021-06-21 | 2021-06-24 | 预模制衬底及制造预模制衬底的方法 |
JP2021562376A JP2023534562A (ja) | 2021-06-21 | 2021-06-24 | プリモールド基板、及びプリモールド基板の製造方法 |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20110124482A (ko) * | 2010-05-11 | 2011-11-17 | 엘지이노텍 주식회사 | 리드 프레임 및 그 제조 방법 |
KR20120050711A (ko) * | 2010-11-11 | 2012-05-21 | 삼성테크윈 주식회사 | 회로 기판 및 회로 기판의 제조 방법 |
KR20150081146A (ko) * | 2014-01-03 | 2015-07-13 | 해성디에스 주식회사 | 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판 |
KR20170008088A (ko) * | 2015-07-13 | 2017-01-23 | 박성실 | 이미지센서 칩 패키지 제조방법 |
KR101999594B1 (ko) * | 2018-02-23 | 2019-10-01 | 해성디에스 주식회사 | 반도체 패키지 기판 제조방법, 이를 이용하여 제조된 반도체 패키지 기판, 반도체 패키지 제조방법 및 이를 이용하여 제조된 반도체 패키지 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4459406B2 (ja) * | 2000-07-27 | 2010-04-28 | ソニーケミカル&インフォメーションデバイス株式会社 | フレキシブル配線板製造方法 |
KR101366992B1 (ko) * | 2009-07-27 | 2014-02-24 | 가부시키가이샤 도요다 지도숏키 | 배선 기판 및 배선 기판의 제조 방법 |
JP6617955B2 (ja) * | 2014-09-16 | 2019-12-11 | 大日本印刷株式会社 | リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法 |
JP2017147272A (ja) * | 2016-02-15 | 2017-08-24 | ローム株式会社 | 半導体装置およびその製造方法、ならびに、半導体装置の製造に使用されるリードフレーム中間体 |
JP6593842B2 (ja) * | 2016-03-16 | 2019-10-23 | 大口マテリアル株式会社 | Ledパッケージ並びに多列型led用リードフレーム及びその製造方法 |
WO2018006738A1 (zh) * | 2016-07-04 | 2018-01-11 | 苏州晶方半导体科技股份有限公司 | 封装结构以及封装方法 |
JP6964477B2 (ja) * | 2017-09-20 | 2021-11-10 | 新光電気工業株式会社 | 半導体素子用基板及びその製造方法、半導体装置及びその製造方法 |
TWI687142B (zh) * | 2018-12-28 | 2020-03-01 | 南亞電路板股份有限公司 | 電路板結構及其製造方法 |
CN112309836B (zh) * | 2019-08-01 | 2022-10-28 | 京东方科技集团股份有限公司 | 一种背板及其制备方法、背光模组和显示装置 |
-
2021
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- 2021-06-24 US US17/428,258 patent/US20240038652A1/en active Pending
- 2021-06-24 CN CN202180002167.XA patent/CN115715427A/zh active Pending
- 2021-06-24 WO PCT/KR2021/007958 patent/WO2022270654A1/ko active Application Filing
- 2021-06-24 JP JP2021562376A patent/JP2023534562A/ja active Pending
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20110124482A (ko) * | 2010-05-11 | 2011-11-17 | 엘지이노텍 주식회사 | 리드 프레임 및 그 제조 방법 |
KR20120050711A (ko) * | 2010-11-11 | 2012-05-21 | 삼성테크윈 주식회사 | 회로 기판 및 회로 기판의 제조 방법 |
KR20150081146A (ko) * | 2014-01-03 | 2015-07-13 | 해성디에스 주식회사 | 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판 |
KR20170008088A (ko) * | 2015-07-13 | 2017-01-23 | 박성실 | 이미지센서 칩 패키지 제조방법 |
KR101999594B1 (ko) * | 2018-02-23 | 2019-10-01 | 해성디에스 주식회사 | 반도체 패키지 기판 제조방법, 이를 이용하여 제조된 반도체 패키지 기판, 반도체 패키지 제조방법 및 이를 이용하여 제조된 반도체 패키지 |
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KR20220169830A (ko) | 2022-12-28 |
CN115715427A (zh) | 2023-02-24 |
JP2023534562A (ja) | 2023-08-10 |
TWI777697B (zh) | 2022-09-11 |
TW202301580A (zh) | 2023-01-01 |
KR102531701B1 (ko) | 2023-05-12 |
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