WO2022267756A1 - 3d滤波电路与3d滤波器 - Google Patents

3d滤波电路与3d滤波器 Download PDF

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Publication number
WO2022267756A1
WO2022267756A1 PCT/CN2022/093484 CN2022093484W WO2022267756A1 WO 2022267756 A1 WO2022267756 A1 WO 2022267756A1 CN 2022093484 W CN2022093484 W CN 2022093484W WO 2022267756 A1 WO2022267756 A1 WO 2022267756A1
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layer
conductive
filter circuit
conductive layers
multilayer structure
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PCT/CN2022/093484
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English (en)
French (fr)
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王晓东
何成功
左成杰
何军
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安徽安努奇科技有限公司
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Application filed by 安徽安努奇科技有限公司 filed Critical 安徽安努奇科技有限公司
Priority to KR1020237009729A priority Critical patent/KR20230054861A/ko
Priority to US18/044,982 priority patent/US20230370039A1/en
Priority to JP2023515089A priority patent/JP7569519B2/ja
Publication of WO2022267756A1 publication Critical patent/WO2022267756A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0153—Electrical filters; Controlling thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0014—Capacitor filters, i.e. capacitors whose parasitic inductance is of relevance to consider it as filter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021—Constructional details
    • H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets

Definitions

  • Embodiments of the present application provide a 3D filter circuit and a 3D filter, so as to meet design requirements for miniaturization and high performance of the filter circuit.
  • the multilayer structure includes at least two conductive layers and at least one organic medium layer, and each organic medium layer is arranged between different conductive layers; the multilayer structure is configured to form at least one capacitor.
  • an embodiment of the present application further provides a 3D filter, including the 3D filter circuit provided in any embodiment of the first aspect.
  • FIG. 1 is a schematic structural diagram of a 3D filter circuit provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another 3D filter circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another 3D filter circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another 3D filter circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another 3D filter circuit provided by an embodiment of the present application.
  • Multilayer structure 110. Conductive layer; 111. First patterned structure; 112. Second patterned structure; 113. Third patterned structure; 120. Organic medium layer;
  • Encapsulation layer 210. Insulation medium layer; 220. Conductive structure.
  • the organic medium layer 120 used in the multilayer structure 100 has a wide variety of materials, strong selectivity, and low cost.
  • the organic dielectric layer 120 has a variety of composition structures and wide adjustment space performance, which can well adjust the performance of the capacitor C, so that the capacitor C can meet the high performance requirement.
  • the 3D filter circuit is composed of at least one multi-layer structure 100, which can increase the integration of the capacitor C, thereby realizing the miniaturization and high-performance design requirements of the filter circuit.
  • FIG. 2 is a schematic structural diagram of another 3D filter circuit provided by an embodiment of the present application.
  • the multilayer structure 100 is a three-dimensional structure composed of three conductive layers 110 and two organic medium layers 120 , wherein an organic medium layer 120 is arranged between every two conductive layers 110 .
  • the multi-layer structure 100 of this solution can form three capacitors C.
  • FIG. 1 exemplarily shows a multilayer structure 100 comprising two conductive layers 110 and an organic medium layer 120 to form a capacitor C
  • FIG. 2 exemplarily shows a multilayer structure 100 Including three layers of conductive layers 110 and two layers of organic medium layers 120 to form a situation with three capacitors C
  • the multilayer structure 100 includes conductive layers 110 and a conductive medium layer disposed between each layer of conductive layers 110 The number can be set according to actual needs, and the number of capacitors C formed in the multilayer structure 100 can be set according to actual needs.
  • At least two conductive layers 110 include a plurality of first patterned structures 111, and vertical projections of the first patterned structures 111 in different conductive layers 110 on the organic medium layer 120 Overlapping, overlapping portions of vertical projections of the first patterned structures 111 in different conductive layers 110 on the organic medium layer 120 are set to form a plurality of capacitors C.
  • one layer of conductive layer 110 in FIG. 1 includes a first patterned structure 111, wherein the first patterned structure 111 is: at least two layers of conductive layer 110 and at least one layer of organic medium layer 120 vertical projection overlap The conductive layer 110. If at least two conductive layers 110 include a plurality of first patterned structures 111, the overlapping portions of vertical projections of the plurality of first patterned structures 111 in different conductive layers 110 on the organic medium layer 120 can form a plurality of capacitors C .
  • a plurality of capacitors C can be centrally arranged in the multi-layer structure 100, which not only meets the requirement of the 3D filter circuit for the capacitor C to ensure high performance of the 3D filter circuit, but also realizes the miniaturization of the 3D filter circuit.
  • At least two conductive layers 110 are further configured to form at least one of the planar inductor L1 and the 3D inductor L2 .
  • the conductive layer 110 in the multilayer structure 100 can form an inductor.
  • types of inductors include planar inductors L1 and 3D inductors L2.
  • the planar inductor L1 is composed of a single conductive layer 110
  • the 3D inductor L2 is composed of at least two conductive layers 110 electrically connected.
  • at least two conductive layers 110 in the multilayer structure 100 can centrally set at least one of the planar inductance L1 and the 3D inductance L2, which not only meets the demand for inductance of the 3D filter circuit to ensure the high performance design requirements of the 3D filter circuit , also realized the miniaturization of the 3D filter circuit.
  • the multilayer structure 100 includes a 3D inductor L2, the organic medium layer 120 is provided with a first through hole T1, and the first through hole T1 is filled with a conductive material; each conductive layer 110 It includes at least one second patterned structure 112 , the second patterned structures 112 in different conductive layers 110 are connected through the first through hole T1 , and is configured to form at least one 3D inductor L2 .
  • the multilayer structure 100 includes at least two conductive layers 110 and at least one organic medium layer 120, and the organic medium layer 120 is disposed between the at least two conductive medium layers.
  • the multilayer structure 100 includes a 3D inductor L2, and at least two conductive layers 110 included in the multilayer structure 100 need to be electrically connected.
  • a first through hole T1 can be provided on the organic medium layer 120, and a conductive material can be filled in the first through hole T1, so that the conductive layers 110 of different layers can be electrically connected through the first through hole T1, thereby forming a 3D Inductor L2.
  • each conductive layer 110 included in the multilayer structure 100 includes at least one second patterned structure 112. If the second patterned structures 112 in different conductive layers 110 are connected through the first through hole T1, at least one 3D inductor can be formed. L2. To sum up, at least two conductive layers 110 in the multilayer structure 100 can be provided with at least one 3D inductor L2 collectively, which improves the compactness of the inductor arrangement and realizes the miniaturization of the 3D filter circuit.
  • the material of the organic medium layer includes at least one of epoxy resin, PPE resin and PI resin.
  • the material of the conductive layer includes copper foil or electroplated copper.
  • copper foil or electroplated copper can be attached to various substrates, such as metals, insulating materials, etc., and has a wide temperature range. Place the conductive copper foil on the substrate surface, combined with the metal substrate, it has excellent conductivity, and provides the effect of electromagnetic shielding; the copper ions in the electrolyte are plated on the surface of the substrate, and a thinner, finer and smoother surface can be obtained. Copper plating with good electrical conductivity.
  • the material of the conductive layer is copper foil or electroplated copper, which can not only ensure the lightness and thinness of the conductive layer, thereby reducing the volume of the conductive layer, but also ensure that the conductive layer has good conductivity.
  • FIG. 3 is a schematic structural diagram of another 3D filter circuit provided by an embodiment of the present application. As shown in FIG. 3 , the 3D filter circuit further includes an encapsulation layer 200 ; the encapsulation layer 200 is configured to encapsulate the multilayer structure 100 .
  • the encapsulation layer 200 is wrapped outside the multilayer structure 100, and the multilayer structure 100 is encapsulated in the encapsulation layer 200, which can protect the multilayer structure 100 and prevent the multilayer structure 100 from being affected by various adverse factors of the external environment.
  • the working stability of the multilayer structure 100 is ensured, and the service life of the multilayer structure 100 is prolonged.
  • the encapsulation layer 200 includes an insulating dielectric layer 210 and a conductive structure 220; the insulating dielectric layer 210 wraps the multilayer structure 100; the insulating dielectric layer 210 is provided with a second through hole T2, and the second through hole T2
  • the conductive material is filled inside to form a conductive structure 220 , and at least two conductive layers 110 are connected to an external circuit through the second through hole T2 .
  • the at least two conductive layers 110 further include at least one third patterned structure 113 , and the third patterned structure 113 is connected to the conductive structure 220 .
  • the third patterned structure 113 can be used as the conductive layer 110 to form a part of the planar inductor L1 or The part in the conductive layer 110 is used to connect the capacitance C and the inductance in the multilayer structure 100 .
  • At least two layers of conductive layers 110 include at least one third patterned structure 113, that is, at least two layers of conductive layers 110 can form at least one planar inductor L1 or include at least one conductive layer for connecting the capacitance C and the inductor in the multilayer structure 100. part.
  • FIG. 1 , FIG. 2 and FIG. 3 are only exemplary schematic diagrams showing the structure of a 3D filter circuit including a multi-layer structure 100, and in other embodiments, the number of multi-layer structures 100 included in the 3D filter circuit may vary. Set according to actual needs.
  • the 3D filter includes the 3D filter circuit provided by any embodiment of the present application, and thus has the beneficial effects of the 3D filter circuit provided by the embodiment of the present application, and details are not repeated here.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
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  • Filters And Equalizers (AREA)

Abstract

本申请实施例公开了一种3D滤波电路与3D滤波器。该3D滤波电路包括多层结构；多层结构包括至少两层导电层和至少一层有机介质层，每层有机介质层设置于不同的导电层之间；多层结构被设置为形成至少一个电容。

Description

3D滤波电路与3D滤波器
本申请要求在2021年06月21日提交中国专利局、申请号为202110685700.9的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及信号处理技术领域，例如3D滤波电路与3D滤波器。
背景技术
滤波器在无线通信中的应用极为广泛，是无线通讯射频前端中必不可少的元器件。随着5G、物联网等无线通信领域的飞速发展，滤波器在射频前端中的需求数量大大提升，由此对滤波器小型化和高性能的要求越来越高。
发明内容
本申请实施例提供一种3D滤波电路与3D滤波器，以实现滤波电路的小型化及高性能的设计要求。
第一方面，本申请实施例提供了一种3D滤波电路，包括多层结构；
多层结构包括至少两层导电层和至少一层有机介质层，每层有机介质层设置于不同的导电层之间；多层结构被设置为形成至少一个电容。
第二方面，本申请实施例还提供了一种3D滤波器，包括第一方面任意实施例提供的3D滤波电路。
附图说明
下面将对实施例或相关技术描述中所需要使用的附图做介绍，下面描述中的附图虽然是本申请的一些实施例，对于本领域的技术人员来说，可以根据本申请的各种实施例所揭示和提示的器件结构，驱动方法和制造方法的基本概念，拓展和延伸到其它的结构和附图，这些都在本申请的权利要求范围之内。
图1为本申请实施例提供的一种3D滤波电路的结构示意图；
图2为本申请实施例提供的另一种3D滤波电路的结构示意图；
图3为本申请实施例提供的另一种3D滤波电路的结构示意图；
图4为本申请实施例提供的另一种3D滤波电路的结构示意图；
图5为本申请实施例提供的另一种3D滤波电路的结构示意图。
图中：
100、多层结构；110、导电层；111、第一图案化结构；112、第二图案化结构；113、第三图案化结构；120、有机介质层；
200、封装层；210、绝缘介质层；220、导电结构。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例进行描述，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供了一种3D滤波电路，图1为本申请实施例提供的一种3D滤波电路的结构示意图。如图1所示，该3D滤波电路包括多层结构100；多层结构100包括至少两层导电层110和至少一层有机介质层120，每层有机介质层120设置于不同的导电层110之间；多层结构100被设置为形成至少一个电容C。
本实施例中，多层结构100是由至少两层导电层110和至少一层有机介质层120组成的三维立体结构。在多层结构100采用的有机介质层120可以作为电容C基板之间的电介质。示例性的，多层结构100包括的至少一层有机介质层120设置于至少两层导电层110之间，在至少两层导电层110与至少一层有机介质层120的垂直投影交叠部位可以形成至少一个电容C。其中，至少两层导电层110与至少一层有机介质层120垂直投影交叠部位的导电层110作为电容C的电极板，至少两层导电层110与至少一层有机介质层120垂直投影交叠部位的有机介质层120作为电容C的电介质。多层结构100采用的有机介质层120的材料种类广泛，可选择性强，成本较低。此外，有机介质层120具有多样化的组成结构和宽广的调节空间性能，能够很好地调节电容C的性能，使电容C满足高性能的要求。综上，3D滤波电路采用至少一个多层结构100构成，能够提高电容C的集成度，从而实现滤波电路的小型化及高性能的设计要求。
示例性的，图2为本申请实施例提供的另一种3D滤波电路的结构示意图。如图2所示，多层结构100是由三层导电层110和两层有机介质层120组成的三维立体结构，其中每两层导电层110之间设置一层有机介质层120。本方案的多层结构100可形成三个电容C。
需要说明的是，图1示例性的示出了多层结构100包含两层导电层110和 一层有机介质层120形成具有一个电容C的情况，图2示例性的示出了多层结构100包含三层导电层110和两层有机介质层120形成具有三个电容C的情况，在其他实施例中多层结构100中包含导电层110和设置在每层导电层110之间的导电介质层数量可根据实际需要进行设置，多层结构100内形成的电容C数量可根据实际需要进行设置。
可选地，继续参考图1或图2，至少两层导电层110包括多个第一图案化结构111，不同的导电层110中的第一图案化结构111在有机介质层120上的垂直投影交叠，不同的导电层110中的第一图案化结构111在有机介质层120上的垂直投影交叠部位被设置为形成多个电容C。
在一实施例中，当多层结构100形成多个器件结构时，不同的器件结构可以通过导电层110中不同的图案化结构形成，避免不同的器件结构之间短路。示例性的，图1中的一层导电层110包括一个第一图案化结构111，其中第一图案化结构111为：至少两层导电层110与至少一层有机介质层120垂直投影交叠部位的导电层110。若至少两层导电层110包括多个第一图案化结构111，不同的导电层110中的多个第一图案化结构111在有机介质层120上的垂直投影交叠部位可以形成多个电容C。由此，多层结构100中可以集中设置多个电容C，不仅满足了3D滤波电路对电容C的需求以保证3D滤波电路高性能的设计要求，还实现了3D滤波电路的小型化。
可选地，继续参考图1或图2，至少两层导电层110还被设置为形成平面电感L1和3D电感L2中的至少一个。
本实施例中，多层结构100中的导电层110可以形成电感。可选地，电感的种类包括平面电感L1和3D电感L2。平面电感L1是由单层导电层110构成的，3D电感L2是由至少两层导电层110电连接构成的。综上，多层结构100中的至少两层导电层110可以集中设置平面电感L1和3D电感L2中的至少一个，不仅满足了3D滤波电路对电感的需求以保证3D滤波电路高性能的设计要求，还实现了3D滤波电路的小型化。
可选地，继续参考图1或图2，多层结构100包括3D电感L2，有机介质层120上设置有第一通孔T1，第一通孔T1内填充有导电材料；每层导电层110包括至少一个第二图案化结构112，不同的导电层110中的第二图案化结构112通过第一通孔T1连接，被设置为形成至少一个3D电感L2。
本实施例中，多层结构100包括至少两层导电层110和至少一层有机介质层120，有机介质层120设置在至少两层导电介质层之间。多层结构100包括3D电感L2，需要将多层结构100包括的至少两层导电层110电连接。可选地，可以在有机介质层120上设置第一通孔T1，并在第一通孔T1内填充导电材料， 使不同层的导电层110通过第一通孔T1实现电连接，从而形成3D电感L2。为避免不同的器件结构之间短路，不同的器件结构通过导电层110中不同的图案化结构形成，例如将通过第一通孔T1实现电连接的不同层的导电层110部分作为第二图案化结构112。多层结构100包括的每一层导电层110包括至少一个第二图案化结构112，若是不同的导电层110中的第二图案化结构112通过第一通孔T1连接，可以形成至少一个3D电感L2。综上，多层结构100中的至少两层导电层110可以集中设置至少一个3D电感L2，提高了电感设置的紧凑性，实现3D滤波电路的小型化。
可选地，有机介质层的材料包括有环氧树脂、PPE树脂和PI树脂中至少之一。
本实施例中，有机介质层采用的材料具有很好的绝缘性，例如环氧树脂、PPE树脂、PI树脂。其中，环氧树脂具有优良的绝缘性能、力学性能及化学稳定性等；PPE树脂介电性能居工程塑料之首，具有良好的机械性能、热性能、耐水性以及阻燃性性等；PI树脂绝缘性稳定，具有抗腐蚀、耐高温、耐磨损、耐冲击、使用寿命長等特点。综上，有机介质层的材料采用环氧树脂、PPE树脂、PI树脂等，能够很好地充当电容的电介质材料，保证电容两极板间的绝缘。
可选地，导电层的材料包括铜箔或电镀铜。
本实施例中，铜箔或电镀铜可以附着与各种不同基材，如金属，绝缘材料等，拥有较宽的温度使用范围。将导电铜箔置于衬底面，结合金属基材，具有优良的导通性，并提供电磁屏蔽的效果；将电解液中的铜离子镀于衬底表面，可以获得较薄的、细致光滑的铜镀层，具有良好的导电性。导电层的材料采用铜箔或电镀铜，既可以保证导电层的轻薄，从而减小导电层的体积，还可以保证导电层具有良好的导电性。
图3为本申请实施例提供的另一种3D滤波电路的结构示意图，如图3所示，3D滤波电路还包括封装层200；封装层200被设置为封装多层结构100。
本实施例中，封装层200包裹在多层结构100外部，将多层结构100封装在封装层200内，可以保护多层结构100，防止多层结构100受到外界环境各种不利因素的影响，保证多层结构100工作的稳定性，延长多层结构100的使用寿命。
可选地，继续参考图3，封装层200包括绝缘介质层210和导电结构220；绝缘介质层210包裹多层结构100；绝缘介质层210上设置有第二通孔T2，第二通孔T2内填充有导电材料被设置为形成导电结构220，至少两层导电层110通过第二通孔T2与外部电路连接。
本实施例中，封装层200由绝缘介质层210和导电结构220构成。可选地，绝缘介质包裹在多层结构100的外部，多层结构100需要与外部电路进行电连接，由此需要在绝缘介质层210上设置第二通孔T2，并在第二通孔T2内填充导电材料，从而形成用于导通多层结构100与外部电路的导电结构220。多层结构100的至少两层导电层110可以通过第二通孔T2与外部设备电路连接，实现电信号的传输。
可选地，继续参考图3，至少两层导电层110还包括至少一个第三图案化结构113，第三图案化结构113与导电结构220连接。
本实施例中，为避免不同的器件结构之间短路，不同的器件结构通过导电层110中不同的图案化结构形成，例如第三图案化结构113可以作为导电层110形成平面电感L1的部分或导电层110内用于连接多层结构100内电容C和电感的部分。至少两层导电层110包括至少一个第三图案化结构113，也就是至少两层导电层110可以形成至少一个平面电感L1或至少包括一个用于连接多层结构100内的电容C和电感的导电部分。第三图案化结构113与导电结构220连接，可以实现不同的多层结构100的第三图案化结构113之间通过导电结构220连接。或者第三图案化结构113与导电结构220连接，实现由第三图案化结构113形成的平面电感L1与导电结构220连接，从而使平面电感L1通过导电结构220与外部电路连接，实现电信号的传输。
需要说明的是图1、图2和图3只是示例性的示出了3D滤波电路包含一个多层结构100的结构示意图，在其他实施例中3D滤波电路中包含的多层结构100的数量可根据实际需要进行设置。
图4为本申请实施例提供的另一种3D滤波电路的结构示意图，图4为本申请实施例提供的另一种3D滤波电路的结构示意图。图5为示例性的示出3D滤波电路包含两个多层结构的结构示意图，图5为示例性的示出3D滤波电路包含三个多层结构的结构示意图。
本申请实施例还提供了一种3D滤波器，包括上述实施例中任一项的3D滤波电路。
3D滤波器包括本申请任意实施例提供的3D滤波电路，因此具有本申请实施例提供的3D滤波电路的有益效果，此处不再赘述。

Claims (10)

  1. 一种3D滤波电路，包括多层结构；
    所述多层结构包括至少两层导电层和至少一层有机介质层，每层所述有机介质层设置于不同的所述导电层之间；所述多层结构被设置为形成至少一个电容。
  2. 根据权利要求1所述的3D滤波电路，其中，至少两层所述导电层包括多个第一图案化结构，不同的所述导电层中的第一图案化结构在所述有机介质层上的垂直投影交叠，不同的所述导电层中的第一图案化结构在所述有机介质层上的垂直投影交叠部位被设置为形成多个电容。
  3. 根据权利要求1所述的3D滤波电路，其中，至少两层所述导电层还被设置为形成平面电感和3D电感中的至少一个。
  4. 根据权利要求3所述的3D滤波电路，其中，所述多层结构包括所述3D电感，所述有机介质层上设置有第一通孔，所述第一通孔内填充有导电材料；每一层所述导电层包括至少一个第二图案化结构，不同的所述导电层中的第二图案化结构通过所述第一通孔连接，被设置为形成至少一个所述3D电感。
  5. 根据权利要求1所述的3D滤波电路，其中，所述有机介质层的材料包括环氧树脂、PPE树脂和PI树脂中至少之一。
  6. 根据权利要求1所述的3D滤波电路，其中，所述导电层的材料包括铜箔或电镀铜。
  7. 根据权利要求1所述的3D滤波电路，还包括封装层；
    所述封装层被设置为封装所述多层结构。
  8. 根据权利要求7所述的3D滤波电路，其中，所述封装层包括绝缘介质层和导电结构；
    所述绝缘介质层包裹所述多层结构；所述绝缘介质层上设置有第二通孔，所述第二通孔内填充有导电材料被设置为形成所述导电结构，至少两层所述导电层通过所述第二通孔与外部电路连接。
  9. 根据权利要求8所述的3D滤波电路，其中，至少两层所述导电层还包括至少一个第三图案化结构，所述第三图案化结构与所述导电结构连接。
  10. 一种3D滤波器，包括权利要求1-9任一项所述的3D滤波电路。
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