WO2022267159A1 - 阵列基板、阵列基板制造方法及显示面板 - Google Patents

阵列基板、阵列基板制造方法及显示面板 Download PDF

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Publication number
WO2022267159A1
WO2022267159A1 PCT/CN2021/108358 CN2021108358W WO2022267159A1 WO 2022267159 A1 WO2022267159 A1 WO 2022267159A1 CN 2021108358 W CN2021108358 W CN 2021108358W WO 2022267159 A1 WO2022267159 A1 WO 2022267159A1
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Prior art keywords
electrode plate
insulating layer
layer
electrode
array substrate
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Ceased
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PCT/CN2021/108358
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English (en)
French (fr)
Inventor
龚帆
艾飞
宋继越
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US17/593,659 priority Critical patent/US12191324B2/en
Publication of WO2022267159A1 publication Critical patent/WO2022267159A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/107—Integrated devices having multiple elements covered by H10F30/00 in a repetitive configuration, e.g. radiation detectors comprising photodiode arrays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/016—Manufacture or treatment of image sensors covered by group H10F39/12 of thin-film-based image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/13—Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance

Definitions

  • the present application relates to the display field, and in particular to an array substrate, a method for manufacturing the array substrate, and a display panel.
  • Embodiments of the present application provide an array substrate, a method for manufacturing the array substrate, and a display panel, which solve the current problem that the ambient light sensor is integrated into the display panel with many film layers and complicated processes.
  • An embodiment of the present application provides an array substrate, including:
  • a thin film transistor disposed on the substrate, including a gate, an active layer, a source and a drain;
  • a photosensitive sensor includes a photosensitive module and a storage module, the photosensitive module includes a photosensitive semiconductor layer, and the storage module includes a first electrode plate and a second electrode plate;
  • the photosensitive semiconductor layer is disposed on the extension of the drain, the first electrode plate is electrically connected to a side of the photosensitive semiconductor layer away from the extension of the drain, and the second electrode plate is electrically connected to the drain.
  • the embodiment of the present application also provides a method for manufacturing an array substrate, including the following manufacturing steps:
  • Step S100 providing a base substrate, and fabricating a thin film transistor on the base substrate, the thin film transistor including a gate, an active layer, a source and a drain connected to the active layer;
  • Step S200 forming a photosensitive semiconductor layer on the extension of the drain
  • Step S300 forming a first insulating layer on the photosensitive semiconductor layer, forming a first metal layer with a patterned shape on the first insulating layer, the first metal layer including a first electrode plate and a second electrode one of the boards;
  • Step S400 forming a second insulating layer on the first metal layer, forming a second metal layer with a patterned shape on the second insulating layer, the second metal layer including the first electrode plate and In the other of the second electrode plates, the first electrode plate is electrically connected to the photosensitive semiconductor layer through a via hole, and the second electrode plate is electrically connected to the drain electrode through another via hole; the first electrode plate is electrically connected to the photosensitive semiconductor layer through another via hole; The electrode plate and the second electrode plate form a storage capacitor.
  • the embodiment of the present application also provides a display panel, including an array substrate; wherein, the array substrate includes:
  • a thin film transistor disposed on the substrate, including a gate, an active layer, a source and a drain connected to the active layer;
  • a photosensitive sensor includes a photosensitive module and a storage module, the photosensitive module includes a photosensitive semiconductor layer, and the storage module includes a first electrode plate and a second electrode plate;
  • the photosensitive semiconductor layer is disposed on the extension of the drain, the first electrode plate is electrically connected to a side of the photosensitive semiconductor layer away from the extension of the drain, and the second electrode plate is electrically connected to the drain.
  • an array substrate a method for manufacturing the array substrate, and a display panel are provided.
  • the photosensitive semiconductor layer is arranged on the extension part of the drain, and one side electrode of the photosensitive semiconductor is in the same layer as the drain, which reduces the number of film layers of the photosensitive sensor and can reduce the number of manufacturing processes of the array substrate.
  • FIG. 1 is a schematic diagram of the first structure of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a second structure of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a third structure of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the process steps of an array substrate manufacturing method provided by an embodiment of the present application.
  • 5 to 16 are schematic diagrams of the manufacturing process of the array substrate provided by an embodiment of the present application.
  • FIG. 17 is a schematic diagram of a display panel provided by an embodiment of the present application.
  • An embodiment of the present application provides an array substrate, including: a substrate; a thin film transistor disposed on the substrate, including a gate, an active layer, a source and a drain connected to the active layer; a photosensitive sensor, the photosensitive sensor includes a photosensitive module and a memory module, the photosensitive module includes a photosensitive semiconductor layer, and the memory module includes a first electrode plate and a second electrode plate; wherein the photosensitive semiconductor layer is arranged on the extension of the drain, and the first electrode plate is electrically connected to the photosensitive semiconductor layer away from the drain One side of the extended part of the pole, and the second electrode plate is electrically connected to the drain.
  • Embodiments of the present application provide an array substrate, a method for manufacturing the array substrate, and a display panel. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • FIG. 1 is a schematic diagram of a first structure of an array substrate provided by an embodiment of the present application.
  • the array substrate 10 includes a substrate 11 , a thin film transistor 20 and a photosensor 100 .
  • the thin film transistor 20 is arranged on the substrate 11, and the thin film transistor 20 includes a gate 22, an active layer 21, a source 23 and a drain 24 connected to the active layer 21;
  • the photosensitive sensor 100 includes a photosensitive module 30 and a memory module 40, and the photosensitive module 30 includes a photosensitive semiconductor layer 31, and the memory module 40 includes a first electrode plate 41 and a second electrode plate 42; wherein, the photosensitive semiconductor layer 31 is arranged on the extension portion 241 of the drain, and the first electrode plate 41 is electrically connected to the photosensitive semiconductor layer 31 away from the side of the extension portion 241 of the drain 24 , the second electrode plate 42 is electrically connected to the drain 24 .
  • the storage module 40 includes a storage capacitor 412 , and the first electrode plate 41 and the second electrode plate 42 constitute the storage capacitor 412 .
  • the thin film transistor 20 is disposed on the substrate 11 , and the thin film transistor 20 includes a gate 22 , an active layer 21 , a source 23 and a drain 24 .
  • the substrate 11 may be made of glass or other materials, and the TFT 20 may be a top-gate TFT, a bottom-gate transistor, etc.
  • the type of the TFT 20 is not limited here.
  • the material of the active layer 21 can be polysilicon, amorphous silicon, metal oxide semiconductor and the like.
  • the drain 24 has an extension 241
  • the photosensitive semiconductor layer 31 is disposed on the extension 241 of the drain 24, and the extension 241 of the drain 24 is used as an electrode on one side of the photosensitive module 30 or for transmitting the photosensitive semiconductor layer 31.
  • electrical signal The first electrode plate 41 is electrically connected to the side of the photosensitive semiconductor layer 31 away from the extension portion 241 of the drain 24, and the part where the first electrode plate 41 is connected to the photosensitive semiconductor layer 31 is used as the other side electrode of the photosensitive module 30 or used for transmitting light.
  • the electrical signal of the semiconductor layer 31 is electrically connected to the side of the photosensitive semiconductor layer 31 away from the extension portion 241 of the drain 24, and the part where the first electrode plate 41 is connected to the photosensitive semiconductor layer 31 is used as the other side electrode of the photosensitive module 30 or used for transmitting light.
  • the storage module 40 includes a first electrode plate 41 and a second electrode plate 42
  • the storage module 40 includes a storage capacitor 412
  • the first electrode plate 41 and the second electrode plate 42 constitute the storage capacitor 412, that is, the first electrode plate 41 and the second electrode plate 42 form a storage capacitor 412.
  • An insulating layer is disposed between the second electrode plates 42 , and the orthographic projection of the first electrode plate 41 on the base 11 overlaps with the orthographic projection of the second electrode plate 42 on the base 11 to form a storage capacitor 412 .
  • the array substrate 10 includes: a light shielding layer 12 disposed on the base, a buffer layer 13 disposed on the light shielding layer 12, an active layer 21 disposed on the buffer layer 13,
  • the gate insulating layer 14 provided on the active layer 21, the gate 22 provided on the gate insulating layer 14, the interlayer insulating layer 15 provided on the gate 22, the source provided on the interlayer insulating layer 15 electrode 23 and drain electrode 24, the protective insulating layer 16 arranged on the source electrode 23 and the drain electrode 24, the photosensitive semiconductor layer 31 arranged on the extension portion 241 of the drain electrode 24, the cover insulating layer arranged on the photosensitive semiconductor layer 31 17.
  • the protective insulating layer 16 has an opening exposing the extension 241 of the drain 24, and the photosensitive semiconductor layer 31 is disposed on the opening of the protective insulating layer 16 and contacts the extension 241 of the drain 24; the array substrate 10 may not include a protective The insulating layer 16, when the array substrate is manufactured, after the source electrode 23 and the drain electrode 24 are manufactured, the photosensitive semiconductor layer 31 is directly formed on the extension portion 241 of the drain electrode 24; the protective insulating layer, the covering insulating layer 17 and the second insulating layer
  • the material of 19 can be an inorganic insulating material, for example, one or both of silicon nitride (SiN x ) and silicon oxide (SiO x ); the material of the planar layer 18 can be an organic material, specifically an
  • the photosensitive semiconductor layer 31 is made of amorphous silicon.
  • amorphous silicon has a high absorption coefficient in the visible region, and basically does not absorb light in the infrared region, which perfectly matches human vision. Therefore, using amorphous silicon as a photosensitive layer can perfectly match the ambient light sensor. After the amorphous silicon absorbs ambient light, photocurrent will be generated between the first electrode plate 41 and the extension part 241 of the drain 24 , so that the photosensitive semiconductor layer 31 forms a conductive channel.
  • the photosensitive semiconductor layer 31 includes N-type amorphous silicon 32 disposed on the extension portion 241 of the drain 24 , and intrinsic amorphous silicon 33 disposed on the N-type amorphous silicon 32 .
  • the N-type amorphous silicon 32 is doped with pentavalent elements, such as phosphorus and arsenic, in the amorphous silicon. Intrinsic amorphous silicon 33 is not doped with other elements. Using intrinsic amorphous silicon 33 to absorb ambient light generates photoelectrons and holes. N-type amorphous silicon 32 has excess electrons to increase the current in the photosensitive semiconductor layer 31. , thereby improving the sensitivity of the photosensor 100 .
  • the photosensitive semiconductor layer 31 includes an N-type amorphous silicon 32 disposed on the extension portion 241 of the drain 24, an intrinsic amorphous silicon 33 disposed on the N-type amorphous silicon 32, and an intrinsic amorphous silicon 33 disposed on the N-type amorphous silicon 32.
  • the P-type amorphous silicon 34 is doped with trivalent elements, such as boron, gallium, etc., in the amorphous silicon. Intrinsic amorphous silicon 33 is not doped with other elements. Using intrinsic amorphous silicon 33 to absorb ambient light generates photoelectrons and holes. P-type amorphous silicon 34 has redundant holes that can increase the current in the photosensitive semiconductor layer 31. size.
  • the photosensitive semiconductor layer uses a three-layer structure of N-type amorphous silicon 32 , intrinsic amorphous silicon 33 , and P-type amorphous silicon 34 , which can further improve the sensitivity of the photosensitive sensor 100 .
  • the photosensitive semiconductor layer 31 may only include intrinsic amorphous silicon 33 , or a two-layer structure including intrinsic amorphous silicon 33 and P-type amorphous silicon 34 .
  • the array substrate 10 also includes a first insulating layer and a second insulating layer 19, the first insulating layer is disposed on the photosensitive semiconductor layer 31 and the thin film transistor 20, and the second electrode plate 42 is disposed on the first insulating layer ;
  • the second insulating layer 19 is arranged on the second electrode plate 42, the first electrode plate 41 is arranged on the second insulating layer 19, and the first electrode plate passes through the first via hole 51 in the first insulating layer and the second insulating layer Connect the photosensitive semiconductor layer.
  • the first insulating layer in FIG. 1 is the covering insulating layer 17 and the flat layer 18.
  • the array substrate may be provided with only one of the covering insulating layer 17 and the flat layer 18.
  • the first The insulating layer is one of the covering insulating layer 17 and the planar layer 18 .
  • the array substrate 10 further includes a connection electrode 43, the connection electrode 43 is disposed on the second insulating layer 19, the second insulating layer 19 includes a second via hole 52, and the first insulating layer and the second insulating layer 19 also A third via hole 53 is included, one end of the connection electrode 43 is connected to the second electrode plate 42 through the second via hole 52 , and the other end of the connection electrode 43 is connected to the drain electrode 24 through the third via hole 53 .
  • the third via hole 53 in FIG. 1 also penetrates the protective insulating layer 16 .
  • the drain 24 has an extension 241
  • the photosensitive semiconductor layer 31 is disposed on the extension 241 of the drain 24, and the extension 241 of the drain 24 is used as one side electrode of the photosensitive module 30 or used for transmitting
  • the electrical signal of the photosensitive semiconductor layer 31 reduces the number of film layers of the photosensitive sensor, which can reduce the number of manufacturing processes of the array substrate and save photomasks.
  • the first electrode plate 41 is electrically connected to the side of the photosensitive semiconductor layer 31 away from the extension portion 241 of the drain 24 through the first via hole 51, and the part where the first electrode plate 41 is connected to the photosensitive semiconductor layer 31 (the first via hole 51) as the electrode on the other side of the photosensitive module 30 or used to transmit the electrical signal of the photosensitive semiconductor layer 31, which further reduces the number of film layers of the photosensitive sensor, reduces the number of manufacturing processes of the array substrate, and saves light. cover.
  • FIG. 2 is a schematic diagram of the second structure of the array substrate provided by the embodiment of the present application.
  • the array substrate 10 of the embodiment of the present application is the same or similar to the first embodiment.
  • the connection relationship between the second electrode plate 42 and the drain electrode 24 is different.
  • the first insulating layer includes a fourth via hole 54 through which the second electrode plate 42 is connected to the drain electrode 24 .
  • the first insulation in FIG. 2 is the covering insulating layer 17 and the flat layer 18.
  • the array substrate 10 may only be provided with one of the covering insulating layer 17 and the flat layer 18.
  • the first insulating The layer is one of the covering insulating layer 17 and the flat layer 18 .
  • connection electrode 43 there is no connection electrode 43 in the first embodiment, and the second electrode plate 42 is directly connected to the drain electrode 24 through the fourth via hole 54 in the first insulating layer.
  • the fourth via hole 54 also penetrates through the protective insulating layer 16 .
  • connection electrode 43 is removed in the embodiment of the present application, which further simplifies the film layer structure of the array substrate, and facilitates the manufacture and operation of the array substrate.
  • Layout is conducive to improving yield.
  • FIG. 3 is a schematic diagram of the third structure of the array substrate provided by the embodiment of the present application.
  • the array substrate 10 of the embodiment of the present application is the same or similar to the first and second embodiments, and the similarities will not be repeated here. The difference is that the positional relationship between the first electrode plate 41 and the second electrode plate 42 is different.
  • the first insulating layer is disposed on the photosensitive semiconductor layer 31 and the thin film transistor 20 , and the first electrode plate 41 is disposed on the first insulating layer.
  • the first insulation in FIG. 3 is the covering insulating layer 17 and the flat layer 18.
  • the array substrate may only be provided with one of the covering insulating layer 17 and the flat layer 18.
  • the first insulating layer It is one of the covering insulating layer 17 and the flat layer 18 .
  • the second insulating layer 19 is disposed on the first electrode plate 41, the second electrode plate 42 is disposed on the second insulating layer 19, and the first electrode plate 41 is connected to the photosensitive semiconductor layer 31 through the fifth via hole 55 in the first insulating layer. , the second electrode plate 42 is connected to the drain 24 through the sixth via hole 56 in the first insulating layer and the second insulating layer 19 .
  • the first electrode plate 41 is disposed on the first insulating layer, and the second electrode plate 42 is disposed on the second insulating layer 19.
  • an array with photosensitive sensors 100 is proposed
  • the structure of the substrate 10 has the same beneficial effects as those of the first and second embodiments, and will not be repeated here.
  • the array substrate 10 further includes a common electrode and a pixel electrode, and two configurations of the common electrode and the pixel electrode will be described below.
  • the common electrode is arranged on the first insulating layer; the pixel electrode is arranged on the second insulating layer; wherein, the common electrode and the corresponding electrode plate on the first insulating layer are made of the same metal, and the pixel electrode and the second insulating layer are made of the same metal.
  • the corresponding electrode plates on layer 19 are made of the same metal.
  • the second electrode plate 42 is disposed on the first insulating layer, the common electrode is disposed on the first insulating layer, and the common electrode and the second electrode plate 42 are made of the same metal;
  • the first The electrode plate 41 is disposed on the second insulating layer 19 , the pixel electrode is disposed on the second insulating layer 19 , and the pixel electrode and the first electrode plate 41 are made of the same metal.
  • the first electrode plate 41 is arranged on the first insulating layer, the common electrode is arranged on the first insulating layer, and the common electrode and the first electrode plate 41 are made of the same metal;
  • the second electrode plate 42 is disposed on the second insulating layer 19, the pixel electrode is disposed on the second insulating layer 19, and the pixel electrode and the second electrode plate 42 are made of the same metal.
  • the pixel electrode is arranged on the first insulating layer; the common electrode is arranged on the second insulating layer 19; wherein, the pixel electrode and the corresponding electrode plate on the first insulating layer are made of the same metal, and the common electrode and the second insulating layer are made of the same metal.
  • the corresponding electrode plates on the insulating layer 19 are made of the same metal.
  • the second electrode plate 42 is disposed on the first insulating layer, the pixel electrode is disposed on the first insulating layer, and the pixel electrode and the second electrode plate 42 are made of the same metal;
  • the first The electrode plate 41 is disposed on the second insulating layer 19 , the common electrode is disposed on the second insulating layer 19 , and the common electrode and the first electrode plate 41 are made of the same metal.
  • the first electrode plate 41 is disposed on the first insulating layer, the pixel electrode is disposed on the first insulating layer, and the pixel electrode and the first electrode plate 41 are made of the same metal;
  • the second electrode plate 42 is disposed on the second insulating layer 19 , the common electrode is disposed on the second insulating layer 19 , and the common electrode and the second electrode plate 42 are made of the same metal.
  • the orthographic projection of the first electrode plate 41 on the substrate 11 and the orthographic projection of the photosensitive semiconductor layer 31 on the substrate at least partially overlap
  • the material of the first electrode plate 41 is translucent or transparent, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), fluorine tin oxide (FTO), etc. Any one of them, so that ambient light can pass through the first electrode plate 41 and reach the photosensitive semiconductor layer 31 .
  • the first electrode plate 41 is electrically connected to the common electrode, that is, the first electrode plate 41 supplies electrical signals through the common electrode.
  • the common electrode and the corresponding electrode plate on the first insulating layer are made of the same metal, and the pixel electrode and the corresponding electrode plate on the second insulating layer 19 are made of the same metal; or
  • the electrode and the corresponding electrode plate on the first insulating layer are made of the same metal, and the common electrode and the corresponding electrode plate on the second insulating layer 19 are made of the same metal, which can further reduce the number of film layers and film layers of the array substrate 10 and the photosensitive sensor.
  • Layer complexity reduces the manufacturing process of the array substrate 10 including the photosensor 100 and reduces the photomask.
  • FIG. 4 is a schematic flow diagram of a method for manufacturing an array substrate according to an embodiment of the present application.
  • the method for manufacturing an array substrate includes step S100 , step S200 , step S300 , and step S400 .
  • 5 to 16 are schematic views of the manufacturing process of the array substrate.
  • Step S100 providing a base substrate, and manufacturing a thin film transistor on the base substrate.
  • the thin film transistor includes a gate, an active layer, a source and a drain connected to the active layer.
  • a light-shielding layer 12 is made on the substrate 11, and a patterned light-shielding layer 12 is formed by means of exposure etching; as shown in Figure 6, a buffer layer 13 is prepared on the light-shielding layer 12, and Active layer 21, adopt exposure etching method to form patterned active layer 21, the material of active layer 21 can be polysilicon, amorphous silicon, metal oxide semiconductor etc., when active layer 21 is polysilicon, can also comprise Carry out P-type ion doping to polysilicon, form N-type polysilicon, make active layer 21 form ohmic contact easily; As shown in Figure 7, form gate insulating layer 14 on active layer 21, on gate insulating layer 14 Form gate 22; As shown in Figure 8, form interlayer insulating layer 15 on gate 22, interlayer insulating layer 15 comprises the via hole that connects active layer; As shown in Figure 9, on interlayer insulating layer 15 The source 23 , the drain 24 and the extension 24
  • Step S200 forming a photosensitive semiconductor layer on the extension of the drain.
  • the protective insulating layer 16 is formed on the source 23, the drain 24 and the extension 241 of the drain 24, and the protective insulating layer 16 has an opening 161 exposing the extension 241 of the drain 24; As shown in FIG. 12 , the photosensitive semiconductor layer 31 is formed on the extension 241 of the drain 24 of the opening 161 .
  • the photosensitive semiconductor layer 31 includes N-type amorphous silicon 32 disposed on the extension portion 241 of the drain 24 , and intrinsic amorphous silicon 33 disposed on the N-type amorphous silicon 32 .
  • the photosensitive semiconductor layer 31 includes N-type amorphous silicon 32 disposed on the extension 241 of the drain 24, intrinsic amorphous silicon 33 disposed on the N-type amorphous silicon 32, and P-type amorphous silicon 34 disposed on intrinsic amorphous silicon 33 .
  • the photosensitive semiconductor layer 31 may only include intrinsic amorphous silicon 33 , or include a two-layer structure of intrinsic amorphous silicon 33 and P-type amorphous silicon 34 .
  • Step S300 forming a first insulating layer on the photosensitive semiconductor layer, forming a first metal layer with a patterned shape on the first insulating layer, the first metal layer including a first electrode plate and a second electrode one of the boards;
  • a first insulating layer is formed on the photosensitive semiconductor layer 31, and the first insulating layer may include a cover insulating layer 17 disposed on the photosensitive semiconductor layer 31 and a planar layer disposed on the cover insulating layer 17. 18, wherein only one of the cover insulating layer 17 and the planar layer 18 may be provided, or both may be provided, and the cover insulating layer 17 and/or the planar layer 18 are the first insulating layer.
  • a first metal layer is formed on the first insulating layer, the first metal layer has a patterned shape, and the first metal layer includes one of the first electrode plate 41 and the second electrode plate 42 .
  • the first insulating layer when making the first insulating layer, includes a first preset via hole 511 and a second preset via hole 531, and the second preset via hole 531 also penetrates the protective insulating layer. 16.
  • Step S400 forming a second insulating layer on the first metal layer, forming a second metal layer with a patterned shape on the second insulating layer, the second metal layer including the first electrode plate and In the other of the second electrode plates, the first electrode plate is electrically connected to the photosensitive semiconductor layer through a via hole, and the second electrode plate is electrically connected to the drain electrode through another via hole; the first electrode plate is electrically connected to the photosensitive semiconductor layer through another via hole; The electrode plate and the second electrode plate form a storage capacitor.
  • a second insulating layer 19 is formed on the first metal layer; as shown in FIG. 16 , a patterned second metal layer is formed on the second insulating layer.
  • the first metal layer includes one of the first electrode plate 41 and the second electrode plate 42
  • the second metal layer includes the other of the first electrode plate 41 and the second electrode plate 42
  • the first electrode plate 41 passes through
  • the via hole is electrically connected to the photosensitive semiconductor layer 31
  • the second electrode plate 42 is electrically connected to the drain electrode 24 through another via hole
  • the first electrode plate 41 and the second electrode plate 42 form a storage capacitor.
  • the second insulating layer 19 when making the second insulating layer 19, includes the third preset via hole 512 and the fourth preset via hole 532, and the first preset via hole 511 and the fourth preset via hole 532.
  • the three preset via holes 512 coaxially constitute the first via hole 51 in the above embodiment
  • the second preset via hole 531 and the fourth preset via hole 532 coaxially constitute the third via hole 53 in the above embodiment, here Taking the structure of the array substrate 10 in the first embodiment as an example, the manufacturing process of the array substrate 10 is illustrated in a drawing.
  • the array substrate described in any one of Embodiment 1, Embodiment 2, Embodiment 3, and Embodiment 4 can be manufactured by using the array substrate manufacturing method in the embodiment of the present application, the first electrode plate 41 and Please refer to Embodiment 1, Embodiment 2, Embodiment 3, and Embodiment 4 for the position or connection relationship of the second electrode plate 42 .
  • the array substrate 10 further includes a common electrode and a pixel electrode, and two configurations of the common electrode and the pixel electrode will be described below.
  • the common electrode is arranged on the first insulating layer; the pixel electrode is arranged on the second insulating layer; wherein, the common electrode and the corresponding electrode plate on the first insulating layer are made of the same metal, and the pixel electrode and the second insulating layer are made of the same metal.
  • the corresponding electrode plates on layer 19 are made of the same metal.
  • the pixel electrode is arranged on the first insulating layer; the common electrode is arranged on the second insulating layer 19; wherein, the pixel electrode and the corresponding electrode plate on the first insulating layer are made of the same metal, and the common electrode and the second insulating layer are made of the same metal.
  • the corresponding electrode plates on the insulating layer 19 are made of the same metal.
  • the fabrication process of the array substrate 10 is described by taking the top-gate polysilicon thin film transistor as an example.
  • the array substrate 10 including the photosensitive sensor 100 includes 12 photomasks. Only two photomasks are added to the array substrate of the sensor, so the process of the array substrate 10 including the photosensitive sensor 100 in the embodiment of the present application is simple and the number of photomasks is small.
  • the array substrate 10 with the photosensitive sensor 100 is manufactured by adopting the array substrate manufacturing method of the embodiment of the present application.
  • the drain 24 has an extension 241.
  • the photosensitive semiconductor layer 31 is arranged on the extension 241 of the drain 24.
  • the extension of the drain 24 The part 241 is used as one side electrode of the photosensitive module 30 or used to transmit the electrical signal of the photosensitive semiconductor layer 31, which reduces the number of film layers of the photosensitive sensor, reduces the number of manufacturing processes of the array substrate, and saves the number of photomasks.
  • the common electrode and the corresponding electrode plate on the first insulating layer 19 are made of the same metal, and the pixel electrode and the corresponding electrode plate on the second insulating layer 19 are made of the same metal ; or the pixel electrode and the corresponding electrode plate on the first insulating layer are made of the same metal, and the common electrode and the corresponding electrode plate on the second insulating layer 19 are made of the same metal, which can further reduce the film layer of the array substrate 10 and the photosensitive sensor The quantity reduces the number of manufacturing steps of the array substrate 10 including the photosensitive sensor 100 and saves the number of photomasks.
  • the array substrate manufacturing method of the embodiment of the present application to manufacture the array substrate 10 with the photosensitive sensor 100 has the effect of simple film layers, and the array substrate manufacturing method of the embodiment of the present application has the advantages of small number of steps, simple process, and saving the number of photomasks Effect.
  • FIG. 17 is a schematic diagram of a display panel 1000 provided by an embodiment of the present application.
  • the display panel 1000 includes any one of the array substrates 10 described in the above embodiments.
  • the display panel 1000 further includes a driving chip 103 , or the display panel 1000 is electrically connected to the driving chip 103 , and the second electrode plate is electrically connected to the driving chip through wires.
  • the second electrode plate 42 of the array substrate 10 is electrically connected to the driving chip 103 through wires.
  • one of the first electrode plate 41 and the second electrode plate 42 is electrically connected to the driver chip 103, and the first electrode plate 41 and the second electrode plate 41 are electrically connected to the driver chip 103.
  • the other of the two electrode plates 42 supplies an inherent signal.
  • the first electrode plate 41 is electrically connected to the common electrode of the array substrate or is supplied with a common electrode signal
  • the second electrode plate 42 is electrically connected to the driving chip 103 through wires.
  • the second electrode plate 42 is in a floating state (floating), the first electrode plate 41 is supplied with a common electrode signal, and the storage capacitor remains unchanged when no photocurrent is generated in the photosensitive semiconductor layer 31;
  • photocurrent is generated on the photosensitive semiconductor layer 31, and the charges in the first electrode plate 41 and the second electrode plate 42 flow, causing the size of the storage capacitor to change, and the size change of the storage capacitor passes through the second electrode.
  • the wiring connected to the board 42 is transmitted to the driver chip 103, and the driver chip 103 can judge whether the ambient light condition has changed or how small the change is based on the change in capacitance, and then the driver chip 103 takes a processing action on the display panel 1000, For example, adjusting the brightness of the display panel 1000 , and increasing the brightness of the display panel 1000 when the brightness of the ambient light is high can facilitate users to observe images better.
  • the display panel 1000 includes a display area 101 and a non-display area 102, and the photosensitive sensor 100 can be arranged in the non-display area 102, so that the photosensitive sensor 100 does not affect the pixel arrangement of the display area 101, thereby The photosensor 100 does not affect the aperture ratio of the pixels of the display panel 1000 .

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Abstract

本申请实施例公开了一种阵列基板、阵列基板制造方法及显示面板。阵列基板包括感光传感器，感光传感器包括感光模块和存储模块，感光模块包括感光半导体层，存储模块包括第一电极板和第二电极板；其中，感光半导体层设置于漏极的延伸部之上。本申请实施例减小了感光传感器的膜层数量，节省光罩。

Description

阵列基板、阵列基板制造方法及显示面板 技术领域
本申请涉及显示领域，具体涉及一种阵列基板、阵列基板制造方法及显示面板。
 背景技术
随着面板产业的迅猛发展，人们除了对显示器高分辨、宽视角、低功耗等要求外，也对显示面板提出了其它要求。丰富面板功能，增加人机互动，提高显示面板的竞争力，是目前显示面板的主要发展方向之一。将环境光感光传感器集成到显示面板，可以避免因外挂环境光感光传感器而在屏幕上打孔或缩减屏幕尺寸，避免了影响屏幕的美观和屏占比。然而当前环境光感光传感器集成在显示面板的膜层繁多，工艺复杂的问题。
 技术问题
本申请实施例提供了一种阵列基板、阵列基板制造方法及显示面板，解决了当前环境光感光传感器集成在显示面板的膜层繁多，工艺复杂的问题。
 技术解决方案
本申请实施例提供了一种阵列基板，包括：
基底；
薄膜晶体管，设于所述基底上，包括栅极、有源层、源极和漏极；
感光传感器，所述感光传感器包括感光模块和存储模块，所述感光模块包括感光半导体层，所述存储模块包括第一电极板和第二电极板；
其中，所述感光半导体层设置于所述漏极的延伸部之上，所述第一电极板电连接所述感光半导体层远离所述漏极的延伸部的一侧，所述第二电极板电连接所述漏极。
相应的，本申请实施例还提供了一种阵列基板制造方法，包括如下制造步骤：
步骤S100：提供一衬底基板，在所述衬底基板上制作薄膜晶体管，所述薄膜晶体管包括栅极、有源层、连接所述有源层的源极和漏极；
步骤S200：在所述漏极的延伸部上形成感光半导体层；
步骤S300：在所述感光半导体层上形成第一绝缘层，在所述第一绝缘层上形成具有图案化形状的第一金属层，所述第一金属层包括第一电极板和第二电极板中的一个；
步骤S400：在所述第一金属层上形成第二绝缘层，在所述第二绝缘层上形成具有图案化形状的第二金属层，所述第二金属层包括所述第一电极板和所述第二电极板中的另一个，所述第一电极板通过过孔电连接所述感光半导体层，所述第二电极板通过另一过孔电连接所述漏极；所述第一电极板和所述第二电极板构成存储电容。
相应的，本申请实施例还提供了一种显示面板，包括阵列基板；其中，所述阵列基板包括：
基底；
薄膜晶体管，设于所述基底上，包括栅极、有源层、连接所述有源层的源极和漏极；
感光传感器，所述感光传感器包括感光模块和存储模块，所述感光模块包括感光半导体层，所述存储模块包括第一电极板和第二电极板；
其中，所述感光半导体层设置于所述漏极的延伸部之上，所述第一电极板电连接所述感光半导体层远离所述漏极的延伸部的一侧，所述第二电极板电连接所述漏极。
 有益效果
本申请实施例中，提供了一种阵列基板、阵列基板制造方法及显示面板。感光半导体层设置于漏极的延伸部之上，感光半导体的一侧电极与漏极同层，减小了感光传感器的膜层数量，可以减小阵列基板的制作工序数量。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例提供的阵列基板的第一种结构示意图；
图2是本申请一实施例提供的阵列基板的第二种结构示意图；
图3是本申请一实施例提供的阵列基板的第三种结构示意图；
图4是本申请一实施例提供的一种阵列基板制造方法的流程步骤示意图；
图5至图16是本申请一实施例提供的阵列基板的制作过程的示意图；
图17是本申请一实施例提供的显示面板的示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
本申请实施例提供了一种阵列基板，包括：基底；薄膜晶体管，设于基底上，包括栅极、有源层、连接有源层的源极和漏极；感光传感器，感光传感器包括感光模块和存储模块，感光模块包括感光半导体层，存储模块包括第一电极板和第二电极板；其中，感光半导体层设置于漏极的延伸部之上，第一电极板电连接感光半导体层远离漏极的延伸部的一侧，第二电极板电连接漏极。
本申请实施例提供一种阵列基板、阵列基板制造方法及显示面板。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
实施例一、
请参阅图1，图1为本申请实施例提供的阵列基板的第一种结构示意图，阵列基板10包括基底11、薄膜晶体管20和感光传感器100。薄膜晶体管20设于基底11上，薄膜晶体管20包括栅极22、有源层21、连接有源层21的源极23和漏极24；感光传感器100包括感光模块30和存储模块40，感光模块30包括感光半导体层31，存储模块40包括第一电极板41和第二电极板42；其中，感光半导体层31设置于漏极的延伸部241之上，第一电极板41电连接感光半导体层31远离漏极24的延伸部241的一侧，第二电极板42电连接漏极24。
进一步的，存储模块40包括存储电容412，第一电极板41和第二电极板42构成存储电容412。
具体的，薄膜晶体管20设于基底11上，薄膜晶体管20包括栅极22、有源层21、源极23和漏极24。基底11可以为玻璃等材质，薄膜晶体管20可以为顶栅型薄膜晶体管、底栅型晶体管等，薄膜晶体管20的类型在此不做限定。有源层21的材质可以为多晶硅、非晶硅、金属氧化物半导体等。
具体的，漏极24具有一延伸部241，感光半导体层31设置于漏极24的延伸部241上，漏极24的延伸部241作为感光模块30的一侧电极或用于传递感光半导体层31的电信号。第一电极板41电连接感光半导体层31远离漏极24的延伸部241的一侧，第一电极板41与感光半导体层31连接的部位作为感光模块30的另一侧电极或用于传递感光半导体层31的电信号。
具体的，存储模块40包括第一电极板41和第二电极板42，存储模块40包括存储电容412，第一电极板41和第二电极板42构成存储电容412，即第一电极板41和第二电极板42之间设置有绝缘层，且第一电极板41在基底11上的正投影与第二电极板42在基底11上的正投影具有重叠部位，以构成存储电容412。
具体的，请参阅图1，本申请实施例中阵列基板10包括：设于基底上的遮光层12、设于遮光层12上的缓冲层13、设于缓冲层13上的有源层21、设于有源层21上的栅极绝缘层14、设于栅极绝缘层14上的栅极22、设于栅极22上的层间绝缘层15、设于层间绝缘层15上的源极23和漏极24、设于源极23和漏极24上的保护绝缘层16、设于漏极24的延伸部241上的感光半导体层31、设于感光半导体层31上的覆盖绝缘层17、设于覆盖绝缘层17上的平坦层18、设于平坦层18上的第二电极板42、设于第二电极板42上的第二绝缘层19、设于第二绝缘层19上的第一电极板41。其中，保护绝缘层16具有露出漏极24的延伸部241的开口，感光半导体层31设置于保护绝缘层16的开口上并与漏极24的延伸部241接触；阵列基板10也可以不包括保护绝缘层16，在阵列基板制作时，制作完源极23和漏极24后，直接在漏极24的延伸部241上制作感光半导体层31；保护绝缘层、覆盖绝缘层17和第二绝缘层19的材料可以为无机绝缘材料，例如包括氮化硅（SiN x）和氧化硅（SiO x）中的一种或两种；平坦层18的材料可以为有机材料，具体的可以为有机透明光阻材料；其中，覆盖绝缘层17和平坦层18可以只设置其中之一，也可以两者都设置，第二电极板42与感光半导体层之间的绝缘层称之为第一绝缘层，因此，覆盖绝缘层17或/和平坦层18为第一绝缘层。
在一些实施例中，感光半导体层31采用非晶硅制备。
具体的，非晶硅在可见区域具有高吸收系数，而且红外光区域基本不吸光，与人眼视觉完美匹配，因此将非晶硅作为感光层能与环境光感光传感器完美契合。非晶硅吸收环境光后会产生光电流，在第一电极板41与漏极24的延伸部241之间产生光电流，使得感光半导体层31形成导电通道。
在一些实施例中，感光半导体层31包括设于漏极24的延伸部241上的N型非晶硅32、设于N型非晶硅32上的本征非晶硅33。
N型非晶硅32中为非晶硅中掺杂了五价元素，例如磷元素、砷元素等。本征非晶硅33中没有掺杂其他元素，使用本征非晶硅33吸收环境光后产生光电子和空穴，N型非晶硅32有多余了电子可以提高感光半导体层31中的电流大小，从而提升感光传感器100的灵敏性。
在一些实施例中，感光半导体层31包括设于漏极24的延伸部241上的N型非晶硅32、设于N型非晶硅32上的本征非晶硅33，以及设于本征非晶硅33上的P型非晶硅34。
P型非晶硅34中为非晶硅中掺杂了三价元素，例如硼元素、镓元素等。本征非晶硅33中没有掺杂其他元素，使用本征非晶硅33吸收环境光后产生光电子和空穴，P型非晶硅34有多余了空穴可以提高感光半导体层31中的电流大小。感光半导体层使用N型非晶硅32、本征非晶硅33、P型非晶硅34的三层结构，可以进一步提升感光传感器100的灵敏性。
在一些实施例中，感光半导体层31可以只包括本征非晶硅33，或包括本征非晶硅33和P型非晶硅34的两层结构。
如图1所示，阵列基板10还包括第一绝缘层和第二绝缘层19，第一绝缘层设于感光半导体层31和薄膜晶体管20上，第二电极板42设于第一绝缘层上；第二绝缘层19设于第二电极板42上，第一电极板41设于第二绝缘层19上，第一电极板通过第一绝缘层和第二绝缘层中的第一过孔51连接感光半导体层。
具体的，图1中的第一绝缘层为覆盖绝缘层17和平坦层18，在一些情况中，可以阵列基板可以只设置覆盖绝缘层17和平坦层18的其中之一，此时，第一绝缘层为覆盖绝缘层17和平坦层18的其中之一。
如图1所示，阵列基板10还包括连接电极43，连接电极43设置于第二绝缘层19上，第二绝缘层19包括第二过孔52，第一绝缘层和第二绝缘层19还包括第三过孔53，连接电极43的一端通过第二过孔52连接第二电极板42，连接电极43的另一端通过第三过孔53连接漏极24。
具体的，图1中第三过孔53还贯穿保护绝缘层16。
在本申请实施例中，漏极24具有一延伸部241，感光半导体层31设置于漏极24的延伸部241上，漏极24的延伸部241作为感光模块30的一侧电极或用于传递感光半导体层31的电信号，减小了感光传感器的膜层数量，可以减小阵列基板的制作工序数量，节省光罩。
进一步的，第一电极板41通过第一过孔51电连接感光半导体层31远离漏极24的延伸部241的一侧，第一电极板41与感光半导体层31连接的部位（第一过孔51中延伸的部位）作为感光模块30的另一侧电极或用于传递感光半导体层31的电信号，进一步减小了感光传感器的膜层数量，可以减小阵列基板的制作工序数量，节省光罩。
实施例二、
请参阅图2，图2为本申请实施例提供的阵列基板的第二种结构示意图，本申请实施例的阵列基板10与实施例一相同或相似，相同之处不再赘述，不同之处在于第二电极板42与漏极24的连接关系不同。
第一绝缘层包括第四过孔54，第二电极板42通过第四过孔54连接漏极24。
具体的，图2中的第一绝缘为覆盖绝缘层17和平坦层18，在一些情况中，阵列基板10可以只设置覆盖绝缘层17和平坦层18的其中之一，此时，第一绝缘层为覆盖绝缘层17和平坦层18的其中之一。
本申请实施例中没有实施例一中的连接电极43，第二电极板42直接通过第一绝缘层中的第四过孔54连接到漏极24。
需要说明的是，图2中第四过孔54还贯穿保护绝缘层16。
本申请实施例具有实施例一中相同的有益效果，在此不再赘述，同时，本申请实施例中去掉了连接电极43，进一步的简化了阵列基板的膜层结构，便于阵列基板的制造和版图（layout）布局，利于良率提升。
实施例三、
请参阅图3，图3为本申请实施例提供的阵列基板的第三种结构示意图，本申请实施例的阵列基板10与实施例一、实施例二相同或相似，相同之处不再赘述，不同之处在于第一电极板41与第二电极板42的位置关系不同。
在本申请实施例中，第一绝缘层设于感光半导体层31和薄膜晶体管20上，第一电极板41设于第一绝缘层上。
具体的，图3中的第一绝缘为覆盖绝缘层17和平坦层18，在一些情况中，阵列基板可以只设置覆盖绝缘层17和平坦层18的其中之一，此时，第一绝缘层为覆盖绝缘层17和平坦层18的其中之一。
第二绝缘层19设于第一电极板41上，第二电极板42设于第二绝缘层19上，第一电极板41通过第一绝缘层中的第五过孔55连接感光半导体层31，第二电极板42通过第一绝缘层和第二绝缘层19中的第六过孔56连接漏极24。
在本申请实施例中，第一电极板41设置于第一绝缘层上，第二电极板42设置于第二绝缘层19上，本申请实施例中又提出了一种具有感光传感器100的阵列基板10的结构，具有与实施例一、二相同的有益效果，在此不再赘述。
实施例四、
在上述实施例一、二、三中所述的任一项阵列基板10中，阵列基板10还包括公共电极和像素电极，下面说明公共电极和像素电极的两种设置情况。
第一种情况，公共电极设于第一绝缘层上；像素电极设于第二绝缘层上；其中，公共电极与第一绝缘层上的对应电极板采用同一金属制备，像素电极与第二绝缘层19上的对应电极板采用同一金属制备。
具体的，如实施例一、二之中：第二电极板42设置于第一绝缘层上，公共电极设置于第一绝缘层上，公共电极与第二电极板42采用同一金属制备；第一电极板41设置于第二绝缘层19上，像素电极设于第二绝缘层19上，像素电极与第一电极板41采用同一金属制备。
具体的，如实施例三之中：第一电极板41设于第一绝缘层上，公共电极设置于第一绝缘层上，公共电极与第一电极板41采用同一金属制备；第二电极板42设于第二绝缘层19上，像素电极设于第二绝缘层19上，像素电极与第二电极板42采用同一金属制备。
第二种情况，像素电极设于第一绝缘层上；公共电极设于第二绝缘层19上；其中，像素电极与第一绝缘层上的对应电极板采用同一金属制备，公共电极与第二绝缘层19上的对应电极板采用同一金属制备。
具体的，如实施例一、二之中：第二电极板42设置于第一绝缘层上，像素电极设置于第一绝缘层上，像素电极与第二电极板42采用同一金属制备；第一电极板41设置于第二绝缘层19上，公共电极设于第二绝缘层19上，公共电极与第一电极板41采用同一金属制备。
具体的，如实施例三之中：第一电极板41设于第一绝缘层上，像素电极设置于第一绝缘层上，像素电极与第一电极板41采用同一金属制备；第二电极板42设于第二绝缘层19上，公共电极设于第二绝缘层19上，公共电极与第二电极板42采用同一金属制备。
需要说明的是，在一些实施情况中，在上述任一项所述的阵列基板10中，第一电极板41在基底11上的正投影与感光半导体层31在基底上的正投影至少部分重叠，此时第一电极板41的材料采用半透明或透明材料，例如为铟锡氧化物（ITO）、铟锌氧化物（IZO）、氧化锌（ZnO）、氟锡氧化物（FTO）等中的任一种，使得环境光可以透过第一电极板41到达感光半导体层31。
需要说明的是，在一些实施例中，第一电极板41电连接至公共电极，即第一电极板41通过公共电极供给电信号。
在本申请实施例中所述的阵列基板中，公共电极与第一绝缘层上的对应电极板采用同一金属制备，像素电极与第二绝缘层19上的对应电极板采用同一金属制备；或像素电极与第一绝缘层上的对应电极板采用同一金属制备，公共电极与第二绝缘层19上的对应电极板采用同一金属制备，可以进一步减小阵列基板10和感光传感器的膜层数量、膜层复杂性，减小包含感光传感器100的阵列基板10的制作工序，减小光罩。
实施例五、
请参与图4，图4为本申请实施例提供的一种阵列基板制造方法的流程步骤示意图，阵列基板制造方法包括步骤S100、步骤S200、步骤S300、步骤S400。图5至图16为阵列基板的制作过程的示意图。
步骤S100：提供一衬底基板，在衬底基板上制作薄膜晶体管，薄膜晶体管包括栅极、有源层、连接有源层的源极和漏极。
具体的，请参阅图5至图9。如图5所示，在基底11上制作遮光层12，采用曝光蚀刻等方式形成图案化的遮光层12；如图6所示，在遮光层12上制备缓冲层13，在缓冲层13上制备有源层21，采用曝光蚀刻方法形成图案化的有源层21，有源层21的材料可以为多晶硅、非晶硅、金属氧化物半导体等，当有源层21为多晶硅时，还可以包括对多晶硅进行P型离子掺杂，形成N型多晶硅，使得有源层21容易形成欧姆接触；如图7所示，在有源层21上形成栅极绝缘层14，在栅极绝缘层14上形成栅极22；如图8所示，在栅极22上形成层间绝缘层15，层间绝缘层15包括连接有源层的过孔；如图9所示，在层间绝缘层15上形成源极23、漏极24和漏极24的延伸部241，源极23和漏极24分别通过层间绝缘层15中的过孔连接有源层21。
步骤S200：在漏极的延伸部上形成感光半导体层。
具体的，请参阅图10至图12。如图10、图11所示，在源极23、漏极24和漏极24的延伸部241上形成保护绝缘层16，保护绝缘层16具有露出漏极24的延伸部241的开口161；如图12所示，在开口161的漏极24的延伸部241上形成感光半导体层31。
具体的，在一些实施例中，感光半导体层31包括设于漏极24的延伸部241上的N型非晶硅32、设于N型非晶硅32上的本征非晶硅33。
具体的，在一些实施例中，感光半导体层31包括设于漏极24的延伸部241上的N型非晶硅32、设于N型非晶硅32上的本征非晶硅33，以及设于本征非晶硅33上的P型非晶硅34。
具体的，在一些实施例中，感光半导体层31可以只包括本征非晶硅33，或包括本征非晶硅33和P型非晶硅34的两层结构。
步骤S300：在所述感光半导体层上形成第一绝缘层，在所述第一绝缘层上形成具有图案化形状的第一金属层，所述第一金属层包括第一电极板和第二电极板中的一个；
具体的，如图13所示，在感光半导体层31上形成第一绝缘层，第一绝缘层可以包括设于感光半导体层31上的覆盖绝缘层17和设于覆盖绝缘层17上的平坦层18，其中，覆盖绝缘层17和平坦层18可以只设置其中之一，也可以两者都设置，覆盖绝缘层17或/和平坦层18为第一绝缘层。如图14所示，在第一绝缘层上形成第一金属层，第一金属层具有图案化的形状，第一金属层包括第一电极板41和第二电极板42中的一个。
具体的，如图14所示，制作第一绝缘层时，第一绝缘层中包括第一预置过孔511和第二预置过孔531，第二预置过孔531还贯穿保护绝缘层16。
步骤S400：在所述第一金属层上形成第二绝缘层，在所述第二绝缘层上形成具有图案化形状的第二金属层，所述第二金属层包括所述第一电极板和所述第二电极板中的另一个，所述第一电极板通过过孔电连接所述感光半导体层，所述第二电极板通过另一过孔电连接所述漏极；所述第一电极板和所述第二电极板构成存储电容。
具体的，如图15所示，第一金属层上形成第二绝缘层19；如图16所示，在第二绝缘层上形成图案化的第二金属层。
具体的，第一金属层包括第一电极板41和第二电极板42中的一个，第二金属层包括第一电极板41和第二电极板42中的另个，第一电极板41通过过孔电连接感光半导体层31，第二电极板42通过另一过孔电连接漏极24，第一电极板41和第二电极板42构成存储电容。
具体的，如图15所示，在制作第二绝缘层19时，第二绝缘层19中包括第三预置过孔512和第四预置过孔532，第一预置过孔511和第三预置过孔512同轴构成上述实施例中的第一过孔51，第二预置过孔531和第四预置过孔532同轴构成上述实施例中的第三过孔53，这里以实施例一中阵列基板10的结构为例作图示意了阵列基板10的制作过程。
需要说明的是，采用本申请实施例中的阵列基板制造方法，可以制造实施例一、实施例二、实施例三、实施例四中任一项所述的阵列基板，第一电极板41和第二电极板42的位置或连接关系请参阅实施例一、实施例二、实施例三、实施例四。
需要说明的是，在一些实施例中，阵列基板10还包括公共电极和像素电极，下面说明公共电极和像素电极的两种设置情况。
第一种情况，公共电极设于第一绝缘层上；像素电极设于第二绝缘层上；其中，公共电极与第一绝缘层上的对应电极板采用同一金属制备，像素电极与第二绝缘层19上的对应电极板采用同一金属制备。
第二种情况，像素电极设于第一绝缘层上；公共电极设于第二绝缘层19上；其中，像素电极与第一绝缘层上的对应电极板采用同一金属制备，公共电极与第二绝缘层19上的对应电极板采用同一金属制备。
在本申请实施例中，请参阅图15至图16，以顶栅型多晶硅薄膜晶体管为例说明了阵列基板10的制作工序，包含感光传感器100的阵列基板10包括12道光罩，在不包含感光传感器的阵列基板上只增加了两道光罩，因此本申请实施例的包含感光传感器100的阵列基板10工序简单，光罩数量小。
采用本申请实施例的阵列基板制造方法来制造具有感光传感器100的阵列基板10，漏极24具有一延伸部241，感光半导体层31设置于漏极24的延伸部241上，漏极24的延伸部241作为感光模块30的一侧电极或用于传递感光半导体层31的电信号，减小了感光传感器的膜层数量，可以减小阵列基板的制作工序数量，节省了光罩数量。
进一步的，在本申请实施例中所述的阵列基板中，公共电极与第一绝缘层上的对应电极板采用同一金属制备，像素电极与第二绝缘层19上的对应电极板采用同一金属制备；或像素电极与第一绝缘层上的对应电极板采用同一金属制备，公共电极与第二绝缘层19上的对应电极板采用同一金属制备，可以进一步减小阵列基板10和感光传感器的膜层数量，减小包含感光传感器100的阵列基板10的制作工序数量，节省了光罩数量。
采用本申请实施例的阵列基板制造方法来制造具有感光传感器100的阵列基板10具有膜层简单的效果，本申请实施例的阵列基板制造方法具有工序数量小、工艺简单、节省了光罩数量的效果。
实施例六、
请参阅图17，图17为本申请实施例提供的显示面板1000的示意图，显示面板1000包括如上述实施例中所述的任一项阵列基板10。
显示面板1000还包括驱动芯片103，或显示面板1000电连接至驱动芯片103，第二电极板通过走线电连接至驱动芯片。上述实施例中的阵列基板10的第二电极板42通过走线电连接至驱动芯片103。
下面说明显示面板1000的薄膜晶体管20和感光传感器100的工作过程，在一些实施例中，第一电极板41和第二电极板42其中之一电连接驱动芯片103，第一电极板41和第二电极板42中的另一个供给一固有信号。
具体的，在一些实施例中，第一电极板41电连接至阵列基板的公共电极或被供给公共电极信号，第二电极板42通过走线电连接至驱动芯片103，以此为例说明显示面板1000的薄膜晶体管20和感光传感器100的工作过程：薄膜晶体管20开启，供给第二电极板42一起始信号，然后薄膜晶体管20关闭，第二电极板42与第一电极板41之间存在一个存储电容，此时第二电极板42处于浮置状态（floating），第一电极板41被供给公共电极信号，感光半导体层31中无光电流产生时存储电容保持不变；当环境光照射到感光半导体层31上时，感光半导体层31上产生光电流，第一电极板41和第二电极板42中的电荷发生流动，导致存储电容的大小发生变化，存储电容的大小变化通过第二电极板42连接的走线传递至驱动芯片103，驱动芯片103依据电容大小的变化量就可以判断环境光条件是否发生了变化或变化了多小，然后驱动芯片103采取对显示面板1000的处理动作，例如调整显示面板1000的亮度，在环境光亮度较高的情况下，调高显示面板1000的亮度，可以便于使用者更好的观察图像。
如图17所示，在一些实施例中，显示面板1000包括显示区101和非显示区102，感光传感器100可以设置于非显示区102，这样感光传感器100不影响显示区101的像素设置，从而感光传感器100不影响显示面板1000的像素的开口率。
以上对本申请实施例所提供的一种阵列基板、阵列基板制造方法及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其中，包括：
    基底；
    薄膜晶体管，设于所述基底上，包括栅极、有源层、连接所述有源层的源极和漏极；
    感光传感器，所述感光传感器包括感光模块和存储模块，所述感光模块包括感光半导体层，所述存储模块包括第一电极板和第二电极板；
    其中，所述感光半导体层设置于所述漏极的延伸部之上，所述第一电极板电连接所述感光半导体层远离所述漏极的延伸部的一侧，所述第二电极板电连接所述漏极。
  2. 如权利要求1所述的阵列基板，其中，所述存储模块包括存储电容，所述第一电极板和所述第二电极板构成所述存储电容。
  3. 如权利要求2所述的阵列基板，其中，还包括：
    第一绝缘层，设于所述感光半导体层和所述薄膜晶体管上，所述第二电极板设于所述第一绝缘层上；
    第二绝缘层，设于所述第二电极板上，所述第一电极板设于所述第二绝缘层上，所述第一电极板通过所述第一绝缘层和所述第二绝缘层中的第一过孔连接所述感光半导体层。
  4. 如权利要求3所述的阵列基板，其中，还包括：
    连接电极，设于所述第二绝缘层上，所述第二绝缘层包括第二过孔，所述第一绝缘层和所述第二绝缘层还包括第三过孔，所述连接电极的一端通过所述第二过孔连接所述第二电极板，所述连接电极的另一端通过所述第三过孔连接所述漏极。
  5. 如权利要求3所述的阵列基板，其中，所述第一绝缘层包括第四过孔，所述第二电极板通过所述第四过孔连接所述漏极。
  6. 如权利要求2所述的阵列基板，其中，还包括：
    第一绝缘层，设于所述感光半导体层和所述薄膜晶体管上，所述第一电极板设于所述第一绝缘层上；
    第二绝缘层，设于所述第一电极板上，所述第二电极板设于所述第二绝缘层上，所述第一电极板通过所述第一绝缘层中的第五过孔连接所述感光半导体层，所述第二电极板通过所述第一绝缘层和所述第二绝缘层中的第六过孔连接所述漏极。
  7. 如权利要求3所述的阵列基板，其中，所述感光半导体层采用非晶硅制备。
  8. 如权利要求7所述的阵列基板，其特征在于，所述感光半导体层包括设于所述漏极的延伸部上的N型非晶硅、设于所述N型非晶硅上的本征非晶硅；或
    所述感光半导体层包括设于所述漏极的延伸部上的N型非晶硅、设于所述N型非晶硅上的本征非晶硅，以及设于所述本征非晶硅上的P型非晶硅。
  9. 如权利要求7所述的阵列基板，其中，还包括：
    公共电极，设于所述第一绝缘层上；
    像素电极，设于所述第二绝缘层上；
    其中，所述公共电极与所述第一绝缘层上的对应电极板采用同一金属制备，所述像素电极与所述第二绝缘层上的对应电极板采用同一金属制备。
  10. 如权利要求7所述的阵列基板，其中，还包括：
    像素电极，设于所述第一绝缘层上；
    公共电极，设于所述第二绝缘层上；
    其中，所述像素电极与所述第一绝缘层上的对应电极板采用同一金属制备，所述公共电极与所述第二绝缘层上的对应电极板采用同一金属制备。
  11. 如权利要求7所述的阵列基板，其中，所述第一电极板在所述基底上的正投影与所述感光半导体层在所述基底上的正投影至少部分重叠；
    所述第一电极板的材料为透明材料。
  12. 如权利要求9所述的阵列基板，其中，所述第一电极板电连接至所述公共电极。
  13. 一种阵列基板制造方法，其中，包括如下制造步骤：
    步骤S100：提供一衬底基板，在所述衬底基板上制作薄膜晶体管，所述薄膜晶体管包括栅极、有源层、连接所述有源层的源极和漏极；
    步骤S200：在所述漏极的延伸部上形成感光半导体层；
    步骤S300：在所述感光半导体层上形成第一绝缘层，在所述第一绝缘层上形成具有图案化形状的第一金属层，所述第一金属层包括第一电极板和第二电极板中的一个；
    步骤S400：在所述第一金属层上形成第二绝缘层，在所述第二绝缘层上形成具有图案化形状的第二金属层，所述第二金属层包括所述第一电极板和所述第二电极板中的另一个，所述第一电极板通过过孔电连接所述感光半导体层，所述第二电极板通过另一过孔电连接所述漏极；所述第一电极板和所述第二电极板构成存储电容。
  14. 一种显示面板，包括阵列基板；其中，所述阵列基板包括：
    基底；
    薄膜晶体管，设于所述基底上，包括栅极、有源层、连接所述有源层的源极和漏极；
    感光传感器，所述感光传感器包括感光模块和存储模块，所述感光模块包括感光半导体层，所述存储模块包括第一电极板和第二电极板；
    其中，所述感光半导体层设置于所述漏极的延伸部之上，所述第一电极板电连接所述感光半导体层远离所述漏极的延伸部的一侧，所述第二电极板电连接所述漏极。
  15. 如权利要求14所述的显示面板，其中，所述存储模块包括存储电容，所述第一电极板和所述第二电极板构成所述存储电容。
  16. 如权利要求15所述的显示面板，其中，所述阵列基板还包括：
    第一绝缘层，设于所述感光半导体层和所述薄膜晶体管上，所述第二电极板设于所述第一绝缘层上；
    第二绝缘层，设于所述第二电极板上，所述第一电极板设于所述第二绝缘层上，所述第一电极板通过所述第一绝缘层和所述第二绝缘层中的第一过孔连接所述感光半导体层。
  17. 如权利要求16所述的显示面板，其中，所述阵列基板还包括：
    连接电极，设于所述第二绝缘层上，所述第二绝缘层包括第二过孔，所述第一绝缘层和所述第二绝缘层还包括第三过孔，所述连接电极的一端通过所述第二过孔连接所述第二电极板，所述连接电极的另一端通过所述第三过孔连接所述漏极。
  18. 如权利要求16所述的显示面板，其中，所述阵列基板还包括：
    所述第一绝缘层包括第四过孔，所述第二电极板通过所述第四过孔连接所述漏极。
  19. 如权利要求15所述的显示面板，其中，所述阵列基板还包括：
    第一绝缘层，设于所述感光半导体层和所述薄膜晶体管上，所述第一电极板设于所述第一绝缘层上；
    第二绝缘层，设于所述第一电极板上，所述第二电极板设于所述第二绝缘层上，所述第一电极板通过所述第一绝缘层中的第五过孔连接所述感光半导体层，所述第二电极板通过所述第一绝缘层和所述第二绝缘层中的第六过孔连接所述漏极。
  20. 如权利要求14所述的显示面板，其中，还包括驱动芯片，
    所述第二电极板通过走线电连接至所述驱动芯片。
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