WO2022264299A1 - ゲート駆動回路 - Google Patents

ゲート駆動回路 Download PDF

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Publication number
WO2022264299A1
WO2022264299A1 PCT/JP2021/022791 JP2021022791W WO2022264299A1 WO 2022264299 A1 WO2022264299 A1 WO 2022264299A1 JP 2021022791 W JP2021022791 W JP 2021022791W WO 2022264299 A1 WO2022264299 A1 WO 2022264299A1
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WO
WIPO (PCT)
Prior art keywords
switching element
gate
voltage
driven
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2021/022791
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English (en)
French (fr)
Japanese (ja)
Inventor
裕次 根本
航平 恩田
隆義 三木
翔太 森崎
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to PCT/JP2021/022791 priority Critical patent/WO2022264299A1/ja
Priority to DE112021007827.5T priority patent/DE112021007827T5/de
Priority to US18/568,294 priority patent/US12368435B2/en
Priority to JP2021559393A priority patent/JP7031078B1/ja
Publication of WO2022264299A1 publication Critical patent/WO2022264299A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/168—Modifications for eliminating interference voltages or currents in composite switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/0406—Modifications for accelerating switching in composite switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0828—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in composite switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches

Definitions

  • the present disclosure relates to gate drive circuits.
  • IGBTs Insulated Gate Bipolar Transistors
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • switching loss When this switching loss is reduced, the power consumption of the power conversion device can be reduced, so the efficiency during power conversion is improved. Therefore, it is desirable to reduce the switching loss of the switching device in order to reduce the size and increase the efficiency of the power converter.
  • Switching losses can be reduced by increasing the switching speed. The switching speed can be increased by making the voltage change faster around the gate threshold voltage of the switching device.
  • high-speed switching is achieved by first applying a first voltage higher than the voltage normally applied, and at a predetermined timing after the switching element is turned on, the voltage at the gate terminal of the switching element is reduced.
  • a technique for speeding up the switching speed at turn-on by switching the voltage to a second voltage lower than the voltage of the first voltage source is disclosed (see, for example, Patent Document 1).
  • an arm short-circuit may occur due to an abnormality in the control circuit and a failure of the paired switching element, which may damage the switching element.
  • the gate voltage of the switching element is high, a large current flows through the switching element when the arm is short-circuited. Therefore, by first applying a first voltage that is lower than the voltage that is normally applied, the current that flows when the arm is short-circuited is limited to ensure the short-circuit resistance.
  • a method of switching the voltage at the gate terminal of the switching element to a second voltage higher than the voltage of the first voltage source is disclosed in order to reduce the effective conduction loss (see, for example, Patent Document 2). .
  • the present application discloses a technique for solving the above problems, and aims to provide a gate drive circuit for a switching element that can satisfy both reduction of switching loss and securing of short-circuit resistance. do.
  • a gate drive circuit disclosed in the present application is a gate drive circuit including a control unit that applies a gate voltage between the gate and source of a switching element to be driven to drive the switching element, wherein the control unit includes the A first voltage is applied between the gate and source of the switching element to turn on the switching element, and after commutation of the drain current of the switching element, the first voltage is cut off, and a voltage is applied between the gate and source of the switching element.
  • a second voltage that is lower than the first voltage and higher than the mirror voltage of the switching element, and cuts off the second voltage when a short-circuit current does not flow in the switching element to be driven.
  • a third voltage higher than the second voltage is applied between the gate and source of the switching element.
  • the gate drive circuit disclosed in the present application switching is performed at a high voltage at turn-on to reduce switching loss, and even if a short-circuit current occurs as a result of turn-on, the gate voltage is immediately suppressed to a low level to prevent a short circuit. Since the current can also be suppressed, the short circuit resistance can be ensured. Furthermore, by increasing the gate voltage after that, it is possible to suppress steady-state conduction loss to a low level.
  • FIG. 1 is a circuit configuration diagram showing an outline of a gate drive circuit according to Embodiment 1;
  • FIG. 1 is a diagram illustrating an example of a power conversion system to which a gate drive circuit and a switching element to be driven according to Embodiment 1 are applied;
  • FIG. 4 is a timing chart showing the operation of the gate drive circuit according to Embodiment 1;
  • 8 is another timing chart showing the operation of the gate drive circuit according to the first embodiment;
  • FIG. 10 is a circuit configuration diagram showing an outline of a gate drive circuit according to a second embodiment; 8 is a timing chart showing the operation of the gate drive circuit according to the second embodiment;
  • FIG. 10 is a circuit configuration diagram showing an outline of a gate drive circuit according to a second embodiment;
  • 8 is a timing chart showing the operation of the gate drive circuit according to the second embodiment;
  • FIG. 11 is a circuit configuration diagram showing an outline of a gate drive circuit according to a third embodiment
  • 9 is a timing chart showing the operation of the gate drive circuit according to the third embodiment
  • 3 is a hardware configuration diagram of a control unit included in the gate drive circuits according to Embodiments 1 to 3;
  • FIG. 11 is a circuit configuration diagram showing an outline of a gate drive circuit according to a third embodiment
  • 9 is a timing chart showing the operation of the gate drive circuit according to the third embodiment
  • 3 is a hardware configuration diagram of a control unit included in the gate drive circuits according to Embodiments 1 to 3
  • FIG. 1 is a circuit configuration diagram showing an outline of a gate drive circuit according to Embodiment 1
  • FIG. 2 is a diagram showing an example of a power conversion system to which a gate drive circuit and switching elements to be driven are applied.
  • the gate drive circuit 100 shown in FIG. 1 is not limited to the first embodiment, and any gate drive circuit of other embodiments can be used in various power converters.
  • the power conversion system shown in FIG. can be used for the gate drive circuit of An example of the power conversion system shown in FIG.
  • an IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • a diode is connected in anti-parallel to the IGBT, but if the switching element 99 is a MOSFET, a body diode of the MOSFET may be used instead.
  • a first power supply 61 for applying a positive voltage to the gate terminal of the switching element 99 is connected to the gate terminal of the switching element 99 via the switching element 1 and the gate resistor 6 for adjusting the switching speed. It is connected.
  • the diode 8, the switching element 15, and the second power supply 62 are connected in series to the gate terminal.
  • a fourth power supply 64 for applying a negative voltage to the gate terminal of the switching element 99 is connected to the gate terminal of the switching element 99 via the switching element 4 and the gate resistor 7 for adjusting the switching speed.
  • each switching element 1, 4, 15 is shown as an example of MOSFET.
  • Each power supply is a DC power supply, and the relationship between voltages V1, V2, and V4 applied from each power supply 61, 62, and 64 to the gate terminals is as follows: V1>V2>mirror voltage of switching element 99>V4 is.
  • the voltage V1 is the voltage to be applied in the ON state, which is specified for each switching element 99.
  • FIG. the voltage V4 is a negative voltage, for example, a voltage of about -5 to -15V.
  • the gate drive circuit 100 also has a control section 5 for controlling the switching elements 1, 4 and 15 in order to control the voltage applied to the gate terminal of the switching element 99.
  • the control section 5 is a switching element.
  • a short-circuit current detector 51 is provided for detecting whether a short-circuit current is flowing through the switching element 99 from the output of the current detector 20 flowing through the element 99 .
  • the gate voltage Vgs which is the voltage between the gate and source
  • the drive signal Vg1 that turns on the switching element 1 the drive signal Vg4 that turns on and off the switching element 4
  • the drive signal Vg3 the drive signal Vg3 that turns on and off the switching element 15
  • the switching element 99 is a timing chart of the drain current Id of the switching element 99 and the drain-source voltage Vds of the switching element 99.
  • the driving signal Vg1 becomes high (H) to turn on the switching element 1, whereby the first voltage V1 is applied to the gate voltage Vgs through the gate resistor 6, and the switching element 99 performs normal switching. turn on at speed.
  • the normal switching speed is the switching speed when turned on with the voltage V1 to be applied in the ON state.
  • the drain current Id of the switching element 99 gradually increases, reaching the current that should flow originally at time t2.
  • the current that should be flowed is the current determined by the input voltage or the state of the motor, etc., and increases to the current that was flowing in the pair arm that had been in the ON state until just before. This completes the commutation of the drain current Id.
  • the drain-source voltage Vds drops, and at time t3, it drops to 0 V, and the turn-on of the switching element 99 ends normally.
  • the gate voltage Vgs rises to the first voltage V1 between time t2 and time t3.
  • the gate voltage Vgs is the first voltage V1 between time t2 and time t3, but the present invention is not limited to this. That is, the gate voltage Vgs should be equal to or higher than the second voltage V2 between time t2 and time t3.
  • the drive signal Vg1 is set to low (L), and the switching element 1 is turned off.
  • drive signal Vg3 is set to high (H) to turn on the gate of switching element 15 .
  • the gate voltage Vgs drops to the second voltage V2 (time t4).
  • the gate voltage Vgs maintains the state of the second voltage V2 until time t5. This time takes into consideration the delay time of the circuit for detecting whether a short-circuit current is flowing through the switching element 99 . That is, the state of the second voltage V2 is maintained for the delay time of the short-circuit current detection unit 51 .
  • the conduction loss of the switching element 99 is increased. little impact on Furthermore, since the gate voltage Vgs is lowered after the switching is completed, the switching loss does not worsen.
  • the driving signal Vg3 is set to low (L) at time t5 to turn off the switching element 15.
  • the drive signal Vg1 is set to high (H) again to turn on the gate of the switching element 1 .
  • the gate voltage Vgs the first voltage V1 is again applied via the gate resistor 6, and the switching element 99 continues to operate with normal conduction loss.
  • the drive signal Vg1 is set to low (L) to turn off the switching element 1 .
  • drive signal Vg4 is set to high (H) to turn on the gate of switching element 4 .
  • the fourth voltage V4 which is a negative voltage, is applied to the gate voltage Vgs through the gate resistor 7, and the drain current Id also becomes zero. This corresponds to the state before time t0.
  • the timing chart of FIG. 3 shows an example in which no short-circuit current is detected.
  • times t0 to t12 are the same as times t0 to t2 in FIG. That is, at time t0, the drive signal Vg1 becomes high (H) and the switching element 1 is turned on, whereby the first voltage V1 is applied to the gate voltage Vgs through the gate resistor 6, and the switching element 99 operates normally. turn on at a switching speed of .
  • the drain current Id of the switching element 99 gradually increases, and at time t12, it increases to the current flowing in the pair arm, and the commutation of the drain current Id is completed. .
  • the drain current Id further increases after time t12 in FIG. 4, resulting in an arm short-circuited state.
  • the switching element 99b is paired with the switching element 99a. Since the switching element 99 has a stipulated short-circuit resistance, it does not break down immediately even when the drain current Id starts to rise. This state continues for a long time, and when the loss becomes excessive, the switching element is damaged.
  • the driving signal Vg1 is set to low (L) to turn off the switching element 1.
  • drive signal Vg3 is set to high (H) to turn on the gate of switching element 15 .
  • the gate voltage Vgs drops to the second voltage V2 (time t14).
  • the gate voltage Vgs maintains the state of the second voltage V2 until time t15. As described above, it is detected whether or not the short-circuit current is flowing through the switching element 99 during this time.
  • the drive signal Vg3 is set to low (L) at time t15 to turn off the switching element 15 .
  • drive signal Vg4 is set to high (H) to turn on the gate of switching element 4 .
  • the fourth voltage V4 which is a negative voltage, is applied to the gate voltage Vgs through the gate resistor 7, and the switching element 99 is turned off. This makes it possible to normally stop the switching element 99 before the switching element 99 breaks down.
  • the gate drive circuit includes the control unit 5 that controls the gate voltage Vgs of the switching element 99 to be driven and drives the switching element 99.
  • the control unit 5 includes at least the first The gate voltage Vgs is controlled by applying to the gate of the switching element 99 one of three types of voltages: one voltage V1, a second voltage V2, and a negative fourth voltage V4. .
  • the switching element 99 is turned on, switching is performed at a high first voltage V1 to reduce switching loss, and even if a short-circuit current occurs as a result of turning on, the gate voltage Vgs is immediately suppressed to a low level (second voltage V). voltage V2), the short-circuit current can be suppressed, and the short-circuit resistance can be ensured.
  • the switching element 99 is turned off by changing the gate voltage Vgs from the second voltage V2 to the fourth voltage V4, which is a negative output voltage, and the switching element 99 is destroyed. The operation can be finished before
  • Embodiment 2 A gate drive circuit according to the second embodiment will be described below with reference to the drawings.
  • the second embodiment is an example of turning on the switching element 99 at a voltage higher than the first voltage V1 used in the first embodiment.
  • FIG. 5 is a circuit configuration diagram showing an outline of the gate drive circuit according to the second embodiment, and
  • FIG. 6 is a timing chart showing the operation of the gate drive circuit.
  • a power supply 63 that supplies a third voltage V3 higher than the first voltage V1 is connected to one end of the switching element 1.
  • a power supply 61 that supplies the first voltage V1 is connected in series with the switching element 13 of the diode 14 and connected to the gate terminal of the switching element 99 .
  • Other configurations are the same as those in FIG. 1 of Embodiment 1, so descriptions thereof are omitted.
  • Each power supply is a DC power supply, and the relationship between voltages V1, V2, V3, and V4 applied to the gate terminals from power supplies 61, 62, 63, and 64 is as follows: V3>V1>V2>mirror voltage of switching element 99>V4 is.
  • the voltage V1 is the voltage to be applied in the ON state specified for each switching element 99, and the voltage V3 is higher than the voltage V1, that is, higher than the voltage to be normally applied.
  • the voltage V4 is a negative voltage.
  • the gate voltage Vgs which is the voltage between the gate and source
  • the drive signal Vg1 that turns on the switching element 1 the drive signal Vg4 that turns on and off the switching element 4
  • the drive signal Vg3 the drive signal Vg3 that turns on and off the switching element 15
  • the switching element 13 is a timing chart of a drive signal Vg5 that turns on and off the switching element 99, a drain current Id of the switching element 99, and a drain-source voltage Vds of the switching element 99.
  • the drive signal Vg1 becomes high (H) to turn on the switching element 1, thereby applying the third voltage V3 to the gate voltage Vgs through the gate resistor 6, and the switching element 99 is activated faster than usual. That is, it turns on at a faster switching speed than when the switching voltage is the first voltage V1.
  • the drain current Id of the switching element 99 gradually increases, and at time t22, it increases to the current flowing in the pair arm. This completes the commutation of the drain current Id.
  • the drain-source voltage Vds drops, and at time t23, it drops to 0 V, and the turn-on of the switching element 99 ends normally.
  • the gate voltage Vgs rises between time t22 and time t23 to reach the third voltage V3. It should be noted that the drain-source voltage Vds does not necessarily need to reach the third voltage V3 by time t23. Since the gate voltage Vgs is high, the period from time t0 to time t23 is also shorter than from time t0 to time t3 in the first embodiment, and switching loss can be made smaller than in the first embodiment.
  • the driving signal Vg1 is set to low (L) to turn off the switching element 1.
  • drive signal Vg3 is set to high (H) to turn on the gate of switching element 15 .
  • the gate voltage Vgs drops to the second voltage V2 (time t24).
  • the gate voltage Vgs maintains the state of the second voltage V2 until time t25. As in the first embodiment, during this time, it is detected whether a short-circuit current is flowing through the switching element 99 . That is, the state of the second voltage V2 is maintained for the delay time of the short-circuit current detection unit 51 .
  • the conduction loss of the switching element 99 is increased. , and the impact on losses is small. Furthermore, since the gate voltage Vgs is lowered after the switching is completed, the switching loss does not worsen.
  • the driving signal Vg3 is set to low (L) at time t25 to turn off the switching element 15.
  • drive signal Vg5 is set to high (H) to turn on the gate of switching element 13 .
  • the gate voltage Vgs becomes the first voltage V1, and the switching element 99 continues to operate with normal conduction loss.
  • the drive signal Vg1 is set to low (L) to turn off the switching element 13 .
  • drive signal Vg4 is set to high (H) to turn on the gate of switching element 4 .
  • the fourth voltage V4 which is a negative voltage, is applied through the gate resistor 7 as the gate voltage Vgs.
  • the drain current Id also becomes zero. This corresponds to the state before time t0.
  • the timing chart of FIG. 6 is an example in which no short-circuit current is detected
  • the operation when a short-circuit current is detected is the same as in FIG. 4 of the first embodiment. That is, at time t25 in FIG. 6, the drive signal Vg3 is set to low (L), and the switching element 15 is turned off. At the same time, drive signal Vg4 is set to high (H) to turn on the gate of switching element 4 .
  • the control unit 5 applies at least one of four types of voltages, ie, a first voltage V1, a second voltage V2, a third voltage V3, and a negative fourth voltage V4, to the switching element 99. It is applied to the gate to control the gate voltage Vgs.
  • a first voltage V1 a second voltage V2, a third voltage V3, and a negative fourth voltage V4
  • Vgs a negative fourth voltage
  • the switching element 99 is turned off by changing the gate voltage Vgs from the second voltage V2 to the fourth voltage V4, which is a negative output voltage, and the switching element 99 is destroyed. The operation can be finished before
  • the switching element 99 to be driven is made of a wide bandgap semiconductor, which is a compound semiconductor such as SiC (silicon carbide) or GaN (gallium nitride)
  • the internal gate resistance is high, and the external gate resistance is Even if 6 is set to 0 ⁇ , the switching loss may be high. Even with the configuration of the first embodiment, a certain effect can be obtained. growing.
  • Embodiment 3 A gate drive circuit according to the third embodiment will be described below with reference to the drawings.
  • the third embodiment is an example of a circuit that lowers the first voltage V1 to the second voltage V2a without using the second power supply of the first embodiment.
  • FIG. 7 is a circuit configuration diagram showing an outline of the gate drive circuit according to the third embodiment, and
  • FIG. 8 is a timing chart showing the operation of the gate drive circuit.
  • a diode 8, a transistor 2, and a resistor 12 for generating the second voltage V2a are connected in series to the gate terminal of a switching element 99, and a Zener diode 10 for determining the voltage is connected to the base of the transistor 2. is connected through a power supply 61, a transistor 3 for turning it on and off is connected through a resistor 11, and the emitter of the transistor 3 is connected to a power supply 64 (voltage V4 is a negative voltage).
  • the time from time t0 to time t32 is the same as the time from time t0 to time t2 in FIG. 3 of the first embodiment, so the description is omitted.
  • the drain-source voltage Vds drops and drops to 0 V at time t33, and the turn-on of the switching element 99 ends normally.
  • the drive signal Vg1 is set to low (L), and the switching element 1 is turned off.
  • the drive signal Vg13 is set to high (H) to turn on the transistor 3 .
  • the emitter voltage of the transistor 2 drops to a voltage lower than the first voltage V1, such as V2, the PNP transistor 2 is turned on, and the base-emitter voltage Vbe of the transistor 2 is added to the gate voltage Vgs of the switching element 99.
  • a second voltage V2a is applied.
  • V2a V2+Vbe, and the voltage Vbe is about 1V.
  • the gate voltage Vgs can be lowered to the second voltage V2a lower than the first voltage V1 (time t34) after the turn-on is completed.
  • the subsequent operation and the operation when a short circuit is detected are the same as those in the first embodiment, and the description thereof will be omitted.
  • the gate drive circuit of the third embodiment also has the same effect as the first embodiment. Moreover, since the number of power sources is smaller than that of the first embodiment, the cost can be reduced.
  • control unit 5 of Embodiments 1 to 3 is composed of a processor 1001 and a storage device 1002, as shown in FIG. 9 as an example of hardware.
  • the storage device includes a volatile storage device such as a random access memory and a non-volatile auxiliary storage device such as a flash memory.
  • an auxiliary storage device such as a hard disk may be provided instead of the flash memory.
  • Processor 1001 executes a program input from storage device 1002 . In this case, the program is input from the auxiliary storage device to the processor 1001 via the volatile storage device.
  • the processor 1001 may output data such as calculation results to the volatile storage device of the storage device 1002, or may store data in an auxiliary storage device via the volatile storage device.
  • the short-circuit current detection unit 51 for detecting the occurrence of an abnormality such as an arm short-circuit in which a short-circuit current flows is provided inside the control unit 5 , but it may be provided outside the control unit 5 . If the short-circuit current detector 51 is provided outside the controller 5, a signal indicating the presence or absence of an arm short-circuit may be input to the controller 5, and the gate voltage Vgs may be controlled based on the signal.
  • switching elements 1, 4, 13, and 15 in the gate drive circuit 100 have been described as MOSFETs in the first to third embodiments, they may be other switching elements such as IGBTs.
  • the circuit configuration of the gate drive circuit shown in the first to third embodiments is not limited to the illustrated diagram, and a plurality of different voltages can be applied as the gate voltage Vgs between the gate and source of the switching element 99 to be driven. Any circuit such as the number of power supplies may be used as long as it is possible.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)
PCT/JP2021/022791 2021-06-16 2021-06-16 ゲート駆動回路 Ceased WO2022264299A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2021/022791 WO2022264299A1 (ja) 2021-06-16 2021-06-16 ゲート駆動回路
DE112021007827.5T DE112021007827T5 (de) 2021-06-16 2021-06-16 Gate-treiberschaltung
US18/568,294 US12368435B2 (en) 2021-06-16 2021-06-16 Gate drive circuit
JP2021559393A JP7031078B1 (ja) 2021-06-16 2021-06-16 ゲート駆動回路

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Application Number Priority Date Filing Date Title
PCT/JP2021/022791 WO2022264299A1 (ja) 2021-06-16 2021-06-16 ゲート駆動回路

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WO2022264299A1 true WO2022264299A1 (ja) 2022-12-22

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026033950A1 (ja) * 2024-08-09 2026-02-12 株式会社デンソー ゲート駆動装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026074624A1 (ja) * 2024-10-02 2026-04-09 日産自動車株式会社 電力変換装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03117211A (ja) * 1989-09-29 1991-05-20 Toshiba Corp 半導体素子の駆動回路
JP2012147625A (ja) * 2011-01-14 2012-08-02 Denso Corp スイッチング素子の駆動回路
JP2013240247A (ja) * 2012-05-17 2013-11-28 Denso Corp スイッチング素子の駆動回路
JP2015019456A (ja) * 2013-07-09 2015-01-29 株式会社デンソー 駆動対象スイッチング素子の駆動回路
JP2017103879A (ja) * 2015-11-30 2017-06-08 株式会社Ihi 電力変換装置
WO2018198426A1 (ja) * 2017-04-26 2018-11-01 三菱電機株式会社 半導体素子の駆動方法および駆動装置、ならびに、電力変換装置
JP2018186691A (ja) * 2017-04-27 2018-11-22 富士電機株式会社 半導体素子の駆動装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4081604B2 (ja) 2002-06-26 2008-04-30 株式会社豊田自動織機 スイッチング素子の駆動装置
US7276954B2 (en) 2002-06-26 2007-10-02 Kabushiki Kaisha Toyota Jidoshokki Driver for switching device
JP4804142B2 (ja) 2005-12-21 2011-11-02 東洋電機製造株式会社 高速ゲート駆動回路
JP2009071956A (ja) 2007-09-12 2009-04-02 Mitsubishi Electric Corp ゲート駆動回路
JP5585514B2 (ja) * 2011-04-01 2014-09-10 株式会社デンソー 負荷駆動装置
JP5646070B2 (ja) 2011-09-13 2014-12-24 三菱電機株式会社 電力用半導体素子のゲート駆動回路、および電力用半導体素子の駆動方法
JP5993749B2 (ja) 2013-01-30 2016-09-14 株式会社 日立パワーデバイス 半導体装置のゲート駆動回路およびそれを用いた電力変換装置
JP5794246B2 (ja) * 2013-03-11 2015-10-14 株式会社デンソー ゲート駆動回路
WO2017037916A1 (ja) * 2015-09-03 2017-03-09 三菱電機株式会社 電力変換装置
US10033377B2 (en) * 2016-03-15 2018-07-24 Avago Technologies General Ip (Singapore) Pte. Ltd. Adaptive power down control system
DE112018003834T5 (de) * 2017-07-28 2020-04-09 Mitsubishi Electric Corporation Treiberschaltung für ein leistungshalbleiterelement
WO2022137452A1 (ja) * 2020-12-24 2022-06-30 三菱電機株式会社 ゲート駆動回路及び電力変換装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03117211A (ja) * 1989-09-29 1991-05-20 Toshiba Corp 半導体素子の駆動回路
JP2012147625A (ja) * 2011-01-14 2012-08-02 Denso Corp スイッチング素子の駆動回路
JP2013240247A (ja) * 2012-05-17 2013-11-28 Denso Corp スイッチング素子の駆動回路
JP2015019456A (ja) * 2013-07-09 2015-01-29 株式会社デンソー 駆動対象スイッチング素子の駆動回路
JP2017103879A (ja) * 2015-11-30 2017-06-08 株式会社Ihi 電力変換装置
WO2018198426A1 (ja) * 2017-04-26 2018-11-01 三菱電機株式会社 半導体素子の駆動方法および駆動装置、ならびに、電力変換装置
JP2018186691A (ja) * 2017-04-27 2018-11-22 富士電機株式会社 半導体素子の駆動装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2026033950A1 (ja) * 2024-08-09 2026-02-12 株式会社デンソー ゲート駆動装置

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US20240275376A1 (en) 2024-08-15

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