WO2022261890A1 - 读操作电路、芯片及电子设备 - Google Patents

读操作电路、芯片及电子设备 Download PDF

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Publication number
WO2022261890A1
WO2022261890A1 PCT/CN2021/100564 CN2021100564W WO2022261890A1 WO 2022261890 A1 WO2022261890 A1 WO 2022261890A1 CN 2021100564 W CN2021100564 W CN 2021100564W WO 2022261890 A1 WO2022261890 A1 WO 2022261890A1
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Prior art keywords
terminal
read operation
column
bit lines
control terminal
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PCT/CN2021/100564
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English (en)
French (fr)
Inventor
翁贞华
叶力
李文静
向清懿
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华为技术有限公司
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Priority to CN202180098465.3A priority Critical patent/CN117396961A/zh
Priority to PCT/CN2021/100564 priority patent/WO2022261890A1/zh
Publication of WO2022261890A1 publication Critical patent/WO2022261890A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals

Definitions

  • the present application relates to the field of electronic technology, in particular to a read operation circuit, chip and electronic equipment.
  • cross-point memory array also called cross-point structure array or cross-point memory array
  • the cross-point memory array stores a single bit (bit) with an area of 4F 2 The lowest storage density achieved.
  • the cross-point memory array is perfectly suitable for two-terminal devices; and the memory cells are directly formed in the metal layer without the participation of transistors, as shown in Figure 1, which makes the cross-point memory array possible without the need for 3D packaging technology.
  • a high-density 3D stack can be formed, which greatly improves the storage density.
  • Memory devices that can use cross-point memory arrays include two-terminal devices and three-terminal devices, and two-terminal devices such as resistive random access memory (resistive random access memory, RRAM), phase change random access memory (phase change random access memory, PCRAM), iron Electric random access memory (FeRAM), spin-transfer torque magnetic random access memory (spin-transfer torque MRAM (magnetic random access memory, magnetic random access memory), STT-MRAM), etc.
  • the cross-point structure can apply write stimulation through the corresponding word line (word line, WL) and bit line (bit line, BL) for its operation.
  • spin-orbit torque MRAM spin-orbit torque MRAM
  • SOT-MRAM spin-orbit torque MRAM
  • the cross-point memory array has many advantages, its disadvantages are also very serious. Since all memory cells in the cross-point memory array are connected through metal layers, if you want to operate a selected memory cell alone, it will be affected by other memory cells, and this effect will increase with the increase in the size of the cross-point memory array. increase. Read operations are more severely affected by this than write operations. For the read operation of the cross-point memory array, in order to read the state of the selected memory cell (such as "1" state or "0" state) in a large number of interconnected memory cells, the selected memory cell needs to be in any state in other memory cells All combinations have a larger read window (that is, the difference between the "1" state current and the "0" state current). People have tried some methods in this regard, but due to various shortcomings in these methods, this effect still cannot be effectively eliminated, so they have not been applied in mass production on a large scale.
  • the present application provides a read operation circuit, chip and electronic equipment, which can effectively eliminate the influence of other memory cells when performing a read operation on a selected memory cell in a cross-point memory array.
  • an embodiment of the present application provides a read operation circuit, the read operation circuit includes a voltage follower and a sense amplifier; the voltage follower and the sense amplifier are respectively coupled to a cross-point memory array, and the The cross-point memory array includes multiple columns of memory cells and a plurality of bit lines corresponding to the multiple columns of memory cells, and one end of each memory cell of each column of memory cells in the multiple columns of memory cells is connected to each of the multiple columns of memory cells.
  • the bit line corresponding to a column of memory cells is connected; the voltage follower is used to copy the voltage on the target bit line connected to the selected memory cell to other bits in the plurality of bit lines except the target bit line On the line; the sense amplifier is used to perform a read operation on the selected memory cell.
  • the voltage follower when the selected memory cell to be read is selected in the cross-point memory array, that is, when the sense amplifier and the selected memory cell form a path for the read operation, the voltage follower The voltage on the target bit line connected with the selected memory cell is copied to other bit lines except the target bit line in the multiple bit lines of the cross-point memory array; the voltage follower copies the voltage on the target bit line to After other bit lines, the sense amplifier performs a read operation on the selected memory cell; in this way, the voltage on the target bit line connected to the selected memory cell can be made the same as the voltage on other bit lines, that is, in the cross-point memory array The voltage of the column where the selected memory cell is located is the same as the voltage of other columns, so that there will be no leakage current between the column where the selected memory cell is located in the cross-point memory array and other columns. On this basis, the selected memory cell in the cross-point memory array The read operation of the unit can effectively eliminate the influence of other storage units.
  • the read operation circuit further includes a plurality of first switches, and the input terminal of the sense amplifier communicates with the plurality of bits through the plurality of first switches.
  • the lines are connected separately.
  • the cross-point storage array includes at least one row of storage units, and the at least one row of storage units includes the selected storage unit; wherein, in the case of selecting a row of storage units including the selected storage unit in the at least one row of storage units , if the first switch connected to the target bit line is turned on and the first switch connected to the other bit lines is turned off, selecting the selected memory cell in the cross-point memory array.
  • the input end of the sense amplifier is respectively connected to a plurality of bit lines through a plurality of first switches, so that the selection of the selected memory cell can be realized by controlling the on-off of the plurality of first switches;
  • the selected memory cell is connected to the target bit line, and when a row of memory cells including the selected memory cell is selected in the cross-point memory array, the first switch connected to the target bit line is controlled to be turned on, and the first switch connected to the other bit line is controlled to be turned on.
  • the sense amplifier can form a path with the column where the selected memory cell is located and not form a path with other columns, so as to achieve the purpose of selecting the selected memory cell.
  • the multiple first switches are multiple first transistors, and any first transistor in the multiple first transistors It includes a first terminal, a second terminal and a control terminal, the control terminal is used to receive a control signal; the input terminal of the sense amplifier is respectively connected to the first terminals of the plurality of first transistors, and the plurality of first transistors The second terminal of a transistor is correspondingly connected with the plurality of bit lines.
  • control terminal of any one of the first transistors is used to control the on-off of signal transmission between the first terminal and the second terminal of any one of the first transistors; In the case of a row of memory cells of the selected memory cells, if the signal transmission between the first end and the second end of the first transistor connected to the target bit line is turned on, and the signal connection between the first transistor connected to the other bit line The signal transmission between the first terminal and the second terminal of the first transistor is turned off, and the selected memory cell is selected in the cross-point memory array.
  • the input end of the sense amplifier is respectively connected to a plurality of bit lines through a plurality of first transistors, so that the selection of the selected memory cell can be realized by controlling the on-off of the plurality of first transistors; Specifically, the selected memory cell is connected to the target bit line, and when a row of memory cells including the selected memory cell is selected in the cross-point memory array, the first transistor connected to the target bit line is controlled to be turned on, and the first transistor connected to the target bit line is controlled to be connected to other bit lines. By turning off the first transistor connected with the line, the sense amplifier can form a path with the column where the selected memory cell is located and not form a path with other columns, so as to achieve the purpose of selecting the selected memory cell.
  • the multiple first switches are multiple first transmission gates, and any first transmission gate in the multiple first transmission gates
  • a transmission gate includes a first terminal, a second terminal, a non-inverting control terminal and an inverting control terminal, the non-inverting control terminal and the inverting control terminal are used to receive a control signal; the input terminal of the sense amplifier is connected to the The first ends of the plurality of first transmission gates are respectively connected, and the second ends of the plurality of first transmission gates are correspondingly connected to the plurality of bit lines.
  • the non-inverting control terminal and the inverting control terminal of any one of the first transmission gates are used to control the on-off of signal transmission between the first terminal and the second terminal of any one of the first transmission gates; In the case of selecting a row of memory cells including the selected memory cell among at least one row of memory cells, if the signal transmission between the first end and the second end of the first transmission gate connected to the target bit line is turned on, and the signal transmission between the first terminal and the second terminal of the first transmission gate connected to the other bit line is cut off, then the selected memory cell is selected in the cross-point memory array.
  • the input end of the sense amplifier is respectively connected to a plurality of bit lines through a plurality of first transmission gates.
  • the selection of the selected memory cell can be realized by controlling the on-off of the plurality of first transmission gates.
  • the selected memory cell is connected to the target bit line, and when a row of memory cells including the selected memory cell is selected in the cross-point memory array, the first transmission gate connected to the target bit line is controlled to be turned on, and the control The first transmission gate connected to other bit lines is turned off, so that the sense amplifier can form a path with the column where the selected memory cell is located and not form a path with other columns, so as to achieve the purpose of selecting the selected memory cell.
  • the read operation circuit further includes a plurality of second switches, and the voltage The input end of the follower is respectively connected to the plurality of bit lines through the plurality of first switches, and the output end of the voltage follower is respectively connected to the plurality of bit lines through the plurality of second switches.
  • the input end of the voltage follower is respectively connected to the plurality of bit lines through the above-mentioned plurality of first switches, and the output end of the voltage follower is respectively connected to the plurality of bit lines through the plurality of second switches ;
  • the voltage of the column where the selected memory cell is located can be copied to other columns by controlling the on-off of a plurality of second switches; specifically, the selected memory cell The cell is connected to the target bit line, the second switch connected to the target bit line is controlled to be turned off, and the second switch connected to other bit lines is controlled to be turned on, so that the input end of the voltage follower and the column where the selected memory cell is located form a path It does not form a path with other columns, and the output terminal of the voltage follower forms a path with other columns but does not form a path with the column where the selected memory cell is located, so as to achieve the purpose of copying the voltage of the column where the selected memory cell is
  • the plurality of second switches are a plurality of second transistors, and any second transistor in the plurality of second transistors It includes a first end, a second end and a control end, the control end is used to receive a control signal; the output end of the voltage follower is respectively connected to the first ends of the plurality of second transistors, and the plurality of first transistors The second ends of the two transistors are correspondingly connected to the plurality of bit lines.
  • control terminal of any second transistor is used to control the on-off of signal transmission between the first terminal and the second terminal of any second transistor;
  • the control terminal of any second transistor is used to control the on-off of signal transmission between the first terminal and the second terminal of any second transistor;
  • the input terminals of the voltage follower are respectively connected to the multiple bit lines through the above-mentioned multiple first switches, and the output terminals of the voltage follower are respectively connected to the multiple bit lines through multiple second transistors ;
  • the voltage of the column where the selected memory cell is located can be copied to other columns by controlling the on-off of a plurality of second transistors; specifically, the selected memory cell The cell is connected to the target bit line, the second transistor connected to the target bit line is controlled to be turned off, and the second transistor connected to other bit lines is controlled to be turned on, so that the input terminal of the voltage follower and the column where the selected memory cell is located form a path It does not form a path with other columns, and the output terminal of the voltage follower forms a path with other columns but does not form a path with the column where the selected memory cell is located, so as to achieve the purpose of copying the voltage of the column where the selected memory cell is located to other columns.
  • the first control signal input to the control terminal of any one of the first transistors is passed to a row of memory cells including the selected memory cell
  • the address is decoded to obtain;
  • the second control signal input by the control terminal of any second transistor is obtained by inverting the first control signal;
  • the second terminal of any first transistor and the second terminal of any A second terminal of a second transistor is connected to the same bit line among the plurality of bit lines.
  • the positive signal is obtained by decoding the address of a column of memory cells including the selected memory cell
  • the negative signal is obtained by inverting the positive signal input or the negative signal is obtained by decoding the address of a column of memory cells including the selected memory cell
  • the positive signal is obtained by inputting the negative signal into an inverter.
  • any first transistor or any second transistor if a positive signal is input to its control terminal, the signal transmission between the first terminal and the second terminal is turned on; When the negative signal is input to the control terminal, the signal transmission between the first terminal and the second terminal is cut off; the positive signal and the negative signal are collectively referred to as control signals.
  • the control signal is obtained by decoding the address of a column of memory cells corresponding to the bit line connected to it. When this column of memory cells needs to be selected, the decoded control signal corresponding to this column of memory cells is a positive signal. Otherwise, it is decoded to obtain The control signal corresponding to this row of memory cells is the inversion signal.
  • the multi-column storage unit has a plurality of first control signals, and a plurality of second control signals corresponding to the inversion of the plurality of first control signals, and the multi-column storage unit is related to the plurality of first control signals and the plurality of first control signals.
  • the multiple second control signals are in one-to-one correspondence; specifically, the multiple first control signals include one positive signal and multiple negative signals, and the multiple second control signals include one negative signal and multiple positive signals, because When it is necessary to select this column of memory cells, the address of this column of memory cells is decoded to obtain the positive signal corresponding to this column of memory cells and the corresponding inverse signals of other column memory cells, and then the positive signal corresponding to this column of memory cells The inverse signal corresponding to this column of memory cells can be obtained by inputting the inverter, and the positive signal corresponding to other column memory cells can be obtained by inputting the inverse signal corresponding to the other column memory cells into the inverter.
  • the first transistor or the second transistor connected to any bit line Since multiple bit lines correspond to multiple columns of memory cells, if the first transistor or the second transistor connected to any bit line is to be turned on, the first transistor or the second transistor connected to any bit line will be turned on.
  • the corresponding positive signal can be input to the control terminal of the transistor; if the first transistor or the second transistor connected to any bit line is to be cut off, input The corresponding inverse signal is sufficient.
  • the control signals input by the control terminals of the first transistor and the second transistor connected to any bit line are opposite.
  • the control terminal of the first transistor When the control terminal of the first transistor inputs a positive signal, the control terminal of the second transistor inputs an inverted signal; When the control terminal of one transistor inputs an inverse signal, the control terminal of the second transistor inputs a positive signal, so that the complementary selection of the voltage follower and the sense amplifier to the bit line can be realized, that is, the voltage follower and the sense amplifier can realize the pairing of the bit line. Complementary selection of a column of memory cells for the bit line.
  • the plurality of second switches are a plurality of second transmission gates, and any first transmission gate in the plurality of second transmission gates
  • the two transmission gates include a first terminal, a second terminal, a non-inverting control terminal and an inverting control terminal, the non-inverting control terminal and the inverting control terminal are used to receive control signals; the output terminal of the voltage follower is connected to the The first ends of the plurality of second transmission gates are respectively connected, and the second ends of the plurality of second transmission gates are correspondingly connected with the plurality of bit lines.
  • the non-inverting control terminal and the inverting control terminal of any second transmission gate are used to control the on-off of signal transmission between the first terminal and the second terminal of any second transmission gate;
  • the signal transmission between the first end and the second end of the second transmission gate connected to the target bit line is cut off, and it is connected to the other bit line
  • the signal transmission between the first terminal and the second terminal of the second transmission gate is turned on, then the voltage follower copies the voltage on the target bit line to the other bit lines.
  • the input terminals of the voltage follower are respectively connected to the multiple bit lines through the above-mentioned multiple first switches, and the output terminals of the voltage follower are respectively connected to the multiple bit lines through the multiple second transmission gates
  • the voltage of the column where the selected memory cell is located can be copied to other columns by controlling the on-off of a plurality of second transmission gates; specifically, The selected memory cell is connected to the target bit line, the second transmission gate connected to the target bit line is controlled to be turned off, and the second transmission gate connected to other bit lines is controlled to be turned on, so that the input end of the voltage follower and the selected memory cell can be realized.
  • the column in which it is located forms a path but does not form a path with other columns, and the output terminal of the voltage follower forms a path with other columns but does not form a path with the column where the selected memory cell is located, so as to copy the voltage of the column where the selected memory cell is located to other columns.
  • the non-inverting control terminal of any first transmission gate and the inverting control terminal of any second transmission gate input The first control signal is obtained by decoding the address of a row of storage units including the selected storage unit; the inverting control terminal of any one of the first transmission gates and the non-inverting control terminal of any second transmission gate input
  • the second control signal is obtained by inverting the first control signal; the second terminal of any one of the first transmission gates and the second terminal of any one of the second transmission gates are connected to the plurality of bit lines The same bit line connection.
  • the signal transmission between the first terminal and the second terminal of any one of the first transmission gates or any one of the second transmission gates is turned on; if any one of the first transmission gates The inverting signal is input to the non-inverting control terminal of the gate or any second transmission gate, and the positive signal is input to the inverting control terminal of any one of the first transmission gates or the any second transmission gate, Then the signal transmission between the first terminal and the second terminal of any one of the first transmission gates or any one of the second transmission gates is cut off; wherein, the positive signal is stored in a column containing the selected memory unit The address of the unit is decoded, and the negative signal is obtained by inputting the positive signal into the inverter; or the negative signal is obtained by decoding the address of a row of storage units including the selected storage unit, and the positive signal Obtained by inputting the
  • any first transmission gate or any second transmission gate if a positive signal is input at its non-inverting control terminal and an inverse signal is input at its inverting control terminal, its first terminal and the second transmission gate The signal transmission between the two terminals is turned on; if the negative signal is input at its non-inverting control terminal and the positive signal is input at its inverting control terminal, the signal transmission between the first terminal and the second terminal is cut off; the positive signal and the negative signal
  • the signals are collectively referred to as control signals.
  • the control signal is obtained by decoding the address of a column of memory cells corresponding to the bit line connected to it. When this column of memory cells needs to be selected, the decoded control signal corresponding to this column of memory cells is a positive signal.
  • the control signal corresponding to this row of memory cells is the inversion signal.
  • the positive and negative of the control signal can be converted to each other through the inverter: when the control signal is a positive signal, the control signal can be input to the inverter to get the reverse signal; on the contrary, when the control signal is the negative signal, the control After the signal is input to the inverter, a positive signal can be obtained. Therefore, the multi-column storage unit has a plurality of first control signals, and a plurality of second control signals corresponding to the inversion of the plurality of first control signals, and the multi-column storage unit is related to the plurality of first control signals and the plurality of first control signals.
  • the multiple second control signals are in one-to-one correspondence; specifically, the multiple first control signals include one positive signal and multiple negative signals, and the multiple second control signals include one negative signal and multiple positive signals, because When it is necessary to select this column of memory cells, the address of this column of memory cells is decoded to obtain the positive signal corresponding to this column of memory cells and the corresponding inverse signals of other column memory cells, and then the positive signal corresponding to this column of memory cells The inverse signal corresponding to this column of memory cells can be obtained by inputting the inverter, and the positive signal corresponding to other column memory cells can be obtained by inputting the inverse signal corresponding to the other column memory cells into the inverter.
  • the first transmission gate or the second transmission gate connected to any one bit line is to be turned on, the first transmission gate connected to any one bit line Or the non-inverting control terminal of the second transmission gate can input the corresponding positive signal, and the inverting control terminal can input the corresponding negative signal; if the first transmission gate or the second transmission gate connected to any bit line is to be cut off, the The non-inverting control terminal of the first transmission gate or the second transmission gate connected to any one of the bit lines may input a corresponding negative signal, and the inverting control terminal may input a corresponding positive signal.
  • control signals input by the non-inverting control terminal and the inverting control terminal of the first transmission gate connected to any bit line and the second transmission gate are opposite.
  • the first transmission gate When the non-inverting control terminal of the first transmission gate inputs a positive signal, the first transmission gate When the inverting control terminal of the gate inputs the negative signal, the non-inverting control terminal of the second transmission gate inputs the negative signal, and the inverting control terminal of the second transmission gate inputs the positive signal; when the non-inverting control terminal of the first transmission gate inputs the negative signal, the When the inverting control terminal of a transmission gate inputs a positive signal, the non-inverting control terminal of the second transmission gate inputs a positive signal, and the inverting control terminal of the second transmission gate inputs an inverse signal, so that the voltage follower and the sense amplifier can realize the Complementary selection of one bit line, that is, complementary selection of a column of memory cells on the one bit line by the voltage follower and the sense amplifier.
  • the read operation circuit further includes a decoder and an inverter; the decoder is configured to include decoding an address of a column of memory cells of the selected memory cell to obtain the first control signal; the inverter is configured to invert the first control signal to obtain the second control signal .
  • the read operation circuit further includes a decoder and an inverter, and the decoder is used to decode the address of a column of storage units including the selected storage unit to obtain a plurality of first control signals; the inverter is used to The multiple first control signals are inverted to obtain corresponding multiple second control signals. Since the control signal includes positive and negative signals, the positive and negative of the control signal can be converted to each other through the inverter: when the control signal is a positive signal, after the control signal is input into the inverter, the negative signal can be obtained; otherwise, when the When the control signal is an inverse signal, a positive signal can be obtained after the control signal is input into the inverter.
  • a plurality of first control signals include a positive signal and a plurality of inverted signals
  • a plurality of second control signals are obtained after being inverted by an inverter
  • the second control signals include an inverted signal and a plurality of positive signals, thus, it can be obtained
  • the voltage follower includes any of the following: an integrated operational amplifier voltage follower, a common-drain amplifier, an inversion voltage follower.
  • the sense amplifier includes any one of the following: a voltage sense amplifier, a current sense amplifier.
  • the embodiment of the present application provides a read operation circuit, including a voltage follower, a sense amplifier, a first switch array, and a second switch array; the input terminal of the sense amplifier passes through the first switch array The input terminals of the voltage follower are connected to the multiple bit lines respectively through the first switch array, and the output terminals of the voltage follower are connected through the The second switch array is respectively connected to the plurality of bit lines; the cross-point storage array also includes a plurality of columns of storage units corresponding to the plurality of bit lines, and each column of storage units in the plurality of columns of storage units One end of each memory cell is connected to the bit line corresponding to each column of memory cells.
  • the input terminals of the sense amplifier are respectively connected to a plurality of bit lines in the cross-point memory array through the first switch array, and the selection and selection of the input terminals of the sense amplifier can be realized by controlling the first switch array.
  • the target bit line connected to the selected memory cell forms a path for the read operation, and does not form a path for the read operation with other bit lines, so that the selected memory cell to be read in the cross-point memory array can be selected.
  • the input end of the voltage follower is also respectively connected to a plurality of bit lines through the first switch array, when the input end of the sense amplifier forms a path for the read operation with the target bit line, it does not form a path for the read operation with other bit lines.
  • the input terminal of the voltage follower When passing through, the input terminal of the voltage follower also forms a path with the target bit line, and does not form a path with other bit lines.
  • the output terminals of the voltage follower are respectively connected to the plurality of bit lines through the second switch array. By controlling the second switch array, the output terminals of the voltage follower do not form a path with the target bit line, but form a path with other bit lines.
  • the sense amplifier performs a read operation on the selected memory cell; in this way, the voltage on the target bit line connected to the selected memory cell can be the same as the voltage on other bit lines. That is, the voltage of the column where the selected memory cell is located in the cross-point memory array is the same as the voltage of other columns, so that there will be no leakage current between the column where the selected memory cell is located and other columns in the cross-point memory array.
  • the selected storage unit in the point storage array is read, which can effectively eliminate the influence of other storage units.
  • the first switch array includes a plurality of first transistors, and any first transistor in the plurality of first transistors includes a first terminal, a second terminal and a control terminal, the control terminal is used to receive a control signal; the input terminal of the sense amplifier is respectively connected to the first terminals of the plurality of first transistors, and the second terminals of the plurality of first transistors are connected to the The plurality of bit lines are correspondingly connected.
  • the first switch array includes a plurality of first transmission gates, and any first transmission gate in the plurality of first transmission gates includes a first terminal, The second terminal, the non-inverting control terminal and the inverting control terminal, the non-inverting control terminal and the inverting control terminal are used to receive control signals; the input terminal of the sense amplifier is connected to the first transmission gate of the plurality of first transmission gates. One ends are respectively connected, and the second ends of the plurality of first transmission gates are correspondingly connected to the plurality of bit lines.
  • the second switch array includes a plurality of second transistors, and the plurality of second transistors Any second transistor in the second transistor includes a first terminal, a second terminal and a control terminal, and the control terminal is used to receive a control signal; the output terminal of the voltage follower and the first terminals of the plurality of second transistors are respectively connected, the second ends of the plurality of second transistors are correspondingly connected to the plurality of bit lines.
  • the first control signal input to the control terminal of any one of the first transistors is passed to the address of a column of storage units including the selected storage unit. It is obtained by decoding; the second control signal input by the control terminal of any second transistor is obtained by inverting the first control signal; the second terminal of any first transistor and the second terminal of any first transistor The second terminals of the two transistors are connected to the same bit line among the plurality of bit lines.
  • the second switch array includes a plurality of second transmission gates, and the plurality of second Any second transmission gate in the transmission gate includes a first terminal, a second terminal, a non-inverting control terminal and an inverting control terminal, and the non-inverting control terminal and the inverting control terminal are used to receive a control signal; the voltage follows The output ends of the switches are respectively connected to the first ends of the plurality of second transmission gates, and the second ends of the plurality of second transmission gates are correspondingly connected to the plurality of bit lines.
  • the non-inverting control terminal of any first transmission gate and the inverting control terminal of any second transmission gate input
  • the first control signal is obtained by decoding the address of a column of memory cells that includes the selected memory cell; the second signal input by the inverting control terminal of any one of the first transmission gates and the non-inverting control terminal of any of the second transmission gates
  • the control signal is obtained by inverting the first control signal; the second end of any one of the first transmission gates and the second end of any one of the second transmission gates are the same as those of the plurality of bit lines A bit line connection.
  • the read operation circuit further includes a decoder and an inverter; the decoder is configured to Decoding the address of a row of storage units including the selected storage unit to obtain the first control signal; the inverter is configured to invert the first control signal to obtain the second control signal Signal.
  • the voltage follower includes any of the following: an integrated operational amplifier voltage follower, a common-drain amplifier, an inversion voltage follower.
  • the sense amplifier includes any one of the following: a voltage sense amplifier, a current sense amplifier.
  • the embodiment of the present application provides a memory, the memory is provided with a plurality of storage units and the read operation circuit in the first aspect or any possible implementation manner of the first aspect; or, the memory is provided with There are a plurality of storage units and the second aspect or the read operation circuit in any possible implementation manner of the second aspect.
  • an embodiment of the present application provides an electronic device, where the electronic device includes a circuit board and the memory as described in the third aspect.
  • Fig. 1 is a schematic structural diagram of a cross-point memory array
  • Fig. 2 is a schematic diagram of a circuit design for simultaneous readout of each column in the prior art
  • Fig. 3 is a schematic diagram of low-density intersection structure array design
  • Fig. 4 is a schematic diagram of simultaneous readout of a cross-point memory array
  • FIG. 5 is a schematic diagram of the read operation of the cross-point memory array provided by the embodiment of the present application-specific voltage application;
  • FIG. 6 is a schematic structural diagram of a read operation circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another read operation circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another read operation circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an integrated operational amplifier voltage follower provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a common-drain amplifier provided in an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of an inversion voltage follower provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a voltage sense amplifier provided in an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a current sense amplifier provided in an embodiment of the present application.
  • FIG. 14 is a schematic diagram of a read operation circuit provided by an embodiment of the present application applied to a cross-point memory array composed of memory devices at both ends;
  • FIG. 15 is an application schematic diagram of a read operation circuit corresponding to a cross-point memory array composed of multiple two-terminal storage devices provided by the embodiment of the present application;
  • 16 is a schematic diagram of a read operation circuit provided by an embodiment of the present application applied to a cross-point memory array composed of three-terminal memory devices;
  • FIG. 17 is an application schematic diagram of a read operation circuit corresponding to a cross-point memory array composed of a plurality of three-terminal memory devices provided by an embodiment of the present application;
  • FIG. 18 is a schematic diagram of a read operation circuit provided by an embodiment of the present application applied to a multi-layer stacked cross-point memory array;
  • FIG. 19 is a schematic diagram of another read operation circuit provided by an embodiment of the present application applied to a multi-layer stacked cross-point memory array;
  • FIG. 20 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • the read operation technologies related to this application include the following three technologies:
  • Figure 2 is a schematic diagram of a circuit design for reading all memory cells of a certain row on all columns at the same time.
  • the sense amplifier (sense Amp unit) in Figure 2 includes the same number of columns as the cross-point memory array Amplifier (sense amplifier, SA).
  • SA sense amplifier
  • When performing a read operation select a row of the cross-point memory array by selecting the word line (GWL); then apply a voltage to all columns of the cross-point memory array at the same time by the sense Amp unit, and finally apply a voltage to the bit line (SL) Appropriate voltage forms a path for reading current; read the current through the sense Amp unit to obtain the state of the selected memory unit to be read.
  • GWL word line
  • SL bit line
  • Defect of technology 1 When this memory access method reads multiple memory cells at the same time, due to the different read currents of different columns, the voltage on each column will be different, so that leakage current will be generated between each column, resulting in The read currents of different columns crosstalk, and the read window is reduced so that it cannot be read.
  • Technique 2 Design an algorithm to overcome read leakage.
  • the steps for reading the memory array in this scheme are: 1) read the current passing through the selected memory cell; 2) write the selected memory cell as "1" state, and then read the current of the selected memory cell “1” state; 3) write Write the selected memory cell as "0" state, and then read the current of the selected memory cell "0” state; 4) Compare the current read for the second time with the current read for the first time, and judge the initial read current Belong to "1" state or "0” state; 5) restore the selected memory cell to the original state.
  • Figure 3 is a schematic diagram of the design of a low-density cross-point structure array.
  • the design of this cross-point memory array without leakage paths is to keep the metal lines of the rows, and connect the ends of the metal lines of the columns to complementary metal oxide semiconductors (complementary metal oxide semiconductor, CMOS) multiplexer.
  • CMOS complementary metal oxide semiconductor
  • the specific technical problems to be solved in this application include the following aspects: on the premise of ensuring the high storage density of the cross-point memory array, during the read operation of the selected storage unit, eliminate the impact of other storage units on the selected storage unit. Influenced by the read operation, the read window of the cross-point memory array is increased.
  • V1 is greater than V0.
  • V1 is greater than V0.
  • V1 when there is a row connection between each column, there will be a current flowing from the second column to the first column on each row between the first column and the second column.
  • the essential reason why the cross-point memory array cannot effectively read is that the voltage/current of different rows/columns will affect other rows/columns through the memory cells.
  • This application copies the voltage on the selected memory cell column in the cross-point memory array to other columns through a voltage follower (voltage follower), thus avoiding the influence of the leakage current of other columns on the current entering the read operation module through the selected memory cell , increasing the window for read operations.
  • this application suppresses leakage by equalizing voltages.
  • This application requires peripheral circuits to provide specific voltages to the rows/columns of the cross-point memory array so that an equipotential state is formed between rows or between columns. To achieve leakage suppression.
  • the current/voltage generated during the read operation is determined by the selected memory cell to be read, so it is impossible to predict how much voltage will be used to suppress other rows/columns to form an equipotential before the read operation.
  • the present application proposes to use a voltage replica circuit (voltage follower circuit) to replicate the voltage on the row/column corresponding to the selected memory cell, and apply the voltage to the row/column where other non-selected memory cells in the same cross-point memory array are located. superior.
  • a voltage replica circuit voltage follower circuit
  • Figure 5 is a schematic diagram of the read operation of the cross-point memory array provided by the embodiment of the present application-specific voltage application; in an N*N cross-point memory array, if it is necessary to read the third row and the first column
  • the memory cells of that is, the memory cells of the third row and the first column are the selected memory cells to be read. Therefore, connect the first column metal line to the sense amplifier.
  • the sense amplifier can compare the input signal with the reference signal, wherein the reference signal is the signal from the reference storage unit (ref cell) in Figure 5, and if the input signal is greater than the reference signal, it outputs "1" or "0".
  • the application may wish to assume that if the input signal is greater than the reference signal, it will output "1"; if the input signal is less than the reference signal, it will output "0"; thus realizing the read operation of the memory cells in the third row and first column.
  • the comparator ie, the sense amplifier
  • the corresponding setting of the voltage in the array is: connect the third row to a voltage V1; disconnect the other rows, that is, floating, so that the third row is selected.
  • a voltage follower is connected to the column where the selected memory cell is located (that is, the first column) to copy the voltage signal to the column where the other non-selected memory cells are located (also known as the first column). i.e. on columns other than the first).
  • the voltage on the metal lines in the first column is V0
  • the voltages on the columns where the other unselected memory cells are located are also V0. Therefore, the current entering the comparator through the selected memory cell will not be affected by the leakage current of other columns, which increases the readout window.
  • FIG. 6 is a schematic structural diagram of a read operation circuit provided by an embodiment of the present application;
  • the read operation circuit includes a voltage follower (voltage follower) and a sense amplifier (SA);
  • the voltage follower and the The sense amplifiers are respectively coupled to the cross-point memory array,
  • the cross-point memory array includes multiple columns of memory cells and a plurality of bit lines corresponding to the multiple columns of memory cells, each column of the multiple columns of memory cells One end of each memory cell of the memory cell is connected to the bit line corresponding to each column of memory cells;
  • the voltage follower is used to copy the voltage on the target bit line connected to the selected memory cell to the multiple Other bit lines in the bit lines except the target bit line;
  • the sense amplifier is used to perform a read operation on the selected memory cell.
  • connection between A and B can be direct connection between A and B, or indirect connection between A and B through one or more other electrical components, for example, it can be direct connection between A and C, and direct connection between C and B. , so that A and B are connected through C.
  • the technical solution provided by the present application can be applied to cross-point memory arrays of various memories.
  • the cross-point memory array can have an independent cross-point structure in the entire array, or can be divided into multiple independent cross-point structure arrays by transistors.
  • the storage unit of the cross-point memory array can be a two-terminal storage unit, such as non-volatile random access memory such as resistive memory (RRAM), phase change memory (PCRAM), ferroelectric memory (FeRAM), magnetic memory (STT-MRAM) .
  • the storage unit of the cross-point memory array may also be a three-terminal memory, such as a spin-orbit torque magnetic random access memory (SOT-MRAM, etc.).
  • SOT-MRAM spin-orbit torque magnetic random access memory
  • the cross-point memory array can be single-layer or multi-layer.
  • the read operation circuit and the cross-point memory array of the present application can be integrated in one die, or can be integrated in respective dies and packaged in a chip package structure; or as an independent
  • the chip is arranged on the printed circuit board PCB.
  • the aforementioned multi-column memory cells can be all column memory cells in the cross-point memory array, and can also be some column memory cells in the cross-point memory array; the aforementioned multiple bit lines can be all the bit lines in the cross-point memory array , can also store part of the bit lines in the array for the cross point.
  • the selected storage unit is one of the storage units in the multiple columns of storage units, and the selected storage unit is a storage unit selected for a read operation.
  • the selected storage unit to be read is selected in the cross-point memory array, that is, the sense amplifier and the selected storage unit form a path for the read operation;
  • One end of each memory cell will be connected to the same bit line, so the voltage follower will copy the voltage on the target bit line to other bit lines, that is, the voltage follower will copy the voltage of the column where the selected memory cell in the cross-point storage array is located. copied to other columns.
  • the process that the sense amplifier performs the read operation on the selected memory cell is: after the sense amplifier forms a path for the read operation in the selected memory cell, there is a flow from the sense amplifier to the selected memory cell between the sense amplifier and the selected memory cell. Therefore, there is an input signal at the input terminal of the sense amplifier; and after the voltage follower copies the voltage of the column where the selected memory cell is located to other columns, the input signal will not be crosstalked by other columns in the cross-point memory array, and the readout
  • the amplifier compares the input signal with a reference signal to determine the state of the selected memory cell.
  • the voltage follower can copy the voltage of the input terminal from its input terminal, and obtain a voltage equal to the input terminal at its output terminal; the voltage follower has a higher input resistance and a lower output resistance.
  • the voltage follower when the selected memory cell to be read is selected in the cross-point memory array, that is, when the sense amplifier and the selected memory cell form a path for the read operation, the voltage follower will The voltage on the target bit line connected to the selected memory cell is copied to other bit lines except the target bit line in the multiple bit lines of the cross-point memory array; the voltage follower copies the voltage on the target bit line to other After the bit line, the sense amplifier reads the selected memory cell; in this way, the voltage on the target bit line connected to the selected memory cell is the same as the voltage on other bit lines, that is, the selected memory cell in the cross-point memory array The voltage of the column where the memory cell is located is the same as the voltage of other columns, so that there will be no leakage current between the column where the selected memory cell is located in the cross-point memory array and other columns. On this basis, the selected memory cell in the cross-point memory array Performing a read operation can effectively eliminate the influence of other storage units.
  • the read operation circuit further includes a plurality of first switches, and an input terminal of the sense amplifier is respectively connected to the plurality of bit lines through the plurality of first switches.
  • the cross-point storage array includes at least one row of storage units, and the at least one row of storage units includes the selected storage unit; wherein, in the case of selecting a row of storage units including the selected storage unit in the at least one row of storage units , if the first switch connected to the target bit line is turned on and the first switch connected to the other bit lines is turned off, selecting the selected memory cell in the cross-point memory array.
  • the input ends of the sense amplifiers are respectively connected to one ends of the plurality of first switches, and the other ends of the plurality of first switches are connected to the plurality of bit lines in a one-to-one correspondence.
  • the first switch in the read operation circuit is connected to the bit line in the cross-point memory array, and each bit line in the plurality of bit lines in the cross-point memory array is connected to one of the column memory cells in the multi-column memory cells.
  • One end of each memory cell of the unit is connected, that is, the first switch is connected to a row of memory cells through a bit line.
  • the present application is briefly described as the first switch and the column in the cross-point memory array ( storage unit) connection.
  • a certain device described elsewhere in this application is connected to a column (memory unit) in the cross-point memory array through a bit line, which can be described as the device being connected to a column (memory unit) in the cross-point memory array.
  • the plurality of first switches are respectively the first switch [0], the first switch [1], the first switch [2], ..., the first switch [2 m+1 -2] and the first switch
  • One switch [2 m+1 -1] multi-column storage units are in[0], in[1], in[2], ..., in[2 m+1 -2] and in [2 m+1 -1]; first switch [0], first switch [1], first switch [2], ..., first switch [2 m+1 -2] and first switch A switch [2 m+1 -1] with in[0], in[1], in[2], ..., in[2 m+1 -2] and in[2 m+1 - 1] One-to-one correspondence connection.
  • the number of columns in the cross-point memory array may be the same as or different from the number of the plurality of first switches.
  • the cross-point storage array is an N*N cross-point storage array
  • the value of N may be 2 m+1
  • the value of N may not be 2 m+1 .
  • the plurality of first switches are connected to all column storage units in the cross-point memory array in a one-to-one correspondence.
  • the number of switches in the plurality of first switches are connected to the multi-column memory cells in the cross-point memory array in a one-to-one correspondence, and part of the first switches
  • the number of switches is the number of columns of the multi-column storage unit.
  • the plurality of first switches are connected in one-to-one correspondence with some column storage units in the cross-point memory array, and the columns of the part column storage units The number is the number of the plurality of first switches.
  • the sense amplifier, the voltage follower and the first switch and the second switch connected to the memory array have very low internal resistance.
  • the specific operation of selecting a row of memory cells containing the selected memory cell among at least one row of memory cells in the cross-point memory array can be as follows: a voltage is applied to the row of memory cells containing the selected memory cell, while the other rows disconnect.
  • other schemes for selecting a column in the cross-point memory array may also be adopted, which is not specifically limited in this application.
  • the input terminals of the sense amplifier are respectively connected to multiple columns of memory cells in the cross-point memory array through a plurality of first switches, so that the cross-point memory array can be selected by controlling the on-off of the plurality of first switches.
  • Determining a column of memory cells for read operation that is, selecting a column of memory cells in the cross-point memory array and forming a path for read operation with the sense amplifier by controlling on-off of a plurality of first switches.
  • selecting a row of memory cells containing the selected memory cell among at least one row of memory cells in the cross-point memory array if a row of memory cells containing the selected memory cell is selected in the cross-point memory array, it can be realized in the cross-point memory array.
  • Select the selected storage unit in the cross-point storage array Specifically, in the case that a row of memory cells containing the selected memory cell is selected among at least one row of memory cells in the cross-point memory array, the first switch connected to the row of memory cells containing the selected memory cell is controlled to be turned on, and the first switch connected to the other column of memory cells is controlled to be turned on.
  • the first switch connected to the column memory unit is turned off; that is, the first switch connected to the target bit line is controlled to be turned on, and the first switch connected to other bit lines is controlled to be turned off, so that the selected memory cell can be selected in the cross-point memory array. unit.
  • the input end of the sense amplifier is respectively connected to a plurality of bit lines through a plurality of first switches, so that the selection of the selected memory cell can be realized by controlling the on-off of the plurality of first switches;
  • the selected memory cell is connected to the target bit line, and when a row of memory cells including the selected memory cell is selected in the cross-point memory array, the first switch connected to the target bit line is controlled to be turned on, and the first switch connected to the other bit line is controlled to be turned on.
  • the sense amplifier can form a path with the column where the selected memory cell is located and not form a path with other columns, so as to achieve the purpose of selecting the selected memory cell.
  • the multiple first switches are multiple first transistors, and any first transistor in the multiple first transistors includes a first terminal, a second terminal, and a control terminal, so The control terminal is used to receive a control signal; the input terminal of the sense amplifier is respectively connected to the first terminals of the plurality of first transistors, and the second terminals of the plurality of first transistors are connected to the plurality of bit lines corresponding connection.
  • control terminal of any one of the first transistors is used to control the on-off of signal transmission between the first terminal and the second terminal of any one of the first transistors; In the case of a row of memory cells of the selected memory cells, if the signal transmission between the first end and the second end of the first transistor connected to the target bit line is turned on, and the signal connection between the first transistor connected to the other bit line The signal transmission between the first terminal and the second terminal of the first transistor is turned off, and the selected memory cell is selected in the cross-point memory array.
  • control terminal of any first transistor is a gate/base terminal; any first transistor may further include a third terminal, and the third terminal of any first transistor is connected to a fixed signal.
  • the second ends of the plurality of first transistors are correspondingly connected to the plurality of bit lines, including: when the number of the plurality of first transistors is the same as the number of the plurality of bit lines, the second ends of the plurality of first transistors are connected to the plurality of bit lines.
  • the bit lines are connected in one-to-one correspondence; when the number of the plurality of first transistors is less than the number of the plurality of bit lines, the second ends of the plurality of first transistors are connected to part of the bit lines in the plurality of bit lines in a one-to-one correspondence, the The number of part of the bit lines is the same as the number of the plurality of first transistors; The bit lines are connected in one-to-one correspondence, and the number of the part of the first transistors is the same as the number of the plurality of bit lines.
  • the plurality of first transistors are respectively Q1[0], Q1[1], Q1[2], ..., Q1[2 m+1 -2], and Q1[2 m+1 - 1 ], the input of the sense amplifier is connected to the The first ends are connected respectively, and the second ends of Q1[0], Q1[1], Q1[2], ..., Q1[2 m+1 -2] and Q1[2 m+1 -1] are connected to in[0], in[1], in[2], ..., in[2 m+1 -2] and in[2 m+1 -1] one-to-one connection, Q1[0], Q1[1] , Q1[2],..., Q1[2 m+1 -2] and the control terminals of Q1[2 m+1 -1] (the unconnected port of the first transistor in Figure 7) are used to control their respective On-off of signal transmission between the first end and the second end.
  • the input end of the sense amplifier is respectively connected to a plurality of bit lines through a plurality of first transistors, so that the selection of the selected memory cell can be realized by controlling the on-off of the plurality of first transistors; Specifically, the selected memory cell is connected to the target bit line, and when a row of memory cells including the selected memory cell is selected in the cross-point memory array, the first transistor connected to the target bit line is controlled to be turned on, and the first transistor connected to the target bit line is controlled to be connected to other bit lines. By turning off the first transistor connected with the line, the sense amplifier can form a path with the column where the selected memory cell is located and not form a path with other columns, so as to achieve the purpose of selecting the selected memory cell.
  • the plurality of first switches are a plurality of first transmission gates, and any first transmission gate in the plurality of first transmission gates includes a first terminal, a second terminal, a non-inverting A control terminal and an inverting control terminal, the non-inverting control terminal and the inverting control terminal are used to receive control signals; the input terminals of the sense amplifier are respectively connected to the first terminals of the plurality of first transmission gates, The second ends of the plurality of first transmission gates are correspondingly connected to the plurality of bit lines.
  • the non-inverting control terminal and the inverting control terminal of any one of the first transmission gates are used to control the on-off of signal transmission between the first terminal and the second terminal of any one of the first transmission gates; In the case of selecting a row of memory cells including the selected memory cell among at least one row of memory cells, if the signal transmission between the first end and the second end of the first transmission gate connected to the target bit line is turned on, and the signal transmission between the first terminal and the second terminal of the first transmission gate connected to the other bit line is cut off, then the selected memory cell is selected in the cross-point memory array.
  • the transmission gate has a small internal resistance
  • the first switch adopts the first transmission gate, which can reduce the internal resistance of the switch, so that the final signal applied to the cross-point memory array is more accurate.
  • the second terminals of the plurality of first transmission gates are correspondingly connected to the plurality of bit lines, including: when the number of the plurality of first transmission gates is the same as the number of the plurality of bit lines, the second ends of the plurality of first transmission gates Terminals are connected to a plurality of bit lines in one-to-one correspondence; when the quantity of the plurality of first transmission gates is less than the quantity of the plurality of bit lines, the second ends of the plurality of first transmission gates are connected to part of the bit lines in the plurality of bit lines.
  • the number of the part of the bit lines is the same as the number of the plurality of first transmission gates; when the number of the plurality of first transmission gates is greater than the number of the plurality of bit lines, part of the first transmission gates
  • the second end of a transmission gate is connected to a plurality of bit lines in one-to-one correspondence, and the number of the first transmission gates in this part is the same as the number of the plurality of bit lines.
  • the multiple first transmission gates are T1[0], T1[1], T1[2], ..., T1[2 m+1 -2] and T1[2 m+1 -1]
  • the input of the sense amplifier is connected to T1[0], T1[1], T1[2], ..., T1[2 m+1 -2] and T1[2 m+1 -1]
  • the first ends of T1[0], T1[1], T1[2], ..., T1[2 m+1 -2] and the second ends of T1[2 m+1 -1] are respectively connected One-to-one connection with in[0], in[1], in[2], ..., in[2 m+1 -2] and in[2 m+1 -1], T1[0], T1[1 ], T1[2],..., T1[2 m+1 -2] and T1[2 m+1 -1] non-inverting control terminal and inverting control terminal (the first transmission gate is not connected in Fig. 8 ports
  • the input end of the sense amplifier is respectively connected to a plurality of bit lines through a plurality of first transmission gates.
  • the selection of the selected memory cell can be realized by controlling the on-off of the plurality of first transmission gates.
  • the selected memory cell is connected to the target bit line, and when a row of memory cells including the selected memory cell is selected in the cross-point memory array, the first transmission gate connected to the target bit line is controlled to be turned on, and the control The first transmission gate connected to other bit lines is turned off, so that the sense amplifier can form a path with the column where the selected memory cell is located and not form a path with other columns, so as to achieve the purpose of selecting the selected memory cell.
  • the read operation circuit further includes a plurality of second switches, the input terminals of the voltage follower are respectively connected to the plurality of bit lines through the plurality of first switches, and the The output terminal of the voltage follower is respectively connected to the plurality of bit lines through a plurality of second switches.
  • the input terminals of the voltage follower are respectively connected to one terminal of the plurality of first switches, and the input terminals of the voltage follower and the input terminals of the sense amplifier are connected to the same terminal of the plurality of first switches;
  • the output ends of the voltage follower are respectively connected to one ends of the plurality of second switches, and the other ends of the plurality of second switches are correspondingly connected to a plurality of bit lines in the cross-point memory array.
  • the plurality of second switches are respectively the second switch [0], the second switch [1], the second switch [2], ..., the second switch [2 m+1 -2], and the second switch [2 m+1 -2] and the second switch [2].
  • the cooperative work of the sense amplifier and the voltage follower is required. Specifically, when the sense amplifier is made to select a certain column of memory cells in the cross-point memory array, the voltage follower does not select the column of memory cells; When , the voltage follower selects the column of memory cells. Therefore, when the selected memory cell is selected in the cross-point memory array, the sense amplifier selects a column of memory cells containing the selected memory cell and does not select other column memory cells, so the voltage follower selects other column memory cells and does not select the other column memory cells. Select a column of memory cells of the memory cell.
  • the sense amplifier selects a column of memory cells containing the selected memory cell and does not select other column memory cells
  • the first switch connected to the column of memory cells containing the selected memory cell has been turned on, and the first switch connected to the other column of memory cells is turned on.
  • the first switch is cut off; if the voltage follower selects other row memory cells but does not select a row of memory cells that include the selected memory cell, it is necessary to make the second switch that is connected to the row of memory cells that includes the selected memory cell be turned off, and then make the connection with other The second switches connected to the column memory cells are turned on.
  • the input end of the voltage follower forms a path with a column of memory cells containing the selected memory cell
  • the output end of the voltage follower forms a path with other column memory cells, so that the voltage follower realizes the voltage on the column of memory cells containing the selected memory cell copied to other column storage units.
  • the input end of the voltage follower is respectively connected to the plurality of bit lines through the above-mentioned plurality of first switches, and the output end of the voltage follower is respectively connected to the plurality of bit lines through the plurality of second switches ;
  • the voltage of the column where the selected memory cell is located can be copied to other columns by controlling the on-off of a plurality of second switches; specifically, the selected memory cell The cell is connected to the target bit line, the second switch connected to the target bit line is controlled to be turned off, and the second switch connected to other bit lines is controlled to be turned on, so that the input end of the voltage follower and the column where the selected memory cell is located form a path It does not form a path with other columns, and the output terminal of the voltage follower forms a path with other columns but does not form a path with the column where the selected memory cell is located, so as to achieve the purpose of copying the voltage of the column where the selected memory cell is
  • a plurality of first switches may form a first switch array, and a plurality of second switches may form a second switch array.
  • the plurality of second switches are a plurality of second transistors, and any second transistor in the plurality of second transistors includes a first terminal, a second terminal, and a control terminal, so The control terminal is used to receive a control signal; the output terminal of the voltage follower is respectively connected to the first terminals of the plurality of second transistors, and the second terminals of the plurality of second transistors are connected to the plurality of bit lines corresponding connection.
  • control terminal of any second transistor is used to control the on-off of signal transmission between the first terminal and the second terminal of any second transistor;
  • the control terminal of any second transistor is used to control the on-off of signal transmission between the first terminal and the second terminal of any second transistor;
  • control terminal of any second transistor is a gate/base terminal; any second transistor can also include a third terminal, and the third terminal of any second transistor is connected to a fixed Signal.
  • the second ends of the plurality of second transistors are correspondingly connected to the plurality of bit lines, including: when the number of the plurality of second transistors is the same as the number of the plurality of bit lines, the second ends of the plurality of second transistors are connected to the plurality of bit lines.
  • the bit lines are connected in one-to-one correspondence; when the number of the plurality of second transistors is less than the number of the plurality of bit lines, the second ends of the plurality of second transistors are connected to part of the bit lines in the plurality of bit lines in a one-to-one correspondence, the The number of part of the bit lines is the same as the number of the plurality of second transistors; The bit lines are connected in one-to-one correspondence, and the number of the part of the second transistors is the same as the number of the plurality of bit lines.
  • the plurality of second transistors are respectively Q2[0], Q2[1], Q2[2], ..., Q2[2 m+1 -2], and Q2[2 m+1 - 1]
  • the input terminal of the voltage follower is connected to the Q1[0], Q1[1], Q1[2], ..., Q1[2 m+1 -2] and Q1[2 m+1 -1]
  • the first terminals are connected respectively, and the output terminals of the voltage follower are connected to Q2[0], Q2[1], Q2[2], ..., Q2[2 m+1 -2] and Q2[2 m+1 - 1] are respectively connected to the first ends of Q2[0], Q2[1], Q2[2], ..., Q2[2 m+1 -2] and Q2[2 m+1 -1]
  • the two ends are connected with in[0], in[1], in[2], ..., in[2 m+1 -2] and in[2 m+1 -1]
  • the input terminals of the voltage follower are respectively connected to the multiple bit lines through the above-mentioned multiple first switches, and the output terminals of the voltage follower are respectively connected to the multiple bit lines through multiple second transistors ;
  • the voltage of the column where the selected memory cell is located can be copied to other columns by controlling the on-off of a plurality of second transistors; specifically, the selected memory cell The cell is connected to the target bit line, the second transistor connected to the target bit line is controlled to be turned off, and the second transistor connected to other bit lines is controlled to be turned on, so that the input terminal of the voltage follower and the column where the selected memory cell is located form a path It does not form a path with other columns, and the output terminal of the voltage follower forms a path with other columns but does not form a path with the column where the selected memory cell is located, so as to achieve the purpose of copying the voltage of the column where the selected memory cell is located to other columns.
  • the first control signal input by the control terminal of any one of the first transistors is obtained by decoding the address of a column of memory cells including the selected memory cell;
  • the second control signal input by the control terminal of the control terminal is obtained by inverting the first control signal;
  • the second terminal of any one of the first transistors and the second terminal of any one of the second transistors are connected to the plurality of The same bit line connection in the bit line.
  • the positive signal is obtained by decoding the address of a column of memory cells including the selected memory cell
  • the negative signal is obtained by inverting the positive signal input or the negative signal is obtained by decoding the address of a column of memory cells including the selected memory cell
  • the positive signal is obtained by inputting the negative signal into an inverter.
  • the address of the multi-column storage unit is decoded, for example, the multi-column storage unit is a 2 m+1 column storage unit, and the address of any column storage unit in the multi-column storage unit is an address of m+1 bits , that is, the address of any column of memory cells can be represented by an address of m+1 bits, and the address corresponding to any column of memory cells of m+1 bits is decoded to obtain 2 m+1 first control signals after decoding, and
  • the 2m+1 first control signals are in one-to-one correspondence with the 2m+1 columns of memory cells, wherein the 2m+1 first control signals include a positive signal corresponding to any column of memory cells and other 2 m+1 -1 columns of memory cells correspond to 2 m+1 -1 inverted signals one by one; at the same time, the corresponding second control signals are obtained after the 2 m+1 first control signals are passed into the inverter signal, that is, to obtain 2 m+1 second control signals corresponding to the 2 m+1 first control signals one by
  • the input terminal of the sense amplifier is connected to the 2 m+1 columns of memory cells in the array through the 2 m+1 first transistors; similarly, the input terminal of the voltage follower is also connected to the array through the 2 m+1 first transistors.
  • the 2 m+1 columns of memory cells in the array are connected, and the output terminal of the voltage follower is also connected to the 2 m+1 columns of memory cells in the array through the 2 m+1 second transistors.
  • the number of columns connected to the sense amplifier and the voltage follower can be set according to the power consumption and performance specifications of the circuit design, which is not specifically limited in this application.
  • the decoded first control signal and the corresponding second control signal are used on the control terminals of these transistors.
  • the decoded first control signal corresponding to the column of memory cells is a positive signal, and is applied to the control read Output the control terminal of the first transistor connected to the storage unit of the column; input the first control signal (positive signal) corresponding to the storage unit of the column into the inverter to obtain the second control signal corresponding to the storage unit of the column.
  • the second control signal corresponding to the memory cell is an inversion signal, and is applied to the control terminal of the second transistor connected to the memory cell of the column of the control voltage follower.
  • the decoded first control signal corresponding to the column of memory cells is an inverse signal, and is applied to the control sense amplifier.
  • the control terminal of the first transistor connected with the memory cell of the column; the first control signal (inverse signal) corresponding to the memory cell is input into the inverter to obtain the second control signal corresponding to the memory cell of the column, and the memory cell of the column corresponds to the second control signal
  • the second control signal is a positive signal, and is applied to the control terminal of the second transistor connected to the column of memory cells of the control voltage follower.
  • the address of any row of memory cells is the address of m+1 bits, and the addresses of the m+1 bits are address [0], address [1], address [ 2], ..., address [m-1] and address [m], 2 m+1 first control signals are respectively control signal a[0], control signal a[1], control signal a[2 ],..., control signal a[2 m+1 -2] and control signal a[2 m+1 -1], 2 m+1 second control signals are control signal b[0] , control signal b[1], control signal b[2], ..., control signal b[2 m+1 -2] and control signal b[2 m+1 -1]; multiple first The transistors are respectively Q1[0], Q1[1], Q1[2], ..., Q1[2 m+1 -2], and Q1[2 m+1 -1], and the plurality of second transistors are respectively Q2[0], Q2[1], Q2[2], ...
  • the control signal a[0] is a positive signal, it is applied to the control of the first transistor Q1[0] that controls the connection between the sense amplifier and the memory cells in the in[0] column terminal (for example, gate terminal), then the control signal b[0] is an inverted signal, and is applied to the control terminal (for example, gate terminal) of the second transistor Q2[0] that is connected to the control voltage follower and the in[0] column memory cells , at this time, the first transistor Q1[0] is turned on, and the second transistor Q2[0] is turned off, then the sense amplifier selects the in[0] column memory cell, and the voltage follower does not select the in[0] column memory cell; if The control signal a[0] is an inverse signal and is applied to the control terminal (such as the gate terminal) of the first transistor Q1[0], then the control signal b[0] is a positive signal and is applied to the second transistor Q
  • the inverter described in this application is any device capable of converting positive signals and negative signals, for example, it may be a level shifter.
  • any first transistor or any second transistor if a positive signal is input to its control terminal, the signal transmission between the first terminal and the second terminal is turned on; When the negative signal is input to the control terminal, the signal transmission between the first terminal and the second terminal is cut off; the positive signal and the negative signal are collectively referred to as control signals.
  • the control signal is obtained by decoding the address of a column of memory cells corresponding to the bit line connected to it. When this column of memory cells needs to be selected, the decoded control signal corresponding to this column of memory cells is a positive signal. Otherwise, it is decoded to obtain The control signal corresponding to this row of memory cells is the inversion signal.
  • the multi-column storage unit has a plurality of first control signals, and a plurality of second control signals corresponding to the inversion of the plurality of first control signals, and the multi-column storage unit is related to the plurality of first control signals and the plurality of first control signals.
  • the multiple second control signals are in one-to-one correspondence; specifically, the multiple first control signals include one positive signal and multiple negative signals, and the multiple second control signals include one negative signal and multiple positive signals, because When it is necessary to select this column of memory cells, the address of this column of memory cells is decoded to obtain the positive signal corresponding to this column of memory cells and the corresponding inverse signals of other column memory cells, and then the positive signal corresponding to this column of memory cells The inverse signal corresponding to this column of memory cells can be obtained by inputting the inverter, and the positive signal corresponding to other column memory cells can be obtained by inputting the inverse signal corresponding to the other column memory cells into the inverter.
  • the first transistor or the second transistor connected to any bit line Since multiple bit lines correspond to multiple columns of memory cells, if the first transistor or the second transistor connected to any bit line is to be turned on, the first transistor or the second transistor connected to any bit line will be turned on.
  • the corresponding positive signal can be input to the control terminal of the transistor; if the first transistor or the second transistor connected to any bit line is to be cut off, input The corresponding inverse signal is sufficient.
  • the control signals input by the control terminals of the first transistor and the second transistor connected to any bit line are opposite.
  • the control terminal of the first transistor When the control terminal of the first transistor inputs a positive signal, the control terminal of the second transistor inputs an inverted signal; When the control terminal of one transistor inputs an inverse signal, the control terminal of the second transistor inputs a positive signal, so that the complementary selection of the voltage follower and the sense amplifier to the bit line can be realized, that is, the voltage follower and the sense amplifier can realize the pairing of the bit line. Complementary selection of a column of memory cells for the bit line.
  • the plurality of second switches are a plurality of second transmission gates, and any second transmission gate in the plurality of second transmission gates includes a first terminal, a second terminal, a non-inverting a control terminal and an inverting control terminal, the non-inverting control terminal and the inverting control terminal are used to receive control signals; the output terminals of the voltage follower are respectively connected to the first terminals of the plurality of second transmission gates, The second ends of the plurality of second transmission gates are correspondingly connected to the plurality of bit lines.
  • the non-inverting control terminal and the inverting control terminal of any second transmission gate are used to control the on-off of signal transmission between the first terminal and the second terminal of any second transmission gate;
  • the signal transmission between the first end and the second end of the second transmission gate connected to the target bit line is cut off, and it is connected to the other bit line
  • the signal transmission between the first terminal and the second terminal of the second transmission gate is turned on, then the voltage follower copies the voltage on the target bit line to the other bit lines.
  • the transmission gate has a small internal resistance
  • the second switch adopts the second transmission gate, which can reduce the internal resistance of the switch, so that the final signal applied to the cross-point memory array is more accurate.
  • the second terminals of the plurality of second transmission gates are correspondingly connected to the plurality of bit lines, including: when the number of the plurality of second transmission gates is the same as the number of the plurality of bit lines, the second ends of the plurality of second transmission gates Terminals are connected to a plurality of bit lines in one-to-one correspondence; when the quantity of the plurality of second transmission gates is less than the quantity of the plurality of bit lines, the second terminals of the plurality of second transmission gates are connected to some bit lines in the plurality of bit lines.
  • the number of the part of the bit lines is the same as the number of the plurality of second transmission gates; when the number of the plurality of second transmission gates is greater than the number of the plurality of bit lines, part of the second transmission gates
  • the second ends of the two transmission gates are connected to the plurality of bit lines in one-to-one correspondence, and the number of the second transmission gates in this part is the same as the number of the plurality of bit lines.
  • the multiple second transmission gates are T2[0], T2[1], T2[2], ..., T2[2 m+1 -2] and T2[2 m+1 -1]
  • the input terminals of the voltage follower are connected to T1[0], T1[1], T1[2], ..., T1[2 m+1 -2] and T1[2 m+1 -1]
  • the first terminals of the voltage follower are connected respectively, and the output terminals of the voltage follower are connected with T2[0], T2[1], T2[2], ..., T2[2 m+1 -2] and T2[2 m+1
  • the first ends of -1] are connected respectively, T2[0], T2[1], T2[2], ..., T2[2 m+1 -2] and T2[2 m+1 -1]
  • the second terminal is connected to in[0], in[1], in[2], ..., in[2 m+1 -2] and in[2 m+1
  • the input terminals of the voltage follower are respectively connected to the multiple bit lines through the above-mentioned multiple first switches, and the output terminals of the voltage follower are respectively connected to the multiple bit lines through the multiple second transmission gates
  • the voltage of the column where the selected memory cell is located can be copied to other columns by controlling the on-off of a plurality of second transmission gates; specifically, The selected memory cell is connected to the target bit line, the second transmission gate connected to the target bit line is controlled to be turned off, and the second transmission gate connected to other bit lines is controlled to be turned on, so that the input end of the voltage follower and the selected memory cell can be realized.
  • the column in which it is located forms a path but does not form a path with other columns, and the output terminal of the voltage follower forms a path with other columns but does not form a path with the column where the selected memory cell is located, so as to copy the voltage of the column where the selected memory cell is located to other columns.
  • the first control signal input by the non-inverting control terminal of any one of the first transmission gates and the inverting control terminal of any second transmission gate is passed to the memory cell containing the selected storage unit.
  • the address of a column of memory cells is decoded to obtain; the second control signal input by the inverting control terminal of any one of the first transmission gates and the non-inverting control terminal of any second transmission gate is performed on the first control signal It is obtained by inversion; the second end of any one of the first transmission gates and the second end of any one of the second transmission gates are connected to the same bit line among the plurality of bit lines.
  • the signal transmission between the first terminal and the second terminal of any one of the first transmission gates or any one of the second transmission gates is turned on; if any one of the first transmission gates The inverting signal is input to the non-inverting control terminal of the gate or any second transmission gate, and the positive signal is input to the inverting control terminal of any one of the first transmission gates or the any second transmission gate, Then the signal transmission between the first terminal and the second terminal of any one of the first transmission gates or any one of the second transmission gates is cut off; wherein, the positive signal is stored in a column containing the selected memory unit The address of the unit is decoded, and the negative signal is obtained by inputting the positive signal into the inverter; or the negative signal is obtained by decoding the address of a row of storage units including the selected storage unit, and the positive signal Obtained by inputting the
  • the address of the multi-column storage unit is decoded, for example, the multi-column storage unit is a 2 m+1 column storage unit, and the address of any column storage unit in the multi-column storage unit is an address of m+1 bits , that is, the address of any column of memory cells can be represented by an address of m+1 bits, and the address corresponding to any column of memory cells of m+1 bits is decoded to obtain 2 m+1 first control signals after decoding, and
  • the 2m+1 first control signals are in one-to-one correspondence with the 2m+1 columns of memory cells, wherein the 2m+1 first control signals include a positive signal corresponding to any column of memory cells and other 2 m+1 -1 columns of storage cells correspond to 2 m+1 -1 inverted signals one by one; at the same time, the second control signal is obtained after the 2 m+1 first control signals are passed into the inverter, That is to say, 2 m+1 second control signals corresponding to the 2 m+1 first control signals one-to-one
  • the input end of the sense amplifier is connected to the 2 m+1 columns of memory cells in the array through the 2 m+1 first transmission gates; similarly, the input end of the voltage follower is also connected through the 2 m+1 first transmission gates It is connected to the 2 m+1 columns of memory cells in the array, and the output terminal of the voltage follower is also connected to the 2 m+1 columns of memory cells in the array through the 2 m+1 second transmission gates. It should be noted that the number of columns connected to the sense amplifier and the voltage follower can be set according to the power consumption and performance specifications of the circuit design, which is not specifically limited in this application.
  • the decoded first control signal and the corresponding second control signal Act on the non-inverting control terminal and the inverting control terminal of these transmission gates; where, after the order of the positive and negative signals of the first transmission gate connected to the control sense amplifier is given, by exchanging the positive and negative signals of the second transmission gate of the control voltage follower
  • the order of the inverse signals can realize the complementary selection of the columns in the cross-point memory array by the sense amplifier and the voltage follower.
  • the first control signal corresponding to the row of memory cells is a positive signal, and is applied to control the sense amplifier and The non-inverting control terminal of the first transmission gate connected to the column storage unit;
  • the first control signal (positive signal) corresponding to the column storage unit is input to the inverter to obtain the second control signal corresponding to the column storage unit, and the column storage unit
  • the corresponding second control signal is an inversion signal, and is applied to the inversion control terminal of the first transmission gate that controls the sense amplifier to be connected to the memory cell of the column; meanwhile, the corresponding second control signal (inversion signal) of the memory cell of the column Applied to the non-inverting control terminal of the second transmission gate of the control voltage follower connected to the column of memory cells, the first control signal (positive signal) corresponding to the column of memory cells is applied to the control voltage follower connected to the column of memory cells.
  • the inverting control terminal of the second transmission gate When the sense amplifier does not select a column of memory cells in the cross-point memory array, and the voltage follower selects the column of memory cells, the first control signal corresponding to the column of memory cells is an inverse signal, and is applied to control the sense amplifier and the column.
  • the second control signal is a positive signal, and is applied to the inverting control terminal of the first transmission gate that controls the sense amplifier to be connected to the row of memory cells; meanwhile, the corresponding second control signal (positive signal) of the row of memory cells is applied to The non-inverting control terminal of the second transmission gate that controls the voltage follower connected to the column memory unit, and the corresponding first control signal (inverted signal) of the column memory unit is applied to the second transmission gate that controls the voltage follower connected to the column memory unit.
  • the inverting control terminal of the gate is a positive signal, and is applied to the inverting control terminal of the first transmission gate that controls the sense amplifier to be connected to the row of memory cells; meanwhile, the corresponding second control signal (positive signal) of
  • the address of any row of memory cells is the address of m+1 bits, and the addresses of the m+1 bits are address [0], address [1], address [ 2], ..., address [m-1] and address [m], 2 m+1 first control signals are respectively control signal a[0], control signal a[1], control signal a[2 ],..., control signal a[2 m+1 -2] and control signal a[2 m+1 -1], 2 m+1 second control signals are control signal b[0] , control signal b[1], control signal b[2], ..., control signal b[2 m+1 -2] and control signal b[2 m+1 -1]; multiple first The transmission gates are T1[0], T1[1], T1[2], ..., T1[2 m+1 -2] and T1[2 m+1 -1], multiple second transmission gates Respectively T2[0], T2[1], T2[2], ..., T2[2[2]
  • the control signal a[0] is a positive signal
  • the control signal b[0] is an inverse signal
  • the control signal a[0] is applied to the control sense amplifier and in[ 0] to the non-inverting control terminal of the first transmission gate T1[0] connected to the column storage unit (for example, C port)
  • the control signal b[0] is applied to the inverting control terminal of the first transmission gate T1[0] (for example, C inversion port)
  • the control signal b[0] is applied to the non-inverting control terminal (such as C port) of the second transmission gate T2[0] that controls the voltage follower connected to the in[0] column memory cells
  • the control signal a[0] Applied to the inverting control terminal of the second transmission gate T1[0] (for example, C inverting port), at this time, the first transmission gate T1[0] is turned on, and the second transmission gate T2[0] is
  • control signal a[0] is an inverse signal
  • the control signal b[0] is a positive signal
  • the control signal a[0] is applied to the non-inverting control terminal (such as C port) of the first transmission gate T1[0]
  • the control signal b[0] is applied to the inverting control terminal of the first transmission gate T1[0] (such as the C negative port)
  • the control signal b[0] is applied to the non-inverting control terminal of the second transmission gate T2[0] (such as the C port )
  • the control signal a[0] is applied to the inverting control terminal of the second transmission gate T1[0] (for example, the inverse port of C)
  • the first transmission gate T1[0] is cut off
  • the second transmission gate T2[ 0] is turned on
  • the sense amplifier does not select the in[0] column memory cell
  • the voltage follower selects the in[0] column memory cell.
  • any first transmission gate or any second transmission gate if a positive signal is input at its non-inverting control terminal and an inverse signal is input at its inverting control terminal, its first terminal and the second transmission gate The signal transmission between the two terminals is turned on; if the negative signal is input at its non-inverting control terminal and the positive signal is input at its inverting control terminal, the signal transmission between the first terminal and the second terminal is cut off; the positive signal and the negative signal
  • the signals are collectively referred to as control signals.
  • the control signal is obtained by decoding the address of a column of memory cells corresponding to the bit line connected to it. When this column of memory cells needs to be selected, the decoded control signal corresponding to this column of memory cells is a positive signal.
  • the control signal corresponding to this row of memory cells is the inversion signal.
  • the positive and negative of the control signal can be converted to each other through the inverter: when the control signal is a positive signal, the control signal can be input to the inverter to get the reverse signal; on the contrary, when the control signal is the negative signal, the control After the signal is input to the inverter, a positive signal can be obtained. Therefore, the multi-column storage unit has multiple first control signals and multiple second control signals corresponding to the multiple first control signals, and the multi-column storage unit is related to the multiple first control signals and the multiple second control signals.
  • the control signals are in one-to-one correspondence; specifically, the multiple first control signals include a positive signal and multiple negative signals, and the multiple second control signals include a negative signal and multiple positive signals, because when it is necessary to select For this column of memory cells, decode the address of this column of memory cells to obtain the positive signal corresponding to this column of memory cells and the corresponding inverse signals of other column memory cells, and then input the positive signal corresponding to this column of memory cells into the inverter The inverse signal corresponding to the memory cells of this column can be obtained, and the positive signal corresponding to the memory cells of other columns can be obtained by inputting the inverse signal corresponding to the memory cells of other columns into the inverter.
  • the first transmission gate or the second transmission gate connected to any one bit line is to be turned on, the first transmission gate connected to any one bit line Or the non-inverting control terminal of the second transmission gate can input the corresponding positive signal, and the inverting control terminal can input the corresponding negative signal; if the first transmission gate or the second transmission gate connected to any bit line is to be cut off, the The non-inverting control terminal of the first transmission gate or the second transmission gate connected to any one of the bit lines may input a corresponding negative signal, and the inverting control terminal may input a corresponding positive signal.
  • control signals input by the non-inverting control terminal and the inverting control terminal of the first transmission gate connected to any bit line and the second transmission gate are opposite.
  • the first transmission gate When the non-inverting control terminal of the first transmission gate inputs a positive signal, the first transmission gate When the inverting control terminal of the gate inputs the negative signal, the non-inverting control terminal of the second transmission gate inputs the negative signal, and the inverting control terminal of the second transmission gate inputs the positive signal; when the non-inverting control terminal of the first transmission gate inputs the negative signal, the When the inverting control terminal of a transmission gate inputs a positive signal, the non-inverting control terminal of the second transmission gate inputs a positive signal, and the inverting control terminal of the second transmission gate inputs an inverse signal, so that the voltage follower and the sense amplifier can realize the Complementary selection of one bit line, that is, complementary selection of a column of memory cells on the one bit line by the voltage follower and the sense amplifier.
  • the read operation circuit further includes a decoder and an inverter; the decoder is configured to decode the address of a column of memory cells including the selected memory cell to obtain The first control signal; the inverter, configured to invert the first control signal to obtain the second control signal.
  • the address (address [0], address [1], address [2], ..., address [m-1] and The address [m]) is input to the decoder, and 2 m+1 first control signals are obtained after decoding, which are control signal a[0], control signal a[1], control signal a[2], ...
  • control signal a[2 m+1 -2] and control signal a[2 m+1 -1] then input the 2 m+1 first control signals to the inverter P[0 ], P[1], P[2], ..., P[2 m+1 -2] and P[2 m+1 -1], correspondingly obtain 2 m+1 second control signals, respectively
  • control signal b[0], control signal b[1], control signal b[2], ..., control signal b[2 m+1 -2] and control signal b[2 m+1 - 1] Wherein, when the first control signal is a positive signal, the corresponding second control signal is a negative signal, and when the first control signal is a negative signal, the corresponding second control signal is a positive signal.
  • control signal a[0] in the 2 m+1 first control signals is positive signal
  • control signal a[1], control signal a[2], ..., control signal a[2 m+1 -2] and control signal a[2 m+1 -1] are all inverse signal
  • the control signal b[0] in the 2 m+1 second control signals is an inverse signal
  • the control signal b[ 1], control signal b[2], ..., control signal b[2 m+1 -2] and control signal b[2 m+1 -1] are all positive signals.
  • the read operation circuit further includes a decoder and an inverter, and the decoder is used to decode the address of a column of storage units including the selected storage unit to obtain a plurality of first control signals; the inverter is used to The multiple first control signals are inverted to obtain corresponding multiple second control signals. Since the control signal includes positive and negative signals, the positive and negative of the control signal can be converted to each other through the inverter: when the control signal is a positive signal, after the control signal is input into the inverter, the negative signal can be obtained; otherwise, when the When the control signal is an inverse signal, a positive signal can be obtained after the control signal is input into the inverter.
  • a plurality of first control signals include a positive signal and a plurality of inverted signals
  • a plurality of second control signals are obtained after being inverted by an inverter
  • the second control signals include an inverted signal and a plurality of positive signals, thus, it can be obtained
  • the read operation circuit of the present application may not include a decoder and an inverter, and the first control signal and the second control signal may also be obtained through other peripheral circuits other than the read operation circuit.
  • the peripheral circuit includes a decoder and an inverter.
  • the decoder of the peripheral circuit decodes the address of any column of memory cells to obtain the first control signal corresponding to any column of memory cells.
  • the inverter of the peripheral circuit The first control signal corresponding to any column of memory cells is processed to obtain the second control signal corresponding to any column of memory cells.
  • the voltage follower includes any one of the following: an integrated operational amplifier voltage follower, a common-drain amplifier, and an inversion voltage follower.
  • the functions realized by the voltage follower in this application include at least: 1) replicating voltage: the voltage at the output terminal is equal to the voltage at the input terminal; 2) isolation: the input resistance is high and the output impedance is low. Therefore, the load at the output end of the voltage follower will not affect the voltage and current at its input end.
  • the voltage follower can be implemented by a common-drain amplifier or negative feedback of an integrated operational amplifier.
  • the voltage follower can be an integrated operational amplifier voltage follower, as shown in Figure 9; the integrated operational amplifier voltage follower performs negative feedback on the operational amplifier, and its negative feedback path impedance, input terminal impedance, and output terminal impedance Proper design can achieve a stable and accurate voltage follower.
  • the voltage follower can also be built according to the common-drain amplifier structure, as shown in Figure 10; Figure 11 shows the flip voltage follower circuit based on the common-drain amplifier.
  • the sense amplifier includes any one of the following: a voltage sense amplifier and a current sense amplifier.
  • the sense amplifier of the present application can adopt voltage amplifier (voltage SA).
  • the output voltage of the cell is compared to obtain the state of the memory cell to be read (the selected memory cell).
  • the sense amplifier of the present application can also adopt a current amplifier (current SA), as shown in Figure 13, the sense amplifier is a current sense amplifier, and the current sense amplifier samples the output current and The output current of the storage unit is referred to and compared to obtain the state of the storage unit to be read (the selected storage unit).
  • current SA current amplifier
  • the read operation circuit includes and is not limited to the following modules: a voltage follower, a sense amplifier and a selection module.
  • the voltage follower can be implemented by an amplifier with negative feedback, such as a unity-gain amplifier, or by a common-source amplifier and a common-collector circuit.
  • the sense amplifier can be a current-type amplifier that compares the read current with a reference current to obtain the state of the memory cell, or a voltage-type amplifier that compares the read voltage with the reference voltage to obtain the state of the memory cell.
  • the selection module can be a decoder that selects a certain row or column through an address.
  • the switch between the sense amplifier and the array to be read out may be a circuit with switching properties such as a transistor and a transmission gate.
  • the switch between the voltage follower and the array to be read out may be a circuit with switching properties such as a transistor and a transmission gate.
  • the input terminal of the voltage follower is connected to the input terminal of the signal to be read of the sense amplifier, and the position of the connection point is located near the switch between the row or column where the signal to be read is located and the sense amplifier, and is located at Close to the side of the sense amplifier, the output terminal of the voltage follower is connected to the memory array through a switch.
  • the cross-point memory array is read.
  • the present application uses time-sharing single readout, copying the voltage of the storage unit to be read (selected storage unit) to suppress other columns/rows, so that equipotentials are formed between different rows/columns and the problem of crosstalk of the read current is avoided.
  • the read operation of the pure cross-point memory array the application increases the readout window of the array without reducing the storage density of the cross-point memory array.
  • This application can be applied to all cross-point memory arrays composed of memory devices at both ends, such as non-volatile memory (RRAM), phase change memory (PCRAM), ferroelectric memory (FeRAM), magnetic memory (STT-MRAM) random access memory.
  • RRAM non-volatile memory
  • PCRAM phase change memory
  • FeRAM ferroelectric memory
  • STT-MRAM magnetic memory random access memory.
  • the cross-point structure is adopted in the design of the storage array, but the read operation window of the cross-point storage array will decrease with the increase of the size of the cross-point structure array, and the leakage of the read operation and the write operation will also be caused by the cross-point
  • the structure array grows in size. Therefore, in the practical application of the cross-point structure array, the designer needs to properly adjust the array size of the cross-point structure array according to the specifications of chip performance and power consumption.
  • the cross-point structure array is divided into four columns as an independent cross-point structure array for block.
  • Figure 14 is a cross-point structure array composed of two-terminal devices, and every 4 memory cells in the same row in the cross-point structure array share a transistor connected to the SL (source line, bit line), The gate of this shared transistor is controlled by the word line (WL).
  • WL word line
  • the transistor connected to SL corresponding to this row is turned on; for example, when the first row is selected, WL0 inputs a control signal, so that the transistor connected to SL0 is turned on (conducted).
  • the step of reading the cross-point structure array can be as follows: 1) according to the address input by the peripheral circuit, the decoder in the peripheral circuit drives the word line (WL) to turn on the transistor of a certain row, and the transistor of this row is given by the transistor that is turned on. 2) According to the address input by the peripheral circuit, the decoder and inverter in the read operation circuit output the corresponding control signal (positive signal or negative signal), so that the voltage follower and The sense amplifier selects the corresponding column, and opens or closes the switching circuit (such as a transistor or transmission gate, etc.) used to connect the voltage follower and the memory array, and is used to connect the sense amplifier and the memory array.
  • the switching circuit such as a transistor or transmission gate, etc.
  • the steps of this step Operation can be simultaneously or different from the operation of the previous step; 3) enable the sense amplifier, the sense amplifier establishes a path between the memory cell to be read (selected memory cell), and the voltage follower will store the memory cell to be read The voltage between the sense amplifier and the sense amplifier is copied to the corresponding columns of other cells not to be read; 4) the sense amplifier outputs the read result; 5) the sense amplifier is enabled and closed, and this row of storage is closed by changing the word line potential transistor on the cell, the read operation is complete.
  • the present application can select one of the multiple memory cells for reading, that is, one read operation circuit corresponds to multiple memory cells.
  • Figure 15 is also a cross-point array structure of two-terminal memory, by changing the number of bits of the address in the read operation circuit, that is, the value of m, the number of controllable columns of the sense amplifier can be increased.
  • a read operation circuit corresponds to n columns of memory cells in the cross-point memory array
  • m log 2 n-1; for example, when m is set to 2 in the read operation circuit, the read operation circuit
  • the read operation of 8 columns of memory cells can be controlled at the same time.
  • the present application can also be applied to a cross-point memory array composed of memory devices, such as a spin-orbit moment magnetic random access memory.
  • the spin-orbit moment magnetic random access memory implements writing "0" and writing "1" through the different directions of the metal wire current connected to the bottom of the memory cell, and obtains the stored state by reading the resistance.
  • the writing and non-writing of the memory cell can be controlled by controlling the voltage at the top of the memory cell while the bottom metal line is energized for operation.
  • a cross-point memory array constructed using spin-orbit moment magnetic random access memory is shown in Figure 16. The number of memory units that can be placed on the same metal line can be adjusted according to the performance specification of the memory chip.
  • the three-terminal memory array can also select one memory cell for reading among multiple memory cells, that is, one read operation circuit corresponds to multiple memory cells, as shown in FIG. 17 .
  • ctrl in FIG. 16 and FIG. 17 represents a bit line
  • ctrl0, ctrl1, ctrl2, ctrl3..., ctrln-3, ctrln-2, ctrln-1, and ctrln represent different bit lines.
  • the read operation circuit of the present application can also be used in three-dimensional stacked cross-point structure arrays, as shown in FIG. 18 and FIG. 19 .
  • connection relationship between the read operation circuit and the storage array in this application can be that one read operation circuit corresponds to one cross-point storage array, as shown in Figure 18 and Figure 19; it can also be multiple read operation circuits
  • the operation circuit corresponds to a cross-point memory array, as shown in Figure 14 and Figure 16, the read operation circuit [0], the read operation circuit [0], the read operation circuit [0], ..., the read operation circuit [k] corresponds to one cross-point array; or one read operation circuit corresponds to multiple cross-point arrays, as shown in FIG. 15 and FIG. 17 .
  • FIG. 20 is a schematic diagram of a memory provided by an embodiment of the present application.
  • the memory is provided with a plurality of storage units 2001 and the read operation circuit 2000 described above in conjunction with FIGS. 6 to 19 .
  • the embodiment of the present application also provides an electronic device, which may include a circuit board and a memory as shown in FIG. 20 .
  • the electronic device may include, but is not limited to, speakers, display screens, communication devices, and the like.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present application.

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Abstract

一种读操作电路，包括电压跟随器和读出放大器；电压跟随器和读出放大器分别与交叉点存储阵列耦合，交叉点存储阵列包含多列存储单元以及与多列存储单元一一对应的多条位线，多列存储单元中的每一列存储单元的每一个存储单元的其中一端与每一列存储单元对应的位线连接；电压跟随器，用于将与选中存储单元连接的目标位线上的电压复制至多条位线中除目标位线之外的其他位线上；读出放大器，用于对选中存储单元进行读操作。在对交叉点存储阵列中的选中存储单元进行读操作时，可以有效消除其他存储单元的影响。

Description

读操作电路、芯片及电子设备 技术领域
本申请涉及电子技术领域，尤其涉及一种读操作电路、芯片及电子设备。
背景技术
随着大数据时代的到来，全球数据存储量快速增长。这使得人们对高密度存储器的需求更加的急迫，也进一步促使设计者探索使用更加高密度的阵列结构来构建存储器。其中，交叉点存储阵列(crossbar，也称交叉点结构阵列或交叉点存储器阵列)结构简单，且具有很高的存储密度，交叉点存储阵列存储单比特(bit)面积为4F 2，是目前可以达到的最低的存储密度。交叉点存储阵列完美适配两端器件；并且直接在金属(metal)层中组成存储单元，无需晶体管的参与，如图1所示，这使得交叉点存储阵列在不需要3D封装技术的条件下，便可形成高密度的3D堆叠，极大的提高了存储密度。
可采用交叉点存储阵列的存储器件包括两端器件和三端器件，两端器件如阻变随机存储器(resistive random access memory，RRAM)、相变随机存储器(phase change random access memory，PCRAM)、铁电随机存储器(ferroelectric random access memory，FeRAM)、自旋转移矩磁性随机存储器(spin-transfer torque MRAM(magnetic random access memory，磁随机存储器)，STT-MRAM)等。对于两端器件，交叉点结构对其操作可以通过相应的字线(word line，WL)和位线(bit line，BL)施加写激励。三端器件如自旋轨道矩磁性随机存储器(spin-orbit torque MRAM，SOT-MRAM)是通过字线施加不同方向的电流实现自旋轨道矩翻转自由层磁矩，进而写入“0”态或“1”态；此外，它可以通过电压调制进行选择性自旋轨道矩写入，这样通过在位线上施加一个控制电压就可以实现特定位置的写入。
虽然交叉点存储阵列有很多的优点，但是其缺点也是非常严重的。由于交叉点存储阵列中所有的存储单元都通过金属层连接，若要去单独操作某个选中存储单元，会受到其他存储单元的影响，而且这种影响随交叉点存储阵列的规模的增大而增大。相比写操作来说，读操作受到这种影响的程度更加严重。对于交叉点存储阵列的读操作，若要在大量相互连接的存储单元中读出选中存储单元的状态(例如“1”态或者“0”态)，需要选中存储单元在其他存储单元处于任何状态组合下都具有较大的读窗口(即“1”态电流和“0”态电流的差)。人们在这方面尝试了一些方法，但是由于这些方法存着各种缺点，仍然无法有效消除这种影响，从而没有大规模应用于量产中。
发明内容
本申请提供了一种读操作电路、芯片及电子设备，在对交叉点存储阵列中的选中存储单元进行读操作时，可以有效消除其他存储单元的影响。
第一方面，本申请实施例提供了一种读操作电路，该读操作电路包括电压跟随器和读出放大器；所述电压跟随器和所述读出放大器分别与交叉点存储阵列耦合，所述交叉点存储阵列包含多列存储单元以及与所述多列存储单元一一对应的多条位线，所述多列存储单元中的每一列存储单元的每一个存储单元的其中一端与所述每一列存储单元对应的位线连 接；所述电压跟随器，用于将与选中存储单元连接的目标位线上的电压复制至所述多条位线中除所述目标位线之外的其他位线上；所述读出放大器，用于对所述选中存储单元进行读操作。
第一方面所描述的技术方案，在交叉点存储阵列中选定要进行读操作的选中存储单元的情况下，也即读出放大器与选中存储单元形成读操作的通路的情况下，电压跟随器将与选中存储单元连接的目标位线上的电压复制至交叉点存储阵列的多条位线中除目标位线之外的其他位线上；在电压跟随器将目标位线上的电压复制至其他位线上之后，读出放大器对选中存储单元进行读操作；如此，可以使得与选中存储单元连接的目标位线上的电压和其他位线上的电压相同，也即使得交叉点存储阵列中选中存储单元所在列的电压与其他列的电压相同，从而交叉点存储阵列中选中存储单元所在列与其他列之间不会产生漏电流，在此基础上，对交叉点存储阵列中的选中存储单元进行读操作，可以有效消除其他存储单元的影响。
结合第一方面，在第一种可能的实现方式中，所述读操作电路还包括多个第一开关，所述读出放大器的输入端通过所述多个第一开关与所述多条位线分别连接。所述交叉点存储阵列包含至少一行存储单元，所述至少一行存储单元包含所述选中存储单元；其中，在所述至少一行存储单元中选定包含所述选中存储单元的一行存储单元的情况下，若与所述目标位线连接的第一开关导通，且与所述其他位线连接的第一开关截止，则在所述交叉点存储阵列中选定所述选中存储单元。
在本实现方式中，读出放大器的输入端是通过多个第一开关与多条位线分别连接的，如此，可以通过控制多个第一开关通断来实现对选中存储单元的选定；具体地，选中存储单元与目标位线连接，在交叉点存储阵列中选定包含选中存储单元的一行存储单元的情况下，控制与目标位线连接的第一开关导通，且控制与其他位线连接的第一开关截止，即可实现读出放大器与选中存储单元所在列形成通路而不与其他列形成通路，达到选定选中存储单元的目的。
结合第一方面第一种可能的实现方式，在第二种可能的实现方式中，所述多个第一开关为多个第一晶体管，所述多个第一晶体管中的任一第一晶体管包括第一端、第二端和控制端，所述控制端用于接收控制信号；所述读出放大器的输入端与所述多个第一晶体管的第一端分别连接，所述多个第一晶体管的第二端与所述多条位线对应连接。其中，所述任一第一晶体管的控制端用于控制所述任一第一晶体管的第一端与第二端之间的信号传输的通断；在所述至少一行存储单元中选定包含所述选中存储单元的一行存储单元的情况下，若与所述目标位线连接的第一晶体管的第一端与第二端之间的信号传输导通，且与所述其他位线连接的第一晶体管的第一端与第二端之间的信号传输截止，则在所述交叉点存储阵列中选定所述选中存储单元。
在本实现方式中，读出放大器的输入端是通过多个第一晶体管与多条位线分别连接的，如此，可以通过控制多个第一晶体管通断来实现对选中存储单元的选定；具体地，选中存储单元与目标位线连接，在交叉点存储阵列中选定包含选中存储单元的一行存储单元的情况下，控制与目标位线连接的第一晶体管导通，且控制与其他位线连接的第一晶体管截止，即可实现读出放大器与选中存储单元所在列形成通路而不与其他列形成通路，达到选定选 中存储单元的目的。
结合第一方面第一种可能的实现方式，在第三种可能的实现方式中，所述多个第一开关为多个第一传输门，所述多个第一传输门中的任一第一传输门包括第一端、第二端、同相控制端和反相控制端，所述同相控制端和所述反相控制端用于接收控制信号；所述读出放大器的输入端与所述多个第一传输门的第一端分别连接，所述多个第一传输门的第二端与所述多条位线对应连接。其中，所述任一第一传输门的同相控制端和反相控制端用于控制所述任一第一传输门的第一端与第二端之间的信号传输的通断；在所述至少一行存储单元中选定包含所述选中存储单元的一行存储单元的情况下，若与所述目标位线连接的第一传输门的第一端与第二端之间的信号传输导通，且与所述其他位线连接的第一传输门的第一端与第二端之间的信号传输截止，则在所述交叉点存储阵列中选定所述选中存储单元。
在本实现方式中，读出放大器的输入端是通过多个第一传输门与多条位线分别连接的，如此，可以通过控制多个第一传输门通断来实现对选中存储单元的选定；具体地，选中存储单元与目标位线连接，在交叉点存储阵列中选定包含选中存储单元的一行存储单元的情况下，控制与目标位线连接的第一传输门导通，且控制与其他位线连接的第一传输门截止，即可实现读出放大器与选中存储单元所在列形成通路而不与其他列形成通路，达到选定选中存储单元的目的。
结合第一方面第一至第三种可能的实现方式中的任一种可能的实现方式，在第四种可能的实现方式中，所述读操作电路还包括多个第二开关，所述电压跟随器的输入端通过所述多个第一开关与所述多条位线分别连接，所述电压跟随器的输出端通过所述多个第二开关与所述多条位线分别连接。在所述交叉点存储阵列中选定选中存储单元的情况下，若与所述目标位线连接的第二开关截止，且与所述其他位线连接的第二开关导通，则所述电压跟随器将所述目标位线上的电压复制至所述其他位线上。
在本实现方式中，电压跟随器的输入端是通过上述多个第一开关与多条位线分别连接的，电压跟随器的输出端是通过多个第二开关与多条位线分别连接的；如此，在交叉点存储阵列中选定选中存储单元的情况下，可以通过控制多个第二开关的通断来实现将选中存储单元所在列的电压复制至其他列上；具体地，选中存储单元与目标位线连接，控制与目标位线连接的第二开关截止，且控制与其他位线连接的第二开关导通，即可实现电压跟随器的输入端与选中存储单元所在列形成通路而不与其他列形成通路，以及电压跟随器的输出端与其他列形成通路而不与选中存储单元所在列形成通路，达到将选中存储单元所在列的电压复制至其他列上的目的。
结合第一方面第四种可能的实现方式，在第五种可能的实现方式中，所述多个第二开关为多个第二晶体管，所述多个第二晶体管中的任一第二晶体管包括第一端、第二端和控制端，所述控制端用于接收控制信号；所述电压跟随器的输出端与所述多个第二晶体管的第一端分别连接，所述多个第二晶体管的第二端与所述多条位线对应连接。其中，所述任一第二晶体管的控制端用于控制所述任一第二晶体管的第一端与第二端之间的信号传输的通断；在所述交叉点存储阵列中选定选中存储单元的情况下，若与所述目标位线连接的第二晶体管的第一端与第二端之间的信号传输截止，且与所述其他位线连接的第二晶体管的第一端与第二端之间的信号传输导通，则所述电压跟随器将所述目标位线上的电压复制至 所述其他位线上。
在本实现方式中，电压跟随器的输入端是通过上述多个第一开关与多条位线分别连接的，电压跟随器的输出端是通过多个第二晶体管与多条位线分别连接的；如此，在交叉点存储阵列中选定选中存储单元的情况下，可以通过控制多个第二晶体管的通断来实现将选中存储单元所在列的电压复制至其他列上；具体地，选中存储单元与目标位线连接，控制与目标位线连接的第二晶体管截止，且控制与其他位线连接的第二晶体管导通，即可实现电压跟随器的输入端与选中存储单元所在列形成通路而不与其他列形成通路，以及电压跟随器的输出端与其他列形成通路而不与选中存储单元所在列形成通路，达到将选中存储单元所在列的电压复制至其他列上的目的。
结合第一方面第五种可能的实现方式，在第六种可能的实现方式中，所述任一第一晶体管的控制端输入的第一控制信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到；所述任一第二晶体管的控制端输入的第二控制信号通过对所述第一控制信号进行取反得到；所述任一第一晶体管的第二端和所述任一第二晶体管的第二端与所述多条位线中的同一条位线连接。其中，若在所述任一第一晶体管或所述任一第二晶体管的控制端输入正信号，则所述任一第一晶体管或所述任一第二晶体管的第一端与第二端之间的信号传输导通；若在所述任一第一晶体管或所述任一第二晶体管的控制端输入反信号，则所述任一第一晶体管或所述任一第二晶体管的第一端与第二端之间的信号传输截止；其中，所述正信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到，所述反信号通过将所述正信号输入反相器得到；或所述反信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到，所述正信号通过将所述反信号输入反相器得到。
在本实现方式中，对于任一第一晶体管或任一第二晶体管而言，若在其控制端输入正信号，则其第一端与第二端之间的信号传输导通；若在其控制端输入反信号，则其第一端与第二端之间的信号传输截止；正信号和反信号统称为控制信号。而控制信号是通过对与其连接的位线对应的一列存储单元的地址进行解码得到，当需要选定这一列存储单元时，解码得到的这一列存储单元对应的控制信号就是正信号，反之解码得到的这一列存储单元对应的控制信号就是反信号。控制信号的正反可以通过反相器进行相互转换：当控制信号为正信号时，将该控制信号输入反相器后，可以得到反信号；反之，当控制信号为反信号时，将该控制信号输入反相器后，可以得到正信号。故多列存储单元就有多个第一控制信号，以及该多个第一控制信号取反后对应得到的多个第二控制信号，且这多列存储单元与这多个第一控制信号以及多个第二控制信号是一一对应的；具体地，这多个第一控制信号包括一个正信号和多个反信号，这多个第二控制信号包括一个反信号和多个正信号，因为当需要选定这一列存储单元时，对这一列存储单元的地址进行解码，从而得到这一列存储单元对应的正信号以及其他列存储单元对应的反信号，再将这一列存储单元对应的正信号输入反相器即可得到这一列存储单元对应的反信号，以及将这其他列存储单元对应的反信号输入反相器即可得到其他列存储单元对应的正信号。由于多条位线是与多列存储单元一一对应的，若要使与任一条位线连接的第一晶体管或第二晶体管导通，在该任一条位线连接的第一晶体管或第二晶体管的控制端输入对应的正信号即可；若要使与任一条位线连接的第一晶体管或第二晶体管截止，在该任一条位线连接的第一晶体管或第二晶体管的控制 端输入对应的反信号即可。此外，任一条位线连接的第一晶体管和第二晶体管的控制端输入的控制信号是相反的，当第一晶体管的控制端输入正信号时，第二晶体管的控制端输入反信号；当第一晶体管的控制端输入反信号时，第二晶体管的控制端输入正信号，从而可以实现电压跟随器和读出放大器对该条位线的互补选择，也即实现电压跟随器和读出放大器对该条位线的一列存储单元的互补选择。
结合第一方面第四种可能的实现方式，在第七种可能的实现方式中，所述多个第二开关为多个第二传输门，所述多个第二传输门中的任一第二传输门包括第一端、第二端、同相控制端和反相控制端，所述同相控制端和所述反相控制端用于接收控制信号；所述电压跟随器的输出端与所述多个第二传输门的第一端分别连接，所述多个第二传输门的第二端与所述多条位线对应连接。其中，所述任一第二传输门的同相控制端和反相控制端用于控制所述任一第二传输门的第一端与第二端之间的信号传输的通断；在所述交叉点存储阵列中选定选中存储单元的情况下，若与所述目标位线连接的第二传输门的第一端与第二端之间的信号传输截止，且与所述其他位线连接的第二传输门的第一端与第二端之间的信号传输导通，则所述电压跟随器将所述目标位线上的电压复制至所述其他位线上。
在本实现方式中，电压跟随器的输入端是通过上述多个第一开关与多条位线分别连接的，电压跟随器的输出端是通过多个第二传输门与多条位线分别连接的；如此，在交叉点存储阵列中选定选中存储单元的情况下，可以通过控制多个第二传输门的通断来实现将选中存储单元所在列的电压复制至其他列上；具体地，选中存储单元与目标位线连接，控制与目标位线连接的第二传输门截止，且控制与其他位线连接的第二传输门导通，即可实现电压跟随器的输入端与选中存储单元所在列形成通路而不与其他列形成通路，以及电压跟随器的输出端与其他列形成通路而不与选中存储单元所在列形成通路，达到将选中存储单元所在列的电压复制至其他列上的目的。
结合第一方面第七种可能的实现方式，在第八种可能的实现方式中，所述任一第一传输门的同相控制端和所述任一第二传输门的反相控制端输入的第一控制信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到；所述任一第一传输门的反相控制端和所述任一第二传输门的同相控制端输入的第二控制信号通过对所述第一控制信号进行取反得到；所述任一第一传输门的第二端和所述任一第二传输门的第二端与所述多条位线中的同一条位线连接。其中，若在所述任一第一传输门或所述任一第二传输门的同相控制端输入正信号，且在所述任一第一传输门或所述任一第二传输门的反相控制端输入反信号，则所述任一第一传输门或所述任一第二传输门的第一端与第二端之间的信号传输导通；若在所述任一第一传输门或所述任一第二传输门的同相控制端输入所述反信号，且在所述任一第一传输门或所述任一第二传输门的反相控制端输入所述正信号，则所述任一第一传输门或所述任一第二传输门的第一端与第二端之间的信号传输截止；其中，所述正信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到，所述反信号通过将所述正信号输入反相器得到；或所述反信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到，所述正信号通过将所述反信号输入反相器得到。
在本实现方式中，对于任一第一传输门或任一第二传输门而言，若在其同相控制端输入正信号且在其反相控制端输入反信号，则其第一端与第二端之间的信号传输导通；若在 其同相控制端输入反信号且在其反相控制端输入正信号，则其第一端与第二端之间的信号传输截止；正信号和反信号统称为控制信号。而控制信号是通过对与其连接的位线对应的一列存储单元的地址进行解码得到，当需要选定这一列存储单元时，解码得到的这一列存储单元对应的控制信号就是正信号，反之解码得到的这一列存储单元对应的控制信号就是反信号。控制信号的正反可以通过反相器进行相互转换：当控制信号为正信号时，将该控制信号输入反相器后，可以得到反信号；反之，当控制信号为反信号时，将该控制信号输入反相器后，可以得到正信号。故多列存储单元就有多个第一控制信号，以及该多个第一控制信号取反后对应得到的多个第二控制信号，且这多列存储单元与这多个第一控制信号以及多个第二控制信号是一一对应的；具体地，这多个第一控制信号包括一个正信号和多个反信号，这多个第二控制信号包括一个反信号和多个正信号，因为当需要选定这一列存储单元时，对这一列存储单元的地址进行解码，从而得到这一列存储单元对应的正信号以及其他列存储单元对应的反信号，再将这一列存储单元对应的正信号输入反相器即可得到这一列存储单元对应的反信号，以及将这其他列存储单元对应的反信号输入反相器即可得到其他列存储单元对应的正信号。由于多条位线是与多列存储单元一一对应的，若要使与任一条位线连接的第一传输门或第二传输门导通，在该任一条位线连接的第一传输门或第二传输门的同相控制端输入对应的正信号、反相控制端输入对应的反信号即可；若要使与任一条位线连接的第一传输门或第二传输门截止，在该任一条位线连接的第一传输门或第二传输门的同相控制端输入对应的反信号、反相控制端输入对应的正信号即可。此外，任一条位线连接的第一传输门和第二传输门的同相控制端以及反相控制端输入的控制信号是相反的，当第一传输门的同相控制端输入正信号、第一传输门的反相控制端输入反信号时，第二传输门的同相控制端输入反信号、第二传输门的反相控制端输入正信号；当第一传输门的同相控制端输入反信号、第一传输门的反相控制端输入正信号时，第二传输门的同相控制端输入正信号、第二传输门的反相控制端输入反信号，从而可以实现电压跟随器和读出放大器对该条位线的互补选择，也即实现电压跟随器和读出放大器对该条位线的一列存储单元的互补选择。
结合第一方面第六或第八种可能的实现方式，在第九种可能的实现方式中，所述读操作电路还包括译码器和反相器；所述译码器，用于对包含所述选中存储单元的一列存储单元的地址进行解码，以得到所述第一控制信号；所述反相器，用于对所述第一控制信号进行取反，以得到所述第二控制信号。
在本实现方式中，读操作电路还包括译码器和反相器，译码器用于对包含选中存储单元的一列存储单元的地址进行解码，以得到多个第一控制信号；反相器用于对多个第一控制信号进行取反，以得到对应的多个第二控制信号。由于控制信号包括正信号和反信号，控制信号的正反可以通过反相器进行相互转换：当控制信号为正信号时，将该控制信号输入反相器后，可以得到反信号；反之，当控制信号为反信号时，将该控制信号输入反相器后，可以得到正信号。而多个第一控制信号包括一个正信号和多个反信号，通过反相器取反后得到多个第二控制信号，第二控制信号包括一个反信号和多个正信号，如此，可以得到用于控制第一晶体管、第二晶体管、第一传输门或第二传输门通断的正信号以及反信号。
结合第一方面或第一方面上述任一种可能的实现方式，在第十种可能的实现方式中， 所述电压跟随器包括以下任意一项：集成运放电压跟随器、共漏放大器、翻转电压跟随器。
结合第一方面或第一方面上述任一种可能的实现方式，在第十一种可能的实现方式中，所述读出放大器包括以下任意一项：电压灵敏放大器、电流灵敏放大器。
第二方面，本申请实施例提供了一种读操作电路，包括电压跟随器、读出放大器、第一开关阵列和第二开关阵列；所述读出放大器的输入端通过所述第一开关阵列与交叉点存储阵列中的多条位线分别连接；所述电压跟随器的输入端通过所述第一开关阵列与所述多条位线分别连接，所述电压跟随器的输出端通过所述第二开关阵列与所述多条位线分别连接；所述交叉点存储阵列还包含与所述多条位线一一对应的多列存储单元，所述多列存储单元中的每一列存储单元的每一个存储单元的其中一端与所述每一列存储单元对应的位线连接。
第二方面所描述的技术方案，读出放大器的输入端通过第一开关阵列与交叉点存储阵列中的多条位线分别连接，通过控制第一开关阵列可实现读出放大器的输入端选择与选中存储单元连接的目标位线形成读操作的通路，而不与其他位线形成读操作的通路，从而可以在交叉点存储阵列中选定要进行读操作的选中存储单元。同时，由于电压跟随器的输入端通过第一开关阵列也与多条位线分别连接，当读出放大器的输入端与目标位线形成读操作的通路，而不与其他位线形成读操作的通路时，电压跟随器的输入端也与目标位线形成通路，而不与其他位线形成通路。此外，电压跟随器的输出端通过第二开关阵列与这多条位线分别连接，通过控制第二开关阵列可实现电压跟随器的输出端与目标位线不形成通路，而与其他位线形成通路，从而电压跟随器可以将与选中存储单元连接的目标位线上的电压复制至交叉点存储阵列的多条位线中除目标位线之外的其他位线上；在电压跟随器将目标位线上的电压复制至其他位线上之后，读出放大器对选中存储单元进行读操作；如此，可以使得与选中存储单元连接的目标位线上的电压和其他位线上的电压相同，也即使得交叉点存储阵列中选中存储单元所在列的电压与其他列的电压相同，从而交叉点存储阵列中选中存储单元所在列与其他列之间不会产生漏电流，在此基础上，对交叉点存储阵列中的选中存储单元进行读操作，可以有效消除其他存储单元的影响。
结合第二方面，在第一种可能的实现方式中，所述第一开关阵列包括多个第一晶体管，所述多个第一晶体管中的任一第一晶体管包括第一端、第二端和控制端，所述控制端用于接收控制信号；所述读出放大器的输入端与所述多个第一晶体管的第一端分别连接，所述多个第一晶体管的第二端与所述多条位线对应连接。
结合第二方面，在第二种可能的实现方式中，所述第一开关阵列包括多个第一传输门，所述多个第一传输门中的任一第一传输门包括第一端、第二端、同相控制端和反相控制端，所述同相控制端和所述反相控制端用于接收控制信号；所述读出放大器的输入端与所述多个第一传输门的第一端分别连接，所述多个第一传输门的第二端与所述多条位线对应连接。
结合第二方面或第二方面第一种或第二种可能的实现方式，在第三种可能的实现方式中，所述第二开关阵列包括多个第二晶体管，所述多个第二晶体管中的任一第二晶体管包括第一端、第二端和控制端，所述控制端用于接收控制信号；所述电压跟随器的输出端与所述多个第二晶体管的第一端分别连接，所述多个第二晶体管的第二端与所述多条位线对 应连接。
结合第二方面第三种可能的实现方式，在第四种可能的实现方式中，所述任一第一晶体管的控制端输入的第一控制信号通过对包含选中存储单元的一列存储单元的地址进行解码得到；所述任一第二晶体管的控制端输入的第二控制信号通过对所述第一控制信号进行取反得到；所述任一第一晶体管的第二端和所述任一第二晶体管的第二端与所述多条位线中的同一条位线连接。
结合第二方面或第二方面第一种或第二种可能的实现方式，在第五种可能的实现方式中，所述第二开关阵列包括多个第二传输门，所述多个第二传输门中的任一第二传输门包括第一端、第二端、同相控制端和反相控制端，所述同相控制端和所述反相控制端用于接收控制信号；所述电压跟随器的输出端与所述多个第二传输门的第一端分别连接，所述多个第二传输门的第二端与所述多条位线对应连接。
结合第二方面第五种可能的实现方式，在第六种可能的实现方式中，所述任一第一传输门的同相控制端和所述任一第二传输门的反相控制端输入的第一控制信号通过对包含选中存储单元的一列存储单元的地址进行解码得到；所述任一第一传输门的反相控制端和所述任一第二传输门的同相控制端输入的第二控制信号通过对所述第一控制信号进行取反得到；所述任一第一传输门的第二端和所述任一第二传输门的第二端与所述多条位线中的同一条位线连接。
结合第二方面第四种或第六种可能的实现方式，在第七种可能的实现方式中，所述读操作电路还包括译码器和反相器；所述译码器，用于对包含所述选中存储单元的一列存储单元的地址进行解码，以得到所述第一控制信号；所述反相器，用于对所述第一控制信号进行取反，以得到所述第二控制信号。
结合第二方面或第二方面上述任一种可能的实现方式，在第八种可能的实现方式中，所述电压跟随器包括以下任意一项：集成运放电压跟随器、共漏放大器、翻转电压跟随器。
结合第二方面或第二方面上述任一种可能的实现方式，在第九种可能的实现方式中，所述读出放大器包括以下任意一项：电压灵敏放大器、电流灵敏放大器。
需要说明的是，本申请第二方面的有益效果可以参见本申请第一方面对应的相关描述，此处不再重复描述。
第三方面，本申请实施例提供了一种存储器，该存储器上设置有多个存储单元以及第一方面或第一方面中的任一可能实现方式中的读操作电路；或，该存储器上设置有多个存储单元以及第二方面或第二方面中的任一可能实现方式中的读操作电路。
第四方面，本申请实施例提供了一种电子设备，该电子设备包括电路板和如第三方面所描述的存储器。
附图说明
图1是交叉点存储阵列的结构示意图；
图2是现有技术的每列同时读出电路设计示意图；
图3是低密度交叉点结构阵列设计示意图；
图4是交叉点存储阵列同时读出的示意图；
图5是本申请实施例提供的交叉点存储阵列读出操作-特定电压施加的示意图；
图6是本申请实施例提供的一种读操作电路的结构示意图；
图7是本申请实施例提供的另一种读操作电路的结构示意图；
图8是本申请实施例提供的又一种读操作电路的结构示意图；
图9是本申请实施例提供的一种集成运放电压跟随器的结构示意图；
图10是本申请实施例提供的一种共漏放大器的结构示意图；
图11是本申请实施例提供的一种翻转电压跟随器的结构示意图；
图12是本申请实施例提供的一种电压灵敏放大器的结构示意图；
图13是本申请实施例提供的一种电流灵敏放大器的结构示意图；
图14是本申请实施例提供的一种读操作电路应用于两端存储器件构成的交叉点存储阵列的示意图；
图15是本申请实施例提供的一种读操作电路对应多个两端存储器件构成的交叉点存储阵列的应用示意图；
图16是本申请实施例提供的一种读操作电路应用于三端存储器件构成的交叉点存储阵列的示意图；
图17是本申请实施例提供的一种读操作电路对应多个三端存储器件构成的交叉点存储阵列的应用示意图；
图18是本申请实施例提供的一种读操作电路应用于多层堆叠的交叉点存储阵列的示意图；
图19是本申请实施例提供的另一种读操作电路应用于多层堆叠的交叉点存储阵列的示意图；
图20是本申请实施例提供的一种存储器的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
首先，进一步分析并提出本申请具体要解决的技术问题。在交叉点存储阵列技术领域中，与本申请相关的读操作技术，包括如下三种技术：
技术一：交叉点存储阵列的每列同时读出。
请参阅图2，图2是同时在所有列上读出某一行所有存储单元的电路设计示意图，图2中的检测放大器(sense Amp unit)中包含了和交叉点存储阵列的列数目相同数量的放大器(sense amplifier，SA)。在进行读操作时，通过选择字线(GWL)选择交叉点存储阵列的一行；然后由sense Amp unit同时在交叉点存储阵列的所有列上施加一个电压，最后在位线(SL)上施加一个合适的电压，形成一个读电流的通路；通过sense Amp unit读取电流大 小，得到待读取的选中存储单元的状态。
技术一的缺陷：这种存储器的访问方法在同时读取多个存储单元时，由于不同列的读电流不同，会导致每列上的电压不同，这样每列之间会产生漏电流，从而导致不同列的读电流发生串扰，读窗口减小以至于无法读出。
技术二：设计算法克服读漏电。
有研究团队试图用一种简单但冗长、繁琐的算法来克服读漏电问题。该方案对存储阵列的读取步骤为：1)读取通过选中存储单元的电流；2)将选中存储单元写成“1”态，然后读取选中存储单元“1”态的电流；3)将选中存储单元写成“0”态，然后读取选中存储单元“0”态的电流；4)将第二次读取到的电流与第一次读取到的电流进行比较，判断初始读取电流属于“1”态还是“0”态；5)将选中存储单元恢复到原始状态。
技术二的缺陷：这种存储器访问方法需要很长的读操作时间和较大面积的外围电路(包括三个采样保持电路、电压比较器、分压器和控制电路)。同时，当阵列规模增大时，由于漏电电流对读电流贡献将占主导地位，选中存储单元的电阻值将可以忽略不计，选中存储单元的读窗口减小，这种技术无法读出。
技术三：设计低密度交叉点存储阵列。
请参阅图3，图3为低密度交叉点结构阵列设计示意图，这种无漏电通路的交叉点存储阵列设计方案是将行的金属线保留，列的金属线末端连接互补金属氧化物半导体(complementary metal oxide semiconductor，CMOS)多路复用器。与原来的经典交叉点存储阵列实现相比，这种方法存储密度低，但有效抑制了漏电。
技术三的缺陷：这种访问方法大大降低了交叉点存储阵列的存储密度。
综上所述，本申请具体要解决的技术问题包括如下方面：在保证交叉点存储阵列的具备高存储密度的前提下，在选中存储单元的读操作过程中，消除其他存储单元对选中存储单元的读操作的影响，增大交叉点存储阵列的读出窗口。
其次，以经典的交叉点存储阵列为例，介绍本申请提供的技术方案。由于经典的交叉点存储阵列，其列与列之间或者行与行之间是通过存储单元相互连接的，因此在读过程中，不同列之间电流/电压会相互影响。
现有技术提出同时读出同一行所有列的存储单元的方案在实际电路设计时会遇到串扰的问题，这种串扰最终会导致同时读出的所有列上的电流/电压信号趋同，即被拉平。一般情况下，同一行所有存储单元中，每个存储单元的状态不可能都相同，而是随机取值为“0”态或者“1”态；而且，由于工艺波动，使得每个存储单元的电阻值都不相同。当形成了从读操作模块(读操作电路)到选中存储单元的通路时，在这个电流通路上的电压分布结果可以看作是读操作模块和选中存储单元之间分压的结果。若假设交叉点存储阵列中每一列都是独立的，列之间不存在电压或者电流的串扰问题。由于同一行上的存储单元的电阻不同，那么每个电流通路上的分压结果也不相同。
请参阅图4，可以假设每列金属线上的电压分别为V0、V1、V2、…、Vn-3、Vn-2和Vn-1。以图4中的第一列和第二列举例，假设第一列读的是低阻态，第二列读的是高阻态，则在不存在列与列之间的串扰的情况下，V1大于V0。然而，当存在每一列之间的行连接 时，在第一列和第二列之间的每行上都会存在一个从第二列流向第一列的电流。并且，当交叉点存储阵列的规模较大时，第一列和第二列之间的电阻由于每行的存储单元的大量并联而显著减小，这导致V0和V1的差别最后被拉平。因此，这种不存在列串扰的假设是不成立的。同理，图4中的每列之间的电流也会由于列与列之间的串扰而被拉平。因此，这种同时读出的方法存在问题。
基于上述，由于交叉点存储阵列无法有效读出问题的本质原因是不同行/列的电压/电流会通过存储单元影响到其他行/列。本申请通过电压跟随器(voltage follower)将交叉点存储阵列中选中存储单元列上的电压复制到其他列上，这样避免了其他列的漏电流对通过选中存储单元进入读操作模块的电流的影响，增大了读操作的窗口。
需要说明的是，本申请是通过电压相等来压制漏电，本申请需要外围电路对交叉点存储阵列的行/列提供特定的电压使得行与行之间或者列与列之间形成等电位状态，来实现漏电的压制。实际情况下读操作时产生的电流/电压是由待读取的选中存储单元决定的，故在读操作之前无法预知用多大的电压压制其他行/列形成等电位。因此本申请提出了用电压复制电路(电压跟随电路)复制选中存储单元对应的行/列上的电压，并将该电压施加在同一交叉点存储阵列中的其他非选中存储单元所在的行/列上。
请参阅图5，图5是本申请实施例提供的交叉点存储阵列读出操作-特定电压施加的示意图；在一个N*N的交叉点存储阵列中，若需要读取第三行第一列的存储单元，也即第三行第一列的存储单元为待读取的选中存储单元。因此，将第一列金属线接上读出放大器。读出放大器可以将输入信号与参考信号相比较，其中，参考信号也即图5中来自参考存储单元(ref cell)的信号，如果输入信号大于参考信号则输出“1”或者“0”，本申请不妨假设若输入信号大于参考信号则输出“1”；若输入信号小于参考信号则输出“0”；从而实现了第三行第一列的存储单元的读操作。在信号比较的过程中，电流是从比较器(也即读出放大器)流向存储单元、最后到地的。因此，对应的阵列中的电压的设置是：将第三行接上一个电压V1；将其他行断开，也即即悬浮(floating)，从而选择定了第三行。这样就形成了读操作的通路；同时，为了复制电压压制漏电，在选中存储单元所在列(也即第一列)接上一个电压跟随器将电压信号复制到其他非选中存储单元所在列(也即除第一列之外的其他列)上。这样当第一列金属线上的电压为V0时，其他非选中存储单元所在列上电压也为V0。因此，通过选中存储单元进入比较器的电流不会受到其他列漏电流的影响，增大了读出的窗口。
下面结合附图对本申请实施例提供的读操作电路的具体结构进行详细介绍。
请参阅图6，图6是本申请实施例提供的一种读操作电路的结构示意图；该读操作电路包括电压跟随器(voltage follower)和读出放大器(SA)；所述电压跟随器和所述读出放大器分别与交叉点存储阵列耦合，所述交叉点存储阵列包含多列存储单元以及与所述多列存储单元一一对应的多条位线，所述多列存储单元中的每一列存储单元的每一个存储单元的其中一端与所述每一列存储单元对应的位线连接；所述电压跟随器，用于将与选中存储单元连接的目标位线上的电压复制至所述多条位线中除所述目标位线之外的其他位线上；所述读出放大器，用于对所述选中存储单元进行读操作。
需要指出的是，本申请中所描述的“耦合”指的是直接或间接连接。例如，A与B连接，既可以是A与B直接连接，也可以是A与B之间通过一个或多个其它电学元器件间接连接，例如可以是A与C直接连接，C与B直接连接，从而使得A与B之间通过C实现了连接。
本申请提供的技术方案可应用于多种存储器的交叉点存储阵列，该交叉点存储阵列可以是整个阵列都是一个独立的交叉点结构，也可以由晶体管分成多个独立的交叉点结构阵列。该交叉点存储阵列的存储单元可以是两端存储单元，如阻变存储器(RRAM)、相变存储器(PCRAM)、铁电存储器(FeRAM)、磁存储器(STT-MRAM)等非挥发性随机存储器。该交叉点存储阵列的存储单元也可以是三端存储器，如自旋轨道力矩磁性随机存储器(SOT-MRAM等)。在该交叉点存储阵列的单个存储单元中，可以单独只包含存储器件，也可以同时包含存储器件和二极管、阈值选通器等选择性器件。该交叉点存储阵列的可以是单层的，也可以是多层的。
需要说明的是，本申请的读操作电路和交叉点存储阵列可以集成在一个裸片die中，也可以分别集成在各自的裸片die中，并封装在一个芯片封装结构中；或者是作为独立的芯片，设置于印刷电路板PCB上。
其中，前述多列存储单元可以为交叉点存储阵列中的全部列存储单元，也可以为交叉点存储阵列中的部分列存储单元；前述多条位线可以为交叉点存储阵列中的全部位线，也可以为交叉点存储阵列中的部分位线。选中存储单元为多列存储单元中的其中一个存储单元，选中存储单元为被选中进行读操作的存储单元。
其中，在交叉点存储阵列中选定要进行读操作的选中存储单元，也即读出放大器与选中存储单元形成读操作的通路；此外，由于交叉点存储阵列中的每列存储单元中的每个存储单元的其中一端都会与同一条位线连接，因此电压跟随器将目标位线上的电压复制至其他位线上，也即电压跟随器将交叉点存储阵列中选中存储单元所在列的电压复制到其他列上。
其中，读出放大器对选中存储单元进行读操作的过程为：在读出放大器于选中存储单元形成读操作的通路之后，读出放大器与选中存储单元之间存在从读出放大器流向选中存储单元的电流，故读出放大器的输入端有输入信号；而电压跟随器将选中存储单元所在列的电压复制到其他列上之后，该输入信号不会受到交叉点存储阵列中其他列的串扰，读出放大器将该输入信号与参考信号进行比较，从而确定出选中存储单元的状态。
其中，该电压跟随器可以从其输入端复制输入端的电压，并在其输出端得到和其输入端相等的电压；该电压跟随器具有较高的输入电阻和较低输出电阻。
本申请所描述的技术方案，在交叉点存储阵列中选定要进行读操作的选中存储单元的情况下，也即读出放大器与选中存储单元形成读操作的通路的情况下，电压跟随器将与选中存储单元连接的目标位线上的电压复制至交叉点存储阵列的多条位线中除目标位线之外的其他位线上；在电压跟随器将目标位线上的电压复制至其他位线上之后，读出放大器对选中存储单元进行读操作；如此，可以使得与选中存储单元连接的目标位线上的电压和其他位线上的电压相同，也即使得交叉点存储阵列中选中存储单元所在列的电压与其他列的电压相同，从而交叉点存储阵列中选中存储单元所在列与其他列之间不会产生漏电流，在 此基础上，对交叉点存储阵列中的选中存储单元进行读操作，可以有效消除其他存储单元的影响。
在一种可能的实现方式中，所述读操作电路还包括多个第一开关，所述读出放大器的输入端通过所述多个第一开关与所述多条位线分别连接。所述交叉点存储阵列包含至少一行存储单元，所述至少一行存储单元包含所述选中存储单元；其中，在所述至少一行存储单元中选定包含所述选中存储单元的一行存储单元的情况下，若与所述目标位线连接的第一开关导通，且与所述其他位线连接的第一开关截止，则在所述交叉点存储阵列中选定所述选中存储单元。
如图6所示，读出放大器的输入端分别与多个第一开关的一端连接，多个第一开关的另一端与该多条位线一一对应连接。应理解，读操作电路中的第一开关与交叉点存储阵列中的位线连接，而交叉点存储阵列中多条位线中的每条位线又是与多列存储单元中的其中一列存储单元的每个存储单元的其中一端连接的，也即第一开关是通过位线与一列存储单元相连的，前述为了便于描述，本申请简述为第一开关与交叉点存储阵列中的列(存储单元)连接。此外，本申请其他处所描述的某一器件通过位线与交叉点存储阵列中的列(存储单元)连接，均可以描述为该器件通与交叉点存储阵列中的列(存储单元)连接。例如，多个第一开关分别为第一开关[0]、第一开关[1]、第一开关[2]、......、第一开关[2 m+1-2]以及第一开关[2 m+1-1]，多列存储单元分别为in[0]、in[1]、in[2]、......、in[2 m+1-2]以及in[2 m+1-1]；第一开关[0]、第一开关[1]、第一开关[2]、......、第一开关[2 m+1-2]以及第一开关[2 m+1-1]与in[0]、in[1]、in[2]、......、in[2 m+1-2]以及in[2 m+1-1]一一对应连接。
其中，交叉点存储阵列中列的数量与多个第一开关的数量可能相同，也可能不同。例如，假设该交叉点存储阵列为一个N*N的交叉点存储阵列，N的取值可能为2 m+1，N的取值也可能不为2 m+1。当交叉点存储阵列中列的数量与多个第一开关的数量相同时，该多个第一开关与交叉点存储阵列中的全部列存储单元一一对应连接。当交叉点存储阵列中列的数量小于多个第一开关的数量时，多个第一开关中的部分第一开关与交叉点存储阵列中的多列存储单元一一对应连接，且部分第一开关的数量为该多列存储单元的列数。当交叉点存储阵列中列的数量大于多个第一开关的数量时，该多个第一开关与该交叉点存储阵列中的部分列存储单元一一对应连接，且该部分列存储单元的列数为该多个第一开关的数量。
其中，读出放大器和电压跟随器和存储阵列的连接的第一开关和第二开关具有很低的内阻。
需要说明的是，在交叉点存储阵列中的至少一行存储单元中选定包含选中存储单元的一行存储单元的具体操作可以为：在包含选中存储单元的一行存储单元接上一个电压，而其他行断开。此外，还可以是采用其他可以在交叉点存储阵列中选定一列的方案，本申请对此不作具体限定。
前述已知，读出放大器的输入端通过多个第一开关分别与交叉点存储阵列中的多列存储单元连接，从而可以通过控制多个第一开关的通断来在交叉点存储阵列中选定一列存储单元进行读操作，也即通过控制多个第一开关的通断来在交叉点存储阵列中选定一列存储单元与读出放大器形成读操作的通路。而在交叉点存储阵列中的至少一行存储单元中选定包含选中存储单元的一行存储单元的情况下，若在交叉点存储阵列中再选定包含选中存储 单元的一列存储单元，即可实现在交叉点存储阵列中选定选中存储单元。具体地，在交叉点存储阵列中的至少一行存储单元中选定包含选中存储单元的一行存储单元的情况下，控制与包含选中存储单元的一列存储单元连接的第一开关导通，控制与其他列存储单元连接的第一开关截止；也即，控制与目标位线连接的第一开关导通，控制与其他位线连接的第一开关截止，即可在交叉点存储阵列中选定选中存储单元。
在本实现方式中，读出放大器的输入端是通过多个第一开关与多条位线分别连接的，如此，可以通过控制多个第一开关通断来实现对选中存储单元的选定；具体地，选中存储单元与目标位线连接，在交叉点存储阵列中选定包含选中存储单元的一行存储单元的情况下，控制与目标位线连接的第一开关导通，且控制与其他位线连接的第一开关截止，即可实现读出放大器与选中存储单元所在列形成通路而不与其他列形成通路，达到选定选中存储单元的目的。
在一种可能的实现方式中，所述多个第一开关为多个第一晶体管，所述多个第一晶体管中的任一第一晶体管包括第一端、第二端和控制端，所述控制端用于接收控制信号；所述读出放大器的输入端与所述多个第一晶体管的第一端分别连接，所述多个第一晶体管的第二端与所述多条位线对应连接。其中，所述任一第一晶体管的控制端用于控制所述任一第一晶体管的第一端与第二端之间的信号传输的通断；在所述至少一行存储单元中选定包含所述选中存储单元的一行存储单元的情况下，若与所述目标位线连接的第一晶体管的第一端与第二端之间的信号传输导通，且与所述其他位线连接的第一晶体管的第一端与第二端之间的信号传输截止，则在所述交叉点存储阵列中选定所述选中存储单元。
其中，任一第一晶体管的控制端为栅极/基极端；任一第一晶体管还可能包括第三端，任一第一晶体管的第三端接一固定信号。
其中，多个第一晶体管的第二端与多条位线对应连接，包括：当多个第一晶体管的数量与多条位线的数量相同时，多个第一晶体管的第二端与多条位线一一对应连接；当多个第一晶体管的数量小于多条位线的数量时，多个第一晶体管的第二端与多条位线中的部分位线一一对应连接，该部分位线的数量与该多个第一晶体管的数量相同；当多个第一晶体管的数量大于多条位线的数量时，多个第一晶体管中的部分第一晶体管的第二端与多条位线一一对应连接，该部分第一晶体管的数量与该多条位线的数量相同。
如图7所示，多个第一晶体管分别为Q1[0]、Q1[1]、Q1[2]、...…、Q1[2 m+1-2]以及Q1[2 m+1-1]，读出放大器的输入端与Q1[0]、Q1[1]、Q1[2]、...…、Q1[2 m+1-2]以及Q1[2 m+1-1]的第一端分别连接，Q1[0]、Q1[1]、Q1[2]、...…、Q1[2 m+1-2]以及Q1[2 m+1-1]的第二端与in[0]、in[1]、in[2]、…、in[2 m+1-2]以及in[2 m+1-1]一一对应连接，Q1[0]、Q1[1]、Q1[2]、...…、Q1[2 m+1-2]以及Q1[2 m+1-1]的控制端(图7中第一晶体管未接线的端口)用于控制其各自的第一端与第二端之间的信号传输的通断。
在本实现方式中，读出放大器的输入端是通过多个第一晶体管与多条位线分别连接的，如此，可以通过控制多个第一晶体管通断来实现对选中存储单元的选定；具体地，选中存储单元与目标位线连接，在交叉点存储阵列中选定包含选中存储单元的一行存储单元的情况下，控制与目标位线连接的第一晶体管导通，且控制与其他位线连接的第一晶体管截止，即可实现读出放大器与选中存储单元所在列形成通路而不与其他列形成通路，达到选定选 中存储单元的目的。
在一种可能的实现方式中，所述多个第一开关为多个第一传输门，所述多个第一传输门中的任一第一传输门包括第一端、第二端、同相控制端和反相控制端，所述同相控制端和所述反相控制端用于接收控制信号；所述读出放大器的输入端与所述多个第一传输门的第一端分别连接，所述多个第一传输门的第二端与所述多条位线对应连接。其中，所述任一第一传输门的同相控制端和反相控制端用于控制所述任一第一传输门的第一端与第二端之间的信号传输的通断；在所述至少一行存储单元中选定包含所述选中存储单元的一行存储单元的情况下，若与所述目标位线连接的第一传输门的第一端与第二端之间的信号传输导通，且与所述其他位线连接的第一传输门的第一端与第二端之间的信号传输截止，则在所述交叉点存储阵列中选定所述选中存储单元。
其中，传输门具有较小的内阻，第一开关采用第一传输门，可以减小开关的内阻，使得最后施加在交叉点存储阵列上的信号更加准确。
其中，多个第一传输门的第二端与多条位线对应连接，包括：当多个第一传输门的数量与多条位线的数量相同时，多个第一传输门的第二端与多条位线一一对应连接；当多个第一传输门的数量小于多条位线的数量时，多个第一传输门的第二端与多条位线中的部分位线一一对应连接，该部分位线的数量与该多个第一传输门的数量相同；当多个第一传输门的数量大于多条位线的数量时，多个第一传输门中的部分第一传输门的第二端与多条位线一一对应连接，该部分第一传输门的数量与该多条位线的数量相同。
如图8所示，多个第一传输门分别为T1[0]、T1[1]、T1[2]、...…、T1[2 m+1-2]以及T1[2 m+1-1]，读出放大器的输入端与T1[0]、T1[1]、T1[2]、...…、T1[2 m+1-2]以及T1[2 m+1-1]的第一端分别连接，T1[0]、T1[1]、T1[2]、...…、T1[2 m+1-2]以及T1[2 m+1-1]的第二端与in[0]、in[1]、in[2]、…、in[2 m+1-2]以及in[2 m+1-1]一一对应连接，T1[0]、T1[1]、T1[2]、...…、T1[2 m+1-2]以及T1[2 m+1-1]的同相控制端和反相控制端(图8中第一传输门未接线的端口)用于控制其各自的第一端与第二端之间的信号传输的通断。
需要说明的是，图7和图8所示的读操作电路的结构基本相同，唯一不同在于：图8所示的读操作电路将图7所示的读操作电路中的晶体管换成传输门。
在本实现方式中，读出放大器的输入端是通过多个第一传输门与多条位线分别连接的，如此，可以通过控制多个第一传输门通断来实现对选中存储单元的选定；具体地，选中存储单元与目标位线连接，在交叉点存储阵列中选定包含选中存储单元的一行存储单元的情况下，控制与目标位线连接的第一传输门导通，且控制与其他位线连接的第一传输门截止，即可实现读出放大器与选中存储单元所在列形成通路而不与其他列形成通路，达到选定选中存储单元的目的。
在一种可能的实现方式中，所述读操作电路还包括多个第二开关，所述电压跟随器的输入端通过所述多个第一开关与所述多条位线分别连接，所述电压跟随器的输出端通过多个第二开关与所述多条位线分别连接。在所述交叉点存储阵列中选定选中存储单元的情况下，若与所述目标位线连接的第二开关截止，且与所述其他位线连接的第二开关导通，则所述电压跟随器将所述目标位线上的电压复制至所述其他位线上。
如图6所示，电压跟随器的输入端分别与多个第一开关的一端连接，且电压跟随器的 输入端与读出放大器的输入端是与多个第一开关的同一端连接的；电压跟随器的输出端分别与多个第二开关的一端连接，多个第二开关的另一端与交叉点存储阵列中的多条位线对应连接。例如，多个第二开关分别为第二开关[0]、第二开关[1]、第二开关[2]、......、第二开关[2 m+1-2]以及第二开关[2 m+1-1]，第二开关[0]、第二开关[1]、第二开关[2]、......、第二开关[2 m+1-2]以及第二开关[2 m+1-1]也与in[0]、in[1]、in[2]、......、in[2 m+1-2]以及in[2 m+1-1]一一对应连接。
本申请在访问交叉点存储阵列，也即对交叉点存储阵列进行读操作时，需要读出放大器与电压跟随器的协同工作。具体地，当使得读出放大器选择交叉点存储阵列中的某一列存储单元时，电压跟随器不选择该列存储单元；反之，当使得读出放大器不选择交叉点存储阵列中的某一列存储单元时，电压跟随器选择该列存储单元。因此，在交叉点存储阵列中选定选中存储单元的情况下，读出放大器选择包含选中存储单元的一列存储单元而不选择其他列存储单元，故电压跟随器选择其他列存储单元而不选择包含选中存储单元的一列存储单元。此时，因读出放大器选择包含选中存储单元的一列存储单元而不选择其他列存储单元，已经使得与包含选中存储单元的一列存储单元连接的第一开关导通，与其他列存储单元连接的第一开关截止；若电压跟随器选择其他列存储单元而不选择包含选中存储单元的一列存储单元，需要再使得与包含选中存储单元的一列存储单元连接的第二开关截止，以及再使得与其他列存储单元连接的第二开关导通。如此，电压跟随器的输入端与包含选中存储单元的一列存储单元形成通路，电压跟随器的输出端其他列存储单元形成通路，从而电压跟随器实现将包含选中存储单元的一列存储单元上的电压复制至其他列存储单元上。
在本实现方式中，电压跟随器的输入端是通过上述多个第一开关与多条位线分别连接的，电压跟随器的输出端是通过多个第二开关与多条位线分别连接的；如此，在交叉点存储阵列中选定选中存储单元的情况下，可以通过控制多个第二开关的通断来实现将选中存储单元所在列的电压复制至其他列上；具体地，选中存储单元与目标位线连接，控制与目标位线连接的第二开关截止，且控制与其他位线连接的第二开关导通，即可实现电压跟随器的输入端与选中存储单元所在列形成通路而不与其他列形成通路，以及电压跟随器的输出端与其他列形成通路而不与选中存储单元所在列形成通路，达到将选中存储单元所在列的电压复制至其他列上的目的。
需要说明的是，如图6所示，多个第一开关可以构成一个第一开关阵列，多个第二开关可以构成一个第二开关阵列。
在一种可能的实现方式中，所述多个第二开关为多个第二晶体管，所述多个第二晶体管中的任一第二晶体管包括第一端、第二端和控制端，所述控制端用于接收控制信号；所述电压跟随器的输出端与所述多个第二晶体管的第一端分别连接，所述多个第二晶体管的第二端与所述多条位线对应连接。其中，所述任一第二晶体管的控制端用于控制所述任一第二晶体管的第一端与第二端之间的信号传输的通断；在所述交叉点存储阵列中选定选中存储单元的情况下，若与所述目标位线连接的第二晶体管的第一端与第二端之间的信号传输截止，且与所述其他位线连接的第二晶体管的第一端与第二端之间的信号传输导通，则所述电压跟随器将所述目标位线上的电压复制至所述其他位线上。
其中，与任一第一晶体管相同的，任一第二晶体管的控制端为栅极/基极端；任一第二 晶体管还可以包括第三端，任一第二晶体管的第三端接一固定信号。
其中，多个第二晶体管的第二端与多条位线对应连接，包括：当多个第二晶体管的数量与多条位线的数量相同时，多个第二晶体管的第二端与多条位线一一对应连接；当多个第二晶体管的数量小于多条位线的数量时，多个第二晶体管的第二端与多条位线中的部分位线一一对应连接，该部分位线的数量与该多个第二晶体管的数量相同；当多个第二晶体管的数量大于多条位线的数量时，多个第二晶体管中的部分第二晶体管的第二端与多条位线一一对应连接，该部分第二晶体管的数量与该多条位线的数量相同。
如图7所示，多个第二晶体管分别为Q2[0]、Q2[1]、Q2[2]、...…、Q2[2 m+1-2]以及Q2[2 m+1-1]，电压跟随器的输入端与Q1[0]、Q1[1]、Q1[2]、...…、Q1[2 m+1-2]以及Q1[2 m+1-1]的第一端分别连接，电压跟随器的输出端与Q2[0]、Q2[1]、Q2[2]、...…、Q2[2 m+1-2]以及Q2[2 m+1-1]的第一端分别连接，Q2[0]、Q2[1]、Q2[2]、...…、Q2[2 m+1-2]以及Q2[2 m+1-1]的第二端与in[0]、in[1]、in[2]、…、in[2 m+1-2]以及in[2 m+1-1]一一对应连接，Q2[0]、Q2[1]、Q2[2]、...…、Q2[2 m+1-2]以及Q2[2 m+1-1]的控制端(图7中第二晶体管未接线的端口)用于控制其各自的第一端与第二端之间的信号传输的通断。
在本实现方式中，电压跟随器的输入端是通过上述多个第一开关与多条位线分别连接的，电压跟随器的输出端是通过多个第二晶体管与多条位线分别连接的；如此，在交叉点存储阵列中选定选中存储单元的情况下，可以通过控制多个第二晶体管的通断来实现将选中存储单元所在列的电压复制至其他列上；具体地，选中存储单元与目标位线连接，控制与目标位线连接的第二晶体管截止，且控制与其他位线连接的第二晶体管导通，即可实现电压跟随器的输入端与选中存储单元所在列形成通路而不与其他列形成通路，以及电压跟随器的输出端与其他列形成通路而不与选中存储单元所在列形成通路，达到将选中存储单元所在列的电压复制至其他列上的目的。
在一种可能的实现方式中，所述任一第一晶体管的控制端输入的第一控制信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到；所述任一第二晶体管的控制端输入的第二控制信号通过对所述第一控制信号进行取反得到；所述任一第一晶体管的第二端和所述任一第二晶体管的第二端与所述多条位线中的同一条位线连接。其中，若在所述任一第一晶体管或所述任一第二晶体管的控制端输入正信号，则所述任一第一晶体管或所述任一第二晶体管的第一端与第二端之间的信号传输导通；若在所述任一第一晶体管或所述任一第二晶体管的控制端输入反信号，则所述任一第一晶体管或所述任一第二晶体管的第一端与第二端之间的信号传输截止；其中，所述正信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到，所述反信号通过将所述正信号输入反相器得到；或所述反信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到，所述正信号通过将所述反信号输入反相器得到。
具体地，将该多列存储单元的地址进行解码，例如，该多列存储单元为2 m+1列存储单元，该多列存储单元中的任一列存储单元的地址为m+1位的地址，也即任一列存储单元的地址可以用m+1位的地址表示，对应任一列存储单元对应的m+1位的地址进行解码，得到解码后的2 m+1个第一控制信号，且这2 m+1个第一控制信号与这2 m+1列存储单元是一一对应的，其中，2 m+1个第一控制信号包含该任一列存储单元对应的1个正信号和其他2 m+1-1列存储单 元一一对应的2 m+1-1个反信号；同时，将这2 m+1个第一控制信号通入反相器后得到了其对应的第二控制信号，也即得到与这2 m+1个第一控制信号一一对应的2 m+1个第二控制信号，其中，2 m+1个第二控制信号包含该任一列存储单元对应的1个反信号和其他2 m+1-1列存储单元一一对应的2 m+1-1个正信号。读出放大器的输入端通过这2 m+1个第一晶体管与阵列中2 m+1列存储单元连接；同样地，电压跟随器的输入端也通过这2 m+1个第一晶体管与阵列中这2 m+1列存储单元连接，电压跟随器的输出端也通过这2 m+1个第二晶体管与阵列中这2 m+1列存储单元连接。需要说明的是，与读出放大器和电压跟随器连接的列的数目可以根据电路设计的功耗、性能的规格进行设定，本申请对此不作具体限定。为了对晶体管的通断进行控制以实现读出放大器和电压跟随器之间对交叉点存储阵列中的某一列存储单元的互补选择，将解码得到的第一控制信号以及相应的第二控制信号作用于这些晶体管的控制端。其中，读出放大器选择交叉点存储阵列中的某一列存储单元、电压跟随器不选择该列存储单元时，解码得到的该列存储单元对应的第一控制信号为正信号，并施加于控制读出放大器与该列存储单元连接的第一晶体管的控制端；将该列存储单元对应的第一控制信号(正信号)输入反相器，得到该列存储单元对应的第二控制信号，该列存储单元对应的第二控制信号为反信号，并施加于控制电压跟随器与该列存储单元连接的第二晶体管的控制端。读出放大器不选择交叉点存储阵列中的某一列存储单元、电压跟随器选择该列存储单元时，解码得到的该列存储单元对应的第一控制信号为反信号，并施加于控制读出放大器与该列存储单元连接的第一晶体管的控制端；将该存储单元对应的第一控制信号(反信号)输入反相器，得到该列存储单元对应的第二控制信号，该列存储单元对应的第二控制信号为正信号，并施加于控制电压跟随器与该列存储单元连接的第二晶体管的控制端。
如图7所示，对于任一列存储单元来说，该任一列存储单元的地址为m+1位的地址，该m+1位的地址分别为地址[0]、地址[1]、地址[2]、...…、地址[m-1]以及地址[m]，2 m+1个第一控制信号分别为控制信号a[0]、控制信号a[1]、控制信号a[2]、......、控制信号a[2 m+1-2]以及控制信号a[2 m+1-1]，2 m+1个第二控制信号分别为控制信号b[0]、控制信号b[1]、控制信号b[2]、......、控制信号b[2 m+1-2]以及控制信号b[2 m+1-1]；多个第一晶体管分别为Q1[0]、Q1[1]、Q1[2]、...…、Q1[2 m+1-2]以及Q1[2 m+1-1]，多个第二晶体管分别为Q2[0]、Q2[1]、Q2[2]、...…、Q2[2 m+1-2]以及Q2[2 m+1-1]；读出放大器的输入端和电压跟随器的输入端均通过Q1[0]、Q1[1]、Q1[2]、...…、Q1[2 m+1-2]以及Q1[2 m+1-1]与in[0]、in[1]、in[2]、…、in[2 m+1-2]以及in[2 m+1-1]分别连接，电压跟随器的输出端通过Q2[0]、Q2[1]、Q2[2]、...…、Q2[2 m+1-2]以及Q2[2 m+1-1]与in[0]、in[1]、in[2]、…、in[2 m+1-2]以及in[2 m+1-1]分别连接；如此，可以通过控制Q1[0]、Q1[1]、Q1[2]、...…、Q1[2 m+1-2]以及Q1[2 m+1-1]，Q2[0]、Q2[1]、Q2[2]、...…、Q2[2 m+1-2]以及Q2[2 m+1-1]的通断来实现读出放大器与电压跟随器对一列存储单元的互补选择。例如，以in[0]列存储单元为例，若控制信号a[0]为正信号，并施加于控制读出放大器与in[0]列存储单元连接的第一晶体管Q1[0]的控制端(例如栅极端)，则控制信号b[0]为反信号，并施加于控制电压跟随器与in[0]列存储单元连接的第二晶体管Q2[0]的控制端(例如栅极端)，此时，第一晶体管Q1[0]导通，第二晶体管Q2[0]截止，则读出放大器选择in[0]列存储单元，电压跟随器不选择in[0]列存储单元；若控制信号a[0]为反信号，并施加于第一晶体管Q1[0]的控制端(例如栅极端)，则控制信号b[0]为正信号，并施加于第二晶体管Q2[0]的的控制 端(例如栅极端)，此时，第一晶体管Q1[0]截止，第二晶体管Q2[0]导通，则读出放大器不选择in[0]列存储单元，电压跟随器选择in[0]列存储单元。
需要说明的是，本申请所描述的反相器为任何能够将正信号和反信号相互转换的器件，例如可以为电平转换器。
在本实现方式中，对于任一第一晶体管或任一第二晶体管而言，若在其控制端输入正信号，则其第一端与第二端之间的信号传输导通；若在其控制端输入反信号，则其第一端与第二端之间的信号传输截止；正信号和反信号统称为控制信号。而控制信号是通过对与其连接的位线对应的一列存储单元的地址进行解码得到，当需要选定这一列存储单元时，解码得到的这一列存储单元对应的控制信号就是正信号，反之解码得到的这一列存储单元对应的控制信号就是反信号。控制信号的正反可以通过反相器进行相互转换：当控制信号为正信号时，将该控制信号输入反相器后，可以得到反信号；反之，当控制信号为反信号时，将该控制信号输入反相器后，可以得到正信号。故多列存储单元就有多个第一控制信号，以及该多个第一控制信号取反后对应得到的多个第二控制信号，且这多列存储单元与这多个第一控制信号以及多个第二控制信号是一一对应的；具体地，这多个第一控制信号包括一个正信号和多个反信号，这多个第二控制信号包括一个反信号和多个正信号，因为当需要选定这一列存储单元时，对这一列存储单元的地址进行解码，从而得到这一列存储单元对应的正信号以及其他列存储单元对应的反信号，再将这一列存储单元对应的正信号输入反相器即可得到这一列存储单元对应的反信号，以及将这其他列存储单元对应的反信号输入反相器即可得到其他列存储单元对应的正信号。由于多条位线是与多列存储单元一一对应的，若要使与任一条位线连接的第一晶体管或第二晶体管导通，在该任一条位线连接的第一晶体管或第二晶体管的控制端输入对应的正信号即可；若要使与任一条位线连接的第一晶体管或第二晶体管截止，在该任一条位线连接的第一晶体管或第二晶体管的控制端输入对应的反信号即可。此外，任一条位线连接的第一晶体管和第二晶体管的控制端输入的控制信号是相反的，当第一晶体管的控制端输入正信号时，第二晶体管的控制端输入反信号；当第一晶体管的控制端输入反信号时，第二晶体管的控制端输入正信号，从而可以实现电压跟随器和读出放大器对该条位线的互补选择，也即实现电压跟随器和读出放大器对该条位线的一列存储单元的互补选择。
在一种可能的实现方式中，所述多个第二开关为多个第二传输门，所述多个第二传输门中的任一第二传输门包括第一端、第二端、同相控制端和反相控制端，所述同相控制端和所述反相控制端用于接收控制信号；所述电压跟随器的输出端与所述多个第二传输门的第一端分别连接，所述多个第二传输门的第二端与所述多条位线对应连接。其中，所述任一第二传输门的同相控制端和反相控制端用于控制所述任一第二传输门的第一端与第二端之间的信号传输的通断；在所述交叉点存储阵列中选定选中存储单元的情况下，若与所述目标位线连接的第二传输门的第一端与第二端之间的信号传输截止，且与所述其他位线连接的第二传输门的第一端与第二端之间的信号传输导通，则所述电压跟随器将所述目标位线上的电压复制至所述其他位线上。
其中，传输门具有较小的内阻，第二开关采用第二传输门，可以减小开关的内阻，使得最后施加在交叉点存储阵列上的信号更加准确。
其中，多个第二传输门的第二端与多条位线对应连接，包括：当多个第二传输门的数量与多条位线的数量相同时，多个第二传输门的第二端与多条位线一一对应连接；当多个第二传输门的数量小于多条位线的数量时，多个第二传输门的第二端与多条位线中的部分位线一一对应连接，该部分位线的数量与该多个第二传输门的数量相同；当多个第二传输门的数量大于多条位线的数量时，多个第二传输门中的部分第二传输门的第二端与多条位线一一对应连接，该部分第二传输门的数量与该多条位线的数量相同。
如图8所示，多个第二传输门分别为T2[0]、T2[1]、T2[2]、...…、T2[2 m+1-2]以及T2[2 m+1-1]，电压跟随器的输入端与T1[0]、T1[1]、T1[2]、...…、T1[2 m+1-2]以及T1[2 m+1-1]的第一端分别连接，电压跟随器的输出端与T2[0]、T2[1]、T2[2]、...…、T2[2 m+1-2]以及T2[2 m+1-1]的第一端分别连接，T2[0]、T2[1]、T2[2]、...…、T2[2 m+1-2]以及T2[2 m+1-1]的第二端与in[0]、in[1]、in[2]、…、in[2 m+1-2]以及in[2 m+1-1]一一对应连接，T2[0]、T2[1]、T2[2]、...…、T2[2 m+1-2]以及T2[2 m+1-1]的同相控制端和反相控制端(图8中第二传输门未接线的端口)用于控制其各自的第一端与第二端之间的信号传输的通断。
在本实现方式中，电压跟随器的输入端是通过上述多个第一开关与多条位线分别连接的，电压跟随器的输出端是通过多个第二传输门与多条位线分别连接的；如此，在交叉点存储阵列中选定选中存储单元的情况下，可以通过控制多个第二传输门的通断来实现将选中存储单元所在列的电压复制至其他列上；具体地，选中存储单元与目标位线连接，控制与目标位线连接的第二传输门截止，且控制与其他位线连接的第二传输门导通，即可实现电压跟随器的输入端与选中存储单元所在列形成通路而不与其他列形成通路，以及电压跟随器的输出端与其他列形成通路而不与选中存储单元所在列形成通路，达到将选中存储单元所在列的电压复制至其他列上的目的。
在一种可能的实现方式中，所述任一第一传输门的同相控制端和所述任一第二传输门的反相控制端输入的第一控制信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到；所述任一第一传输门的反相控制端和所述任一第二传输门的同相控制端输入的第二控制信号通过对所述第一控制信号进行取反得到；所述任一第一传输门的第二端和所述任一第二传输门的第二端与所述多条位线中的同一条位线连接。其中，若在所述任一第一传输门或所述任一第二传输门的同相控制端输入正信号，且在所述任一第一传输门或所述任一第二传输门的反相控制端输入反信号，则所述任一第一传输门或所述任一第二传输门的第一端与第二端之间的信号传输导通；若在所述任一第一传输门或所述任一第二传输门的同相控制端输入所述反信号，且在所述任一第一传输门或所述任一第二传输门的反相控制端输入所述正信号，则所述任一第一传输门或所述任一第二传输门的第一端与第二端之间的信号传输截止；其中，所述正信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到，所述反信号通过将所述正信号输入反相器得到；或所述反信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到，所述正信号通过将所述反信号输入反相器得到。
具体地，将该多列存储单元的地址进行解码，例如，该多列存储单元为2 m+1列存储单元，该多列存储单元中的任一列存储单元的地址为m+1位的地址，也即任一列存储单元的地址可以用m+1位的地址表示，对应任一列存储单元对应的m+1位的地址进行解码，得到解 码后的2 m+1个第一控制信号，且这2 m+1个第一控制信号与这2 m+1列存储单元是一一对应的，其中，2 m+1个第一控制信号包含该任一列存储单元对应的1个正信号和其他2 m+1-1列存储单元一一对应的2 m+1-1个反信号；同时，将这2 m+1个第一控制信号通入反相器后得到了其第二控制信号，也即得到与这2 m+1个第一控制信号一一对应的2 m+1个第二控制信号，其中，2 m+1个第二控制信号包含该任一列存储单元对应的1个反信号和其他2 m+1-1列存储单元一一对应的2 m+1-1个正信号。读出放大器的输入端通过这2 m+1个第一传输门与阵列中2 m+1列存储单元连接；同样地，电压跟随器的输入端也通过这2 m+1个第一传输门与阵列中这2 m+1列存储单元连接，电压跟随器的输出端也通过这2 m+1个第二传输门与阵列中这2 m+1列存储单元连接。需要说明的是，与读出放大器和电压跟随器连接的列的数目可以根据电路设计的功耗、性能的规格进行设定，本申请对此不作具体限定。为了对传输门的通断进行控制以实现读出放大器和电压跟随器之间对交叉点存储阵列中的某一列存储单元的互补选择，将解码得到的第一控制信号以及相应的第二控制信号作用于这些传输门的同相控制端和反相控制端；其中，给定控制读出放大器连接的第一传输门的正反信号的顺序后，通过调换控制电压跟随器的第二传输门的正反信号的顺序，可以实现读出放大器与电压跟随器对交叉点存储阵列中的列的互补性选择。例如，读出放大器选择交叉点存储阵列中的某一列存储单元、电压跟随器不选择该列存储单元时，该列存储单元对应的第一控制信号为正信号，并施加于控制读出放大器与该列存储单元连接的第一传输门的同相控制端；该列存储单元对应的第一控制信号(正信号)输入反相器，得到该列存储单元对应的第二控制信号，该列存储单元对应的第二控制信号为反信号，并施加于控制读出放大器与该列存储单元连接的第一传输门的反相控制端；同时，该列存储单元对应的第二控制信号(反信号)施加于控制电压跟随器与该列存储单元连接的第二传输门的同相控制端，该列存储单元对应的第一控制信号(正信号)施加于控制电压跟随器与该列存储单元连接的第二传输门的反相控制端。读出放大器不选择交叉点存储阵列中的某一列存储单元、电压跟随器选择该列存储单元时，该列存储单元对应的第一控制信号为反信号，并施加于控制读出放大器与该列存储单元连接的第一传输门的同相控制端；该列存储单元对应的第一控制信号(反信号)输入反相器，得到该列存储单元对应的第二控制信号，该列存储单元对应的第二控制信号为正信号，并施加于控制读出放大器与该列存储单元连接的第一传输门的反相控制端；同时，该列存储单元对应的第二控制信号(正信号)施加于控制电压跟随器与该列存储单元连接的第二传输门的同相控制端，该列存储单元对应的第一控制信号(反信号)施加于控制电压跟随器与该列存储单元连接的第二传输门的反相控制端。
如图8所示，对于任一列存储单元来说，该任一列存储单元的地址为m+1位的地址，该m+1位的地址分别为地址[0]、地址[1]、地址[2]、...…、地址[m-1]以及地址[m]，2 m+1个第一控制信号分别为控制信号a[0]、控制信号a[1]、控制信号a[2]、......、控制信号a[2 m+1-2]以及控制信号a[2 m+1-1]，2 m+1个第二控制信号分别为控制信号b[0]、控制信号b[1]、控制信号b[2]、......、控制信号b[2 m+1-2]以及控制信号b[2 m+1-1]；多个第一传输门分别为T1[0]、T1[1]、T1[2]、...…、T1[2 m+1-2]以及T1[2 m+1-1]，多个第二传输门分别为T2[0]、T2[1]、T2[2]、...…、T2[2 m+1-2]以及T2[2 m+1-1]；读出放大器的输入端和电压跟随器的输入端均通过T1[0]、T1[1]、T1[2]、...…、T1[2 m+1-2]以及T1[2 m+1-1]与in[0]、in[1]、in[2]、…、in[2 m+1-2]以及in[2 m+1-1] 分别连接，电压跟随器的输出端通过T2[0]、T2[1]、T2[2]、...…、T2[2 m+1-2]以及T2[2 m+1-1]与in[0]、in[1]、in[2]、…、in[2 m+1-2]以及in[2 m+1-1]分别连接；如此，可以通过控制T1[0]、T1[1]、T1[2]、...…、T1[2 m+1-2]以及T1[2 m+1-1]，T2[0]、T2[1]、T2[2]、...…、T2[2 m+1-2]以及T2[2 m+1-1]的通断来实现读出放大器与电压跟随器对一列存储单元的互补选择。例如，以in[0]列存储单元为例，若控制信号a[0]为正信号，则控制信号b[0]为反信号，控制信号a[0]施加于控制读出放大器与in[0]列存储单元连接的第一传输门T1[0]的同相控制端(例如C端口)，控制信号b[0]施加于第一传输门T1[0]的反相控制端(例如C反端口)，控制信号b[0]施加于控制电压跟随器与in[0]列存储单元连接的第二传输门T2[0]的同相控制端(例如C端口)，以及控制信号a[0]施加于第二传输门T1[0]的反相控制端(例如C反端口)，此时，第一传输门T1[0]导通，第二传输门T2[0]截止，则读出放大器选择in[0]列存储单元，电压跟随器不选择in[0]列存储单元。若控制信号a[0]为反信号，则控制信号b[0]为正信号，控制信号a[0]施加于第一传输门T1[0]的同相控制端(例如C端口)，控制信号b[0]施加于第一传输门T1[0]的反相控制端(例如C反端口)，控制信号b[0]施加于第二传输门T2[0]的同相控制端(例如C端口)，以及控制信号a[0]施加于第二传输门T1[0]的反相控制端(例如C反端口)，此时，第一传输门T1[0]截止，第二传输门T2[0]导通，则读出放大器不选择in[0]列存储单元，电压跟随器选择in[0]列存储单元。
在本实现方式中，对于任一第一传输门或任一第二传输门而言，若在其同相控制端输入正信号且在其反相控制端输入反信号，则其第一端与第二端之间的信号传输导通；若在其同相控制端输入反信号且在其反相控制端输入正信号，则其第一端与第二端之间的信号传输截止；正信号和反信号统称为控制信号。而控制信号是通过对与其连接的位线对应的一列存储单元的地址进行解码得到，当需要选定这一列存储单元时，解码得到的这一列存储单元对应的控制信号就是正信号，反之解码得到的这一列存储单元对应的控制信号就是反信号。控制信号的正反可以通过反相器进行相互转换：当控制信号为正信号时，将该控制信号输入反相器后，可以得到反信号；反之，当控制信号为反信号时，将该控制信号输入反相器后，可以得到正信号。故多列存储单元就有多个第一控制信号，以及该多个第一控制信号对应的多个第二控制信号，且这多列存储单元与这多个第一控制信号以及多个第二控制信号是一一对应的；具体地，这多个第一控制信号包括一个正信号和多个反信号，这多个第二控制信号包括一个反信号和多个正信号，因为当需要选定这一列存储单元时，对这一列存储单元的地址进行解码，从而得到这一列存储单元对应的正信号以及其他列存储单元对应的反信号，再将这一列存储单元对应的正信号输入反相器即可得到这一列存储单元对应的反信号，以及将这其他列存储单元对应的反信号输入反相器即可得到其他列存储单元对应的正信号。由于多条位线是与多列存储单元一一对应的，若要使与任一条位线连接的第一传输门或第二传输门导通，在该任一条位线连接的第一传输门或第二传输门的同相控制端输入对应的正信号、反相控制端输入对应的反信号即可；若要使与任一条位线连接的第一传输门或第二传输门截止，在该任一条位线连接的第一传输门或第二传输门的同相控制端输入对应的反信号、反相控制端输入对应的正信号即可。此外，任一条位线连接的第一传输门和第二传输门的同相控制端以及反相控制端输入的控制信号是相反的，当第一传输门的同相控制端输入正信号、第一传输门的反相控制端输入反信号时，第二传输 门的同相控制端输入反信号、第二传输门的反相控制端输入正信号；当第一传输门的同相控制端输入反信号、第一传输门的反相控制端输入正信号时，第二传输门的同相控制端输入正信号、第二传输门的反相控制端输入反信号，从而可以实现电压跟随器和读出放大器对该条位线的互补选择，也即实现电压跟随器和读出放大器对该条位线的一列存储单元的互补选择。
在一种可能的实现方式中，所述读操作电路还包括译码器和反相器；所述译码器，用于对包含所述选中存储单元的一列存储单元的地址进行解码，以得到所述第一控制信号；所述反相器，用于对所述第一控制信号进行取反，以得到所述第二控制信号。
如图7或图8所示，将任一列存储单元对应的m+1位的地址(地址[0]、地址[1]、地址[2]、...…、地址[m-1]以及地址[m])输入到译码器，解码得到2 m+1个第一控制信号，分别为控制信号a[0]、控制信号a[1]、控制信号a[2]、......、控制信号a[2 m+1-2]以及控制信号a[2 m+1-1]；再将该2 m+1个第一控制信号一一对应输入到反相器P[0]、P[1]、P[2]、...…、P[2 m+1-2]以及P[2 m+1-1]，对应得到2 m+1个第二控制信号，分别为控制信号b[0]、控制信号b[1]、控制信号b[2]、......、控制信号b[2 m+1-2]以及控制信号b[2 m+1-1]；其中，当第一控制信号为正信号时，对应的第二控制信号为反信号，当第一控制信号为反信号时，对应的第二控制信号为正信号。例如，将第一列存储单元in[0]的地址输入译码器，解码得到2 m+1个第一控制信号，2 m+1个第一控制信号中的控制信号a[0]为正信号，而控制信号a[1]、控制信号a[2]、......、控制信号a[2 m+1-2]以及控制信号a[2 m+1-1]均为反信号；再将该2 m+1个第一控制信号一一对应输入到反相器P[0]、P[1]、P[2]、...…、P[2 m+1-2]以及P[2 m+1-1]，对应得到2 m+1个第二控制信号，2 m+1个第二控制信号中的控制信号b[0]为反信号，而控制信号b[1]、控制信号b[2]、......、控制信号b[2 m+1-2]以及控制信号b[2 m+1-1]均为正信号。
在本实现方式中，读操作电路还包括译码器和反相器，译码器用于对包含选中存储单元的一列存储单元的地址进行解码，以得到多个第一控制信号；反相器用于对多个第一控制信号进行取反，以得到对应的多个第二控制信号。由于控制信号包括正信号和反信号，控制信号的正反可以通过反相器进行相互转换：当控制信号为正信号时，将该控制信号输入反相器后，可以得到反信号；反之，当控制信号为反信号时，将该控制信号输入反相器后，可以得到正信号。而多个第一控制信号包括一个正信号和多个反信号，通过反相器取反后得到多个第二控制信号，第二控制信号包括一个反信号和多个正信号，如此，可以得到用于控制第一晶体管、第二晶体管、第一传输门或第二传输门通断的正信号以及反信号。
需要说明的是，本申请的读操作电路也可以不包括译码器和反相器，第一控制信号和第二控制信号还可以是通过读操作电路以外的其他外围电路得到。例如，该外围电路包括译码器和反相器，该外围电路的译码器对该任一列存储单元的地址进行解码得到任一列存储单元对应的第一控制信号，该外围电路的反相器对任一列存储单元对应的第一控制信号进行处理，得到任一列存储单元对应的第二控制信号。
在一种可能的实现方式中，所述电压跟随器包括以下任意一项：集成运放电压跟随器、共漏放大器、翻转电压跟随器。
本申请中的电压跟随器实现的功能至少包括：1)复制电压：其输出端的电压等于输入端的电压；2)隔离：其输入电阻很高，输出阻抗较低。因此，电压跟随器的输出端的负载 大小不会对其输入端的电压、电流产生影响。
示例性的，电压跟随器可以通过共漏放大器或者集成运放负反馈实现。
例如，电压跟随器可以为集成运放电压跟随器，如图9所示；集成运放电压跟随器通过对运放进行负反馈，并对其负反馈通路阻抗，输入端阻抗，输出端阻抗的适当设计可以实现稳定，精准的电压跟随器。
此外，电压跟随器也可以根据共漏放大器结构搭建，如图10所示；如图11所示的是基于共漏放大器实现的翻转电压跟随器电路。
在一种可能的实现方式中，所述读出放大器包括以下任意一项：电压灵敏放大器、电流灵敏放大器。
本申请的读出放大器可以采用电压放大器(voltage SA)，如图12所示，读出放大器为电压灵敏放大器，该电压灵敏放大器采样待读出存储单元(选中存储单元)的输出电压和参考存储单元的输出电压，并进行比较得到待读出存储单元(选中存储单元)的状态。
此外，本申请的读出放大器也可以采用电流放大器(current SA)，如图13所示，读出放大器为电流灵敏放大器，电流灵敏放大器采样待读出存储单元(选中存储单元)的输出电流和参考存储单元的输出电流，并进行比较得到待读出存储单元(选中存储单元)的状态。
综上介绍，本申请提供的读操作电路中，包含并且不限于以下模块：电压跟随器、读出放大器以及选择模块。其中，电压跟随器可以采用带有负反馈的放大器实现，如单位增益放大器，也可以由共源极放大器，共集电极电路实现。读出放大器可以是比较读出电流和参考电流得到存储单元状态的电流型放大器，也可以是比较读出电压和参考电压得到存储单元状态的电压型放大器。选择模块可以是通过地址选择某一行或列的译码器。在读出放大器和待读出阵列间的开关可以是晶体管、传输门等具有开关性质的电路。在电压跟随器和待读出阵列间的开关可以是晶体管、传输门等具有开关性质的电路。在读操作电路中，电压跟随器的输入端连接读出放大器的待读信号的输入端，该连接点的位置位于待读出信号所在的行或者列与读出放大器之间的开关附近，并且位于靠近读出放大器的一侧，电压跟随器的输出端通过开关连接到存储阵列。现有技术对交叉点存储阵列进行读操作，由于电压分压和电流分流的原理，行与行之间或者列与列之间的电压不同，会造成不同列和不同行之间读电流的串扰。而本申请通过分时单个读出，复制待读存储单元(选中存储单元)电压压制其他列/行，使得不同行/列之间形成等电位而避免了读电流的串扰的问题，实现了在存储单元中无选择性器件条件下，纯交叉点存储阵列的读操作；本申请在不降低交叉点存储阵列的存储密度的前提下，增大了阵列的读出窗口。
下面结合图14至图19对本申请提供的读操作电路的具体应用进行示例性说明。
(1)读操作电路在两端存储器件构成的交叉点存储阵列中的应用。
本申请可以适用于所有的两端存储器件构成的交叉点存储阵列，如阻变存储器(RRAM)、相变存储器(PCRAM)、铁电存储器(FeRAM)、磁存储器(STT-MRAM)等非挥发性随机存储器。在存储阵列的设计上采用交叉点结构，但是由于交叉点存储阵列的读操作窗口会随着交叉点结构阵列的规模的增大而减小，同时读操作和写操作的漏电也 会由于交叉点结构阵列的规模增大而增大。因此，在交叉点结构阵列的实际应用中，设计者需要根据芯片性能和功耗的规格对交叉点结构阵列的阵列规模进行适当的调整。
本申请实施例将交叉点结构阵列按4列为一个独立的交叉点结构阵列进行分块。如图14所示，图14是由两端器件构成的交叉点结构阵列，该交叉点结构阵列中同一个行的每4个存储单元共用一个晶体管连接到SL(source line，位线)上，这个共用的晶体管的栅极由字线(WL)控制。当选中某一行时，对应与这一行与SL连接的晶体管打开；例如，当选中第一行时，WL0输入控制信号，使得与SL0连接的晶体管打开(导通)。对于读操作电路，设定其地址的位数为2，也即m＝1；若选择了这4列中的其中一列进行读操作，如选择了第一列，则这一列与读出放大器连接，其他3列则与电压跟随器连接，这样就读出了阵列中第一行、第一列的一个存储单元的状态。
其中，对交叉点结构阵列进行读操作的步骤可以为：1)根据外围电路输入的地址，外围电路中的译码器驱动字线(WL)打开某一行的晶体管，通过打开的晶体管给这一行的存储单元行金属线施加一个电压V1；2)根据外围电路输入的地址，读操作电路中的译码器和反相器输出相应的控制信号(正信号或反信号)，使得电压跟随器和读出放大器选择了相应的列，并打开或者关闭用于连接电压跟随器和存储阵列，以及用于连接读出放大器和存储阵列之间的开关电路(如晶体管或者传输门等)，此步骤的操作可同时或者不同时于前一步骤的操作；3)使能读出放大器，读出放大器建立和待读出存储单元(选中存储单元)之间的通路，电压跟随器将待读出存储单元与读出放大器之间的电压复制至其他非待读出单元的对应的列上；4)读出放大器输出读出结果；5)读出放大器使能关闭，通过改变字线电位关闭这一行存储单元上的晶体管，读操作完成。
此外，为了节省读出放大器以及电压跟随器的数目，减少电路面积，本申请可以在多个存储单元中选择其中一个存储单元进行读取，即一个读操作电路对应于多个存储单元。如图15所示，图15同样是两端存储器的交叉点阵列结构，通过改变读操作电路中地址的位数，即m的值，可以实现读出放大器可控制列的数目增多。如图15所示，假设一个读操作电路对应交叉点存储阵列中的n列存储单元，则m＝log 2n-1；例如，当设定读操作电路中m的为2时，读操作电路可以同时控制8列存储单元的读操作。
(2)读操作电路在两端存储器件构成的交叉点存储阵列中的应用。
本申请也可应用于存储器件构成的交叉点存储阵列，如自旋轨道矩磁性随机存储器。自旋轨道矩磁性随机存储器通过存储单元底部连接的金属线电流的方向不同实现写“0”和写“1”，并通过读取电阻大小得到存储的状态。当一根金属线上有多个存储单元时，在底部金属线通电进行操作的同时，可以通过控制存储单元顶部的电压控制该存储单元的写入和非写入。使用自旋轨道矩磁性随机存储器构建的交叉点存储阵列如图16所示。同一金属线上可放置的存储单元个数可以根据存储芯片性能规格进行调整。在本申请实施例中，假设4个存储单元共用一根金属线，底部金属线的两端各连接了一个晶体管用于控制写电流的通断，这两个晶体管共用一根WL。如图16所示，假设读取第一列第一行的存储单元，则当WL0信号拉高时，即选中第一行；在读操作电路[0]中选择第一列，则读操作电路[0]的读出放大器连接在第一列上，而剩余的3列则与读操作电路[0]的电压跟随器连接，这样就实现第一行第一列存储单元的访问。
同样地，三端存储阵列也可以在多个存储单元选择中一个存储单元进行读取，即一个读操作电路对应于多个存储单元，如图17所示。
其中，图16和图17中的ctrl表示位线，ctrl0、ctrl1、ctrl2、ctrl3......、ctrln-3、ctrln-2、ctrln-1、ctrln表示不同的位线。
(3)读操作电路在三维堆叠的交叉点存储阵列中的应用。
除了在二维阵列中的应用，本申请的读操作电路还可以用于三维堆叠的交叉点结构阵列中，如图18和图19所示。
在实际应用时，本申请中的读操作电路和存储阵列之间的连接关系，可以是一个读操作电路对应于一个交叉点存储阵列，如图18和图19所示；也可以是多个读操作电路对应于一个交叉点存储阵列，如图14和图16所示，读操作电路[0]、读操作电路[0]、读操作电路[0]、......、读操作电路[k]对应一个交叉点阵列；或者是一个读操作电路对应于多个交叉点阵列，如图15和图17所示。
此外，本申请实施例还提供了一种存储器。请参考图20，图20为本申请实施例提供的一种存储器的示意图。如图20所示，该存储器上设置有多个存储单元2001以及前文结合图6至图19所描述的读操作电路2000。
本申请实施例还提供了一种电子设备，该电子设备可以包括电路板和如图20所示的存储器。例如，该电子设备可以包括但不限于扬声器、显示屏、通信设备等。
需要说明的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例方案的目的。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (24)

  1. 一种读操作电路，其特征在于，包括电压跟随器和读出放大器；所述电压跟随器和所述读出放大器分别与交叉点存储阵列耦合，所述交叉点存储阵列包含多列存储单元以及与所述多列存储单元一一对应的多条位线，所述多列存储单元中的每一列存储单元的每一个存储单元的其中一端与所述每一列存储单元对应的位线连接；
    所述电压跟随器，用于将与选中存储单元连接的目标位线上的电压复制至所述多条位线中除所述目标位线之外的其他位线上；
    所述读出放大器，用于对所述选中存储单元进行读操作。
  2. 根据权利要求1所述的读操作电路，其特征在于，所述读操作电路还包括多个第一开关，所述读出放大器的输入端通过所述多个第一开关与所述多条位线分别连接。
  3. 根据权利要求2所述的读操作电路，其特征在于，所述多个第一开关为多个第一晶体管，所述多个第一晶体管中的任一第一晶体管包括第一端、第二端和控制端，所述控制端用于接收控制信号；
    所述读出放大器的输入端与所述多个第一晶体管的第一端分别连接，所述多个第一晶体管的第二端与所述多条位线对应连接。
  4. 根据权利要求2所述的读操作电路，其特征在于，所述多个第一开关为多个第一传输门，所述多个第一传输门中的任一第一传输门包括第一端、第二端、同相控制端和反相控制端，所述同相控制端和所述反相控制端用于接收控制信号；
    所述读出放大器的输入端与所述多个第一传输门的第一端分别连接，所述多个第一传输门的第二端与所述多条位线对应连接。
  5. 根据权利要求2-4任一项所述的读操作电路，其特征在于，所述读操作电路还包括多个第二开关，所述电压跟随器的输入端通过所述多个第一开关与所述多条位线分别连接，所述电压跟随器的输出端通过所述多个第二开关与所述多条位线分别连接。
  6. 根据权利要求5所述的读操作电路，其特征在于，所述多个第二开关为多个第二晶体管，所述多个第二晶体管中的任一第二晶体管包括第一端、第二端和控制端，所述控制端用于接收控制信号；
    所述电压跟随器的输出端与所述多个第二晶体管的第一端分别连接，所述多个第二晶体管的第二端与所述多条位线对应连接。
  7. 根据权利要求6所述的读操作电路，其特征在于，所述任一第一晶体管的控制端输入的第一控制信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到；
    所述任一第二晶体管的控制端输入的第二控制信号通过对所述第一控制信号进行取反 得到；
    所述任一第一晶体管的第二端和所述任一第二晶体管的第二端与所述多条位线中的同一条位线连接。
  8. 根据权利要求5所述的读操作电路，其特征在于，所述多个第二开关为多个第二传输门，所述多个第二传输门中的任一第二传输门包括第一端、第二端、同相控制端和反相控制端，所述同相控制端和所述反相控制端用于接收控制信号；
    所述电压跟随器的输出端与所述多个第二传输门的第一端分别连接，所述多个第二传输门的第二端与所述多条位线对应连接。
  9. 根据权利要求8所述的读操作电路，其特征在于，所述任一第一传输门的同相控制端和所述任一第二传输门的反相控制端输入的第一控制信号通过对包含所述选中存储单元的一列存储单元的地址进行解码得到；
    所述任一第一传输门的反相控制端和所述任一第二传输门的同相控制端输入的第二控制信号通过对所述第一控制信号进行取反得到；
    所述任一第一传输门的第二端和所述任一第二传输门的第二端与所述多条位线中的同一条位线连接。
  10. 根据权利要求7或9所述的读操作电路，其特征在于，所述读操作电路还包括译码器和反相器；
    所述译码器，用于对包含所述选中存储单元的一列存储单元的地址进行解码，以得到所述第一控制信号；
    所述反相器，用于对所述第一控制信号进行取反，以得到所述第二控制信号。
  11. 根据权利要求1-10任一项所述的读操作电路，其特征在于，所述电压跟随器包括以下任意一项：集成运放电压跟随器、共漏放大器、翻转电压跟随器。
  12. 根据权利要求1-11任一项所述的读操作电路，其特征在于，所述读出放大器包括以下任意一项：电压灵敏放大器、电流灵敏放大器。
  13. 一种读操作电路，其特征在于，包括电压跟随器、读出放大器、第一开关阵列和第二开关阵列；
    所述读出放大器的输入端通过所述第一开关阵列与交叉点存储阵列中的多条位线分别连接；
    所述电压跟随器的输入端通过所述第一开关阵列与所述多条位线分别连接，所述电压跟随器的输出端通过所述第二开关阵列与所述多条位线分别连接；
    所述交叉点存储阵列还包含与所述多条位线一一对应的多列存储单元，所述多列存储单元中的每一列存储单元的每一个存储单元的其中一端与所述每一列存储单元对应的位线 连接。
  14. 根据权利要求13所述的读操作电路，其特征在于，所述第一开关阵列包括多个第一晶体管，所述多个第一晶体管中的任一第一晶体管包括第一端、第二端和控制端，所述控制端用于接收控制信号；
    所述读出放大器的输入端与所述多个第一晶体管的第一端分别连接，所述多个第一晶体管的第二端与所述多条位线对应连接。
  15. 根据权利要求13所述的读操作电路，其特征在于，所述第一开关阵列包括多个第一传输门，所述多个第一传输门中的任一第一传输门包括第一端、第二端、同相控制端和反相控制端，所述同相控制端和所述反相控制端用于接收控制信号；
    所述读出放大器的输入端与所述多个第一传输门的第一端分别连接，所述多个第一传输门的第二端与所述多条位线对应连接。
  16. 根据权利要求13-15任一项所述的读操作电路，其特征在于，所述第二开关阵列包括多个第二晶体管，所述多个第二晶体管中的任一第二晶体管包括第一端、第二端和控制端，所述控制端用于接收控制信号；
    所述电压跟随器的输出端与所述多个第二晶体管的第一端分别连接，所述多个第二晶体管的第二端与所述多条位线对应连接。
  17. 根据权利要求16所述的读操作电路，其特征在于，所述任一第一晶体管的控制端输入的第一控制信号通过对包含选中存储单元的一列存储单元的地址进行解码得到；
    所述任一第二晶体管的控制端输入的第二控制信号通过对所述第一控制信号进行取反得到；
    所述任一第一晶体管的第二端和所述任一第二晶体管的第二端与所述多条位线中的同一条位线连接。
  18. 根据权利要求13-15任一项所述的读操作电路，其特征在于，所述第二开关阵列包括多个第二传输门，所述多个第二传输门中的任一第二传输门包括第一端、第二端、同相控制端和反相控制端，所述同相控制端和所述反相控制端用于接收控制信号；
    所述电压跟随器的输出端与所述多个第二传输门的第一端分别连接，所述多个第二传输门的第二端与所述多条位线对应连接。
  19. 根据权利要求18所述的读操作电路，其特征在于，所述任一第一传输门的同相控制端和所述任一第二传输门的反相控制端输入的第一控制信号通过对包含选中存储单元的一列存储单元的地址进行解码得到；
    所述任一第一传输门的反相控制端和所述任一第二传输门的同相控制端输入的第二控制信号通过对所述第一控制信号进行取反得到；
    所述任一第一传输门的第二端和所述任一第二传输门的第二端与所述多条位线中的同一条位线连接。
  20. 根据权利要求17或19所述的读操作电路，其特征在于，所述读操作电路还包括译码器和反相器；
    所述译码器，用于对包含所述选中存储单元的一列存储单元的地址进行解码，以得到所述第一控制信号；
    所述反相器，用于对所述第一控制信号进行取反，以得到所述第二控制信号。
  21. 根据权利要求13-20任一项所述的读操作电路，其特征在于，所述电压跟随器包括以下任意一项：集成运放电压跟随器、共漏放大器、翻转电压跟随器。
  22. 根据权利要求13-21任一项所述的读操作电路，其特征在于，所述读出放大器包括以下任意一项：电压灵敏放大器、电流灵敏放大器。
  23. 一种存储器，其特征在于，所述存储器中包括多个存储单元和如权利要求1-12或13-22任一项所述的读操作电路。
  24. 一种电子设备，其特征在于，所述电子设备包括电路板和如权利要求23所述的存储器。
PCT/CN2021/100564 2021-06-17 2021-06-17 读操作电路、芯片及电子设备 WO2022261890A1 (zh)

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Publication number Priority date Publication date Assignee Title
CN1417802A (zh) * 2001-10-31 2003-05-14 惠普公司 混合阻性交叉点存储单元阵列及其制造方法
CN102280128A (zh) * 2010-06-09 2011-12-14 上海宏力半导体制造有限公司 存储器
CN104992723A (zh) * 2015-06-11 2015-10-21 北京时代民芯科技有限公司 一种高可靠sram编译器控制电路
CN106601290A (zh) * 2016-11-01 2017-04-26 中国科学院上海微系统与信息技术研究所 具有温度跟随特性的相变存储器读电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1417802A (zh) * 2001-10-31 2003-05-14 惠普公司 混合阻性交叉点存储单元阵列及其制造方法
CN102280128A (zh) * 2010-06-09 2011-12-14 上海宏力半导体制造有限公司 存储器
CN104992723A (zh) * 2015-06-11 2015-10-21 北京时代民芯科技有限公司 一种高可靠sram编译器控制电路
CN106601290A (zh) * 2016-11-01 2017-04-26 中国科学院上海微系统与信息技术研究所 具有温度跟随特性的相变存储器读电路

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