WO2022242019A1 - 一种管脚状态的配置电路、配置方法及电子设备 - Google Patents

一种管脚状态的配置电路、配置方法及电子设备 Download PDF

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Publication number
WO2022242019A1
WO2022242019A1 PCT/CN2021/123626 CN2021123626W WO2022242019A1 WO 2022242019 A1 WO2022242019 A1 WO 2022242019A1 CN 2021123626 W CN2021123626 W CN 2021123626W WO 2022242019 A1 WO2022242019 A1 WO 2022242019A1
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Prior art keywords
configuration
voltage
resistor
pin
capacitor
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PCT/CN2021/123626
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English (en)
French (fr)
Inventor
陈建
刘源俊
张贵平
莫尚林
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华为数字能源技术有限公司
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Publication of WO2022242019A1 publication Critical patent/WO2022242019A1/zh

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005Modifications of input or output impedance
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1737Controllable logic circuits using multiplexers

Definitions

  • the present application relates to the field of electronic technology, and in particular to a pin state configuration circuit, configuration method and electronic equipment.
  • the pin In the design of an integrated circuit (Integrated Circuit IC) chip, the pin (PIN) is used to transmit the input and output signals of the chip, including data signals, clock signals, and power signals.
  • the pin state In order to realize more functions on the same chip and improve the cost performance of the chip, most chips provide the configuration function of the pin state during manufacture. According to different configurations of the pin state, the chip can be in different working states, so that different functions or performances can be realized.
  • There are generally two ways to configure the pin state the first way is to configure different voltages for the pins, and different voltages represent different pin states; the second way is to modify the internal register unit of the chip through an external processor. Content, to realize the configuration of the pin state.
  • FIG. 1 is a schematic structural diagram of a pin state configuration circuit in the related art.
  • the configuration circuit implements mode configuration based on a resistor voltage division strategy, and uses resistors R01 and R02 to configure the voltage of the mode configuration pin MOD between VCC and GND.
  • the IC mode detection stage read and latch the voltage value on the mode configuration pin MOD at the startup time, and then determine the corresponding mode state according to the read voltage value, so different configurations of R01 and R02 can configure different modes.
  • FIG. 2 is a schematic diagram of the working principle of pin state configuration in another related art.
  • the resistor R01 is the external connection resistor of the chip
  • the resistor R02 is the variable resistor inside the chip.
  • the resistance value of the resistor R01 and the resistance value of the resistor R02 are adjusted. Compare to determine the corresponding mode, so different R01 configurations can be configured with different modes.
  • mode configuration is based on a single pin MOD to achieve a set of configuration states, but due to the difference in the characteristics of internal and external resistors, the comparison accuracy is low, resulting in a reduction in the number of configurable states.
  • the present application provides a pin state configuration circuit, configuration method and electronic equipment, which are used to increase the number of configurable states.
  • a pin state configuration circuit provided in an embodiment of the present application includes: a configuration resistor load, a voltage acquisition unit, and a comparator.
  • the configuration resistor load is used to connect the first configuration pin and the second configuration pin of the chip; Configure the resistor load to provide a second reference voltage, and collect the voltage of the first configuration pin and the voltage of the second configuration pin respectively; Calculate the first voltage ratio between the voltage of the first configuration pin and the voltage of the second configuration pin collected when the configuration pin provides the second reference voltage to the configuration resistor load, according to the voltage acquisition unit in calculating a second voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin collected when the second configuration pin provides a second reference voltage to the configuration resistor load, and The first voltage ratio and the second voltage ratio determine corresponding pin configuration states.
  • the configuration circuit provided in the present application can obtain the first voltage ratio of N states and the second voltage ratio of N states by configuring the resistance in the configuration resistor load. Therefore, combining the first voltage ratio and the second voltage ratio can configure N ⁇ N states, that is, the application can determine N ⁇ N pin configuration states according to the first voltage ratio and the second voltage ratio, so that the chip can be configured Configure N ⁇ N mode states.
  • the configuration resistor load is not working, so there is no power loss.
  • the configuration resistor load may include a configurable first resistor, a configurable second resistor, and a configurable third resistor; the first terminal of the first resistor is connected to the first reference voltage, and the second terminal of the first resistor The two terminals are connected to the first configuration pin; the first terminal of the second resistor is connected to the first reference voltage, the second terminal of the second resistor is connected to the second configuration pin, and the third resistor is connected to the second terminal of the first resistor and the second terminal of the second resistor. between the second terminals of the two resistors.
  • the comparator may include a voltage ratio calculation unit and a state machine unit, wherein the voltage ratio unit may be based on the voltage of the first configuration pin collected by the voltage acquisition unit when the second reference voltage is provided to the configuration resistor load through the first configuration pin and the voltage of the second configuration pin to calculate the first voltage ratio, and according to the voltage of the first configuration pin collected by the voltage acquisition unit when the second reference voltage is provided to the configuration resistor load through the second configuration pin and the second Configure the voltage of the pin to calculate the second voltage ratio; thus the state machine unit can determine the corresponding configuration state of the pin according to the first voltage ratio and the second voltage ratio.
  • this application configures the voltage division by configuring the resistance ratio of the second resistor and the third resistor to obtain the first voltage ratio of N states, and configures the voltage division by configuring the resistance ratio of the first resistor and the third resistor The second voltage ratios of N states can be obtained. Moreover, since the application is configured according to the ratio of the resistor voltage division, the accuracy of the state value can be improved.
  • the voltage acquisition unit in this application may include a voltage supply circuit and a voltage acquisition circuit.
  • the voltage supply circuit is used to provide the second reference voltage to the first configuration pin and the second configuration pin in time division, so as to provide the second reference voltage to the configuration resistor load through the first configuration pin or the second configuration pin .
  • the voltage acquisition circuit is used to respectively collect the voltage of the first configuration pin and the voltage of the second configuration pin when the voltage supply circuit provides the second reference voltage to the first configuration pin; When the second reference voltage is provided, the voltage of the first configuration pin and the voltage of the second configuration pin are respectively collected.
  • a first capacitor can also be added to the configuration resistor load, and the first capacitor is set in parallel with the third resistor;
  • the configured resistor load provides the second reference voltage, detect the charging time or discharging time of the first capacitor;
  • the state machine unit is specifically configured to according to the first voltage ratio, the second voltage ratio and The detected charging time or discharging time of the first capacitor determines a corresponding pin configuration state.
  • M kinds of states can be obtained, so that the charging time or discharging time of the first capacitor, the first voltage ratio and the second voltage ratio are combined to determine the corresponding pin configuration state, which can realize Configuration of N ⁇ N ⁇ M states.
  • a first capacitor and a second capacitor can also be added to the configuration resistor load, wherein the first capacitor is set in parallel with the first resistor, and the second capacitor is connected to the first capacitor Two resistors are set in parallel; the comparator is also used to respectively detect the charging time or discharging time of the first capacitor and the second The charging time or discharging time of the capacitor; the state machine unit is specifically used to detect the charging time or discharging time of the first capacitor according to the first voltage ratio, the second voltage ratio and the time detection unit The charging time or discharging time of the second capacitor determines the corresponding pin configuration state.
  • M states By configuring the capacitance value of the first capacitor, M states can be obtained, and by configuring the capacitance value of the second capacitor, M states can be obtained. Therefore, the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, the first voltage ratio and the second voltage ratio are combined to determine the corresponding pin configuration state, and N ⁇ N ⁇ M ⁇ Configuration of M states.
  • configuration pins may be added to the chip, that is, the chip has three configuration pins, namely the first configuration pin, the second configuration pin and the third configuration pin.
  • the configuration resistor load may also include a configurable fourth resistor and a configurable fifth resistor; the first terminal of the fourth resistor is used to connect to the first reference voltage, and the second terminal of the fourth resistor For connecting with the third configuration pin, the fifth resistor is connected between the second terminal of the fourth resistor and the second terminal of the second resistor; the voltage acquisition unit is also used for When the second reference voltage is provided to the configuration resistor load through the second configuration pin, the voltage of the third configuration pin is collected; the voltage ratio unit also needs to pass calculating a third voltage ratio between the voltage of the second configuration pin and the voltage of the third configuration pin collected when the second configuration pin provides a second reference voltage to the configuration resistor load;
  • the state machine unit is specifically configured to determine a corresponding pin configuration state according to the first voltage ratio, the second voltage ratio, and the third voltage ratio. Therefore, the first voltage ratio,
  • the configuration resistor load when the second reference voltage is provided to the configuration resistor load through the first configuration pin, the voltage of the first configuration pin and the voltage of the second configuration pin are respectively collected; When the configuration resistor load provides the second reference voltage, the voltage of the first configuration pin, the voltage of the second configuration pin and the voltage of the third configuration pin are respectively collected.
  • a first capacitance and a second capacitance can also be added to the configuration resistor load, wherein the first capacitance and the third resistance are set in parallel, and the The second capacitor is set in parallel with the fifth resistor; the comparator is also used to respectively detect the charging of the first capacitor when the voltage acquisition unit provides the second reference voltage to the configuration resistor load time or discharge time and the charging time or discharging time of the second capacitor; the state machine unit is specifically used for according to the first voltage ratio, the second voltage ratio, the third voltage ratio, the first The charging time or discharging time of a capacitor and the charging time or discharging time of the second capacitor determine the corresponding pin configuration state.
  • the capacitance value of the first capacitor By configuring the capacitance value of the first capacitor, M states can be obtained, and by configuring the capacitance value of the second capacitor, M states can be obtained. Therefore, the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, the first voltage ratio, the second voltage ratio and the third voltage ratio are combined to determine the corresponding pin configuration state, and N ⁇ N ⁇ N ⁇ M ⁇ M configurations of states.
  • the embodiment of the present application also provides another pin state configuration circuit, including: a configuration resistor load, a voltage acquisition unit and a comparator.
  • the configuration resistor load is used to connect the first configuration pin, the second configuration pin and the third configuration pin of the chip.
  • the configurable resistor load may include a configurable first resistor, a configurable second resistor, a configurable third resistor, a configurable fourth resistor, and a configurable fifth resistor; the first resistor The first terminal of the second resistor is connected to the first reference voltage such as ground, the second terminal of the first resistor is connected to the first configuration pin; the first terminal of the second resistor is connected to the first reference voltage such as ground, and the second terminal of the second resistor The two terminals are connected to the second configuration pin, the third resistor is connected between the second terminal of the first resistor and the second terminal of the second resistor; the first terminal of the fourth resistor is used to connect the first The reference voltage, the second terminal of the fourth resistor is used to connect with the third configuration pin, and the fifth resistor is connected between the second terminal of the fourth resistor and the second terminal of the second resistor.
  • the voltage acquisition unit can provide a second reference voltage to the configuration resistor load through the first configuration pin, the second configuration pin or the third configuration pin, and collect the voltage of the first configuration pin, the voltage of the second configuration pin, and the voltage of the second configuration pin respectively. pin voltage and the voltage of the third configuration pin.
  • the resistance value of the third resistor is configured to be equal to the resistance value of the fifth resistor.
  • the second reference voltage When the second reference voltage is provided to the configuration resistor load through the second configuration pin, the voltage of the first configuration pin, The voltage of the second configuration pin and the voltage of the third configuration pin; when the second reference voltage is provided to the configuration resistor load through the first configuration pin and the third configuration pin at the same time, respectively collect the voltage of the first configuration pin voltage, the voltage of the second configuration pin, and the voltage of the third configuration pin.
  • the voltage ratio unit may be configured to collect the voltage of the first configuration pin, the The voltage of the second configuration pin and the voltage of the third configuration pin calculate the first voltage ratio and the third voltage ratio; according to the voltage acquisition unit through the third configuration pin and the first configuration When the pins provide the second reference voltage to the configuration resistor load at the same time, the collected voltage of the first configuration pin, the voltage of the second configuration pin and the voltage of the third configuration pin are used to calculate the second Two voltage ratios.
  • the first voltage ratio may be calculated according to the collected voltage of the first configuration pin and the voltage of the second configuration pin when the second reference voltage is provided to the configuration resistor load through the second configuration pin, according to the first
  • a third voltage ratio is calculated from the voltage of the third configuration pin and the voltage of the second configuration pin.
  • the first voltage ratio may be equal to the ratio of the voltage of the first configuration pin to the voltage of the second configuration pin collected when the second reference voltage is provided to the configuration resistor load through the second configuration pin.
  • the third voltage ratio may be equal to a ratio of a voltage of the third configuration pin to a voltage of the second configuration pin acquired when the second reference voltage is provided to the configuration resistor load through the second configuration pin.
  • the voltage of the pin and the voltage of the second configuration pin calculate a second voltage ratio.
  • the second voltage ratio may be equal to the voltage of the second configuration pin and the voltage of the first configuration pin collected when the second reference voltage is provided to the configuration resistor load through the first configuration pin and the third configuration pin simultaneously. Or the ratio of the voltages of the three configuration pins.
  • the state machine unit can be used to determine the corresponding pin configuration state according to the first voltage ratio, the second voltage ratio and the third voltage ratio. Therefore, the first voltage ratio, the second voltage ratio and the third voltage ratio are combined to determine the corresponding pin configuration state, and configurations of N ⁇ N ⁇ N states can be realized.
  • a first capacitor and a second capacitor can also be added to the configured resistor load, wherein the first capacitor is set in parallel with the third resistor, and the second capacitor is set in parallel with the fifth resistor ;
  • a time detection unit also needs to be set, and the time detection unit detects the voltage of the first capacitor when the voltage acquisition unit provides the second reference voltage to the configuration resistor load.
  • the charging time or discharging time and the charging time or discharging time of the second capacitor; the state machine unit is specifically used for according to the first voltage ratio, the second voltage ratio, the third voltage ratio, the The charging time or discharging time of the first capacitor and the charging time or discharging time of the second capacitor determine the corresponding pin configuration state.
  • the capacitance value of the first capacitor By configuring the capacitance value of the first capacitor, M states can be obtained, and by configuring the capacitance value of the second capacitor, M states can be obtained. Therefore, the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, the first voltage ratio, the second voltage ratio and the third voltage ratio are combined to determine the corresponding pin configuration state, and N ⁇ N ⁇ N ⁇ M ⁇ M configurations of states.
  • the embodiment of the present application also provides an electronic device, including a chip and the state configuration circuit of the pin state as described in the first aspect or various implementation manners of the first aspect, or the state configuration circuit as described in the second aspect or the second aspect
  • the state configuration circuit of the pin state is used for connecting the configuration pins of the chip. Since the problem-solving principle of the electronic device is similar to the one-state configuration circuit mentioned above, the implementation of the electronic device can refer to the implementation of the above-mentioned state configuration circuit, and the repetition will not be repeated.
  • the embodiment of the present application also provides a pin state configuration method, including the following steps: firstly connect the configuration resistor load to the first configuration pin and the second configuration pin of the chip; The first configuration pin or the second configuration pin provides a second reference voltage to the configuration resistor load, and collects the voltage of the first configuration pin and the voltage of the second configuration pin, respectively; and calculating a first voltage based on a voltage of the first configuration pin and a voltage of the second configuration pin acquired when the second reference voltage is provided to the configuration resistor load through the first configuration pin ratio, and calculated from the voltage of the first configuration pin and the voltage of the second configuration pin acquired when the second reference voltage is provided to the configuration resistor load through the second configuration pin The second voltage ratio; finally, determine the corresponding pin configuration state according to the first voltage ratio and the second voltage ratio.
  • the configuration resistor load may include a configurable first resistor, a configurable second resistor, and a third resistor; the first terminal of the first resistor is connected to a first reference voltage, and the first resistor The second terminal of the second resistor is connected to the first configuration pin; the first terminal of the second resistor is connected to the first reference voltage, the second terminal of the second resistor is connected to the second configuration pin, and the third The resistor is connected between the second terminal of the first resistor and the second terminal of the second resistor.
  • a second reference voltage is provided to the configuration resistor load through the first configuration pin or the second configuration pin, and the voltage of the first configuration pin and the voltage of the second configuration pin are respectively collected.
  • Configuring the voltage of the pin may include: providing a second reference voltage to the first configuration pin and the second configuration pin in time division, so as to pass the first configuration pin or the second configuration pin providing the second reference voltage to the configuration resistor load; collecting the voltage of the first configuration pin and the second configuration pin respectively when the second reference voltage is provided to the first configuration pin When the second reference voltage is provided to the second configuration pin, respectively collect the voltage of the first configuration pin and the voltage of the second configuration pin.
  • the configuration resistor load further includes a first capacitor connected in parallel with the third resistor;
  • the configuration method may specifically include: first connecting the configuration resistor load to the first capacitor of the chip A configuration pin and a second configuration pin. Then, the second reference voltage can be provided to the configuration resistor load through the first configuration pin or the second configuration pin, and the charging time or discharging time of the first capacitor can be detected, and the voltage of the first configuration pin and the second voltage can be collected respectively. Configure the voltage of the pin.
  • the corresponding pin configuration status can be determined according to the charging time or discharging time of the first capacitor, the first voltage ratio and the second voltage ratio. Since M states can be obtained by configuring the capacitance value passing through the first capacitor, the charging time or discharging time of the first capacitor, the first voltage ratio and the second voltage ratio are combined to determine the corresponding pin configuration state, which can be Realize the configuration of N ⁇ N ⁇ M states.
  • the configuration resistor load further includes a first capacitor connected in parallel with the first resistor, and a second capacitor connected in parallel with the second resistor;
  • the configuration method may specifically be It includes: first, the configuration resistor load can be connected to the first configuration pin and the second configuration pin of the chip. Then the second reference voltage can be provided to configure the resistor load through the first configuration pin or the second configuration pin, respectively detect the charging time or discharging time of the first capacitor and the charging time or discharging time of the second capacitor, and collect the The voltage of the first configuration pin and the voltage of the second configuration pin.
  • the corresponding pin configuration state is determined according to the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, the first voltage ratio and the second voltage ratio. Because by configuring the capacitance value of the first capacitor, M kinds of states can be obtained, and by configuring the capacitance value of the second capacitor, M kinds of states can be obtained. Therefore, the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, the first voltage ratio and the second voltage ratio are combined to determine the corresponding pin configuration state, which can realize N ⁇ N ⁇ M ⁇ Configuration of M states.
  • the chip further has a third configuration pin;
  • the configuration resistor load may further include a configurable fourth resistor and a configurable fifth resistor; the fourth The first terminal of the resistor is used to connect to the first reference voltage, the second terminal of the fourth resistor is used to connect to the third configuration pin, and the fifth resistor is connected to the second terminal of the fourth resistor and the second terminal of the second resistor.
  • the configuration method may specifically include: firstly connecting a configuration resistor load to the first configuration pin, the second configuration pin and the third configuration pin of the chip. Then provide the second reference voltage to the configuration resistor load through the first configuration pin or the second configuration pin, and collect the voltage of the first configuration pin, the voltage of the second configuration pin and the voltage of the third configuration pin respectively .
  • a first voltage ratio is then calculated based on the voltage at the first configuration pin and the voltage at the second configuration pin that are captured when the second reference voltage is supplied to the configuration resistor load through the first configuration pin, based on the voltage at the second configuration pin
  • the voltage of the first configuration pin and the voltage of the second configuration pin collected when the pin provides the second reference voltage to the configuration resistor load calculates the second voltage ratio; according to providing the first configuration resistor load through the second configuration pin
  • a third voltage ratio is calculated from the voltage of the second configuration pin and the voltage of the third configuration pin collected when the second reference voltage is used.
  • the corresponding pin configuration state is determined according to the first voltage ratio, the second voltage ratio and the third voltage ratio. Therefore, the first voltage ratio, the second voltage ratio and the third voltage ratio are combined to determine the corresponding pin configuration state, and configurations of N ⁇ N ⁇ N states can be realized.
  • the first voltage ratio may be equal to the ratio of the voltage of the second configuration pin to the voltage of the first configuration pin collected when the second reference voltage is provided to the configuration resistor load through the first configuration pin.
  • the second voltage ratio may be equal to a ratio of a voltage of the first configuration pin to a voltage of the second configuration pin acquired when the second reference voltage is provided to the configuration resistor load through the second configuration pin.
  • the third voltage ratio may be equal to a ratio of a voltage of the second configuration pin to a voltage of the third configuration pin acquired when the second reference voltage is provided to the configuration resistor load through the second configuration pin.
  • the first voltage ratio may also be based on the voltage of the second configuration pin and the voltage of the third configuration pin respectively collected when the second reference voltage is provided to the configuration resistor load through the third configuration pin calculate.
  • the first voltage ratio may be equal to the ratio of the voltage of the second configuration pin to the voltage of the third configuration pin.
  • the configuration resistor load may also include a first capacitor connected in parallel with the third resistor, and a second capacitor connected in parallel with the fifth resistor; the configuration method may also include: adding to the configuration resistor When the load of the device provides the second reference voltage, the charging time or discharging time of the first capacitor and the charging time or discharging time of the second capacitor are respectively detected.
  • the determining the corresponding pin configuration state according to the first voltage ratio, the second voltage ratio, and the third voltage ratio may specifically include: according to the first voltage ratio, the second voltage ratio, the The third voltage ratio, the charging time or discharging time of the first capacitor and the charging time or discharging time of the second capacitor determine the corresponding pin configuration state.
  • the capacitance value of the first capacitor By configuring the capacitance value of the first capacitor, M states can be obtained, and by configuring the capacitance value of the second capacitor, M states can be obtained. Therefore, the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, the first voltage ratio and the second voltage ratio are combined to determine the corresponding pin configuration state, and N ⁇ N ⁇ N ⁇ Configuration of M ⁇ M states.
  • the embodiment of the present application also provides a pin state configuration method
  • the configuration method may specifically include: first, the configuration resistor load may be connected to the first configuration pin and the second configuration pin of the chip and a third configuration pin. Then the second reference voltage can be provided to the configuration resistor load through the first configuration pin, the second configuration pin or the third configuration pin, and the voltage of the first configuration pin, the voltage of the second configuration pin and the voltage of the second configuration pin can be collected respectively. The voltage of the third configuration pin.
  • the corresponding pin configuration state can be determined according to the first voltage ratio, the second voltage ratio and the third voltage ratio.
  • combining the first voltage ratio, the second voltage ratio and the third voltage ratio, N ⁇ N ⁇ N states can be configured, that is, the application can determine N according to the first voltage ratio, the second voltage ratio and the third voltage ratio ⁇ N ⁇ N pin configuration states, so that N ⁇ N ⁇ N mode states can be configured for the chip.
  • the configuration circuit in this application is not working, the configuration resistor load is not working, so there is no power loss.
  • the configurable resistor load may include a configurable first resistor, a configurable second resistor, a configurable third resistor, a configurable fourth resistor, and a configurable fifth resistor; the first resistor of the first resistor The terminal is connected to a first reference voltage such as ground, and the second terminal of the first resistor is connected to the first configuration pin; the first terminal of the second resistor is connected to the first reference voltage such as ground, and the second terminal of the second resistor is connected to the first reference voltage such as ground.
  • the second terminal is connected to the second configuration pin
  • the third resistor is connected between the second terminal of the first resistor and the second terminal of the second resistor
  • the first terminal of the fourth resistor is used for The first reference voltage
  • the second terminal of the fourth resistor is used to connect with the third configuration pin
  • the fifth resistor is connected between the second terminal of the fourth resistor and the second terminal of the second resistor.
  • the resistance value of the third resistor is configured to be equal to the resistance value of the fifth resistor.
  • the second reference voltage is provided to the configuration resistor load through the second configuration pin, the voltage of the first configuration pin, The voltage of the second configuration pin and the voltage of the third configuration pin; when the second reference voltage is provided to the configuration resistor load through the first configuration pin and the third configuration pin at the same time, respectively collect the voltage of the first configuration pin voltage, the voltage of the second configuration pin, and the voltage of the third configuration pin.
  • the first voltage ratio may be calculated according to the collected voltage of the first configuration pin and the voltage of the second configuration pin when the second reference voltage is provided to the configuration resistor load through the second configuration pin, according to the first
  • a third voltage ratio is calculated from the voltage of the third configuration pin and the voltage of the second configuration pin.
  • the first voltage ratio may be equal to the ratio of the voltage of the first configuration pin to the voltage of the second configuration pin collected when the second reference voltage is provided to the configuration resistor load through the second configuration pin.
  • the third voltage ratio may be equal to a ratio of a voltage of the third configuration pin to a voltage of the second configuration pin acquired when the second reference voltage is provided to the configuration resistor load through the second configuration pin.
  • the voltage of the pin and the voltage of the second configuration pin calculate a second voltage ratio.
  • the second voltage ratio may be equal to the voltage of the second configuration pin and the voltage of the first configuration pin collected when the second reference voltage is provided to the configuration resistor load through the first configuration pin and the third configuration pin simultaneously. Or the ratio of the voltages of the three configuration pins.
  • the configuration method may specifically include: firstly connecting the configuration resistor load to the first configuration pin, the second configuration pin and the third configuration pin of the chip. Then the second reference voltage can be provided to configure the resistor load through the first configuration pin, the second configuration pin or the third configuration pin, respectively to detect the charging time or discharging time of the first capacitor and the charging time or discharge time, and respectively collect the voltage of the first configuration pin, the voltage of the second configuration pin and the voltage of the third configuration pin.
  • the first voltage ratio and the second voltage ratio are then calculated based on the voltage of the first configuration pin, the voltages of the second configuration pin and the voltages of the third configuration pin collected when the second reference voltage is provided to the configuration resistor load through the second configuration pin.
  • a ratio of three voltages based on the voltage of the first configuration pin, the voltage of the second configuration pin and the third The voltage of the configuration pin is used to calculate the second voltage ratio.
  • the corresponding pin configuration status can be determined according to the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, the first voltage ratio, the second voltage ratio and the third voltage ratio.
  • the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, the first voltage ratio, the second voltage ratio and the third voltage ratio are combined to determine the corresponding pin configuration state, and N ⁇ N ⁇ N ⁇ M ⁇ M configurations of states.
  • FIG. 1 is a schematic structural diagram of a pin state configuration circuit in a related art
  • FIG. 2 is a schematic diagram of the working principle of pin state configuration in another related technology
  • FIG. 3 is a schematic structural diagram of a configuration resistor load provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a pin state configuration method provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a pin state configuration circuit provided in an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another pin state configuration circuit provided by an embodiment of the present application.
  • FIG. 7 is a timing diagram of the voltage output by the voltage acquisition circuit in the embodiment of the present application.
  • Fig. 8a to Fig. 8d are working diagrams of the voltage acquisition unit in the embodiment of the present application.
  • FIG. 9 is a schematic flowchart of determining the corresponding pin configuration state according to the first voltage ratio and the second voltage ratio in the present application.
  • FIG. 10 is a schematic structural diagram of another pin state configuration circuit provided by the embodiment of the present application.
  • FIG. 11 is a schematic flowchart of a pin state configuration method provided in Embodiment 2 of the present application.
  • FIG. 12 is a schematic diagram of the time detection unit detecting the charging time or discharging time of the first capacitor in Embodiment 2 of the present application;
  • FIG. 13 is a schematic structural diagram of another pin state configuration circuit provided by the embodiment of the present application.
  • FIG. 14 is a schematic flowchart of a pin state configuration method provided in Embodiment 3 of the present application.
  • FIG. 15 is a schematic diagram of the time detection unit detecting the charging time or discharging time of the first capacitor and the charging time or discharging time of the second capacitor in Embodiment 3 of the present application;
  • FIG. 16 is a schematic structural diagram of another pin state configuration circuit provided by the embodiment of the present application.
  • FIG. 17 is a schematic flowchart of a pin state configuration method provided in Embodiment 4 of the present application.
  • FIG. 18 is a schematic structural diagram of another pin state configuration circuit provided by the embodiment of the present application.
  • FIG. 19 is a schematic flowchart of a pin state configuration method provided in Embodiment 5 of the present application.
  • FIG. 20 is a schematic structural diagram of another configuration resistor load provided by the embodiment of the present application.
  • FIG. 21 is a schematic structural diagram of another pin state configuration circuit provided by the embodiment of the present application.
  • FIG. 22 is a schematic flowchart of a pin state configuration method provided in Embodiment 6 of the present application.
  • FIG. 23 is a schematic structural diagram of another pin state configuration circuit provided by the embodiment of the present application.
  • FIG. 24 is a schematic flowchart of a pin state configuration method provided in Embodiment 7 of the present application.
  • the chip can be in different working states by configuring the state of the pins of the chip, thereby realizing different functions or performances.
  • the pin state configuration circuit and configuration method provided in the present application can be applied to mode configuration for various chips of electronic equipment.
  • some electronic devices need to configure internal settings (such as address or operation mode) when the device is started, and the configuration signal for defining internal settings can be provided to the electronic device by configuring the pin state of the chip in the electronic device to fulfill.
  • the electronic device may be a smart phone, a smart TV, a smart TV set-top box, a personal computer (personal computer, PC) and other devices.
  • the configuration circuits proposed in the embodiments of the present application are intended to be applied in these and any other suitable types of electronic devices including but not limited to.
  • FIG. 3 is a schematic structural diagram of a configuration resistor load provided by an embodiment of the present application.
  • the configuration resistor load 01 is used to connect the configuration pins of the chip 1, for example, the configuration resistor load 01 in Figure 3 is connected to the first configuration pin MOD1 and the second configuration pin MOD2 of the chip 1.
  • the configuration resistor load 01 can adopt a ⁇ -type resistor topology, that is, the configuration resistor load 01 includes a configurable first resistor R1, a configurable second resistor R2, and a configurable third resistor R3; the first resistor The first terminal of R1 is connected to a first reference voltage such as ground, the second terminal of the first resistor R1 is connected to the first configuration pin MOD1; the first terminal of the second resistor R2 is connected to the first reference voltage such as ground , the second terminal of the second resistor R2 is connected to the second configuration pin MOD2, and the third resistor R3 is connected to the second terminal of the first resistor R1 and the second terminal of the second resistor R2 between.
  • the voltage vmod1 of the first configuration pin MOD1 can be made to be the same as that of the second resistor R3. 2.
  • the voltage ratio of vmod1/vmod2 of the voltage vmod2 of the configuration pin MOD2 is different, so by configuring R1/R3 and R2/R3, different vmod1/vmod2 can be obtained, so that different pin configurations can be obtained according to different vmod1/vmod2 state.
  • the resistance ratio R1/R3 of the first resistor R1 and the third resistor R3 can be configured by configuring the resistance of the first resistor R1 or by configuring the resistance of the third resistor R3.
  • the resistance ratio R2/R3 of the second resistor R2 and the third resistor R3 can be configured by configuring the resistance value of the second resistor R2.
  • the third resistor R3 is a configurable resistor, it can also be configured by configuring the third resistor The resistance value of R3 is configured.
  • FIG. 4 is a schematic flowchart of a pin state configuration method provided by an embodiment of the present application. As shown in Figure 4, the configuration method may include the following steps:
  • S102 Provide the second reference voltage to the configuration resistor load through the first configuration pin or the second configuration pin, and respectively collect the voltage of the first configuration pin and the voltage of the second configuration pin.
  • the voltage vmod1 of the first configuration pin MOD1 and the voltage vmod2 of the second configuration pin MOD2 are respectively collected.
  • the vmod1 obtained by dividing the voltage can be configured in various states.
  • the second reference voltage may be provided to the first configuration pin and the second configuration pin in time division, so as to provide the second reference voltage to the configuration resistor load through the first configuration pin or the second configuration pin.
  • This application does not limit the smoothness of providing the second reference voltage to the first configuration pin or the second configuration pin.
  • the second reference voltage may be provided to the first configuration pin first, and then to the second configuration pin. The second reference voltage; or provide the second reference voltage to the second configuration pin first, and then provide the second reference voltage to the first configuration pin, as long as it is guaranteed not to provide the first configuration pin and the second configuration pin at the same time The second reference voltage is enough.
  • the second reference voltage when the second reference voltage is provided to the first configuration pin, the voltage of the first configuration pin and the voltage of the second configuration pin are respectively collected.
  • the second reference voltage is provided to the second configuration pin, the voltage of the first configuration pin and the voltage of the second configuration pin are respectively collected.
  • N ⁇ N states can be configured, that is, the application can determine N ⁇ N pin configuration states according to the first voltage ratio and the second voltage ratio, so that Configure N ⁇ N mode states for the chip.
  • step S101 can be omitted, that is, in the circuit where the connection between the pin and the configuration resistor load has been established, step S102 can be directly performed to solve the same technical problem and achieve the same technical effect.
  • the above configuration method may be implemented by using a configuration circuit as shown in FIG. 5 .
  • the configuration circuit provided in the embodiment of the present application includes: a configuration resistor load 01 , a voltage acquisition unit 02 and a comparator 03 .
  • the comparator 03 may include a voltage ratio calculation unit 031 and a state machine unit 0032 . in:
  • the resistor load 01 which may include a configurable first resistor R1, a configurable second resistor R2, and a third resistor R3; the first terminal of the first resistor R1 is connected to the first reference voltage, and the first resistor The second terminal of R1 is connected to the first configuration pin MOD1; the first terminal of the second resistor R2 is connected to the first reference voltage, the second terminal of the second resistor R2 is connected to the second configuration pin MOD2, and the third resistor R3 is connected to the first Between the second terminal of the first resistor R1 and the second terminal of the second resistor R2.
  • the voltage acquisition unit 02 is used to provide the second reference voltage Vcc to the configuration resistor load 01 through the first configuration pin MOD1 or the second configuration pin MOD2, and collect the voltage vmod1 of the first configuration pin MOD1 and the second configuration pin MOD1 respectively.
  • the voltage ratio calculation unit 031 is used to collect the voltage vmod1 of the first configuration pin MOD1 and the second configuration pin according to the voltage acquisition unit 02 when the second reference voltage Vcc is provided to the configuration resistor load 01 through the first configuration pin MOD1.
  • the voltage vmod2 of MOD2 calculates the first voltage ratio, and the voltage vmod1 and the first configuration pin MOD1 collected by the voltage acquisition unit 02 when the second reference voltage Vcc is provided to the configuration resistor load 01 through the second configuration pin MOD2 Second, configure the voltage vmod2 of the pin MOD2 to calculate the second voltage ratio.
  • the state machine unit 04 is configured to determine a corresponding pin configuration state according to the first voltage ratio and the second voltage ratio.
  • the voltage acquisition unit 02 and the comparator 03 can be set in the chip 1, and the configuration resistor load 01 can be set independently of the chip 1.
  • the The configuration resistor load 01 is connected to the configuration pin of chip 1 .
  • the voltage acquisition unit 02 in this application may include a voltage supply circuit 021 and a voltage acquisition circuit 022 .
  • the voltage supply circuit 021 is used to provide the second reference voltage Vcc to the first configuration pin MOD1 and the second configuration pin MOD2 in time division, so as to provide the configuration resistor with the first configuration pin MOD1 or the second configuration pin MOD2
  • the load 01 provides a second reference voltage Vcc.
  • the voltage collection circuit 022 is used to respectively collect the voltage vmod1 of the first configuration pin MOD1 and the voltage vmod2 of the second configuration pin MOD2 when the voltage supply circuit 021 provides the second reference voltage Vcc to the first configuration pin MOD1; When the supply circuit 021 supplies the second reference voltage Vcc to the second configuration pin MOD2, the voltage vmod1 of the first configuration pin MOD1 and the voltage vmod2 of the second configuration pin MOD2 are respectively collected.
  • the voltage supply circuit 021 can first provide the second reference voltage Vcc to the first configuration pin MOD1, and then provide the second reference voltage Vcc to the second configuration pin MOD2; or first provide the second reference voltage Vcc to the second configuration pin MOD2 The second reference voltage Vcc is provided, and then the second reference voltage Vcc is provided to the first configuration pin MOD1, which is not limited herein.
  • the voltage supply circuit 021 may include a first data strobe D1 and a switch K1.
  • the switch K1 When the mode state of the chip needs to be configured, the switch K1 is turned on, and the first data strobe The device D1 selects to provide the second reference voltage Vcc to the first configuration pin MOD1 or the second configuration pin MOD2.
  • the switch K1 When the configuration of the mode state of the chip is completed, the switch K1 is turned off, and the configuration resistor load 01 does not work, and there is no power loss.
  • the voltage acquisition circuit 022 may include a second data strobe D2, and the second data strobe D2 may convert the voltage vmod1 of the first configuration pin MOD1 or the voltage vmod1 of the second configuration pin MOD2 to The voltage vmod2 is supplied to the voltage ratio calculation unit 031 .
  • the voltage supply circuit 021 firstly providing the second reference voltage Vcc to the first configuration pin MOD1 and then providing the second reference voltage Vcc to the second configuration pin MOD2 as an example, the working process of the voltage acquisition unit 02 is described below.
  • the timing diagram of the voltage vmod output by the voltage acquisition circuit 022 in the voltage acquisition unit 02 is shown in FIG. 7 .
  • the solid line indicates voltage transmission
  • the dotted line indicates no voltage transmission
  • the initial value of i is equal to 0, and ref_ratio1_1 ⁇ ref_ratio1_N increases sequentially.
  • Embodiment 1 of the present application realizes the configuration of N*N states by using the ⁇ -type resistor topology structure for configuring resistor loads through two configuration pins.
  • the precision of the state value is improved according to the ratio of the resistor voltage divider; secondly, more configurable states can be realized through two configuration pins; finally, when the configuration circuit in this application is not working, the configuration Resistor loads are inactive, so there is no power loss.
  • the configuration resistor load 01 may also include a first capacitor C1 connected in parallel with the third resistor R3; the comparator 03 may also include a time detection unit 033, and the time detection unit 033 is used in the voltage acquisition unit 02
  • the second reference voltage Vcc is provided to the configuration resistor load 01
  • the charging time or discharging time of the first capacitor C1 is detected;
  • the state machine unit 032 is specifically used for the first voltage ratio, the second voltage ratio, and the first voltage detected by the time detection unit 033.
  • a charging time or discharging time of the capacitor C1 determines a corresponding pin configuration state.
  • the configuration method corresponding to the configuration circuit shown in FIG. 10 is shown in FIG. 11, and may include the following steps:
  • S202 Provide the second reference voltage to the configuration resistor load through the first configuration pin or the second configuration pin, detect the charging time or discharging time of the first capacitor, and collect the voltage of the first configuration pin and the second configuration respectively pin voltage.
  • the voltage vmod1 of the first configuration pin MOD1 is detected, or when the second reference voltage Vcc is provided to the second configuration pin MOD2, the first configuration pin MOD2 is detected. Both the voltage vmod2 of the configuration pin MOD2 can be detected to obtain the charging time t1 or the discharging time t1' of the first capacitor C1.
  • the time detection unit 033 can be connected to the first configuration pin MOD1, and can also be connected to the second configuration pin MOD2.
  • FIG. 10 illustrates an example in which the time detection unit 033 is connected to the second configuration pin MOD2.
  • the time constant ⁇ [R2R3/(R2+R3)]*C1 of the first capacitor C1
  • the time constant ⁇ of the first capacitor C1 [R1R3/(R1+R3)]*C1.
  • Embodiment 2 of the present application can refer to Embodiment 1.
  • Embodiment 2 of the present application adds a first capacitor and a time detection unit, and the charging time or discharging time of the first capacitor, the first voltage The ratio and the second voltage ratio are combined to determine the corresponding pin configuration state, and configurations of N ⁇ N ⁇ M states can be realized.
  • the values of N and M may be the same or different, which are not limited here.
  • the configuration resistor load 01 may also include a first capacitor C1 connected in parallel with the first resistor R1, and a second capacitor C2 connected in parallel with the second resistor R2;
  • the comparator 03 may also include a time detection unit 033 , the time detection unit 033 is used to respectively detect the charging time or discharging time of the first capacitor C1 and the charging time or discharging time of the second capacitor C2 when the voltage acquisition unit 02 provides the second reference voltage Vcc to the configuration resistor load 01;
  • the state machine unit 032 is specifically used to determine the corresponding pin according to the first voltage ratio, the second voltage ratio, and the charging time or discharging time of the first capacitor C1 and the charging time or discharging time of the second capacitor C2 detected by the time detection unit 033 configuration status.
  • the configuration method corresponding to the configuration circuit shown in FIG. 13 is shown in FIG. 14, and may include the following steps:
  • S302. Provide the second reference voltage to the configuration resistor load through the first configuration pin or the second configuration pin, respectively detect the charging time or discharging time of the first capacitor and the charging time or discharging time of the second capacitor, and respectively collect The voltage of the first configuration pin and the voltage of the second configuration pin.
  • detecting the voltage vmod2 of the second configuration pin MOD2 can detect the charging time t2 or discharging time t2' of the second capacitor C2;
  • the configuration pin MOD2 provides the second reference voltage Vcc
  • the voltage vmod1 of the first configuration pin MOD1 can be detected to obtain the charging time t1 or discharging time t1' of the first capacitor C1.
  • the time detection unit 033 is respectively connected to the first configuration pin MOD1 and the second configuration pin MOD2.
  • the second reference voltage Vcc is provided to the first configuration pin MOD1
  • S304 Determine a corresponding pin configuration state according to the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, the first voltage ratio, and the second voltage ratio.
  • the third embodiment of the present application can refer to the first embodiment.
  • the third embodiment of the present application adds the first capacitor, the second capacitor and the time detection unit, and the charging time or discharging time of the first capacitor , the charging time or discharging time of the second capacitor, the first voltage ratio and the second voltage ratio are combined to determine the corresponding pin configuration state, and configurations of N ⁇ N ⁇ M ⁇ M states can be realized.
  • the values of N and M may be the same or different, which are not limited here.
  • the configuration resistor load 01 is also used to connect the third configuration pin MOD3 of the chip; the configuration resistor load 01 may also include a configurable fourth resistor R4 and a configurable fifth resistor R5;
  • the first terminal of the fourth resistor R4 is used to connect to the first reference voltage, such as ground, the second terminal of the fourth resistor R4 is used to connect to the third configuration pin MOD3, and the fifth resistor R5 is connected to the first terminal of the fourth resistor R4.
  • the voltage acquisition unit 02 is also used to collect the third configuration pin MOD3 when the second reference voltage Vcc is provided to the configuration resistor load 01 through the second configuration pin MOD2
  • the voltage vmod3 of the voltage ratio calculation unit 031 is also used to collect the voltage vmod2 and
  • the voltage vmod3 of the third configuration pin MOD3 is used to calculate the third voltage ratio;
  • the state machine unit 032 is specifically configured to determine the corresponding pin configuration state according to the first voltage ratio, the second voltage ratio and the third voltage ratio.
  • the configuration method corresponding to the configuration circuit shown in FIG. 16 is shown in FIG. 17, and may include the following steps:
  • S402. Provide the second reference voltage to the configuration resistor load through the first configuration pin or the second configuration pin, and respectively collect the voltage of the first configuration pin, the voltage of the second configuration pin, and the voltage of the third configuration pin Voltage.
  • the voltage vmod1 of the first configuration pin [R1/(R1+R3)]Vcc
  • the voltage of the third configuration pin vmod3 [R4/(R4+R5)]Vcc.
  • the first voltage ratio may also be based on the voltage of the second configuration pin and the voltage of the third configuration pin respectively collected when the second reference voltage is provided to the configuration resistor load through the third configuration pin calculate.
  • the voltage vmod3 of the third configuration pin Vcc
  • Embodiment 4 of the present application For the specific implementation of Embodiment 4 of the present application, reference may be made to Embodiment 1. Compared with Embodiment 1, Embodiment 4 of the present application adds a fourth resistor and a fifth resistor to the configuration resistor load, and adds a configuration pin. Combining the first voltage ratio, the second voltage ratio and the third voltage value to determine the corresponding pin configuration state can realize the configuration of N ⁇ N ⁇ N states.
  • the configuration resistor load 01 may also include a first capacitor C1 connected in parallel with the third resistor R3, and a second capacitor C2 connected in parallel with the fifth resistor R5;
  • the comparator 03 may also include a time detection unit 033 , the time detection unit 033 is used to respectively detect the charging time or discharging time of the first capacitor C1 and the charging time or discharging time of the second capacitor C2 when the voltage acquisition unit 02 provides the second reference voltage Vcc to the configuration resistor load 01;
  • the state machine unit 032 is specifically used to determine the corresponding pin according to the first voltage ratio, the second voltage ratio, and the charging time or discharging time of the first capacitor C1 and the charging time or discharging time of the second capacitor C2 detected by the time detection unit 033 configuration status.
  • the configuration method corresponding to the configuration circuit shown in FIG. 18 is shown in FIG. 19, and may include the following steps:
  • S502 Provide the second reference voltage to the configuration resistor load through the first configuration pin or the second configuration pin, respectively detect the charging time or discharging time of the first capacitor and the charging time or discharging time of the second capacitor, and respectively collect The voltage of the first configuration pin, the voltage of the second configuration pin and the voltage of the third configuration pin.
  • the configuration resistor load when the second reference voltage is provided to the configuration resistor load through the first configuration pin, the voltage of the first configuration pin and the voltage of the second configuration pin are respectively collected; When the configuration resistor load provides the second reference voltage, the voltage of the first configuration pin, the voltage of the second configuration pin and the voltage of the third configuration pin are respectively collected.
  • the time detection unit 033 is respectively connected to the first configuration pin MOD1 and the third configuration pin MOD3, by configuring the capacitance value of the first capacitor C1, M states can be obtained, and by configuring the capacitance value of the second capacitor C2 , and M states can be obtained.
  • Embodiment 5 of the present application adds a first capacitor, a second capacitor, and a time detection unit.
  • the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, and the first voltage ratio , the second voltage ratio and the third voltage ratio are combined to determine the corresponding pin configuration state, and configurations of N ⁇ N ⁇ N ⁇ M ⁇ M states can be realized.
  • the values of N and M may be the same or different, which are not limited here.
  • FIG. 21 is a schematic structural diagram of another pin state configuration circuit provided by an embodiment of the present application.
  • the configuration circuit may include a configuration resistor load 01 , a voltage acquisition unit 02 and a comparator 03 , and the comparator 03 may include a voltage ratio calculation unit 031 and a state machine unit 032 .
  • the voltage acquisition unit 02 is used to provide the second reference voltage Vcc to the configuration resistor load 01 through the second configuration pin MOD2, and respectively collect the voltage vmod1, the voltage of the first configuration pin MOD1, and the The voltage vmod2 of the second configuration pin MOD2 and the voltage vmod3 of the third configuration pin MOD3; simultaneously load 01 to the configuration resistor through the first configuration pin MOD1 and the third configuration pin MOD3
  • the second reference voltage Vcc is provided, and the voltage vmod1 of the first configuration pin MOD1, the voltage vmod2 of the second configuration pin MOD2, and the voltage vmod3 of the third configuration pin MOD3 are respectively collected.
  • the voltage ratio calculation unit 031 is configured to collect the first configuration tube according to the voltage acquisition unit 02 when the second configuration pin MOD2 is used to provide the second reference voltage Vcc to the configuration resistor load 01.
  • the voltage vmod1 of the pin MOD1, the voltage vmod2 of the second configuration pin MOD2 and the voltage vmod3 of the third configuration pin MOD3 calculate the first voltage ratio and the third voltage ratio; according to the voltage acquisition unit 02 through the When the third configuration pin MOD3 and the first configuration pin MOD1 provide the second reference voltage Vcc to the configuration resistor load 01 at the same time, the collected voltage vmod1 of the first configuration pin MOD1, the first configuration pin MOD1 The voltage vmod2 of the second configuration pin MOD2 and the voltage vmod3 of the third configuration pin MOD3 calculate a second voltage ratio.
  • the state machine unit 032 is configured to determine a corresponding pin configuration state according to the first voltage ratio, the second voltage ratio and the third voltage ratio.
  • the configuration resistor load 01 may include a configurable first resistor R1, a configurable second resistor R2, a configurable third resistor R3, a configurable third resistor Four resistors R4 and a configurable fifth resistor R5;
  • the first terminal of the first resistor R1 is connected to a first reference voltage such as ground, and the second terminal of the first resistor R1 is connected to the first configuration pin MOD1;
  • the first terminal of the second resistor R2 is connected to a first reference voltage such as ground, the second terminal of the second resistor R2 is connected to the second configuration pin MOD2, and the third resistor R3 is connected to the first resistor
  • the first terminal of the fourth resistor R4 is used for connecting the first reference voltage
  • the second terminal of the fourth resistor R4 is used for connecting with the third configuration tube
  • the pin MOD3 is connected, and the fifth resistor R5 is connected between the second terminal of the
  • the voltage acquisition unit 02 in this application may include a voltage supply circuit 021 and a voltage acquisition circuit 022 .
  • the voltage supply circuit 021 may include a first data strobe D1 and a switch K3, wherein the first data strobe D1 may include 3 switches K0-K2, when the mode state of the chip needs to be configured, the switch K3 leads is turned on, the first data gate D1 selects to provide the second reference voltage Vcc to the first configuration pin MOD1 , the second configuration pin MOD2 or the third configuration pin MOD3 .
  • the switch K3 is turned off, and the configuration resistor load 01 does not work, and there is no power loss.
  • the voltage acquisition circuit 022 may include a second data strobe D2, and the second data strobe D2 may convert the voltage vmod1 of the first configuration pin MOD1, the voltage vmod2 of the second configuration pin MOD2 or the voltage of the third configuration pin MOD3
  • the voltage vmod2 is supplied to the voltage ratio calculation unit 031 .
  • the configuration method corresponding to the configuration circuit shown in FIG. 21 is shown in FIG. 22, and may include the following steps:
  • S602. Provide the second reference voltage to the configuration resistor load through the first configuration pin, the second configuration pin or the third configuration pin, and respectively collect the voltage of the first configuration pin, the voltage of the second configuration pin, and The voltage of the third configuration pin.
  • the structure shown in FIG. 20 may be adopted for configuring the resistor load.
  • the second reference voltage is provided to the configuration resistor load through the second configuration pin, the first configuration is collected respectively.
  • the first voltage ratio may be calculated according to the collected voltage of the first configuration pin and the voltage of the second configuration pin when the second reference voltage is provided to the configuration resistor load through the second configuration pin, according to the first A third voltage ratio is calculated from the voltage of the third configuration pin and the voltage of the second configuration pin.
  • the second voltage ratio may be equal to the voltage of the second configuration pin and the voltage of the first configuration pin collected when the second reference voltage is provided to the configuration resistor load through the first configuration pin and the third configuration pin simultaneously.
  • the first voltage ratio, the second voltage ratio and the third voltage value are combined to determine the corresponding pin configuration state, and configurations of N ⁇ N ⁇ N states can also be realized.
  • Embodiment 6 Compared with Embodiment 4, although the structure of configuring the resistor load is the same, the method for the voltage acquisition unit to provide the second reference voltage to the configuration resistor load is different, causing the voltage ratio calculation unit to calculate the first voltage ratio and the second voltage ratio. The voltage ratio and the method of the third voltage ratio are also different.
  • the sixth embodiment has easier selection of resistors and a wider design range, so the configuration design is simpler.
  • the configuration resistor load 01 may further include a first capacitor C1 connected in parallel with the third resistor R3, and a second capacitor C2 connected in parallel with the fifth resistor R5;
  • the comparator 03 may also include a time detection unit 033 , the time detection unit 033 is used to respectively detect the charging time or discharging time of the first capacitor C1 and the charging time or discharging time of the second capacitor C2 when the voltage acquisition unit 02 provides the second reference voltage Vcc to the configuration resistor load 01;
  • the state machine unit 032 is specifically used to determine the corresponding pin according to the first voltage ratio, the second voltage ratio, and the charging time or discharging time of the first capacitor C1 and the charging time or discharging time of the second capacitor C2 detected by the time detection unit 033 configuration status.
  • the configuration method corresponding to the configuration circuit shown in FIG. 23 is shown in FIG. 24, and may include the following steps:
  • S702. Provide the second reference voltage to the configuration resistor load through the first configuration pin, the second configuration pin or the third configuration pin, and respectively detect the charging time or discharging time of the first capacitor and the charging time or the charging time of the second capacitor discharge time, and respectively collect the voltage of the first configuration pin, the voltage of the second configuration pin and the voltage of the third configuration pin.
  • the second reference voltage when the second reference voltage is provided to the configuration resistor load through the second configuration pin, the voltage of the first configuration pin, the voltage of the second configuration pin and the voltage of the third configuration pin are respectively collected;
  • the second reference voltage is simultaneously provided to the configuration resistor load through the first configuration pin and the third configuration pin, the voltage of the first configuration pin, the voltage of the second configuration pin and the voltage of the third configuration pin are respectively collected.
  • the time detection unit 033 is respectively connected to the first configuration pin MOD1 and the third configuration pin MOD3, by configuring the capacitance value of the first capacitor C1, M states can be obtained, and by configuring the capacitance value of the second capacitor C2 , and M states can be obtained.
  • the voltages of the second configuration pin and the third configuration pin calculate the first voltage ratio and The third voltage ratio, based on the voltage of the first configuration pin, the voltage of the second configuration pin and the The voltage of the three configuration pins is used to calculate the second voltage ratio.
  • Embodiment 7 of the present application adds a first capacitor, a second capacitor, and a time detection unit.
  • the charging time or discharging time of the first capacitor, the charging time or discharging time of the second capacitor, and the first voltage ratio , the second voltage ratio and the third voltage ratio are combined to determine the corresponding pin configuration state, and configurations of N ⁇ N ⁇ N ⁇ M ⁇ M states can be realized.
  • the values of N and M may be the same or different, which are not limited here.
  • the present application can further increase the number of configurable states of the chip by increasing the number of configuration pins in the chip.
  • the configuration resistor load can be formed by multiple ⁇ -type resistor topologies shown in Figure 3, for example, when the number of configuration pins is 4, the configuration resistor load can be formed by 2 ⁇
  • the configuration resistor load can be formed by three ⁇ -type resistor topologies, and so on when the number of configuration pins increases.
  • the configuration resistor load can add one or more ⁇ -type resistor topologies on the basis of Embodiment 4 or Embodiment 6.
  • the configuration resistor load On the basis of configuring the resistor load in Embodiment 4, a ⁇ -type resistor topology can be added to form it.
  • the configuring resistor load can be increased on the basis of configuring the resistor load in Embodiment 4.
  • 2 ⁇ -type resistor topology forms, when the number of configuration pins increases, and so on.
  • the configurable states can be increased by N times.
  • the present application can also increase the number of configurable states by increasing the capacitance in the configuration resistor load.
  • the capacitance please refer to Embodiment 2, Embodiment 3, Embodiment 5 and Embodiment 7, which will not be repeated here. .
  • this application can improve the precision of state values by performing state configuration according to the ratio of resistor voltage division; secondly, through two or more configuration pins, more configurable states can be realized; finally, this The applied configuration resistor load is inactive after configuration, so there is no power loss.
  • the embodiment of the present application also provides an electronic device, including a chip and a state configuration circuit for any one of the above-mentioned pin states provided in the embodiment of the present application, and the configuration circuit is used to connect the configuration pins of the chip. Since the problem-solving principle of the electronic device is similar to the one-state configuration circuit mentioned above, the implementation of the electronic device can refer to the implementation of the above-mentioned state configuration circuit, and the repetition will not be repeated.
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions
  • the device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

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Abstract

本申请提供了一种管脚状态的配置电路、配置方法及电子设备。其中,配置电路包括配置电阻器负载、电压采集单元和比较器;电压采集单元通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压,并分别采集第一配置管脚和第二配置管脚的电压;比较器根据在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第二电压比值,根据第一电压比值和第二电压比值确定对应的管脚配置状态。本申请通过对两个配置管脚进行配置可以得到N×N种管脚配置状态。

Description

一种管脚状态的配置电路、配置方法及电子设备
相关申请的交叉引用
本申请要求在2021年05月21日提交中国专利局、申请号为202110558493.0、申请名称为“一种管脚状态的配置电路、配置方法及电子设备”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域,尤其涉及一种管脚状态的配置电路、配置方法及电子设备。
背景技术
在集成电路(Integrated Circuit IC)芯片的设计中,管脚(PIN)是用来传输芯片的输入、输出信号,包含数据信号、时钟信号以及电源信号等。为了在同一颗芯片上能够实现更多的功能,提高芯片的性价比,芯片在制造时大都提供了管脚状态的配置功能。根据管脚状态的不同配置,芯片可以处于不同的工作状态,从而可以实现不同的功能或性能。管脚状态的配置一般有两种方式;第一种方式是给管脚配置不同的电压,不同电压表示不同的管脚状态;第二种方式是通过外部处理器来修改芯片内部的寄存器单元的内容,实现对管脚状态的配置。
参见图1,图1为一种相关技术中管脚状态的配置电路的结构示意图。如图1所示,该配置电路是基于电阻分压策略实现模式配置,利用电阻R01和R02分压配置VCC与GND之间的模式配置管脚MOD的电压。在IC模式检测阶段,读取并锁存启动时刻模式配置管脚MOD上的电压值,再根据读取的电压值确定对应的模式状态,因此配置不同的R01和R02可配置不同的模式。但是在该技术中需要两个管脚才能配置一组状态,且在IC模式配置完成后,电阻R01和R02会持续存在功率损耗,尤其是需要采用多个管脚进行配置时,会带来较大损耗。
参见图2,图2为另一种相关技术中进行管脚状态配置的工作原理示意图。如图2所示,电阻R01是芯片外部连接电阻,电阻R02是芯片内部的可变电阻,在配置过程中,通过改变R2的电阻值,将电阻R01的电阻值与电阻R02的电阻值的进行比较,从而确定对应的模式,因此配置不同的R01可配置不同的模式。在该技术中,模式配置是基于单个管脚MOD实现一组配置状态,但是由于内外电阻特性差异,因此比较精度较低,导致可配置的状态数量减少。
发明内容
本申请提供一种管脚状态的配置电路、配置方法及电子设备,用于提高可配置的状态数量。
第一方面,本申请实施例提供的一种管脚状态的配置电路,包括:配置电阻器负载、电压采集单元和比较器。其中,所述配置电阻器负载用于连接芯片的第一配置管脚和第二配置管脚;所述电压采集单元可以通过所述第一配置管脚或所述第二配置管脚向所述配置 电阻器负载提供第二参考电压,并分别采集所述第一配置管脚的电压和所述第二配置管脚的电压;所述比较器可以根据所述电压采集单元在通过所述第一配置管脚向所述配置电阻器负载提供第二参考电压时采集的所述第一配置管脚的电压和所述第二配置管脚的电压计算第一电压比值,根据所述电压采集单元在通过所述第二配置管脚向所述配置电阻器负载提供第二参考电压时采集的所述第一配置管脚的电压和所述第二配置管脚的电压计算第二电压比值,以及根据所述第一电压比值和所述第二电压比值确定对应的管脚配置状态。
本申请提供的配置电路通过配置配置电阻器负载中的电阻可以得到N种状态的第一电压比值,N种状态的第二电压比值。从而将第一电压比值和第二电压比值进行结合,可以配置N×N种状态,即本申请根据第一电压比值和第二电压比值可以确定N×N种管脚配置状态,从而可以对芯片配置N×N种模式状态。另外,本申请中的配置电路不工作时,配置电阻器负载是不工作的,因此无功率损耗。
在具体实施时,配置电阻器负载可以包括可配置的第一电阻、可配置的第二电阻和可配置的第三电阻;第一电阻的第一端子连接第一参考电压,第一电阻的第二端子连接第一配置管脚;第二电阻的第一端子连接第一参考电压,第二电阻的第二端子连接第二配置管脚,第三电阻连接于第一电阻的第二端子和第二电阻的第二端子之间。电压采集单元可以通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压,当通过第一配置管脚向配置电阻器负载提供第二参考电压Vcc时,分别采集第一配置管脚的电压vmod1和第二配置管脚的电压vmod2,此时,第一配置管脚的电压vmod1=Vcc,第二配置管脚的电压vmod2=[R2/(R2+R3)]Vcc;当通过第二配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压vmod1和第二配置管脚的电压vmod2,此时,第二配置管脚的电压vmod2=Vcc,第一配置管脚的电压vmod1=[R1/(R1+R3)]Vcc。比较器可以包括电压比值计算单元和状态机单元,其中,电压比值单元可以根据电压采集单元在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压来计算第一电压比值,以及根据电压采集单元在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压来计算第二电压比值;从而状态机单元可以根据第一电压比值和第二电压比值确定对应的管脚配置状态。
由此,本申请通过配置第二电阻和第三电阻的阻值比例来配置分压可以得到N种状态的第一电压比值,通过配置第一电阻和第三电阻的阻值比例来配置分压可以得到N种状态的第二电压比值。并且,由于本申请是根据电阻分压的比值进行配置因此可以提高状态值的精度。
示例性的,本申请中的电压采集单元可以包括电压提供电路和电压采集电路。其中,电压提供电路用于分时向第一配置管脚和第二配置管脚提供第二参考电压,以通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压。电压采集电路用于在电压提供电路向第一配置管脚提供第二参考电压时,分别采集第一配置管脚的电压和第二配置管脚的电压;在电压提供电路向第二配置管脚提供第二参考电压时,分别采集第一配置管脚的电压和第二配置管脚的电压。
一种实施例中,还可以在所述配置电阻器负载中增加第一电容,所述第一电容与所述第三电阻并联设置;所述比较器还用于在所述电压采集单元向所述配置电阻器负载提供所述第二参考电压时,检测所述第一电容的充电时间或放电时间;所述状态机单元具体用于 根据所述第一电压比值、所述第二电压比值以及检测的所述第一电容的充电时间或放电时间确定对应的管脚配置状态。通过配置通过第一电容的电容值,可以得到M种状态,从而将第一电容的充电时间或放电时间、第一电压比值以及第二电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×M种状态的配置。
另一种实施例中,还可以在所述配置电阻器负载中增加第一电容和第二电容,其中所述第一电容与所述第一电阻并联设置,所述第二电容与所述第二电阻并联设置;所述比较器还用于在所述电压采集单元向所述配置电阻器负载提供第二参考电压时,分别检测所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间;所述状态机单元具体用于根据所述第一电压比值、所述第二电压比值以及所述时间检测单元检测的所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间确定对应的管脚配置状态。通过配置第一电容的电容值,可以得到M种状态,通过配置第二电容的电容值,又可以得到M种状态。从而将第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值以及第二电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×M×M种状态的配置。
又一种实施例中,可以在芯片中增加配置管脚,即芯片中具有3个配置管脚,分别为第一配置管脚、第二配置管脚和第三配置管脚。所述配置电阻器负载中还可以包括可配置的第四电阻和可配置的第五电阻;所述第四电阻的第一端子用于连接第一参考电压,所述第四电阻的第二端子用于与所述第三配置管脚连接,所述第五电阻连接于所述第四电阻的第二端子和所述第二电阻的第二端子之间;所述电压采集单元还用于在通过所述第二配置管脚向所述配置电阻器负载提供所述第二参考电压时,采集所述第三配置管脚的电压;所述电压比值单元还需要根据所述电压采集单元在通过所述第二配置管脚向所述配置电阻器负载提供第二参考电压时采集的所述第二配置管脚的电压和所述第三配置管脚的电压,计算第三电压比值;所述状态机单元具体用于根据所述第一电压比值、所述第二电压比值以及所述第三电压比值确定对应的管脚配置状态。从而将第一电压比值、第二电压比值以及第三电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×N种状态的配置。
在具体实施时,在通过第一配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压和第二配置管脚的电压;在通过第二配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。
进一步地,当芯片中具有3个配置管脚时,还可以在所述配置电阻器负载中增加第一电容和第二电容,其中所述第一电容与所述第三电阻并联设置,所述第二电容与所述第五电阻并联设置;所述比较器还用于在所述电压采集单元向所述配置电阻器负载提供所述第二参考电压时,分别检测所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间;所述状态机单元具体用于根据所述第一电压比值、所述第二电压比值、所述第三电压比值、所述第一电容的充电时间或放电时间以及所述第二电容的充电时间或放电时间确定对应的管脚配置状态。通过配置第一电容的电容值,可以得到M种状态,通过配置第二电容的电容值,又可以得到M种状态。从而将第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值、第二电压比值以及第三电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×N×M×M种状态的配置。
第二方面,本申请实施例还提供了另一种管脚状态的配置电路,包括:配置电阻器负 载、电压采集单元和比较器。其中,配置电阻器负载用于连接芯片的第一配置管脚、第二配置管脚和第三配置管脚。示例性的,所述配置电阻器负载可以包括可配置的第一电阻、可配置的第二电阻、可配置的第三电阻、可配置第四电阻和可配置第五电阻;所述第一电阻的第一端子连接第一参考电压例如接地,所述第一电阻的第二端子连接第一配置管脚;第二电阻的第一端子连接第一参考电压例如接地,所述第二电阻的第二端子连接第二配置管脚,所述第三电阻连接于所述第一电阻的第二端子和所述第二电阻的第二端子之间;第四电阻的第一端子用于连接第一参考电压,第四电阻的第二端子用于与第三配置管脚连接,第五电阻连接于第四电阻的第二端子和第二电阻的第二端子之间。
所述电压采集单元可以通过第一配置管脚、第二配置管脚或第三配置管脚向配置电阻器负载提供第二参考电压,并分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。在具体实施时,例如配置第三电阻的阻值等于第五电阻的阻值,在通过第二配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压;在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。
所述电压比值单元可以用于根据所述电压采集单元在通过所述第二配置管脚向所述配置电阻器负载提供第二参考电压时,采集的所述第一配置管脚的电压、所述第二配置管脚的电压和所述第三配置管脚的电压计算第一电压比值和第三电压比值;根据所述电压采集单元在通过所述第三配置管脚和所述第一配置管脚同时向所述配置电阻器负载提供第二参考电压时,采集的所述第一配置管脚的电压、所述第二配置管脚的电压和所述第三配置管脚的电压计算第二电压比值。
示例性的,可以根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时,采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,根据第三配置管脚的电压和第二配置管脚的电压计算第三电压比值。例如,第一电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压与第二配置管脚的电压的比值。第三电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第三配置管脚的电压与第二配置管脚的电压的比值。可以根据在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时,采集的第一配置管脚的电压和第二配置管脚的电压,或者第三配置管脚的电压和第二配置管脚的电压计算第二电压比值。例如,第二电压比值可以等于在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时采集的第二配置管脚的电压与第一配置管脚的电压或三配置管脚的电压的比值。
所述状态机单元可以用于根据所述第一电压比值、所述第二电压比值以及所述第三电压比值确定对应的管脚配置状态。从而将第一电压比值、第二电压比值以及第三电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×N种状态的配置。
进一步地,还可以在所述配置电阻器负载中增加第一电容和第二电容,其中所述第一电容与所述第三电阻并联设置,所述第二电容与所述第五电阻并联设置;所述多状态配置电路中还需要设置时间检测单元,所述时间检测单元在所述电压采集单元向所述配置电阻器负载提供所述第二参考电压时,分别检测所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间;所述状态机单元具体用于根据所述第一电压比值、所述第 二电压比值、所述第三电压比值、所述第一电容的充电时间或放电时间以及所述第二电容的充电时间或放电时间确定对应的管脚配置状态。通过配置第一电容的电容值,可以得到M种状态,通过配置第二电容的电容值,又可以得到M种状态。从而将第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值、第二电压比值以及第三电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×N×M×M种状态的配置。
第三方面,本申请实施例还提供了一种电子设备,包括芯片和如第一方面或第一方面的各种实施方式所述的管脚状态的态配置电路或者如第二方面或第二方面的各种实施方式所述的管脚状态的态配置电路,所述配置电路用于连接所述芯片的配置管脚。由于该电子设备解决问题的原理与前述一种态配置电路相似,因此该电子设备的实施可以参见前述态配置电路的实施,重复之处不再赘述。
第四方面,本申请实施例还提供了一种管脚状态的配置方法,包括以下步骤:首先将配置电阻器负载连接于芯片的第一配置管脚和第二配置管脚;然后通过所述第一配置管脚或所述第二配置管脚向所述配置电阻器负载提供第二参考电压,并分别采集所述第一配置管脚的电压和所述第二配置管脚的电压;并且根据在通过所述第一配置管脚向所述配置电阻器负载提供所述第二参考电压时采集的所述第一配置管脚的电压和所述第二配置管脚的电压计算第一电压比值,以及根据在通过所述第二配置管脚向所述配置电阻器负载提供所述第二参考电压时采集的所述第一配置管脚的电压和所述第二配置管脚的电压计算第二电压比值;最后根据所述第一电压比值和所述第二电压比值确定对应的管脚配置状态。
示例性的,所述配置电阻器负载可以包括可配置的第一电阻、可配置的第二电阻和第三电阻;所述第一电阻的第一端子连接第一参考电压,所述第一电阻的第二端子连接所述第一配置管脚;所述第二电阻的第一端子连接第一参考电压,所述第二电阻的第二端子连接所述第二配置管脚,所述第三电阻连接于所述第一电阻的第二端子和所述第二电阻的第二端子之间。
示例性的,通过所述第一配置管脚或所述第二配置管脚向所述配置电阻器负载提供第二参考电压,并分别采集所述第一配置管脚的电压和所述第二配置管脚的电压,可以包括:分时向所述第一配置管脚和所述第二配置管脚提供第二参考电压,以通过所述第一配置管脚或所述第二配置管脚向所述配置电阻器负载提供所述第二参考电压;在向所述第一配置管脚提供第二参考电压时,分别采集所述第一配置管脚的电压和所述第二配置管脚的电压;在向所述第二配置管脚提供第二参考电压时,分别采集所述第一配置管脚的电压和所述第二配置管脚的电压。
可选地,在一种实施例中,所述配置电阻器负载还包括与所述第三电阻并联的第一电容;所述配置方法具体可以包括:首先将配置电阻器负载连接于芯片的第一配置管脚和第二配置管脚。然后可以通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压,并检测第一电容的充电时间或放电时间,以及分别采集第一配置管脚的电压和第二配置管脚的电压。接着再根据在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,以及根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第二电压比值。最后可以根据第一电容的充电时间或放电时间、第一电压比值以及第二电压比值确定对应的管脚配置状态。由于通过配置通过第一电容的电容值,可以得到M种状态,因此将第一电容的充电时间或放电时间、第一电压比值以及第二电压 比值进行结合来确定对应的管脚配置状态,可以实现N×N×M种状态的配置。
可选地,在另一种实施例中,所述配置电阻器负载还包括与所述第一电阻并联的第一电容,与所述第二电阻并联的第二电容;所述配置方法具体可以包括:首先可以将配置电阻器负载连接于芯片的第一配置管脚和第二配置管脚。然后可以通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压,分别检测第一电容的充电时间或放电时间和第二电容的充电时间或放电时间,并分别采集第一配置管脚的电压和第二配置管脚的电压。接着再根据在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,以及根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第二电压比值。最后根据第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值以及第二电压比值确定对应的管脚配置状态。由于通过配置第一电容的电容值,可以得到M种状态,通过配置第二电容的电容值,又可以得到M种状态。因此将第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值以及第二电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×M×M种状态的配置。
可选地,在又一种实施例中,所述芯片还具有第三配置管脚;所述配置电阻器负载还可以包括可配置的第四电阻和可配置的第五电阻;所述第四电阻的第一端子用于连接第一参考电压,所述第四电阻的第二端子用于与所述第三配置管脚连接,所述第五电阻连接于所述第四电阻的第二端子和所述第二电阻的第二端子之间。所述配置方法具体可以包括:首先将配置电阻器负载连接于芯片的第一配置管脚、第二配置管脚和第三配置管脚。然后通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压,并分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。接着根据在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第二电压比值;根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第二配置管脚的电压和第三配置管脚的电压计算第三电压比值。最后根据第一电压比值、第二电压比值以及第三电压比值确定对应的管脚配置状态。从而将第一电压比值、第二电压比值以及第三电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×N种状态的配置。
在具体实施时,可以在通过第一配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压和第二配置管脚的电压;在通过第二配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。其中,第一电压比值可以等于在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第二配置管脚的电压与第一配置管脚的电压的比值。第二电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压与第二配置管脚的电压的比值。第三电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第二配置管脚的电压与第三配置管脚的电压的比值。
当然,在具体实施时,第一电压比值也可以根据通过第三配置管脚向配置电阻器负载提供第二参考电压时,分别采集的第二配置管脚的电压和第三配置管脚的电压计算。例如 第一电压比值可以等于第二配置管脚的电压与第三配置管脚的电压的比值。
进一步地,所述配置电阻器负载还可以包括与所述第三电阻并联的第一电容,与所述第五电阻并联的第二电容;所述配置方法还可以包括:在向所述配置电阻器负载提供所述第二参考电压时,分别检测所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间。所述根据所述第一电压比值、所述第二电压比值以及第三电压比值确定对应的管脚配置状态,具体可以包括:根据所述第一电压比值、所述第二电压比值、所述第三电压比值、所述第一电容的充电时间或放电时间以及所述第二电容的充电时间或放电时间确定对应的管脚配置状态。通过配置第一电容的电容值,可以得到M种状态,通过配置第二电容的电容值,又可以得到M种状态。从而将第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值以及第二电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×N×M×M种状态的配置。
第五方面,本申请实施例还提供了一种管脚状态的配置方法,所述配置方法具体可以包括:首先可将配置电阻器负载连接于芯片的第一配置管脚、第二配置管脚和第三配置管脚。然后可以通过第一配置管脚、第二配置管脚或第三配置管脚向配置电阻器负载提供第二参考电压,并分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。接着再根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压,第二配置管脚的电压和第三配置管脚的电压计算第一电压比值和第三电压比值,根据在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压计算第二电压比值。最后可以根据第一电压比值、第二电压比值以及第三电压比值确定对应的管脚配置状态。从而将第一电压比值、第二电压比值和第三电压比值进行结合,可以配置N×N×N种状态,即本申请根据第一电压比值、第二电压比值和第三电压比值可以确定N×N×N种管脚配置状态,从而可以对芯片配置N×N×N种模式状态。另外,本申请中的配置电路不工作时,配置电阻器负载是不工作的,因此无功率损耗。
示例性的,配置电阻器负载可以包括可配置的第一电阻、可配置的第二电阻、可配置第三电阻、可配置第四电阻和可配置第五电阻;所述第一电阻的第一端子连接第一参考电压例如接地,所述第一电阻的第二端子连接所述第一配置管脚;所述第二电阻的第一端子连接第一参考电压例如接地,所述第二电阻的第二端子连接所述第二配置管脚,所述第三电阻连接于所述第一电阻的第二端子和所述第二电阻的第二端子之间;第四电阻的第一端子用于连接第一参考电压,第四电阻的第二端子用于与第三配置管脚连接,第五电阻连接于第四电阻的第二端子和第二电阻的第二端子之间。
在具体实施时,例如配置第三电阻的阻值等于第五电阻的阻值,在通过第二配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压;在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。
示例性的,可以根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时,采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,根据第三配置管脚的电压和第二配置管脚的电压计算第三电压比值。例如,第一电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压与第二配置 管脚的电压的比值。第三电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第三配置管脚的电压与第二配置管脚的电压的比值。可以根据在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时,采集的第一配置管脚的电压和第二配置管脚的电压,或者第三配置管脚的电压和第二配置管脚的电压计算第二电压比值。例如,第二电压比值可以等于在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时采集的第二配置管脚的电压与第一配置管脚的电压或三配置管脚的电压的比值。
进一步地,当所述配置电阻器负载包括第一电阻至第五电阻五个电阻时,所述配置电阻器负载还包括与所述第三电阻并联的第一电容,与所述第五电阻并联的第二电容;所述配置方法具体可以包括:首先将配置电阻器负载连接于芯片的第一配置管脚、第二配置管脚和第三配置管脚。然后可以通过第一配置管脚、第二配置管脚或第三配置管脚向配置电阻器负载提供第二参考电压,分别检测第一电容的充电时间或放电时间和第二电容的充电时间或放电时间,并分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。接着根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压,第二配置管脚和第三配置管脚的电压计算第一电压比值和第三电压比值,根据在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压计算第二电压比值。最后可以根据第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值、第二电压比值以及第三电压比值确定对应的管脚配置状态。由于通过配置第一电容的电容值,可以得到M种状态,通过配置第二电容的电容值,又可以得到M种状态。从而将第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值、第二电压比值以及第三电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×N×M×M种状态的配置。
附图说明
图1为一种相关技术中管脚状态配置电路的结构示意图;
图2为另一种相关技术中进行管脚状态配置的工作原理示意图;
图3为本申请实施例提供的一种配置电阻器负载的结构示意图;
图4为本申请实施例提供的一种管脚状态的配置方法的流程示意图;
图5为本申请实施例提供的一种管脚状态的配置电路的结构示意图;
图6为本申请实施例提供的另一种管脚状态的配置电路的结构示意图;
图7为本申请实施例中电压采集电路输出的电压的时序图;
图8a至图8d为本申请实施例中电压采集单元的工作示意图;
图9为本申请的根据第一电压比值和第二电压比值确定对应的管脚配置状态的流程示意图;
图10为本申请实施例提供的又一种管脚状态的配置电路的结构示意图;
图11为本申请实施例二提供的管脚状态的配置方法的流程示意图;
图12为本申请实施例二中时间检测单元检测第一电容的充电时间或放电时间的示意图;
图13为本申请实施例提供的又一种管脚状态的配置电路的结构示意图;
图14为本申请实施例三提供的管脚状态的配置方法的流程示意图;
图15为本申请实施例三中时间检测单元检测第一电容的充电时间或放电时间以及第二电容的充电时间或放电时间的示意图;
图16为本申请实施例提供的又一种管脚状态的配置电路的结构示意图;
图17为本申请实施例四提供的管脚状态的配置方法的流程示意图;
图18为本申请实施例提供的又一种管脚状态的配置电路的结构示意图;
图19为本申请实施例五提供的管脚状态的配置方法的流程示意图;
图20为本申请实施例提供的另一种配置电阻器负载的结构示意图;
图21为本申请实施例提供的又一种管脚状态的配置电路的结构示意图;
图22为本申请实施例六提供的管脚状态的配置方法的流程示意图;
图23为本申请实施例提供的又一种管脚状态的配置电路的结构示意图;
图24为本申请实施例七提供的管脚状态的配置方法的流程示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚,下面将结合附图对本申请作进一步地详细描述。然而,示例实施方式能够以多种形式实施,且不应被理解为限于在此阐述的实施方式;相反,提供这些实施方式使得本申请更全面和完整,并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构,因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词,均是以附图为例进行的说明,但根据需要也可以做出改变,所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
需要说明的是,在以下描述中阐述了具体细节以便于充分理解本申请。但是本申请能够以多种不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本申请内涵的情况下做类似推广。因此本申请不受下面公开的具体实施方式的限制。说明书后续描述为实施本申请的较佳实施方式,然所述描述乃以说明本申请的一般原则为目的,并非用以限定本申请的范围。本申请的保护范围当视所附权利要求所界定者为准。
为了方便理解本申请实施例提供的一种管脚状态的配置电路及配置方法,下面首先介绍一下其应用场景。
为了使芯片能够实现较多的功能,可以通过对芯片的管脚状态进行配置,使芯片处于不同的工作状态,从而实现不同的功能或性能。本申请提供的一种管脚状态的配置电路及配置方法可以应用于为电子设备的各种芯片进行模式配置。例如,一些电子设备需要在设备启动时配置内部设置(例如地址或操作模式),可以通过对该电子设备中芯片的管脚状态进行配置,将用于定义内部设置的配置信号提供给该电子设备来实现。示例性的,该电子设备可以为智能手机、智能电视、智能电视机顶盒、个人电脑(personal computer,PC)等设备。应注意的是,本申请实施例提出的配置电路旨在包括但不限于应用在这些和任意其它适合类型的电子设备中。
为了使本申请的目的、技术方案和优点更加清楚,下面将结合附图对本申请作进一步地详细描述。
参见图3,图3为本申请实施例提供的一种配置电阻器负载的结构示意图。如图3所示,该配置电阻器负载01用于连接芯片1的配置管脚,例如图3中配置电阻器负载01连 接芯片1的第一配置管脚MOD1和第二配置管脚MOD2。该配置电阻器负载01可以采用π型电阻拓扑结构,即配置电阻器负载01包括可配置的第一电阻R1、可配置的第二电阻R2和可配置的第三电阻R3;所述第一电阻R1的第一端子连接第一参考电压例如接地,所述第一电阻R1的第二端子连接所述第一配置管脚MOD1;所述第二电阻R2的第一端子连接第一参考电压例如接地,所述第二电阻R2的第二端子连接所述第二配置管脚MOD2,所述第三电阻R3连接于所述第一电阻R1的第二端子和所述第二电阻R2的第二端子之间。当第一电阻R1与第三电阻R3的阻值比例R1/R3和第二电阻R2与第三电阻R3的阻值比例R2/R3不同时,可以使第一配置管脚MOD1的电压vmod1与第二配置管脚MOD2的电压vmod2的电压值比例vmod1/vmod2不同,从而通过配置R1/R3和R2/R3,可以得到不同的vmod1/vmod2,从而可以根据不同的vmod1/vmod2得到不同的管脚配置状态。下面结合具体实施例进行详细介绍。
在本申请中,第一电阻R1与第三电阻R3的阻值比例R1/R3可以通过配置第一电阻R1的阻值进行配置,也可以通过配置第三电阻R3的阻值进行配置。同理,第二电阻R2与第三电阻R3的阻值比例R2/R3可以通过配置第二电阻R2的阻值进行配置,当第三电阻R3为可配置电阻时,也可以通过配置第三电阻R3的阻值进行配置。
实施例一
参见图4,图4为本申请实施例提供的一种管脚状态的配置方法的流程示意图。如图4所示,该配置方法可以包括以下步骤:
S101、将配置电阻器负载连接于芯片的第一配置管脚和第二配置管脚。
S102、通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压,并分别采集第一配置管脚的电压和第二配置管脚的电压。
结合图3,当通过第一配置管脚MOD1向配置电阻器负载01提供第二参考电压Vcc时,分别采集第一配置管脚MOD1的电压vmod1和第二配置管脚MOD2的电压vmod2,此时,第一配置管脚MOD1的电压vmod1=Vcc,第二配置管脚MOD2的电压vmod2=[R2/(R2+R3)]Vcc,由此,通过配置第二电阻R2和第三电阻R3的阻值比例来配置分压而得到的vmod2可以配置多种状态。当通过第二配置管脚MOD2向配置电阻器负载01提供第二参考电压Vcc时,分别采集第一配置管脚MOD1的电压vmod1和第二配置管脚MOD2的电压vmod2,此时,第二配置管脚MOD2的电压vmod2=Vcc,第一配置管脚MOD1的电压vmod1=[R1/(R1+R3)]Vcc,由此,通过配置第一电阻R1和第三电阻R3的阻值比例来配置分压而得到的vmod1可以配置多种状态。
在具体实施时,可以分时向第一配置管脚和第二配置管脚提供第二参考电压,以通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压。本申请对向第一配置管脚或第二配置管脚提供第二参考电压的顺利不作限定,例如,可以先向第一配置管脚提供第二参考电压,之后再向第二配置管脚提供第二参考电压;或者先向第二配置管脚提供第二参考电压,之后再向第一配置管脚提供第二参考电压,只要保证不同时向第一配置管脚和第二配置管脚提供第二参考电压即可。
进一步地,当向第一配置管脚提供第二参考电压时,分别采集第一配置管脚的电压和第二配置管脚的电压。当向第二配置管脚提供第二参考电压时,分别采集第一配置管脚的电压和第二配置管脚的电压。
S103、根据在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第一配 置管脚的电压和第二配置管脚的电压计算第一电压比值,以及根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第二电压比值。
其中,第一电压比值可以等于在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第二配置管脚的电压与第一配置管脚的电压的比值,即第一电压比值mod_ratio1=vmod2/vmod1=R2/(R2+R3)。第二电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压与第二配置管脚的电压的比值,即第二电压比值mod_ratio2=vmod1/vmod2=R1/(R1+R3)。
S104、根据第一电压比值和第二电压比值确定对应的管脚配置状态。
其中,第一电压比值mod_ratio1=R2/(R2+R3),例如通过配置第二电阻R2和第三电阻R3的阻值比例可以配置N种状态,那么根据第一电压比值同样可以配置N种状态。同理,第二电压比值mod_ratio2=R1/(R1+R3),例如通过配置第一电阻R1和第三电阻R3的阻值比例可以配置N种状态,那么根据第二电压比值同样可以配置N种状态。综上,将第一电压比值和第二电压比值进行结合,可以配置N×N种状态,即本申请根据第一电压比值和第二电压比值可以确定N×N种管脚配置状态,从而可以对芯片配置N×N种模式状态。
可选的,上述步骤S101可以省略,即在已经建立管脚与配置电阻器负载之间的连接的电路中,可以直接进行步骤S102,进而解决相同的技术问题,达到相同的技术效果。
在具体实施时,上述配置方法可以采用如图5所示配置电路实现。参见图5,在本申请实施例提供的配置电路中,包括:配置电阻器负载01、电压采集单元02和比较器03。其中比较器03可以包括电压比值计算单元031和状态机单元0032。其中:
配置电阻器负载01可以参见图3,可以包括可配置的第一电阻R1、可配置的第二电阻R2和第三电阻R3;第一电阻R1的第一端子连接第一参考电压,第一电阻R1的第二端子连接第一配置管脚MOD1;第二电阻R2的第一端子连接第一参考电压,第二电阻R2的第二端子连接第二配置管脚MOD2,第三电阻R3连接于第一电阻R1的第二端子和第二电阻R2的第二端子之间。
电压采集单元02用于通过第一配置管脚MOD1或第二配置管脚MOD2向配置电阻器负载01提供第二参考电压Vcc,并分别采集第一配置管脚MOD1的电压vmod1和第二配置管脚MOD2的电压vmod2。
电压比值计算单元031用于根据电压采集单元02在通过第一配置管脚MOD1向配置电阻器负载01提供第二参考电压Vcc时采集的第一配置管脚MOD1的电压vmod1和第二配置管脚MOD2的电压vmod2计算第一电压比值,以及根据电压采集单元02在通过第二配置管脚MOD2向配置电阻器负载01提供第二参考电压Vcc时采集的第一配置管脚MOD1的电压vmod1和第二配置管脚MOD2的电压vmod2计算第二电压比值。
状态机单元04用于根据第一电压比值和第二电压比值确定对应的管脚配置状态。
在实际应用时,如图6所示,电压采集单元02和比较器03可以设置在芯片1中,配置电阻器负载01可以独立于芯片1设置,当需要对芯片的模式状态进行配置时,将配置电阻器负载01连接于芯片1的配置管脚上。
示例性的,如图6所示,本申请中的电压采集单元02可以包括电压提供电路021和电压采集电路022。其中,电压提供电路021用于分时向第一配置管脚MOD1和第二配置 管脚MOD2提供第二参考电压Vcc,以通过第一配置管脚MOD1或第二配置管脚MOD2向配置电阻器负载01提供第二参考电压Vcc。电压采集电路022用于在电压提供电路021向第一配置管脚MOD1提供第二参考电压Vcc时,分别采集第一配置管脚MOD1的电压vmod1和第二配置管脚MOD2的电压vmod2;在电压提供电路021向第二配置管脚MOD2提供第二参考电压Vcc时,分别采集第一配置管脚MOD1的电压vmod1和第二配置管脚MOD2的电压vmod2。
在具体实施时,电压提供电路021可以先向第一配置管脚MOD1提供第二参考电压Vcc,之后再向第二配置管脚MOD2提供第二参考电压Vcc;或者先向第二配置管脚MOD2提供第二参考电压Vcc,之后再向第一配置管脚MOD1提供第二参考电压Vcc,在此不作限定。
示例性的,如图6所示,电压提供电路021可以包括一个第一数据选通器D1和一个开关K1,当需要对芯片的模式状态进行配置时,开关K1导通,第一数据选通器D1选择向第一配置管脚MOD1或第二配置管脚MOD2提供第二参考电压Vcc。当对芯片的模式状态完成配置后,开关K1截止,配置电阻器负载01不工作,无功率损耗。
示例性的,如图6所示,电压采集电路022可以包括一第二数据选通器D2,第二数据选通器D2可以将第一配置管脚MOD1的电压vmod1或第二配置管脚MOD2的电压vmod2提供给电压比值计算单元031。
下面以电压提供电路021先向第一配置管脚MOD1提供第二参考电压Vcc,之后再向第二配置管脚MOD2提供第二参考电压Vcc为例,说明电压采集单元02的工作过程。其中,电压采集单元02中电压采集电路022输出的电压vmod的时序图如图7所示。
在第一阶段,mod_sel=100,参见图8a,mod_sel0=1,mod_sel1=0,mod_sel2=0,开关K1导通,第一数据选通器D1将第二参考电压Vcc提供给第一配置管脚MOD1,第二数据选通器D2将第一配置管脚MOD1的电压vmod1提供给电压比值计算单元031。如图7所示,此时,电压采集电路022输出的电压vmod=vmod1=Vcc。
在第二阶段,mod_sel=101,参见图8b,mod_sel0=1,mod_sel1=0,mod_sel2=1,开关K1导通,第一数据选通器D1将第二参考电压Vcc提供给第一配置管脚MOD1,第二数据选通器D2将第二配置管脚MOD2的电压vmod2提供给电压比值计算单元031。如图7所示,此时,电压采集电路022输出的电压vmod=vmod2=[R2/(R2+R3)]Vcc。
在第三阶段,mod_sel=111,参见图8c,mod_sel0=1,mod_sel1=1,mod_sel2=1,开关K1导通,第一数据选通器D1将第二参考电压Vcc提供给第二配置管脚MOD2,第二数据选通器D2将第二配置管脚MOD2的电压vmod2提供给电压比值计算单元031。如图7所示,此时,电压采集电路022输出的电压vmod=vmod2=Vcc。
在第四阶段,mod_sel=110,参见图8d,mod_sel0=1,mod_sel1=1,mod_sel2=0,开关K1导通,第一数据选通器D1将第二参考电压Vcc提供给第二配置管脚MOD2,第二数据选通器D2将第一配置管脚MOD1的电压vmod1提供给电压比值计算单元031。如图7所示,此时,电压采集电路022输出的电压vmod=vmod1=[R1/(R1+R3)]Vcc。
其中在图8a至图8d中,实线表示有电压传输,虚线表示无电压传输。
电压比值计算单元031根据第一阶段时第一配置管脚MOD1的电压vmod1和第二阶段时第二配置管脚MOD2的电压vmod2计算的第一电压比值mod_ratio1=vmod2/vmod1=R2/(R2+R3),根据第三阶段时第二配置管脚MOD2的电压vmod2和第四阶段时第一配置 管脚MOD1的电压vmod1计算的第二电压比值mod_ratio2=vmod1/vmod2=R1/(R1+R3)。然后状态机单元032可以根据第一电压比值和第二电压比值确定对应的管脚配置状态。
在一种可行的实现方式中,可以将第一电压比值mod_ratio1与第一预设比值ref_ratio1_i进行比较,确定出当前第一电压比值mod_ratio1所对应的状态,其中,ref_ratio1_i表示第i种状态给定的第一预设比值;将第二电压比值mod_ratio2与第二预设比值ref_ratio2_j进行比较,确定出当前第二电压比值mod_ratio2所对应的状态,其中,ref_ratio2_j表示第j种状态给定的第二预设比值。从而根据确定出的两种状态确定出对应的管脚配置状态。如果i=1~N,j=1~N,那么本申请通过配置N个不同的第一电压比值,以及N个不同的第二电压比值,可以确定出N×N种管脚配置状态,从而可以对芯片配置N×N种模式状态。
在具体实施时,如图9所示,例如i初始值等于0,且ref_ratio1_1~ref_ratio1_N依次增大,在根据第一电压比值mod_ratio1确定对应的状态cfg_mod1时,可以先确定mod_ratio1是否小于ref_ratio1_i,如果是,则确定i是否等于0,如果i等于0则确定此时对应的状态为短路状态,即cfg_mod1=short_state;如果i不等于0则确定对应的状态cfg_mod1=i。如果mod_ratio1不小于ref_ratio1_i,则确定i是否小于N,如果i大于或等于N,则确定对应的状态为开路状态,即cfg_mod1=open_state;如果i小于N,则使i=i+1后继续确定mod_ratio1是否小于ref_ratio1_i,直到确定出第一电压比值mod_ratio1对应的状态cfg_mod1。例如j初始值等于0,且ref_ratio2_1~ref_ratio2_N依次增大,在根据第二电压比值mod_ratio2确定对应的状态cfg_mod2时,可以先确定mod_ratio2是否小于ref_ratio2_j,如果是,则确定j是否等于0,如果j等于0则确定此时对应的状态为短路状态,即cfg_mod2=short_state;如果j不等于0则确定对应的状态cfg_mod2=j。如果mod_ratio2不小于ref_ratio2_j,则确定j是否小于N,如果j大于或等于N,则确定对应的状态为开路状态,即cfg_mod2=open_state;如果j小于N,则使j=j+1后重新开始确定mod_ratio2是否小于ref_ratio1_j,直到确定出第二电压比值mod_ratio2对应的状态cfg_mod2。最后根据确定出的两种状态cfg_mod1和cfg_mod2确定出对应的管脚配置状态。
综上所述,本申请实施例一通过两个配置管脚,利用配置电阻器负载的π型电阻拓扑结构实现了N*N种状态的配置。相对于相关技术:首先,根据电阻分压的比值提高了状态值的精度;其次,通过两个配置管脚,可以实现更多可配置状态;最后,本申请中的配置电路不工作时,配置电阻器负载是不工作的,因此无功率损耗。
实施例二
示例性的,参见图10,配置电阻器负载01还可以包括与第三电阻R3并联的第一电容C1;比较器03还可以包括时间检测单元033,时间检测单元033用于在电压采集单元02向配置电阻器负载01提供第二参考电压Vcc时,检测第一电容C1的充电时间或放电时间;状态机单元032具体用于第一电压比值、第二电压比值以及时间检测单元033检测的第一电容C1的充电时间或放电时间确定对应的管脚配置状态。
其中,图10所示的配置电路所对应的配置方法如图11所示,可以包括以下步骤:
S201、将配置电阻器负载连接于芯片的第一配置管脚和第二配置管脚。
S202、通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压,检测第一电容的充电时间或放电时间,并分别采集第一配置管脚的电压和第二配置管脚的电压。
参见图12,当向第一配置管脚MOD1提供第二参考电压Vcc时,检测第一配置管脚 MOD1的电压vmod1,或者当向第二配置管脚MOD2提供第二参考电压Vcc时,检测第二配置管脚MOD2的电压vmod2,都可以检测得到第一电容C1的充电时间t1或放电时间t1’。
在具体实施时,时间检测单元033可以连接于第一配置管脚MOD1,也可以连接于第二配置管脚MOD2,图10以时间检测单元033连接于第二配置管脚MOD2为例进行示意。当时间检测单元033连接于第一配置管脚MOD1时,第一电容C1的时间常数τ=[R2R3/(R2+R3)]*C1,当时间检测单元033连接于第二配置管脚MOD2时,第一电容C1的时间常数τ=[R1R3/(R1+R3)]*C1。通过配置第一电容C1的电容值,可以得到M种状态。
S203、根据在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,以及根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第二电压比值。
S204、根据第一电容的充电时间或放电时间、第一电压比值以及第二电压比值确定对应的管脚配置状态。
本申请实施例二的具体实施方式可以参考实施例一,本申请实施例二与实施例一相比增加了第一电容和时间检测单元,将第一电容的充电时间或放电时间、第一电压比值以及第二电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×M种状态的配置。其中,N和M的值可以相同,也可以不相同,在此不作限定。
实施例三
示例性的,参见图13,配置电阻器负载01还可以包括与第一电阻R1并联的第一电容C1,与第二电阻R2并联的第二电容C2;比较器03还可以包括时间检测单元033,时间检测单元033用于在电压采集单元02向配置电阻器负载01提供第二参考电压Vcc时,分别检测第一电容C1的充电时间或放电时间和第二电容C2的充电时间或放电时间;状态机单元032具体用于根据第一电压比值、第二电压比值以及时间检测单元033检测的第一电容C1的充电时间或放电时间和第二电容C2的充电时间或放电时间确定对应的管脚配置状态。
其中,图13所示的配置电路所对应的配置方法如图14所示,可以包括以下步骤:
S301、将配置电阻器负载连接于芯片的第一配置管脚和第二配置管脚。
S302、通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压,分别检测第一电容的充电时间或放电时间和第二电容的充电时间或放电时间,并分别采集第一配置管脚的电压和第二配置管脚的电压。
参见图15,当向第一配置管脚MOD1提供第二参考电压Vcc时,检测第二配置管脚MOD2的电压vmod2可以检测得到第二电容C2的充电时间t2或放电时间t2’;当向第二配置管脚MOD2提供第二参考电压Vcc时,检测第一配置管脚MOD1的电压vmod1,可以检测得到第一电容C1的充电时间t1或放电时间t1’。
在具体实施时,时间检测单元033分别连接第一配置管脚MOD1和第二配置管脚MOD2,当向第一配置管脚MOD1提供第二参考电压Vcc时,第二电阻R2、第三电阻R3和第二电容C2组成RC串并联电路,第二电容C2的时间常数τ=[R2R3/(R2+R3)]*C2。当向第二配置管脚MOD2提供第二参考电压Vcc时,第一电阻R1、第三电阻R3和第一电容C1组成RC串并联电路,第一电容C1的时间常数τ=[R1R3/(R1+R3)]*C1。通过配 置第一电容C1的电容值,可以得到M种状态,通过配置第二电容C2的电容值,又可以得到M种状态。
S303、根据在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,以及根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第二电压比值。
S304、根据第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值以及第二电压比值确定对应的管脚配置状态。
本申请实施例三的具体实施方式可以参考实施例一,本申请实施例三与实施例一相比增加了第一电容、第二电容和时间检测单元,将第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值以及第二电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×M×M种状态的配置。其中,N和M的值可以相同,也可以不相同,在此不作限定。
实施例四
示例性的,参见图16,配置电阻器负载01还用于连接芯片的第三配置管脚MOD3;配置电阻器负载01还可以包括可配置的第四电阻R4和可配置的第五电阻R5;第四电阻R4的第一端子用于连接第一参考电压,例如接地,第四电阻R4的第二端子用于与第三配置管脚MOD3连接,第五电阻R5连接于第四电阻R4的第二端子和第二电阻R2的第二端子之间;电压采集单元02还用于在通过第二配置管脚MOD2向配置电阻器负载01提供第二参考电压Vcc时,采集第三配置管脚MOD3的电压vmod3;电压比值计算单元031还用于根据电压采集单元02在通过第二配置管脚MOD2向配置电阻器负载01提供第二参考电压Vcc时采集的第二配置管脚MOD2的电压vmod2和第三配置管脚MOD3的电压vmod3,计算第三电压比值;状态机单元032具体用于根据第一电压比值、第二电压比值以及第三电压比值确定对应的管脚配置状态。
其中,图16所示的配置电路所对应的配置方法如图17所示,可以包括以下步骤:
S401、将配置电阻器负载连接于芯片的第一配置管脚、第二配置管脚和第三配置管脚。
S402、通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压,并分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。
在具体实施时,在通过第一配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压和第二配置管脚的电压,此时第一配置管脚的电压vmod1=Vcc,第二配置管脚的电压vmod2=[Rx/(Rx+R3)]Vcc,其中1/Rx=1/R2+1/(R4+R5);在通过第二配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压,此时第二配置管脚的电压vmod2=Vcc,第一配置管脚的电压vmod1=[R1/(R1+R3)]Vcc,第三配置管脚的电压vmod3=[R4/(R4+R5)]Vcc。
S403、根据在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第二电压比值;根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第二配置管脚的电压和第三配置管脚的电压计算第三电压比值。
其中,第一电压比值可以等于在通过第一配置管脚向配置电阻器负载提供第二参考电 压时采集的第二配置管脚的电压与第一配置管脚的电压的比值,即第一电压比值mod_ratio1=vmod2/vmod1=Rx/(Rx+R3)。第二电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压与第二配置管脚的电压的比值,即第二电压比值mod_ratio2=vmod1/vmod2=R1/(R1+R3)。第三电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第二配置管脚的电压与第三配置管脚的电压的比值,即第三电压比值mod_ratio3=vmod3/vmod2=R4/(R4+R5)。
当然,在具体实施时,第一电压比值也可以根据通过第三配置管脚向配置电阻器负载提供第二参考电压时,分别采集的第二配置管脚的电压和第三配置管脚的电压计算。例如,当通过第三配置管脚向配置电阻器负载提供第二参考电压时,此时第三配置管脚的电压vmod3=Vcc,第二配置管脚的电压vmod2=[Ry/(Ry+R5)]Vcc,其中1/Ry=1/R2+1/(R1+R3),第一电压比值可以等于第二配置管脚的电压与第三配置管脚的电压的比值,即第一电压比值mod_ratio1=vmod2/vmod3=Ry/(Ry+R5)。
S404、根据第一电压比值、第二电压比值以及第三电压比值确定对应的管脚配置状态。
本申请实施例四的具体实施方式可以参考实施例一,本申请实施例四与实施例一相比,配置电阻器负载中增加了第四电阻和第五电阻,并且增加了一个配置管脚,将第一电压比值、第二电压比值以及第三电压值进行结合来确定对应的管脚配置状态,可以实现N×N×N种状态的配置。
实施例五
示例性的,参见图18,配置电阻器负载01还可以包括与第三电阻R3并联的第一电容C1,与第五电阻R5并联的第二电容C2;比较器03还可以包括时间检测单元033,时间检测单元033用于在电压采集单元02向配置电阻器负载01提供第二参考电压Vcc时,分别检测第一电容C1的充电时间或放电时间和第二电容C2的充电时间或放电时间;状态机单元032具体用于根据第一电压比值、第二电压比值以及时间检测单元033检测的第一电容C1的充电时间或放电时间和第二电容C2的充电时间或放电时间确定对应的管脚配置状态。
其中,图18所示的配置电路所对应的配置方法如图19所示,可以包括以下步骤:
S501、将配置电阻器负载连接于芯片的第一配置管脚、第二配置管脚和第三配置管脚。
S502、通过第一配置管脚或第二配置管脚向配置电阻器负载提供第二参考电压,分别检测第一电容的充电时间或放电时间和第二电容的充电时间或放电时间,并分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。
在具体实施时,在通过第一配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压和第二配置管脚的电压;在通过第二配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。
在具体实施时,时间检测单元033分别连接第一配置管脚MOD1和第三配置管脚MOD3,通过配置第一电容C1的电容值,可以得到M种状态,通过配置第二电容C2的电容值,又可以得到M种状态。
S503、根据在通过第一配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,根据在通过第二配置管脚向配置 电阻器负载提供第二参考电压时采集的第一配置管脚的电压和第二配置管脚的电压计算第二电压比值;根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第二配置管脚的电压和第三配置管脚的电压计算第三电压比值。
S504、根据第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值、第二电压比值以及第三电压比值确定对应的管脚配置状态。
本申请实施例五与实施例四相比增加了第一电容、第二电容和时间检测单元,将第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值、第二电压比值以及第三电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×N×M×M种状态的配置。其中,N和M的值可以相同,也可以不相同,在此不作限定。
实施例六
参见图21,图21为本申请实施例提供的又一种管脚状态的配置电路的结构示意图。如图21所示,该配置电路中可以包括配置电阻器负载01、电压采集单元02和比较器03,而比较器03可以包括电压比值计算单元031和状态机单元032。其中:所述电压采集单元02用于通过所述第二配置管脚MOD2向所述配置电阻器负载01提供第二参考电压Vcc,并分别采集所述第一配置管脚MOD1的电压vmod1、所述第二配置管脚MOD2的电压vmod2和所述第三配置管脚MOD3的电压vmod3;通过所述第一配置管脚MOD1和所述第三配置管脚MOD3同时向所述配置电阻器负载01提供所述第二参考电压Vcc,并分别采集所述第一配置管脚MOD1的电压vmod1、所述第二配置管脚MOD2的电压vmod2和所述第三配置管脚MOD3的电压vmod3。所述电压比值计算单元031用于根据所述电压采集单元02在通过所述第二配置管脚MOD2向所述配置电阻器负载01提供第二参考电压Vcc时,采集的所述第一配置管脚MOD1的电压vmod1、所述第二配置管脚MOD2的电压vmod2和所述第三配置管脚MOD3的电压vmod3计算第一电压比值和第三电压比值;根据所述电压采集单元02在通过所述第三配置管脚MOD3和所述第一配置管脚MOD1同时向所述配置电阻器负载01提供第二参考电压Vcc时,采集的所述第一配置管脚MOD1的电压vmod1、所述第二配置管脚MOD2的电压vmod2和所述第三配置管脚MOD3的电压vmod3计算第二电压比值。所述状态机单元032用于根据所述第一电压比值、所述第二电压比值以及所述第三电压比值确定对应的管脚配置状态。
示例性的,参见图20,当芯片具有三个配置管脚,配置电阻器负载01可以包括可配置的第一电阻R1、可配置的第二电阻R2、可配置第三电阻R3、可配置第四电阻R4和可配置第五电阻R5;所述第一电阻R1的第一端子连接第一参考电压例如接地,所述第一电阻R1的第二端子连接所述第一配置管脚MOD1;所述第二电阻R2的第一端子连接第一参考电压例如接地,所述第二电阻R2的第二端子连接所述第二配置管脚MOD2,所述第三电阻R3连接于所述第一电阻R1的第二端子和所述第二电阻R2的第二端子之间;第四电阻R4的第一端子用于连接第一参考电压,第四电阻R4的第二端子用于与第三配置管脚MOD3连接,第五电阻R5连接于第四电阻R4的第二端子和第二电阻R2的第二端子之间。
示例性的,如图21所示,本申请中的电压采集单元02可以包括电压提供电路021和电压采集电路022。电压提供电路021可以包括一个第一数据选通器D1和一个开关K3,其中第一数据选通器D1可以包括3个开关K0~K2,当需要对芯片的模式状态进行配置时,开关K3导通,第一数据选通器D1选择向第一配置管脚MOD1、第二配置管脚MOD2或第三配置管脚MOD3提供第二参考电压Vcc。当对芯片的模式状态完成配置后,开关K3 截止,配置电阻器负载01不工作,无功率损耗。电压采集电路022可以包括一第二数据选通器D2,第二数据选通器D2可以将第一配置管脚MOD1的电压vmod1、第二配置管脚MOD2的电压vmod2或者第三配置管脚MOD3的电压vmod2提供给电压比值计算单元031。
其中,图21所示的配置电路所对应的配置方法如图22所示,可以包括以下步骤:
S601、将配置电阻器负载连接于芯片的第一配置管脚、第二配置管脚和第三配置管脚。
S602、通过第一配置管脚、第二配置管脚或第三配置管脚向配置电阻器负载提供第二参考电压,并分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。
示例性的,配置电阻器负载可以采用图20所示的结构。在具体实施时,例如配置第三电阻的阻值等于第五电阻的阻值,即R3=R5,在通过第二配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压,此时第二配置管脚的电压vmod2=Vcc,第一配置管脚的电压vmod1=[R1/(R1+R3)]Vcc,第三配置管脚的电压vmod3=[R4/(R4+R3)]Vcc;在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压,此时第一配置管脚的电压vmod1和第三配置管脚的电压Vmod3均等于Vcc,第二配置管脚的电压vmod2=[R2/(R2+R3/2)]Vcc。
S603、根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压,第二配置管脚的电压和第三配置管脚的电压计算第一电压比值和第三电压比值,根据在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压计算第二电压比值。
示例性的,可以根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时,采集的第一配置管脚的电压和第二配置管脚的电压计算第一电压比值,根据第三配置管脚的电压和第二配置管脚的电压计算第三电压比值。例如,第一电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压与第二配置管脚的电压的比值,即第一电压比值mod_ratio1=vmod1/vmod2=R1/(R1+R3)。第三电压比值可以等于在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第三配置管脚的电压与第二配置管脚的电压的比值,即第三电压比值mod_ratio3=vmod3/vmod2=R4/(R4+R3)。
示例性的,可以根据在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时,采集的第一配置管脚的电压和第二配置管脚的电压,或者第三配置管脚的电压和第二配置管脚的电压计算第二电压比值。例如,第二电压比值可以等于在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时采集的第二配置管脚的电压与第一配置管脚的电压或三配置管脚的电压的比值,即第二电压比值mod_ratio3=vmod2/vmod1=R2/(R2+R3/2)。
S604、根据第一电压比值、第二电压比值以及第三电压比值确定对应的管脚配置状态。
本申请实施例六将第一电压比值、第二电压比值以及第三电压值进行结合来确定对应的管脚配置状态,同样可以实现N×N×N种状态的配置。实施例六与实施例四相比,虽然配置电阻器负载的结构相同,但是电压采集单元向配置电阻器负载提供第二参考电压的 方法不同,导致电压比值计算单元计算第一电压比值、第二电压比值和第三电压比值的方法也不同。实施例六与实施例四相比,各电阻的选择更容易,设计范围更宽,因此配置设计更加简单。
实施例七
示例性的,参见图23,配置电阻器负载01还可以包括与第三电阻R3并联的第一电容C1,与第五电阻R5并联的第二电容C2;比较器03还可以包括时间检测单元033,时间检测单元033用于在电压采集单元02向配置电阻器负载01提供第二参考电压Vcc时,分别检测第一电容C1的充电时间或放电时间和第二电容C2的充电时间或放电时间;状态机单元032具体用于根据第一电压比值、第二电压比值以及时间检测单元033检测的第一电容C1的充电时间或放电时间和第二电容C2的充电时间或放电时间确定对应的管脚配置状态。
其中,图23所示的配置电路所对应的配置方法如图24所示,可以包括以下步骤:
S701、将配置电阻器负载连接于芯片的第一配置管脚、第二配置管脚和第三配置管脚。
S702、通过第一配置管脚、第二配置管脚或第三配置管脚向配置电阻器负载提供第二参考电压,分别检测第一电容的充电时间或放电时间和第二电容的充电时间或放电时间,并分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压。
在具体实施时,在通过第二配置管脚向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压,第二配置管脚的电压和第三配置管脚的电压;通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时,分别采集第一配置管脚的电压、第二配置管脚的电压和第三配置管脚电压。
在具体实施时,时间检测单元033分别连接第一配置管脚MOD1和第三配置管脚MOD3,通过配置第一电容C1的电容值,可以得到M种状态,通过配置第二电容C2的电容值,又可以得到M种状态。
S703、根据在通过第二配置管脚向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压,第二配置管脚和第三配置管脚的电压计算第一电压比值和第三电压比值,根据在通过第一配置管脚和第三配置管脚同时向配置电阻器负载提供第二参考电压时采集的第一配置管脚的电压、第二配置管脚的电压和第三配置管脚的电压计算第二电压比值。
S704、根据第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值、第二电压比值以及第三电压比值确定对应的管脚配置状态。
本申请实施例七与实施例六相比增加了第一电容、第二电容和时间检测单元,将第一电容的充电时间或放电时间、第二电容的充电时间或放电时间、第一电压比值、第二电压比值以及第三电压比值进行结合来确定对应的管脚配置状态,可以实现N×N×N×M×M种状态的配置。其中,N和M的值可以相同,也可以不相同,在此不作限定。
可选地,本申请还可以通过增加芯片中的配置管脚数量来进一步增加芯片可配置的状态的数量。例如,当配置管脚数为偶数时,配置电阻器负载可以由多个图3所示的π型电阻拓扑结构形成,例如配置管脚数为4个时,配置电阻器负载可以由2个π型电阻拓扑结构形成,配置管脚数为6个时,配置电阻器负载可以由3个π型电阻拓扑结构形成,当配置管脚数量增加时,依次类推。当配置管脚数为奇数时,配置电阻器负载可以在实施例四或实施例六的基础上增加一个或多个π型电阻拓扑结构,例如配置管脚数为5个时,配置电阻器负载可以在实施例四的配置电阻器负载的基础上增加1个π型电阻拓扑结构形成, 配置管脚数为7个时,配置电阻器负载可以在实施例四的配置电阻器负载的基础上增加2个π型电阻拓扑结构形成,当配置管脚数量增加时,依次类推。本申请中,每增加一个配置管脚,可配置的状态就可以增加N倍。
进一步地,本申请还可以通过在配置电阻器负载中增加电容来增加可配置的状态数量,增加电容的情况可以参考实施例二、实施例三、实施例五和实施例七,在此不作赘述。
综上,本申请与相关技术相比,根据电阻分压的比值进行状态配置可以提高状态值的精度;其次,通过两个或者多个配置管脚,可以实现更多可配置状态;最后,本申请的配置电阻器负载在配置完成后是不工作的,因此无功率损耗。
本申请实施例还提供了一种电子设备,包括芯片和本申请实施例提供的上述任一种管脚状态的态配置电路,所述配置电路用于连接所述芯片的配置管脚。由于该电子设备解决问题的原理与前述一种态配置电路相似,因此该电子设备的实施可以参见前述态配置电路的实施,重复之处不再赘述。
本领域内的技术人员应明白,本申请的实施例可提供为方法、系统、或计算机程序产品。因此,本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且,本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器,使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中,使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品,该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上,使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理,从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
显然,本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样,倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内,则本申请也意图包含这些改动和变型在内。

Claims (19)

  1. 一种管脚状态的配置电路,其特征在于,包括:配置电阻器负载、电压采集单元和比较器;
    所述配置电阻器负载用于连接芯片的第一配置管脚和第二配置管脚;
    所述电压采集单元用于通过所述第一配置管脚或所述第二配置管脚向所述配置电阻器负载提供第二参考电压,并分别采集所述第一配置管脚的电压和所述第二配置管脚的电压;
    所述比较器用于根据所述电压采集单元在通过所述第一配置管脚向所述配置电阻器负载提供第二参考电压时采集的所述第一配置管脚的电压和所述第二配置管脚的电压计算第一电压比值,根据所述电压采集单元在通过所述第二配置管脚向所述配置电阻器负载提供第二参考电压时采集的所述第一配置管脚的电压和所述第二配置管脚的电压计算第二电压比值,以及根据所述第一电压比值和所述第二电压比值确定对应的管脚配置状态。
  2. 如权利要求1所述的配置电路,其特征在于,所述配置电阻器负载包括:可配置的第一电阻、可配置的第二电阻和可配置的第三电阻;
    所述第一电阻的第一端子用于连接第一参考电压,所述第一电阻的第二端子用于连接所述第一配置管脚;所述第二电阻的第一端子用于连接第一参考电压,所述第二电阻的第二端子用于连接所述第二配置管脚,所述第三电阻连接于所述第一电阻的第二端子和所述第二电阻的第二端子之间。
  3. 如权利要求2所述的配置电路,其特征在于,所述配置电阻器负载还包括与所述第三电阻并联的第一电容;
    所述比较器还用于在所述电压采集单元向所述配置电阻器负载提供所述第二参考电压时,检测所述第一电容的充电时间或放电时间,以根据所述第一电压比值、所述第二电压比值以及所述第一电容的充电时间或放电时间确定对应的管脚配置状态。
  4. 如权利要求2所述的配置电路,其特征在于,所述配置电阻器负载还包括与所述第一电阻并联的第一电容,与所述第二电阻并联的第二电容;
    所述比较器还用于在所述电压采集单元向所述配置电阻器负载提供第二参考电压时,分别检测所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间,以根据所述第一电压比值、所述第二电压比值、所述第一电容的充电时间或放电时间以及所述第二电容的充电时间或放电时间确定对应的管脚配置状态。
  5. 如权利要求2所述的配置电路,其特征在于,所述配置电阻器负载还包括可配置的第四电阻和可配置的第五电阻;所述第四电阻的第一端子用于连接第一参考电压,所述第四电阻的第二端子用于与所述芯片的第三配置管脚连接,所述第五电阻连接于所述第四电阻的第二端子和所述第二电阻的第二端子之间;
    所述电压采集单元还用于在通过所述第二配置管脚向所述配置电阻器负载提供所述第二参考电压时,采集所述第三配置管脚的电压;
    所述比较器还用于根据所述电压采集单元在通过所述第二配置管脚向所述配置电阻器负载提供第二参考电压时采集的所述第二配置管脚的电压和所述第三配置管脚的电压,计算第三电压比值,以根据所述第一电压比值、所述第二电压比值以及所述第三电压比值确定对应的管脚配置状态。
  6. 如权利要求5所述的配置电路,其特征在于,所述配置电阻器负载还包括与所述第三电阻并联的第一电容,与所述第五电阻并联的第二电容;
    所述比较器还用于在所述电压采集单元向所述配置电阻器负载提供所述第二参考电压时,分别检测所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间,以根据所述第一电压比值、所述第二电压比值、所述第三电压比值、所述第一电容的充电时间或放电时间以及所述第二电容的充电时间或放电时间确定对应的管脚配置状态。
  7. 一种管脚状态的配置电路,其特征在于,包括:配置电阻器负载、电压采集单元和比较器;
    所述配置电阻器负载用于连接芯片的第一配置管脚、第二配置管脚和第三配置管脚;
    所述电压采集单元用于通过所述第二配置管脚向所述配置电阻器负载提供第二参考电压,并分别采集所述第一配置管脚的电压、所述第二配置管脚的电压和所述第三配置管脚的电压;通过所述第一配置管脚和所述第三配置管脚同时向所述配置电阻器负载提供所述第二参考电压,并分别采集所述第一配置管脚的电压、所述第二配置管脚的电压和所述第三配置管脚的电压;
    所述比较器用于根据所述电压采集单元在通过所述第二配置管脚向所述配置电阻器负载提供第二参考电压时,采集的所述第一配置管脚的电压、所述第二配置管脚的电压和所述第三配置管脚的电压计算第一电压比值和第三电压比值;根据所述电压采集单元在通过所述第三配置管脚和所述第一配置管脚同时向所述配置电阻器负载提供第二参考电压时,采集的所述第一配置管脚的电压、所述第二配置管脚的电压和所述第三配置管脚的电压计算第二电压比值;以及根据所述第一电压比值、所述第二电压比值以及所述第三电压比值确定对应的管脚配置状态。
  8. 如权利要求7所述的配置电路,其特征在于,所述配置电阻器负载包括:可配置的第一电阻、可配置的第二电阻、可配置的第三电阻、可配置的第四电阻和可配置的第五电阻;
    所述第一电阻的第一端子用于连接第一参考电压,所述第一电阻的第二端子用于连接所述第一配置管脚;所述第二电阻的第一端子用于连接第一参考电压,所述第二电阻的第二端子用于连接所述第二配置管脚,所述第三电阻连接于所述第一电阻的第二端子和所述第二电阻的第二端子之间;所述第四电阻的第一端子用于连接所述第一参考电压,所述第四电阻的第二端子用于与所述第三配置管脚连接,所述第五电阻连接于所述第四电阻的第二端子和所述第二电阻的第二端子之间。
  9. 如权利要求8所述的配置电路,其特征在于,所述配置电阻器负载还包括与所述第三电阻并联的第一电容,与所述第五电阻并联的第二电容;
    所述比较器还用于在所述电压采集单元向所述配置电阻器负载提供所述第二参考电压时,分别检测所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间,以根据所述第一电压比值、所述第二电压比值、所述第三电压比值、所述第一电容的充电时间或放电时间以及所述第二电容的充电时间或放电时间确定对应的管脚配置状态。
  10. 一种电子设备,其特征在于,包括芯片和如权利要求1-9任一项所述的管脚状态的配置电路,所述配置电路用于连接所述芯片的配置管脚。
  11. 一种管脚状态的配置方法,其特征在于,包括:
    将配置电阻器负载连接于芯片的第一配置管脚和第二配置管脚;
    通过所述第一配置管脚或所述第二配置管脚向所述配置电阻器负载提供第二参考电压,并分别采集所述第一配置管脚的电压和所述第二配置管脚的电压;
    根据在通过所述第一配置管脚向所述配置电阻器负载提供所述第二参考电压时采集的所述第一配置管脚的电压和所述第二配置管脚的电压计算第一电压比值,以及根据在通过所述第二配置管脚向所述配置电阻器负载提供所述第二参考电压时采集的所述第一配置管脚的电压和所述第二配置管脚的电压计算第二电压比值;
    根据所述第一电压比值和所述第二电压比值确定对应的管脚配置状态。
  12. 如权利要求11所述的配置方法,其特征在于,所述配置电阻器负载包括:可配置的第一电阻、可配置的第二电阻和可配置的第三电阻;
    所述第一电阻的第一端子连接第一参考电压,所述第一电阻的第二端子连接所述第一配置管脚;所述第二电阻的第一端子连接第一参考电压,所述第二电阻的第二端子连接所述第二配置管脚,所述第三电阻连接于所述第一电阻的第二端子和所述第二电阻的第二端子之间。
  13. 如权利要求12所述的配置方法,其特征在于,所述配置电阻器负载还包括与所述第三电阻并联的第一电容;所述配置方法还包括:
    在向所述配置电阻器负载提供所述第二参考电压时,检测所述第一电容的充电时间或放电时间;
    所述根据所述第一电压比值和所述第二电压比值确定对应的管脚配置状态,包括:
    根据所述第一电压比值、所述第二电压比值以及所述第一电容的充电时间或放电时间确定对应的管脚配置状态。
  14. 如权利要求12所述的配置方法,其特征在于,所述配置电阻器负载还包括与所述第一电阻并联的第一电容,与所述第二电阻并联的第二电容;所述配置方法还包括:
    在向所述配置电阻器负载提供第二参考电压时,分别检测所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间;
    所述根据所述第一电压比值和所述第二电压比值确定对应的管脚配置状态,包括:
    根据所述第一电压比值、所述第二电压比值、所述第一电容的充电时间或放电时间以及所述第二电容的充电时间或放电时间确定对应的管脚配置状态。
  15. 如权利要求12所述的配置方法,其特征在于,所述配置方法还包括:
    将所述配置电阻器负载连接芯片的第三配置管脚;其中,所述配置电阻器负载还包括可配置的第四电阻和可配置的第五电阻;所述第四电阻的第一端子用于连接第一参考电压,所述第四电阻的第二端子用于与所述第三配置管脚连接,所述第五电阻连接于所述第四电阻的第二端子和所述第二电阻的第二端子之间;
    在通过所述第二配置管脚向所述配置电阻器负载提供所述第二参考电压时,采集所述第三配置管脚的电压;
    根据在通过所述第二配置管脚向所述配置电阻器负载提供所述第二参考电压时采集的所述第二配置管脚的电压和所述第三配置管脚的电压,计算第三电压比值;
    所述根据所述第一电压比值和所述第二电压比值确定对应的管脚配置状态,包括:根据所述第一电压比值、所述第二电压比值以及第三电压比值确定对应的管脚配置状态。
  16. 如权利要求15所述的配置方法,其特征在于,所述配置电阻器负载还包括与所述第三电阻并联的第一电容,与所述第五电阻并联的第二电容;所述配置方法还包括:
    在向所述配置电阻器负载提供所述第二参考电压时,分别检测所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间;
    所述根据所述第一电压比值、所述第二电压比值以及第三电压比值确定对应的管脚配置状态,包括:根据所述第一电压比值、所述第二电压比值、所述第三电压比值、所述第一电容的充电时间或放电时间以及所述第二电容的充电时间或放电时间确定对应的管脚配置状态。
  17. 一种管脚状态的配置方法,其特征在于,包括:
    将配置电阻器负载连接于芯片的第一配置管脚、第二配置管脚和第三配置管脚;
    通过所述第二配置管脚向所述配置电阻器负载提供第二参考电压,并分别采集所述第一配置管脚的电压、所述第二配置管脚的电压和所述第三配置管脚的电压;通过所述第一配置管脚和所述第三配置管脚同时向所述配置电阻器负载提供所述第二参考电压,并分别采集所述第一配置管脚的电压、所述第二配置管脚的电压和所述第三配置管脚的电压;
    根据在通过所述第二配置管脚向所述配置电阻器负载提供第二参考电压时,采集的所述第一配置管脚的电压、所述第二配置管脚的电压和所述第三配置管脚的电压计算第一电压比值和第三电压比值;根据在通过所述第三配置管脚和所述第一配置管脚同时向所述配置电阻器负载提供第二参考电压时,采集的所述第一配置管脚的电压、所述第二配置管脚的电压和所述第三配置管脚的电压计算第二电压比值;
    根据所述第一电压比值、所述第二电压比值以及所述第三电压比值确定对应的管脚配置状态。
  18. 如权利要求17所述的配置方法,其特征在于,所述配置电阻器负载包括:可配置的第一电阻、可配置的第二电阻、可配置的第三电阻、可配置的第四电阻和可配置的第五电阻;
    所述第一电阻的第一端子用于连接第一参考电压,所述第一电阻的第二端子用于连接 所述第一配置管脚;所述第二电阻的第一端子用于连接第一参考电压,所述第二电阻的第二端子用于连接所述第二配置管脚,所述第三电阻连接于所述第一电阻的第二端子和所述第二电阻的第二端子之间;所述第四电阻的第一端子用于连接所述第一参考电压,所述第四电阻的第二端子用于与所述第三配置管脚连接,所述第五电阻连接于所述第四电阻的第二端子和所述第二电阻的第二端子之间。
  19. 如权利要求18所述的配置方法,其特征在于,所述配置电阻器负载还包括与所述第三电阻并联的第一电容,与所述第五电阻并联的第二电容;所述配置方法还包括:
    在向所述配置电阻器负载提供所述第二参考电压时,分别检测所述第一电容的充电时间或放电时间和所述第二电容的充电时间或放电时间;
    所述根据所述第一电压比值、所述第二电压比值以及第三电压比值确定对应的管脚配置状态,包括:
    根据所述第一电压比值、所述第二电压比值、所述第三电压比值、所述第一电容的充电时间或放电时间以及所述第二电容的充电时间或放电时间确定对应的管脚配置状态。
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