WO2022241993A1 - 半导体结构及半导体结构的制备方法 - Google Patents

半导体结构及半导体结构的制备方法 Download PDF

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Publication number
WO2022241993A1
WO2022241993A1 PCT/CN2021/120107 CN2021120107W WO2022241993A1 WO 2022241993 A1 WO2022241993 A1 WO 2022241993A1 CN 2021120107 W CN2021120107 W CN 2021120107W WO 2022241993 A1 WO2022241993 A1 WO 2022241993A1
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region
tsv
well region
annular
substrate
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PCT/CN2021/120107
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to EP21870481.5A priority Critical patent/EP4117030A4/en
Priority to US17/651,792 priority patent/US20220375879A1/en
Publication of WO2022241993A1 publication Critical patent/WO2022241993A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields

Definitions

  • the present application relates to the field of semiconductor technology, in particular to a semiconductor structure and a method for preparing the semiconductor structure.
  • Stacked semiconductor structure packaging technology is also called three-dimensional packaging technology, which refers to the packaging technology of stacking two or more semiconductor structures in the vertical direction in the same package.
  • TSV Through Silicon Via
  • the first aspect of the embodiments of the present application provides a semiconductor structure, including:
  • a substrate having a first region and a second region adjacently disposed, the first region being provided with a functional device
  • the TSV structure is disposed in the second region and electrically connected to the functional device;
  • the first protection structure is disposed around the TSV structure and is electrically connected to the TSV structure;
  • the first protection structure is located between the TSV structure and the functional device.
  • a second aspect of the embodiments of the present application provides a method for preparing a semiconductor structure, which includes the following steps:
  • the first protection structure surrounds the TSV structure, and the TSV structure is electrically connected to the functional device and the first protection structure respectively.
  • FIG. 1 is a top view of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 2 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 3 is a process flow diagram of a method for preparing a semiconductor structure provided in an embodiment of the present application
  • FIG. 4 is a flow chart of a process for forming a first protection structure in the method for manufacturing a semiconductor structure provided by an embodiment of the present application.
  • Stacked semiconductor structure packaging technology also known as three-dimensional packaging technology, refers to the packaging technology in which two or more semiconductor structures are stacked in the vertical direction in the same package, and adjacent semiconductor structures are connected through TSV structures.
  • a large amount of electrons will be generated during the process of etching the semiconductor structure by plasma to form the through hole, and the electrons will be transferred to the device of the semiconductor structure through the conductive layer, causing damage to the device and reducing the performance of the semiconductor structure.
  • the embodiment of the present application provides a semiconductor structure and a method for preparing the semiconductor structure.
  • the first protection structure By setting the first protection structure connected to the TSV structure in the second region, the first protection structure can absorb the time when the TSV structure is formed.
  • the generated current prevents the current from being transmitted to the functional device, prevents the current from damaging the functional device, improves the service life of the functional device, and further improves the performance of the semiconductor structure.
  • This embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be described below as an example of a dynamic random access memory (DRAM). However, this embodiment is not limited to this.
  • the semiconductor structure in this embodiment can also be other structures. .
  • a semiconductor structure provided by an embodiment of the present application includes a substrate 10 , and a TSV structure 20 and a first protection structure 30 disposed on the substrate 10 .
  • the substrate 10 is used as a supporting component of the semiconductor structure for supporting other components disposed thereon, wherein the substrate 10 can be made of semiconductor materials, and the semiconductor materials can be silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds. One or more.
  • the substrate 10 may include a first region 11 and a second region 12 disposed adjacently, wherein the first region 11 is used for setting a functional device 50 , for example, the functional device 50 may include a gate 51 and an active region 52 .
  • the second region 12 is used to form the TSV structure 20, and the TSV structure 20 can be electrically connected with the functional device 50, wherein, the TSV structure 20 can be directly or indirectly connected with the functional device 50, when the TSV structure 20 and the functional device
  • a conductive layer 13 may be provided on the substrate 10 , and the TSV structure 20 is electrically connected to the functional device 50 through the conductive layer 13 .
  • TSV structure 20 may be formed in the second region 12, but devices such as word lines or capacitors may also be formed in the second region 12, but at this time, the TSV structure 20 and the The devices are isolated from each other.
  • a plasma etching process is usually used to form a TSV through hole 21 on the substrate, and then a deposition process is used to form a TSV structure 20 in the TSV through hole 21, and a current is usually generated when the TSV through hole 21 is etched. The current will be transmitted to the functional device through the conductive layer or other components, causing damage to the functional device.
  • the embodiment of the present application provides a first protection structure 30 in the second region 12, the first protection structure 30 is arranged around the TSV structure 20, and is electrically connected to the TSV structure 20, and the first protection structure 30 is located on the TSV structure 20 and the functional device 50, the current generated during the formation of the TSV structure will be preferentially transmitted to the first protection structure 30 when it is transmitted to the outside, and the first protection structure 30 can absorb the current, which can prevent the current from being transmitted to the function device 50 , causing damage to the functional device 50 .
  • the TSV structure may be directly connected to the first protection structure 30 , or may be electrically connected to the first protection structure 30 through the conductive layer 13 .
  • the first protection structure 30 may include a first well region 31 , a second well region 32 and a doped region 33 arranged around the TSV structure 20 , wherein the second well The region 32 is disposed in the first well region 31 , the doped region 33 is disposed on the second well region 32 , and the end of the doped region 33 away from the second well region 32 is electrically connected to the TSV structure 20 .
  • the first protection structure 30 formed by the first well region 31, the second well region 32 and the doped region 33 can absorb the current generated when the TSV via hole 21 is formed, and prevent the current from passing through the conductive layer or other components. To the functional device, reduce the damage of the current to the functional device.
  • the first well region 31 is a P-type well region
  • the second well region 32 is an N-type well region
  • the doped region 33 is a P+ doped region, so that the first protective structure forms a PNP junction, and the ion doping concentration of the P+ doped region Can be greater than the ion doping concentration of the P-type well region; or, the first well region 31 is an N-type well region, the second well region 32 is a P-type well region and the doped region 33 is an N+ doped region, so that the first well region
  • the protective structure forms an NPN junction, and the ion doping concentration of the N+ doped region may be greater than that of the N-type well region.
  • the depth of the active region 52 of the functional device 50 is not greater than the depth of the doped region 33 , preventing the active region 52 of the functional device from extending into the second well region 32 and affecting the performance of the functional device.
  • first protection structures 30 may be arranged at intervals along the circumferential direction of the TSV structure, or the first protection structure 30 may include an integral annular PNP junction or NPN junction.
  • the specific structure of the first protection structure is not specifically limited, as long as the first protection structure can absorb the current generated by forming the TSV structure.
  • the first well region 31 may include a first annular region extending along the circumferential direction of the TSV structure
  • the second well region 32 may include a second annular region extending along the circumferential direction of the TSV structure
  • the doped region 33 may include The third ring-shaped area extending in the circumferential direction of the structure, the centers of the first ring-shaped area, the second ring-shaped area and the third ring-shaped area are all located on the axis of the TSV structure 20, so that the current can quickly spread to the first protection structure, increasing the first Protecting the amount of current the structure sinks improves the performance of the semiconductor structure.
  • the widths of the first annular region, the second annular region and the third annular region may be equal or different, for example, the width of the third annular region is smaller than the width of the second annular region , the width of the second annular region is smaller than the width of the first annular region, that is to say, the width of the first annular region, the width of the second annular region and the width of the third annular region decrease in sequence.
  • width of the first annular area, the width of the second annular area, and the width of the third annular area may also be equal, which is not specifically limited in this embodiment.
  • the width of the first annular region is between 0.3 ⁇ m and 2 ⁇ m. If the width of the first annular region is less than 0.3 ⁇ m, the width of the first annular region will be too small, which will reduce the absorption of the first protective structure to form TSV channels. If the width of the first ring-shaped area is too large, the junction capacitance forming the first protection structure will be increased. Therefore, this embodiment limits the width of the first ring-shaped area to ensure that the first The protection structure fully absorbs the current generated when the TSV via hole is formed, and also reduces the junction capacitance of the first protection structure.
  • the distance between the first ring region and the TSV structure is also limited, so that the distance between the first ring region and the TSV structure is between 2 ⁇ m and 10 ⁇ m, so as to ensure that the first protection structure can fully absorb and form the TSV through hole.
  • the current generated at the same time, it will not take up too much area.
  • an isolation structure 16 and a dielectric layer 15 are further provided between the substrate 10 and the conductive layer 13.
  • the isolation structure 16 is used to isolate the active region 52 from the first protection structure 30; two conductive plugs 14, wherein the two ends of one conductive plug 14 are directly connected to the conductive layer 13 and the functional device 50 respectively, and the two ends of the other conductive plug 14 are directly connected to the conductive layer 13 and the first protective structure 30 respectively,
  • One end of the TSV structure 20 penetrates the dielectric layer 15 and is directly connected to the conductive layer 13 .
  • a dielectric layer 15 is provided between the substrate 10 and the conductive layer 13 , and the dielectric layer 15 can prevent the conductive layer 13 from being electrically connected to other components of the substrate 10 .
  • the semiconductor structure further includes a second protection structure 40 disposed around the first protection structure 30 and located between the first protection structure 30 and the functional device 50; wherein the second protection structure 40 Electrically isolated from the TSV structure 20 .
  • the second protection structure 40 can also be disposed around the TSV structure 20 , and the second protection structure 40 can be a wall-shaped metal wall.
  • the material of the TSV structure is usually copper and other metals. Copper has a large thermal expansion coefficient.
  • the TSV structure or other functional devices will generate a large amount of heat, which will cause the TSV structure to expand when heated, making the substrate and TSV structure Stress deformation is formed in the contact region, which affects the performance of the semiconductor structure. Therefore, in this embodiment, a second protection structure is formed on the substrate. The second protection structure is used to buffer the stress of the TSV structure on the surrounding dielectric layer and improve the performance of the semiconductor structure.
  • the second aspect of the embodiment of the present application provides a method for preparing a semiconductor structure, including the following steps:
  • Step S100 providing a substrate, the substrate has a first region and a second region disposed adjacently.
  • the substrate may be a semiconductor substrate, such as a silicon (Si) substrate.
  • a semiconductor substrate such as a silicon (Si) substrate.
  • the substrate can also be germanium (Ge) substrate, silicon on insulator (Silicon on Insulator, SOI for short), silicon germanium (SiGe) substrate, silicon carbide (SiC) or gallium nitride (GaN) substrates, etc.
  • the substrate 10 has a first area 11 and a second area 12 adjacently arranged, wherein the sizes of the first area and the second area can be designed according to actual conditions, and are not specifically limited in this embodiment.
  • Step S200 forming functional devices in the first region, devices such as transistors or capacitors can be formed in the first region by using a conventional manufacturing process.
  • Step S300 forming a TSV structure and a first protection structure in the second region; wherein, the first protection structure surrounds the TSV structure, and the TSV structure is electrically connected to the functional device and the first protection structure respectively.
  • step S310 forming a first photoresist layer on the substrate 10 , the first photoresist layer has a first annular opening, and the first annular opening exposes the second region 12 .
  • Step S320 Perform ion doping on the second region 12 exposed in the first annular opening to form the first well region 31 .
  • the first well region 31 may be a P-type well region.
  • boron ions may be doped into the second region 12 exposing the first annular opening, so that the second region 12 forms a P-type well region.
  • the first well region 31 may also be an N-type well region.
  • phosphorus ions or arsenic ions may be doped into the second region exposed in the first annular opening to form an N-type well region.
  • Step S330 removing the first photoresist layer, the first photoresist layer may be removed by using a cleaning solution.
  • Step S340 forming a second photoresist layer on the substrate, the second photoresist layer has a second annular opening, and the projection of the second annular opening on the substrate is located in the first well region.
  • a coating process may be used to form a second photoresist layer with a certain thickness on the substrate, and then a second annular opening is formed in the second photoresist layer through exposure, development or etching processes.
  • the size of the second annular opening is not limited to the above method, and it may also be that the projection of the second annular opening on the substrate just exposes the first well region.
  • Step S350 Doping the first well region exposed in the second annular opening to form a second well region.
  • the second well region 32 is an N-type well region.
  • phosphorus ions or arsenic can be doped into the first well region 31 exposed in the second annular opening. ions to form an N-type well region.
  • the second well region 32 is a P-type well region.
  • boron ions can be doped into the first well region exposed in the second annular opening to form P-type well region.
  • Step S360 removing the second photoresist layer, the second photoresist layer may be removed by using a cleaning solution.
  • Step S370 forming a third photoresist layer on the substrate, the third photoresist layer has a third annular opening, and the projection of the third annular opening on the substrate is located in the second well region.
  • the size of the third annular opening is not limited to the above manner, and it may also be that the projection of the third annular opening on the substrate just exposes the second well region.
  • Step S380 Doping the second well region exposed in the third annular opening to form a doped region, and the first well region, the second well region and the doped region form a first protection structure.
  • the doped region 33 is a P+ doped region. Boron ions are doped in the well region to form a P+ doped region.
  • the doped region 33 is an N+ doped region. Phosphorus ions and arsenic ions are doped in the well region to form an N+ doped region.
  • the following steps are also included:
  • the dielectric layer is formed on the substrate, for example, the dielectric layer can be formed on the substrate by a chemical vapor deposition process or a physical vapor deposition process.
  • At least two through holes are formed in the dielectric layer, one of which exposes the first protection structure, and the other exposes the functional device.
  • the dielectric layer can be patterned to form at least two through holes in the dielectric layer, for example, three through holes are provided in the dielectric layer, one of which exposes the functional device, and the other two through holes expose the second through hole.
  • a protective structure for example, three through holes are provided in the dielectric layer, one of which exposes the functional device, and the other two through holes expose the second through hole.
  • a conductive material may be deposited in the through hole by a physical vapor deposition process or a chemical vapor deposition process to form a conductive plug.
  • a conductive layer is formed on the dielectric layer by chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process, and the conductive layer covers at least the conductive plugs, so as to achieve the conductive layer and the first protection structure and the TSV structure respectively. electrical connection.
  • the method for preparing the semiconductor structure further includes:
  • a fourth photoresist layer is formed on the surface of the substrate away from the conductive layer, the fourth photoresist layer has an opening pattern, and the projection of the opening pattern on the surface of the substrate is located inside the first protection structure.
  • the substrate and the dielectric layer in the opening pattern are etched by plasma to form TSV through holes exposing the conductive layer.
  • TSV through holes electrons will be generated, and the electrons will be transferred to the device of the semiconductor structure through the conductive layer.
  • a conductive material is filled in the TSV via hole to form a TSV structure.

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Abstract

本申请实施例提供一种半导体结构及半导体结构的制备方法，涉及半导体技术领域，该半导体结构包括基底、TSV结构和第一保护结构，基底具有相邻设置的第一区域和第二区域，第一区域设有功能器件；TSV结构设置在第二区域内，并与功能器件电连接；第一保护结构，第一保护结构环绕TSV结构设置，并与TSV结构电连接；其中，第一保护结构位于TSV结构和功能器件之间。本申请实施例通过在第二区域内设置与TSV结构连接的第一保护结构，第一保护结构能够吸收形成TSV结构时所产生的电流，防止该电流传递至功能器件处，避免该电流损坏功能器件，提高功能器件的寿命，进而提高半导体结构的性能。

Description

半导体结构及半导体结构的制备方法
本申请要求于2021年05月21日提交中国专利局、申请号为202110556051.2、申请名称为“半导体结构及半导体结构的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及半导体结构的制备方法。
背景技术
随着集成电路制造水平的不断发展，电子产品趋向小型化、高度集成化，叠层半导体结构封装技术应运而生。叠层半导体结构封装技术也称为三维封装技术，是指在同一个封装体内的垂直方向叠放两个以上半导体结构的封装技术。
在三维封装技术中，利用硅通孔技术(Through Silicon Via，简称TSV)在各半导体结构上制作相对应的通孔，通孔中填充导电材料，以形成TSV结构，利用TSV结构来实现堆叠的半导体结构之间的垂直导通。
但是，在形成通孔时会形成大量的电荷，该电荷会传递至半导体结构内损伤半导体结构内的器件，降低半导体结构的性能。
发明内容
本申请实施例的第一方面提供一种半导体结构，包括：
基底，所述基底具有相邻设置的第一区域和第二区域，所述第一区域设有功能器件；
TSV结构，所述TSV结构设置在所述第二区域内，并与所述功能器件电连接；
第一保护结构，所述第一保护结构环绕所述TSV结构设置，并与所述TSV结构电连接；
其中，所述第一保护结构位于所述TSV结构和所述功能器件之间。
本申请实施例的第二方面提供一种半导体结构的制备方法，其包括如下步骤：
提供基底，所述基底具有相邻设置的第一区域和第二区域；
在所述第一区域内形成功能器件；
在所述第二区域内形成TSV结构和第一保护结构；
其中，所述第一保护结构环绕所述TSV结构，且所述TSV结构分别与所述功能器件和所述第一保护结构电连接。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的半导体结构及半导体结构的制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的半导体结构的俯视图；
图2为本申请实施例提供的半导体结构的剖视图；
图3为本申请实施例提供的半导体结构的制备方法的工艺流程图；
图4为本申请实施例提供的半导体结构的制备方法中形成第一保护结构的工艺流程图。
具体实施方式
叠层半导体结构封装技术也称为三维封装技术，是指在同一个封装体内的垂直方向叠放两个及其以上半导体结构的封装技术，相邻的半导体结 构通过TSV结构连接。利用等离子体刻蚀半导体结构形成通孔过程中会产生大量电子，该电子会通过导电层传递至半导体结构的器件，对器件造成损伤，降低半导体结构的性能。
针对上述的技术问题，本申请实施例提供了一种半导体结构及半导体结构的制备方法，通过在第二区域内设置与TSV结构连接的第一保护结构，第一保护结构能够吸收形成TSV结构时所产生的电流，防止该电流传递至功能器件处，避免该电流损坏功能器件，提高功能器件的寿命，进而提高半导体结构的性能。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1和图2所示，本申请实施例提供的一种半导体结构，包括基底10、以及设置在基底10上的TSV结构20和第一保护结构30。
其中，基底10作为半导体结构的支撑部件，用于支撑设在其上的其他部件，其中，基底10可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
基底10可以包括相邻设置的第一区域11和第二区域12，其中第一区域11用于设置功能器件50，比如，功能器件50可以包括栅极51和有源区52。
如图2所示，第二区域12用于形成TSV结构20，TSV结构20可以与功能器件50电连接，其中，TSV结构20可以与功能器件50直接连接或者间接连接，当TSV结构20与功能器件50间接连接时，可以在基底10上设置导电层13，TSV结构20通过导电层13与功能器件50电连接。
需要说明的是，第二区域12可以不单单只形成TSV结构20，第二区 域12内也可以形成字线或者电容器等器件，但是此时就需要TSV结构20与设置在第二区域12内的器件互相绝缘设置。
在形成TSV结构时，通常会利用等离子刻蚀工艺在基底上形成TSV通孔21，然后利用沉积工艺在TSV通孔21内形成TSV结构20，在蚀刻TSV通孔21的时候通常会产生电流，该电流会通过导电层或者其他的部件传递至功能器件处，造成功能器件的损伤。
鉴于此，本申请实施例在第二区域12内设有第一保护结构30，第一保护结构30环绕TSV结构20设置，并与TSV结构20电连接，且第一保护结构30位于TSV结构20与功能器件50之间，这样在形成TSV结构时所产成的电流在向外部传输时会优先传递至第一保护结构30上，第一保护结构30能够吸收该电流，可以防止电流传递至功能器件50处，造成功能器件50的损伤。
需要说明的，TSV结构可以直接与第一保护结构30连接，也可以通过导电层13与第一保护结构30电连接。
在一些实施例中，如图1和图2所示，第一保护结构30可以包括环绕TSV结构20设置的第一阱区31、第二阱区32以及掺杂区33，其中，第二阱区32设置在第一阱区31内，掺杂区33设置在第二阱区32上，掺杂区33背离第二阱区32的一端与TSV结构20电连接。
本实施例通过第一阱区31、第二阱区32以及掺杂区33形成的第一保护结构30能够吸收形成TSV通孔21时所产生的电流，防止电流通过导电层或者其他的部件传递至功能器件处，降低电流对功能器件的损伤。
第一阱区31为P型阱区、第二阱区32为N型阱区以及掺杂区33为P+掺杂区，使得第一保护结构形成PNP结，P+掺杂区的离子掺杂浓度可以比P型阱区的离子掺杂浓度大；或者，第一阱区31为N型阱区、第二阱区32为P型阱区以及掺杂区33为N+掺杂区，使得第一保护结构形成NPN结，N+掺杂区的离子掺杂浓度可以比N型阱区的离子掺杂浓度大。
示例性地，功能器件50的有源区52的深度不大于掺杂区33的深度，防止功能器件的有源区52延伸至第二阱区32内，影响功能器件的性能。
需要是说明的是，可以沿着TSV结构的圆周方向间隔设置多个第一保护结构30，或者是，第一保护结构30可以包括一体式的环形PNP结或NPN 结，本实施例在此对第一保护结构的具体结构不做具体的限定，只要第一保护结构能够吸收形成TSV结构的所产生的电流即可。
示例性地，第一阱区31可以包括沿TSV结构的圆周方向延伸的第一环形区，第二阱区32包括沿TSV结构的圆周方向延伸的第二环形区，掺杂区33包括沿TSV结构的圆周方向延伸的第三环形区，第一环形区、第二环形区以及第三环形区的中心均位于TSV结构20的轴线上，使得电流能够快速扩散至第一保护结构，增加第一保护结构的吸收电流的量，提高了半导体结构的性能。
沿垂直于TSV结构的轴线方向，第一环形区、第二环形区以及第三环形区的宽度可以相等，也可以不等，示例性地，第三环形区的宽度小于第二环形区的宽度，第二环形区的宽度小于第一环形区的宽度，也就是说，第一环形区的宽度、第二环形区的宽度和第三环形区的宽度依次降低。
需要说明的是，第一环形区的宽度、第二环形区的宽度以及第三环形区的宽度也可以相等，本实施例在此不做具体的限定。
在一些实施例中，第一环形区的宽度位于0.3μm～2μm，若是第一环形区的宽度小于0.3μm，则会造成第一环形区的宽度过小，降低第一保护结构吸收形成TSV通孔时所产生的电流；若是第一环形区的宽度过大，则会增加形成第一保护结构的结电容，因此，本实施例对第一环形区的宽度进行了限定，既要保证第一保护结构充分吸收形成TSV通孔时所产生的电流，也要降低第一保护结构的结电容。
本实施例还对第一环形区与TSV结构之间的间距进行了限定，使得第一环形区与TSV结构的间距位于2μm～10μm之间，以保证第一保护结构能够充分吸收形成TSV通孔时所产生的电流，同时，又不至于占用过大的面积。
在一些实施例中，基底10与导电层13之间还设置有隔离结构16和介质层15，隔离结构16用于隔离有源区52和第一保护结构30；介质层15内设置有至少两个导电插塞14，其中一个导电插塞14的两端分别与导电层13和功能器件50直接相连，另一个导电插塞14的两端分别与导电层13和第一保护结构30直接相连，TSV结构20的一端贯穿介质层15与导电层13直接相连。
本实施例在基底10与导电层13之间设置介质层15，利用介质层15可以防止导电层13与基底10的其他部件电连接。
在一些实施例中，半导体结构还包括第二保护结构40，第二保护结构40环绕第一保护结构30设置，且位于第一保护结构30和功能器件50之间；其中，第二保护结构40电绝缘于TSV结构20。第二保护结构40可以同样环绕TSV结构20设置，第二保护结构40可以为壁状的金属墙。
TSV结构的材质通常为铜等金属，铜的热膨胀系数较大，半导体结构在使用的过程中，TSV结构或者其他的功能器件会产生较大的热量，使得TSV结构受热膨胀，使得基底与TSV结构接触区域形成应力形变，影响半导体结构的性能，因此，本实施例在基底上形成第二保护结构，第二保护结构用于缓冲TSV结构对周边介质层的应力，提高半导体结构的性能。
如图3所示，本申请实施例第二方向提供了一种半导体结构的制备方法，包括如下的步骤：
步骤S100：提供基底，基底具有相邻设置的第一区域和第二区域。
基底可以为半导体基底，例如硅(Si)基底。当然本申请实施例中的并不是限定的，示例性的，基底还可以为锗(Ge)衬底、绝缘体上硅(Silicon on Insulator，简称SOI)、锗化硅(SiGe)衬底、碳化硅(SiC)或者氮化镓(GaN)基底等。
基底10具有相邻设置的第一区域11和第二区域12，其中，第一区域和第二区域的大小，可以根据实际的情况进行设计，本实施例在此不做具体的限定。
步骤S200：在第一区域内形成功能器件，可以利用常规的制备工艺在第一区域内形成晶体管或者电容器等器件。
其中，晶体管和电容器的制备工艺为现有技术，本实施例在此不再多加赘述。
步骤S300：在第二区域内形成TSV结构和第一保护结构；其中，第一保护结构环绕TSV结构，且TSV结构分别与功能器件和第一保护结构电连接。
示例性地，如图4所示，步骤S310：在基底10上形成第一光刻胶层，第一光刻胶层具有第一环形开口，第一环形开口暴露出第二区域12。
步骤S320：对暴露在第一环形开口内的第二区域12进行离子掺杂， 以形成第一阱区31。
其中，第一阱区31可以为P型阱区，示例性地，可以向暴露第一环形开口的第二区域12内掺杂硼离子，以使第二区域12形成P型阱区。
第一阱区31也可以为N型阱区，示例性地，可以向暴露在第一环形开口内的第二区域内掺杂磷离子或者砷离子，以形成N型阱区。
步骤S330：去除第一光刻胶层，可以利用清洗液去除第一光刻胶层。
步骤S340：在基底上形成第二光刻胶层，第二光刻胶层具有第二环形开口，第二环形开口在基底上的投影位于第一阱区内。
示例性地，可以采用涂覆工艺在基底上形成一定厚度的第二光刻胶层，然后通过曝光、显影或者刻蚀的工艺在第二光刻胶层内形成第二环形开口。
需要说明的是，本实施例中，第二环形开口的大小并不仅限于上述的方式，也可以是，第二环形开口在基底上的投影正好暴露出第一阱区。
步骤S350：对暴露在第二环形开口内的第一阱区进行掺杂，以形成第二阱区。
当第一阱区31为P型阱区时，第二阱区32为N型阱区，示例性地，可以向暴露在第二环形开口内的第一阱区31内掺杂磷离子或者砷离子，以形成N型阱区。
当第一阱区31为N型阱区时，第二阱区32为P型阱区，示例性地，可以向暴露在第二环形开口内的第一阱区内掺杂硼离子，以形成P型阱区。
步骤S360：去除第二光刻胶层，可以采用清洗液去除第二光刻胶层。
步骤S370：在基底上形成第三光刻胶层，第三光刻胶层具有第三环形开口，第三环形开口在基底上的投影位于第二阱区内。
需要说明的是，本实施例中，第三环形开口的大小并不仅限于上述的方式，也可以是，第三环形开口在基底上的投影正好暴露出第二阱区。
步骤S380：对暴露在第三环形开口内的第二阱区进行掺杂，以形成掺杂区，第一阱区、第二阱区以及掺杂区构成第一保护结构。
当第一阱区31为P型阱区，第二阱区32为N型阱区时，掺杂区33为P+掺杂区，示例性地，可以向暴露在第三环形开口内的第二阱区内掺杂硼离子，以形成P+掺杂区。
当第一阱区31为N型阱区，第二阱区32为P型阱区时，掺杂区33为N+掺杂区，示例性地，可以向暴露在第三环形开口内的第二阱区内掺杂 磷离子和砷离子，以形成N+掺杂区。
在一些实施例中，在提供基底的步骤中，还包括如下的步骤：
在基底上形成介质层，例如，可以通过化学气相沉积工艺或者物理气相沉积工艺在基底上形成介质层。
待形成介质层之后，在介质层内形成至少两个通孔，其中一个通孔暴露出第一保护结构，另一个通孔暴露出功能器件。
示例性地，可以图形化介质层，以在介质层内形成至少两个通孔，比如，介质层内设置有三个通孔，其中一个通孔暴露出功能器件，另外两个通孔暴露出第一保护结构。
待形成通孔之后，可以通过物理气相沉积工艺或者化学气相沉积工艺在通孔内沉积导电材质，以形成导电插塞。
最后，利用化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺等方法在介质层上形成导电层，且导电层至少覆盖在导电插塞，以实现导电层分别与第一保护结构和TSV结构的电连接。
待形成导电层之后，半导体结构的制备方法还包括：
首先，在基底背离导电层的表面上形成第四光刻胶层，第四光刻胶层具有开口图案，开口图案在基底表面上的投影位于第一保护结构的内部。
其次，利用等离子体刻蚀开口图案中的基底和介质层形成暴露导电层的TSV通孔，在形成TSV通孔的时候会产生电子，该电子会通过导电层传递至半导体结构的器件的过程中，会优先传递第一保护结构处，第一保护结构至少吸收部分的电子，降低对功能器件的损伤，提高了半导体结构的性能
最后，在TSV通孔内填充导电材料形成TSV结构。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方 式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (16)

  1. 一种半导体结构，包括：
    基底，所述基底具有相邻设置的第一区域和第二区域，所述第一区域设有功能器件；
    TSV结构，所述TSV结构设置在所述第二区域内，并与所述功能器件电连接；
    第一保护结构，所述第一保护结构环绕所述TSV结构设置，并与所述TSV结构电连接；
    其中，所述第一保护结构位于所述TSV结构和所述功能器件之间。
  2. 根据权利要求1所述的半导体结构，其中，还包括：
    TSV通孔，所述TSV结构形成在所述TSV通孔内；
    所述第一保护结构用于吸收形成所述TSV通孔时所产生的电流。
  3. 根据权利要求2所述的半导体结构，其中，所述第一保护结构包括环绕所述TSV结构设置的第一阱区、第二阱区以及掺杂区；
    所述第二阱区设置在所述第一阱区内；
    所述掺杂区设置在所述第二阱区上，所述掺杂区背离所述第二阱区的一端与所述TSV结构电连接。
  4. 根据权利要求3所述的半导体结构，其中，所述第一阱区为P型阱区、所述第二阱区为N型阱区以及所述掺杂区为P+掺杂区；
    或，所述第一阱区为N型阱区、所述第二阱区为P型阱区以及所述掺杂区为N+掺杂区。
  5. 根据权利要求3所述的半导体结构，其中，所述功能器件的有源区的深度不大于所述掺杂区的深度。
  6. 根据权利要求3所述的半导体结构，其中，所述第一阱区包括沿所述TSV结构的圆周方向延伸的第一环形区，所述第二阱区包括沿所述TSV结构的圆周方向延伸的第二环形区，所述掺杂区包括沿所述TSV结构的圆周方向延伸的第三环形区；
    所述第一环形区、所述第二环形区以及所述第三环形区的中心均位于所述TSV结构的轴线上；
    沿垂直于所述TSV结构的轴线方向，所述第三环形区的宽度小于所述 第二环形区的宽度，所述第二环形区的宽度小于所述第一环形区的宽度。
  7. 根据权利要求6所述的半导体结构，其中，所述第一环形区平行于基底表面的横截面形状包括多边形或者圆环形。
  8. 根据权利要求6所述的半导体结构，其中，所述第一环形区的宽度位于0.3μm～2μm之间。
  9. 根据权利要求8所述的半导体结构，其中，所述第一环形区与所述TSV结构的间距位于2μm～10μm之间。
  10. 根据权利要求1-4任一项所述的半导体结构，其中，所述基底上设置有导电层，所述TSV结构通过所述导电层分别与所述功能器件和所述第一保护结构电连接。
  11. 根据权利要求10所述的半导体结构，其中，所述基底与所述导电层之间还设置有介质层，所述介质层内设置有至少两个导电插塞，其中一个所述导电插塞的两端分别与所述导电层和所述功能器件直接相连，另一个所述导电插塞的两端分别与所述导电层和所述第一保护结构直接相连；
    所述TSV结构背离所述基底的一端贯穿所述介质层与所述导电层直接相连。
  12. 根据权利要求11所述的半导体结构，其中，还包括：
    第二保护结构，所述第二保护结构环绕所述第一保护结构设置，且位于所述第一保护结构和所述功能器件之间；
    其中，所述第二保护结构电绝缘于所述TSV结构。
  13. 一种半导体结构的制备方法，包括如下步骤：
    提供基底，所述基底具有相邻设置的第一区域和第二区域；
    在所述第一区域内形成功能器件；
    在所述第二区域内形成TSV结构和第一保护结构；
    其中，所述第一保护结构环绕所述TSV结构，且所述TSV结构分别与所述功能器件和所述第一保护结构电连接。
  14. 根据权利要求13所述的半导体结构的制备方法，其中，在所述第二区域内形成TSV结构和第一保护结构的步骤中包括：
    在所述基底上形成第一光刻胶层，所述第一光刻胶层具有第一环形开口，所述第一环形开口暴露出部分所述第二区域；
    对暴露在所述第一环形开口内的所述第二区域进行离子掺杂，以形成 第一阱区；
    去除所述第一光刻胶层；
    在所述基底上形成第二光刻胶层，所述第二光刻胶层具有第二环形开口，所述第二环形开口在所述基底上的投影位于所述第一阱区内；
    对暴露在所述第二环形开口内的所述第一阱区进行掺杂，以形成第二阱区；
    去除所述第二光刻胶层；
    在所述基底上形成第三光刻胶层，所述第三光刻胶层具有第三环形开口，所述第三环形开口在所述基底上的投影位于所述第二阱区内；
    对暴露在所述第三环形开口内的所述第二阱区进行掺杂，以形成掺杂区，所述第一阱区、第二阱区以及掺杂区构成所述第一保护结构。
  15. 根据权利要求14所述的半导体结构的制备方法，其中，还包括：
    在所述基底上形成介质层；
    在所述介质层内形成至少两个通孔，其中一个所述通孔暴露出所述第一保护结构，另一个所述通孔暴露出所述功能器件；
    在所述通孔形成导电插塞；
    在所述介质层上形成导电层，所述导电层至少覆盖在所述导电插塞上。
  16. 根据权利要求15所述的半导体结构的制备方法，其中，在所述第二区域内形成TSV结构步骤中，包括：
    在所述基底背离所述导电层的表面上形成第四光刻胶层，所述第四光刻胶层具有开口图案，所述开口图案在所述基底表面上的投影位于所述第一保护结构的内部；
    利用等离子体刻蚀所述开口图案中的所述基底和所述介质层形成暴露所述导电层的TSV通孔；
    在所述TSV通孔内填充导电材料形成所述TSV结构。
PCT/CN2021/120107 2021-05-21 2021-09-24 半导体结构及半导体结构的制备方法 WO2022241993A1 (zh)

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