WO2022241847A1 - 栅极驱动电路及显示面板 - Google Patents

栅极驱动电路及显示面板 Download PDF

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Publication number
WO2022241847A1
WO2022241847A1 PCT/CN2021/097681 CN2021097681W WO2022241847A1 WO 2022241847 A1 WO2022241847 A1 WO 2022241847A1 CN 2021097681 W CN2021097681 W CN 2021097681W WO 2022241847 A1 WO2022241847 A1 WO 2022241847A1
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WO
WIPO (PCT)
Prior art keywords
transistor
pull
drain
source
module
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Application number
PCT/CN2021/097681
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English (en)
French (fr)
Inventor
潘优
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武汉华星光电技术有限公司
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Priority to US17/623,630 priority Critical patent/US20240054941A1/en
Publication of WO2022241847A1 publication Critical patent/WO2022241847A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present application relates to the field of display technology, in particular to a gate drive circuit and a display panel.
  • Gate Driver On Array (Gate Driver On Array, array substrate row drive) technology is to use the array (Array) process of the thin film transistor display panel to make the Gate (gate) row scanning drive signal circuit on the Array substrate to realize the progressive scanning of the Gate.
  • the pull-up node in the gate drive circuit has a leakage condition, which easily leads to failure of the gate drive circuit.
  • the pull-up node in the gate drive circuit maintains the same potential for a long period of time, causing the pull-up node to be subjected to long-term stress, which reduces the reliability of the gate drive circuit.
  • the present application provides a gate driving circuit and a display panel to alleviate the technical problem of low reliability of the gate driving circuit.
  • the present application provides a gate driving circuit, the gate driving circuit includes a plurality of cascaded gate driving units, wherein the Nth level gate driving unit includes a high potential wiring, an Nth level scanning wiring , a first transistor, a second transistor, and a third transistor; the high-potential wiring is configured to transmit a high-potential signal; the Nth-level scanning wiring is configured to transmit an N-level scanning signal; the source/drain of the first transistor One is connected to the high potential trace; one of the source/drain of the second transistor is connected to the high potential trace; the gate of the third transistor is connected to the other source/drain of the first transistor and the second The other one of the source/drain of the transistor is connected, and one of the source/drain of the third transistor is connected to the Nth-level scanning wire.
  • the Nth level gate driving unit includes a high potential wiring, an Nth level scanning wiring , a first transistor, a second transistor, and a third transistor
  • the high-potential wiring is configured to transmit a high
  • the Nth-level gate driving unit further includes a first clock wiring, a second clock wiring, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the configuration of the first clock wiring To transmit the first clock signal; the second clock line is configured to transmit the second clock signal; one of the source/drain of the fourth transistor is connected to the gate of the fourth transistor and the first clock line; the fifth transistor One of the source/drain of the fourth transistor is connected to the other of the source/drain of the fourth transistor, and the other of the source/drain of the fifth transistor is connected to the source/drain of the first transistor Another connection; one of the source/drain of the sixth transistor to the gate of the sixth transistor and the second clock trace; one of the source/drain of the seventh transistor to the source of the sixth transistor The other one of the /drains is connected, and the other one of the source/drains of the seventh transistor is connected to the other one of the source/drains of the second transistor.
  • the Nth-level gate driving unit further includes a low-potential wiring, an eighth transistor, a ninth transistor, and a tenth transistor; the low-potential wiring is configured to transmit a low-potential signal; the source of the eighth transistor One of the /drains is connected to the high potential trace; the gate of the ninth transistor is connected to the other of the source/drain of the eighth transistor, and one of the source/drains of the ninth transistor is connected to the low potential Wiring connection, the other of the source/drain of the ninth transistor is connected to the N-th level scanning wire; the gate of the tenth transistor is connected to the other of the source/drain of the first transistor, and the tenth One of the source/drain of the transistor is connected to the low potential wiring, and the other of the source/drain of the tenth transistor is connected to the gate of the ninth transistor.
  • the low-potential wiring is configured to transmit a low-potential signal
  • the source of the eighth transistor One of the /drains is connected to the
  • the Nth-level gate drive unit further includes an eleventh transistor, one of the source/drain of the eleventh transistor is connected to the low potential wiring, and the source/drain of the eleventh transistor The other of the electrodes is connected to the other of the source/drain of the first transistor, and the gate of the eleventh transistor is connected to the other of the source/drain of the tenth transistor.
  • the Nth-level gate drive unit further includes a twelfth transistor, one of the source/drain of the twelfth transistor is connected to the low potential wire, and the source/drain of the twelfth transistor The other of the electrodes is connected to the other of the source/drain of the first transistor.
  • the gate driving unit of the Nth level further includes a first scanning wiring, a second scanning wiring, a forward scanning control wiring, a reverse scanning control wiring, a third clock wiring and a fourth Clock wiring; the first scanning wiring is configured to transmit the first scanning signal, and the first scanning wiring is connected to the gate of the first transistor; the second scanning wiring is configured to transmit the second scanning signal, and the second scanning wiring is connected to the gate of the first transistor.
  • the gate of the second transistor is connected; the forward scanning control wiring is configured to transmit a forward scanning control signal, and the forward scanning control wiring is connected to the gate of the fifth transistor; the reverse scanning control wiring is configured to transmit a reverse scanning control signal, the reverse scanning control line is connected to the gate of the seventh transistor; the third clock line is configured to transmit the third clock signal, and the third clock line is connected to the other of the source/drain of the third transistor connection; the fourth clock wiring is configured to transmit a fourth clock signal, and the fourth clock wiring is connected to the gate of the eighth transistor and the gate of the twelfth transistor.
  • the Nth-level gate drive unit further includes a thirteenth transistor, the gate of the thirteenth transistor is connected to the high potential wiring, and one of the source/drain of the thirteenth transistor is connected to the thirteenth transistor. The other of the source/drain of the first transistor is connected, and one of the source/drain of the thirteenth transistor is connected to the gate of the third transistor.
  • the present application provides a gate drive circuit, the gate drive circuit includes a plurality of cascaded gate drive units, wherein the Nth-level gate drive unit includes a pull-up control module, a pull-up output module, and a scanning Direction control module; the input terminal of the pull-up control module is used to access the high potential signal, and the control terminal of the pull-up control module is used to access the N-2 level scanning signal and the N+2 level scanning signal; the pull-up output module The control end of the pull-up control module is connected to the output end of the pull-up control module, the input end of the pull-up output module is used to access the N-level clock signal, and the output end of the pull-up output module is used to output the N-level scan signal; the scan direction control module The input end of the input terminal is used to access the N-2th level clock signal and the N+2th level clock signal, and the control terminal of the scanning direction control module is used to access the forward scanning control signal, reverse scanning control signal, N-2nd Level clock signal and
  • the gate driving unit of the Nth stage further includes a pull-down control module and a pull-down output module; +4-level clock signal; the control terminal of the pull-down output module is connected to the output terminal of the pull-down control module, the input terminal of the pull-down output module is used to access low potential signals, and the output terminal of the pull-down output module is connected to the output terminal of the pull-up output module .
  • the Nth-level gate drive unit further includes a first pull-down module; the input terminal of the first pull-down module is used to access a low potential signal, and the control terminal of the first pull-down module is connected The output terminals of the modules are connected, and the output terminals of the first pull-down module are connected with the output terminals of the pull-down control module.
  • the Nth-level gate drive unit further includes a second pull-down module; the input terminal of the second pull-down module is used to access a low potential signal, and the output terminal of the second pull-down module is connected to the output of the pull-up control module The terminal is connected, and the control terminal of the second pull-down module is connected with the output terminal of the pull-down control module.
  • the gate driving unit of the Nth level further includes a third pull-down module; the input terminal of the third pull-down module is used to access a low potential signal, and the output terminal of the third pull-down module is connected to the output of the pull-up control module terminal, and the control terminal of the third pull-down module is connected to the N+4th stage clock signal.
  • the Nth-level gate drive unit further includes a first voltage stabilizing module and/or a second voltage stabilizing module; one end of the first voltage stabilizing module is connected to the output end of the pull-up control module, and the first stabilizing module The other end of the voltage stabilization module is used to access the low potential signal; one end of the second voltage stabilization module is connected to the output end of the pull-down control module, and the other end of the second voltage stabilization module is used to access the low potential signal.
  • the Nth-level gate drive unit further includes at least one of a third voltage stabilizing module, a global pull-up module, and a global pull-down module; the input terminal of the third voltage stabilizing module and the output of the pull-up control module The control terminal of the third voltage stabilizing module is connected to the high potential signal, the output terminal of the third voltage stabilizing module is connected to the control terminal of the pull-up output module; the input terminal of the global pull-up module is used to access the global pull-up signal , the control terminal of the global pull-up module is used to access the global pull-up signal, the output terminal of the global pull-up module is connected to the output terminal of the pull-up output module; the input terminal of the global pull-down module is used to The control terminal of the module is used to access the global pull-down signal, and the output terminal of the global pull-down module is connected with the output terminal of the pull-up output module.
  • the pull-up control module includes a first thin film transistor and a second thin film transistor; one of the source/drain of the first thin film transistor is used to access a high potential signal, and the gate of the first thin film transistor Used to access the N-2th scan signal; one of the source/drain of the second thin film transistor is used to access the high potential signal, and the gate of the second thin film transistor is used to access the N+2th scan signal, the other of the source/drain of the second thin film transistor is connected to the other of the source/drain of the first thin film transistor and the output terminal of the scan direction control module.
  • the scan direction control module includes a forward scan control module and a reverse scan control module; the input terminal of the forward scan control module is used to access the N+2th level clock signal, and the The control terminal is used to access the N+2 level clock signal and the forward scanning control signal; the input terminal of the reverse scanning control module is used to access the N-2 level clock signal, and the control terminal of the reverse scanning control module is used to connect The N-2th level clock signal and the reverse scan control signal are input, and the output terminal of the reverse scan control module is connected with the output terminal of the forward scan control module and the output terminal of the pull-up control module.
  • the forward scanning control module includes a third thin film transistor and a fourth thin film transistor, one of the source/drain of the third thin film transistor is used to access the N+2th level clock signal, and the third thin film transistor The gate of the thin film transistor is used to access the N+2th level clock signal, the other of the source/drain of the third thin film transistor is connected to one of the source/drain of the fourth thin film transistor, and the fourth thin film transistor The gate of the transistor is used to access the forward scanning control signal, and the other of the source/drain of the fourth thin film transistor is connected to the output end of the pull-up control module; and/or, the reverse scanning control module includes a fifth The thin film transistor and the sixth thin film transistor, one of the source/drain of the fifth thin film transistor is used to access the N-2th level clock signal, and the gate of the fifth thin film transistor is used to access the N-2th level clock signal, the other of the source/drain of the fifth thin film transistor is connected to one of the source/drain
  • the pull-up output module includes a seventh thin film transistor; the gate of the seventh thin film transistor is connected to the other of the source/drain of the fourth thin film transistor and/or the source/drain of the sixth thin film transistor.
  • the other of the drains is connected; one of the source/drain of the seventh thin film transistor is used to access the Nth level clock signal; the other of the source/drain of the seventh thin film transistor T8 is used to output the first N level scanning signal.
  • the present application provides a display panel, which includes the gate driving circuit in any one of the above implementation manners.
  • the working phase of the display panel includes a row scanning phase; the row scanning phase includes a touch scanning phase; and the gate driving circuit works time-divisionally in the row scanning phase and the touch scanning phase.
  • the gate drive circuit and display panel provided by the present application can alleviate the failure of the gate drive circuit by connecting the input terminal of the pull-up control module to a high potential signal, thereby improving the reliability of the gate drive circuit; at the same time, Controlling the scanning direction control module by the clock signal can realize the alternating forward and reverse scanning, the output terminal of the scanning direction control module is connected with the output terminal of the pull-up control module, and the potential of the output terminal of the pull-up control module can be changed alternately, which alleviates the problem of pulling up. Pulling the stress on the output end of the control module to maintain the same potential for a long time further improves the reliability of the gate drive circuit.
  • FIG. 1 is a schematic diagram of a first structure of a gate driving circuit provided by an embodiment of the present application.
  • FIG. 2 is a timing diagram of the gate driving circuit shown in FIG. 1 .
  • FIG. 3 is a schematic diagram of a second structure of the gate driving circuit provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a third structure of the gate driving circuit provided by the embodiment of the present application.
  • FIG. 5 is a timing diagram of the gate driving circuit shown in FIG. 4 .
  • FIG. 6 is another timing diagram of the gate driving circuit shown in FIG. 4 .
  • this embodiment provides a gate drive circuit
  • the gate drive circuit includes a plurality of cascaded gate drive units, and in one of the gate drive units, the positive
  • the scan control signal U2D is connected to one of the source/drain of the transistor NT1 and the gate of the transistor NT3; the gate of the transistor NT1 is connected to the gate scan signal Gate (N ⁇ 2).
  • One of the /drains is connected and used as a pull-up node Q;
  • the second end of the capacitor C1 is connected to the low potential signal VGL;
  • the gate of the transistor NT7 is connected to the high potential signal VGH;
  • the source/drain of the transistor NT7 The other is connected to the gate of the transistor NT9; one of the source/drain of the transistor NT9 is connected to the clock signal CKN;
  • the other of the source/drain of the transistor NT9 is connected to the source/drain of the transistor NT10
  • One, the other of the source/drain of the transistor NT11 , and one of the source/drain of the transistor NT13 are connected, and output a gate scan signal Gate(N).
  • One of the source/drain of the transistor NT3 is connected to the clock signal CKN+2; the other of the source/drain of the transistor NT3 is connected to the other of the source/drain of the transistor NT4, the gate of the transistor NT8 And one of the source/drain of the transistor NT14 is connected; one of the source/drain of the transistor NT4 is connected with the clock signal CKN-2; one of the source/drain of the transistor NT8 is connected with the high potential signal VGH .
  • the other of the source/drain of the transistor NT8 and one of the source/drain of the transistor NT6, the gate of the transistor NT5, the second end of the capacitor C2, one of the source/drain of the transistor NT12, and The gate of the transistor NT10 is connected to serve as a pull-down node P; the first end of the capacitor C2 is connected to the low potential signal VGL.
  • the reverse scan control signal D2U is connected to one of the gate of the transistor NT4 and the source/drain of the transistor NT2; the other of the source/drain of the transistor NT2 is connected to the pull-up node Q and the gate of the transistor NT6 .
  • the low potential signal VGL is connected to the other of the source/drain of the transistor NT5, the other of the source/drain of the transistor NT6, the other of the source/drain of the transistor NT12, and the source/drain of the transistor NT14.
  • the other of the drains, the other of the sources/drains of the transistor NT10 , and the other of the source/drains of the transistor NT13 are connected.
  • the global control signal Gas1 is connected to one of the gate of the transistor NT12, the gate of the transistor NT14, the gate of the transistor NT11, and the source/drain of the transistor NT11.
  • the global control signal Gas2 is connected to the gate of the transistor NT13.
  • the gate of the transistor NT2 is connected to the scan signal Gate (N+2).
  • the leakage path existing at the node Q is pulled up.
  • the transistor NT1 when scanning forward, the transistor NT1 is in a relatively serious NBTS (Negative-Bias-voltage and Temperature Stress, negative bias and temperature stress) state, in this state, the voltage Vds between the drain and source of transistor NT1 is equal to the potential difference between the high potential signal VGH and the low potential signal VGL, long-term In operation, the threshold voltage Vth of the transistor NT1 will have a negative drift or its off-current I-off will increase. Entering the pause period of TP (Touch Panel, touch display panel), that is, the gate drive circuit needs to realize the function of suspending scanning during the display period.
  • TP Touch Panel, touch display panel
  • the potential of the pull-up node Q is maintained at the level of the high potential signal VGH, and the potential of the pull-down node P is maintained at the potential of the low potential signal VGL.
  • one of the source/drain of the transistor NT1 is connected to the forward scan control signal U2D.
  • the forward scan control signal U2D is at a high potential consistent with the potential of the high potential signal VGH, and the node is pulled up Q cannot leak current through transistor NT1.
  • the forward scan control signal U2D becomes a low potential consistent with the potential of the low potential signal VGL.
  • the pull-up node Q can form a leakage path through the transistor NT1. Therefore, the pull-up node Q and The quasi-potential of the potential of the high-potential signal VGH is pulled down, causing the gate drive circuit to fail during the TP stop period, thereby causing a technical problem about the reliability of the gate drive circuit.
  • the above-mentioned gate drive circuit is under the control of the corresponding initial signal STV and the clock signal, wherein the clock signal can be clock signal CK (1), clock signal CK (3), clock signal CK (5) , clock signal CK (7), etc.
  • the above-mentioned gate drive circuit can generate a corresponding scanning signal, for example, the scanning signal can be scanning signal G (1), scanning signal G (3), scanning signal G (N-2) , scan signal G(N) and scan signal G(N+2), etc.
  • the potential of the Nth pull-up node Q(N) and the Nth pull-down node P(N) of the above-mentioned gate drive circuit Potentials are described below.
  • the gate drive unit of level N in one frame that is, from the rising edge of the scan signal Gate (N-2) to the scan signal Gate (N+ 2)
  • the potential of the Nth-level pull-up node Q(N) is kept at the same potential as the high-potential signal VGH, and in the rest of the time, the potential of the N-th level pull-up node Q(N) is Maintaining a potential consistent with the low level signal VGL causes transistor NT6 to be subjected to NBTS for a long time.
  • the potential of the Nth level pull-down node P (N) is kept at the same potential as the low potential signal VGL, and the rest During this time, the potential of the Nth-level pull-down node P(N) remains at the same potential as the high potential signal VGH, causing the transistor NT5 to be subjected to a long-term PBTS (Positive-Bias-voltage and Temperature Stress, positive bias and temperature stress) state.
  • PBTS Personal-Bias-voltage and Temperature Stress, positive bias and temperature stress
  • this embodiment provides a gate drive circuit
  • the gate drive circuit includes a plurality of cascaded gate drive units, wherein the Nth gate
  • the pole drive unit includes a pull-up control module 10, a pull-up output module 20, and a scan direction control module 30;
  • the input terminal of the pull-up control module 10 is used for connecting the high potential signal VGH, and the control terminal of the pull-up control module 10 is used for connecting Input the N-2 level scan signal G(N-2) and the N+2 level scan signal G(N+2);
  • the control terminal of the pull-up output module 20 is connected to the output terminal of the pull-up control module 10, and the pull-up
  • the input terminal of the output module 20 is used to access the N-level clock signal CK(N), and the output terminal of the pull-up output module 20 is used to output the N-level scanning signal G(N);
  • the input terminal of the scanning direction control module 30 is used for In order to access the N-2th level clock signal CK (N-
  • the high potential signal VGH can be connected to the input terminal of the pull-up control module 10, so that the work failure of the gate drive circuit can be alleviated, thereby improving the working efficiency of the gate drive circuit.
  • the output terminal of scanning direction control module 30 is connected with the output terminal of pull-up control module 10, the output of pull-up control module 10
  • the terminal potentials can be changed alternately, which alleviates the stress on the output terminal of the pull-up control module 10 to maintain the same potential for a long time, and further improves the reliability of the gate drive circuit.
  • N may be a positive integer, for example, 1, 2, 3, 8 and so on.
  • the pull-up control module 10 includes a first thin film transistor T1 and a second thin film transistor T2; one of the source/drain of the first thin film transistor T1 is used to connect the high Potential signal VGH, the gate of the first thin film transistor T1 is used to access the N-2th level scanning signal G (N-2); one of the source/drain of the second thin film transistor T2 is used to access the high potential Signal VGH, the gate of the second thin film transistor T2 is used to access the N+2th level scanning signal G (N+2), the other of the source/drain of the second thin film transistor T2 is connected with the first thin film transistor T1 The other of the source/drain is connected to the output terminal of the scan direction control module 30 .
  • the node Q(N) may be at least one of the output terminal of the pull-up control module 10 , the output terminal of the scan direction control module 30 , the control terminal of the pull-up output module 20 and the input terminal of the third voltage stabilizing module 110 .
  • the scan direction control module 30 includes a forward scan control module and a reverse scan control module; the input terminal of the forward scan control module is used to access the N+2th level clock signal CK (N+2) , the control terminal of the forward scanning control module is used to access the clock signal CK (N+2) of the N+2 level and the forward scanning control signal U2D; the input terminal of the reverse scanning control module is used to access the N-2 level
  • the clock signal CK (N-2) the control terminal of the reverse scan control module is used to access the N-2 level clock signal CK (N-2) and the reverse scan control signal D2U, the output terminal of the reverse scan control module It is connected with the output end of the forward scanning control module and the output end of the pull-up control module 10 .
  • the Nth-level gate drive unit can be driven to perform forward scanning through the N+2th level clock signal CK (N+2); through the N-2th level clock signal CK (N -2) It can drive the Nth-level gate drive unit to perform reverse scanning.
  • the clock signal CK(N+2) of the N+2th stage and the clock signal CK(N-2) of the N-2nd stage will be transmitted to the node Q(N), and the potential of the node Q(N) can be changed according to The corresponding clock signal is used for potential conversion, which can alleviate the reliability problem caused by the stress or temperature stress on the node Q(N) that needs to withstand the same potential for a long time.
  • the forward scanning control module includes a third thin film transistor T12 and a fourth thin film transistor T13, and one of the source/drain of the third thin film transistor T12 is used to connect to the first The N+2 level clock signal CK (N+2), the gate of the third thin film transistor T12 is used to access the N+2 level clock signal CK (N+2), the source/drain of the third thin film transistor T12 The other one is connected to one of the source/drain of the fourth thin film transistor T13, the gate of the fourth thin film transistor T13 is used to access the forward scanning control signal U2D, the source/drain of the fourth thin film transistor T13 The other pole is connected to the output terminal of the pull-up control module 10.
  • the reverse scan control module includes a fifth thin film transistor T14 and a sixth thin film transistor T15, one of the source/drain of the fifth thin film transistor T14 is used to access the N-2th level clock signal CK (N-2), the gate of the fifth thin film transistor T14 is used to access the N-2th stage clock signal CK (N-2), the other of the source/drain of the fifth thin film transistor T14 is connected to the second One of the sources/drains of the six thin film transistors T15 is connected, the gate of the sixth thin film transistor T15 is used to access the reverse scanning control signal D2U, and the other of the source/drains of the sixth thin film transistor T15 is connected to The output end of the pull-up control module 10 is connected.
  • the pull-up output module 20 includes a seventh thin film transistor T8; the gate of the seventh thin film transistor T8 is connected to the other of the source/drain of the first thin film transistor T1; the seventh thin film transistor T8 One of the sources/drains of T8 is used to access the N-level clock signal CK(N); the other of the source/drain of the seventh thin film transistor T8 is used to output the N-level scanning signal G(N) .
  • the Nth level gate drive unit further includes a pull-down control module 40 and a pull-down output module 50;
  • the control terminal of the pull-down output module 50 is connected to the output terminal of the pull-down control module 40, and the input terminal of the pull-down output module 50 is used to access the low potential signal VGL,
  • the output end of the pull-down output module 50 is connected to the output end of the pull-up output module 20 .
  • At least one of the control terminal of the pull-down output module 50 and the output terminal of the pull-down control module 40 can serve as the node P(N).
  • the pull-down control module 40 includes an eighth thin film transistor T4; the gate of the eighth thin film transistor T4 is used to access the N+4th level clock signal CK (N+4); the source/drain of the eighth thin film transistor T4 One of them is used to access the high potential signal VGH; the other of the source/drain of the eighth thin film transistor T4 can serve as the node P(N).
  • the pull-down output module 50 includes the ninth thin film transistor T9; the gate of the ninth thin film transistor T9 is connected to the other of the source/drain of the eighth thin film transistor T4; One is used to access the low potential signal VGL; the other of the source/drain of the ninth thin film transistor T9 is connected to the other of the source/drain of the seventh thin film transistor T8.
  • the Nth level gate drive unit further includes a first pull-down module 60; the input terminal of the first pull-down module 60 is used to access the low potential signal VGL, and the control terminal of the first pull-down module 60 It is connected with the output terminal of the pull-up control module 10 , and the output terminal of the first pull-down module 60 is connected with the output terminal of the pull-down control module 40 .
  • the first pull-down module 60 includes a tenth thin film transistor T6; the other of the gate of the tenth thin film transistor T6 and the source/drain of the first thin film transistor T1 and the source/drain of the second thin film transistor T2 One of the source/drain of the tenth thin film transistor T6 is used to access the low potential signal VGL; the other of the source/drain of the tenth thin film transistor T6 is connected with the eighth thin film transistor Another connection in the source/drain of T4.
  • the potential of the node Q(N) can turn on the tenth thin film transistor T6, the potential of the node P(N) is pulled down to the potential of the low potential signal VGL, for example, when the tenth thin film transistor T6 is In the case of an N-channel TFT, the high potential of the node Q(N) can pull down the potential of the node P(N) to the potential of the low potential signal VGL.
  • the potential of node P(N) will also be adjusted to the corresponding potential, thereby alleviating the situation that the potential of node P(N) remains at the same potential for a long time, thereby improving
  • the tenth thin film transistor T6 withstands the continuous NBTS condition for a long time, which can improve the reliability of the gate driving circuit.
  • the Nth level gate drive unit further includes a second pull-down module 70; the input terminal of the second pull-down module 70 is used to access the low potential signal VGL, and the output terminal of the second pull-down module 70 is connected to the pull-up The output terminal of the control module 10 is connected, and the control terminal of the second pull-down module 70 is connected with the output terminal of the pull-down control module 40 .
  • the second pull-down module 70 includes the eleventh thin film transistor T5; the gate of the eleventh thin film transistor T5 is connected to the other of the source/drain of the eighth thin film transistor T4; the source of the eleventh thin film transistor T5 One of the electrodes/drains is used to access the low potential signal VGL; the other of the source/drain of the eleventh thin film transistor T5 is connected with the other of the source/drain of the first thin film transistor T1 and the second The other of the source/drain of the two thin film transistors T2 is connected.
  • the potential of the node P(N) can turn on the eleventh TFT T5
  • the potential of the node Q(N) is pulled down to the potential of the low potential signal VGL
  • the eleventh TFT When T5 is an N-channel thin film transistor, the high potential of the node P(N) can pull down the potential of the node Q(N) to the potential of the low potential signal VGL.
  • the eleventh thin film transistor T5 withstands continuous BTS (Bias-voltage and Temperature Stress, bias voltage and temperature stress) can improve the reliability of the gate drive circuit.
  • the Nth level gate drive unit further includes a third pull-down module 80; the input terminal of the third pull-down module 80 is used to access the low potential signal VGL, and the output terminal of the third pull-down module 80 is connected to the pull-up The output end of the control module 10 is connected, and the control end of the third pull-down module 80 is connected to the N+4th stage clock signal CK (N+4).
  • the third pull-down module 80 includes a twelfth thin film transistor T3; the gate of the twelfth thin film transistor T3 is used to access the N+4th level clock signal CK (N+4); the twelfth One of the source/drain of the thin film transistor T3 is used to access the low potential signal VGL; one of the source/drain of the twelfth thin film transistor T3 and one of the source/drain of the first thin film transistor T1 The other, the other of the source/drain of the second thin film transistor T2, the other of the source/drain of the fourth thin film transistor T13, and the other of the source/drain of the sixth thin film transistor T15 At least one connection in .
  • the Nth-level gate drive unit further includes a first voltage stabilizing module 90 and/or a second voltage stabilizing module 100; one end of the first voltage stabilizing module 90 is connected to the output end of the pull-up control module 10 , the other end of the first voltage stabilizing module 90 is used to access the low potential signal VGL; one end of the second voltage stabilizing module 100 is connected to the output end of the pull-down control module 40, and the other end of the second voltage stabilizing module 100 is used to access Low potential signal VGL.
  • the first voltage stabilizing module 90 includes a first capacitor C1; one end of the first capacitor C1 is connected to the other of the source/drain of the first thin film transistor T1 and the source of the second thin film transistor T2 At least one of the other of the /drains is connected; the other end of the first capacitor C1 is used to access the low potential signal VGL.
  • the first voltage stabilizing module 90 is beneficial to stabilizing the potential of the node Q(N).
  • the second voltage stabilizing module 100 includes a second capacitor C2; one end of the second capacitor C2 is connected to the other of the source/drain of the eighth thin film transistor T4; the other end of the first capacitor C1 Used to access the low potential signal VGL.
  • the second voltage stabilizing module 100 is beneficial to stabilizing the potential of the node P(N).
  • the Nth level gate drive unit further includes at least one of the third voltage stabilizing module 110, the global pull-up module 120 and the global pull-down module 130;
  • the output terminal of the control module 10 is connected, the control terminal of the third voltage stabilizing module 110 is connected with the high potential signal VGH, the output terminal of the third voltage stabilizing module 110 is connected with the control terminal of the pull-up output module 20;
  • the global pull-up module 120 The input terminal is used to access the global pull-up signal GAS1, the control terminal of the global pull-up module 120 is used to access the global pull-up signal GAS1, and the output terminal of the global pull-up module 120 is connected to the output terminal of the pull-up output module 20;
  • the input terminal of the pull-down module 130 is used to connect to the low potential signal VGL, the control terminal of the global pull-down module 130 is used to connect to the global pull-down signal GAS2 , and the output terminal of the global pull-down module 130 is connected to the output terminal of the pull-up output module 20 .
  • the third voltage stabilizing module 110 includes a thirteenth thin film transistor T7; one of the source/drain of the thirteenth thin film transistor T7 can be connected with the other of the source/drain of the first thin film transistor T1 and the thirteenth thin film transistor T7. At least one of the other of the source/drain of the second thin film transistor T2 is connected; the other of the source/drain of the thirteenth thin film transistor T7 may be connected to the gate of the seventh thin film transistor T8; The gates of the three thin film transistors T7 are used to access the high potential signal VGH.
  • the thirteenth thin film transistor T7 when the potential of one of the source/drain of the thirteenth thin film transistor T7 is equal to the potential of the other source/drain of the thirteenth thin film transistor T7, then the thirteenth thin film transistor T7 The transistor T7 is turned off or cut off, and at this time, it is beneficial to maintain the potential of one of the source/drain of the thirteenth thin film transistor T7 and/or the potential of the other of the source/drain of the thirteenth thin film transistor T7 .
  • the global pull-up module 120 may include a fourteenth thin film transistor T10; one of the sources/drains of the fourteenth thin film transistor T10 is used to access the global pull-up signal GAS1; the source/drain of the fourteenth thin film transistor T10 The other of the poles is connected to the other of the source/drain of the seventh thin film transistor T8; the gate of the fourteenth thin film transistor T10 is used to access the global pull-up signal GAS1.
  • the global pull-down module 130 may include a fifteenth thin film transistor T11; one of the source/drain of the fifteenth thin film transistor T11 is used to access the low potential signal VGL; one of the source/drain of the fifteenth thin film transistor T11 The other one is connected to the other source/drain of the seventh thin film transistor T8; the gate of the fifteenth thin film transistor T11 is used to access the global pull-down signal GAS2.
  • the gate driving circuit can generate corresponding scanning signals under the control of the corresponding initial signal STV and the clock signal.
  • the clock signal may be, but not limited to, the first clock signal CK( 1 ), the third clock signal CK( 3 ), the fifth clock signal CK( 5 ), the seventh clock signal CK( 7 ) and the like.
  • the scanning signal can be, but not limited to, the first level scanning signal G(1), the third level scanning signal G(3), the N-2th level scanning signal G(N-2), the Nth level scanning signal G( N) and the N+2-th level scan signal G(N+2), etc.
  • potential states of nodes Q(N) and P(N) can be as follows:
  • the potential of the node Q(N) can maintain a high potential;
  • the potential of the node P(N) is maintained at a low potential.
  • the potential of the node Q(N) can be maintain a high potential; correspondingly, the potential of the node P(N) maintains a low potential.
  • the potential of the node Q(N) can be maintain a high potential; correspondingly, the potential of the node P(N) maintains a low potential.
  • the potential of the node Q(N) can be maintained High potential;
  • the potential of node P(N) is maintained at low potential.
  • node Q(N) always has a corresponding low potential between two adjacent high potentials.
  • node P(N) always has a corresponding high potential between two adjacent low potentials.
  • the potential state of any one of the node Q(N) and the node P(N) can always appear alternately in different potential states of high potential and low potential, and the frequency of alternating occurrence has also been increased, so that The corresponding thin film transistor is relieved of the bias voltage caused by the same potential state for a long time, that is, the temperature stress.
  • the bias voltage can be but not limited to a positive bias voltage or a negative bias voltage, thereby improving the reliability of the gate drive circuit.
  • this embodiment provides a gate driving circuit
  • the gate driving circuit includes a plurality of cascaded gate driving units, wherein the Nth-level gate driving unit includes high potential wiring, The Nth-level scanning wiring, the first transistor, the second transistor, and the third transistor; the high-potential wiring is configured to transmit a high-potential signal VGH; the N-level scanning wiring is configured to transmit an N-level scanning signal G(N); One of the source/drain of the first transistor is connected to the high potential trace; one of the source/drain of the second transistor is connected to the high potential trace; the gate of the third transistor is connected to the source of the first transistor The other of the electrodes/drains is connected to the other of the source/drains of the second transistor, and one of the source/drains of the third transistor is connected to the Nth-level scanning wire.
  • one of the source/drain of the first transistor and one of the source/drain of the second transistor are connected to the high potential wiring, which can reduce or prevent the third Leakage current occurs on the gate of the transistor, which alleviates the failure problem of the gate drive circuit and improves the reliability of the gate drive circuit at the same time.
  • the first transistor may be a first thin film transistor T1.
  • the second transistor may be a second thin film transistor T2.
  • the third transistor may be the seventh thin film transistor T8.
  • the Nth-level gate drive unit further includes a first clock wiring, a second clock wiring, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; the configuration of the first clock wiring To transmit the first clock signal; the second clock line is configured to transmit the second clock signal; one of the source/drain of the fourth transistor is connected to the gate of the fourth transistor and the first clock line; the fifth transistor One of the source/drain of the fourth transistor is connected to the other of the source/drain of the fourth transistor, and the other of the source/drain of the fifth transistor is connected to the source/drain of the first transistor Another connection; one of the source/drain of the sixth transistor to the gate of the sixth transistor and the second clock trace; one of the source/drain of the seventh transistor to the source of the sixth transistor The other one of the /drains is connected, and the other one of the source/drains of the seventh transistor is connected to the other one of the source/drains of the second transistor.
  • the potential of the other of the source/drain of the first transistor and the potential of the other of the source/drain of the second transistor are controlled through the first clock wiring and the second clock wiring,
  • the potential of the other of the source/drain of the first transistor and the potential of the other of the source/drain of the second transistor can be alternately changed, relieving the potential of the other of the source/drain of the first transistor.
  • the potential of the source/drain of the second transistor and the stress of the other one of the source/drain of the second transistor maintaining the same potential for a long time further improve the reliability of the gate drive circuit.
  • the first clock signal may be, but not limited to, the N+2th stage clock signal CK(N+2).
  • the second clock signal may be, but not limited to, the N-2th stage clock signal CK(N-2).
  • the fourth transistor may be the third thin film transistor T12.
  • the fifth transistor may be a fourth thin film transistor T13.
  • the sixth transistor may be the fifth thin film transistor T14.
  • the seventh transistor may be the sixth thin film transistor T15.
  • the Nth-level gate driving unit further includes a low-potential wiring, an eighth transistor, a ninth transistor, and a tenth transistor; the low-potential wiring is configured to transmit a low-potential signal VGL; the source of the eighth transistor One of the poles/drains is connected to the high potential trace; the gate of the ninth transistor is connected to the other source/drain of the eighth transistor, and one of the source/drains of the ninth transistor is connected to the low The other of the source/drain of the ninth transistor is connected to the N-th level scanning wire; the gate of the tenth transistor is connected to the other of the source/drain of the first transistor, and the other of the source/drain of the first transistor is connected One of the sources/drains of the ten transistors is connected to the low potential wiring, and the other of the source/drains of the tenth transistor is connected to the gate of the ninth transistor.
  • the tenth transistor can realize the corresponding alternation of the potential of the source/drain of the eighth transistor based on the alternation of the other of the source/drain of the first transistor, It can improve the stress effect on the potential of the other of the source/drain of the eighth transistor to maintain the same potential for a long time, and further improve the reliability of the gate driving circuit.
  • the eighth transistor may be an eighth thin film transistor T4.
  • the ninth transistor may be a ninth thin film transistor T9.
  • the tenth transistor may be a tenth thin film transistor T6.
  • the Nth-level gate drive unit further includes an eleventh transistor, one of the source/drain of the eleventh transistor is connected to a low potential wire, and the source/drain of the eleventh transistor The other of the electrodes is connected to the other of the source/drain of the first transistor, and the gate of the eleventh transistor is connected to the other of the source/drain of the tenth transistor.
  • the potential of the other of the source/drain of the eleventh transistor can be alternately changed based on the potential of the other of the source/drain of the first transistor, which can improve the source voltage of the eleventh transistor.
  • the potential of the other electrode/drain maintains the same potential for a long period of time due to stress, which further improves the reliability of the gate drive circuit.
  • the eleventh transistor may be the eleventh thin film transistor T5.
  • the Nth-level gate drive unit further includes a twelfth transistor, one of the source/drain of the twelfth transistor is connected to the low potential wire, and the source/drain of the twelfth transistor The other of the electrodes is connected to the other of the source/drain of the first transistor.
  • the potential of the other of the source/drain of the twelfth transistor can be alternately changed based on the potential of the other of the source/drain of the first transistor, which can improve the source voltage of the twelfth transistor.
  • the potential of the other electrode/drain maintains the same potential for a long period of time due to stress, which further improves the reliability of the gate drive circuit.
  • the twelfth transistor may be the twelve thin film transistor T3.
  • the Nth level gate driving unit further includes a first scanning wiring, a second scanning wiring, a forward scanning control wiring, a reverse scanning control wiring, a third clock wiring and a fourth Clock wiring; the first scanning wiring is configured to transmit the first scanning signal, and the first scanning wiring is connected to the gate of the first transistor; the second scanning wiring is configured to transmit the second scanning signal, and the second scanning wiring is connected to the gate of the first transistor.
  • the gate of the second transistor is connected; the forward scanning control wiring is configured to transmit a forward scanning control signal, and the forward scanning control wiring is connected to the gate of the fifth transistor; the reverse scanning control wiring is configured to transmit a reverse scanning control signal, the reverse scan control line is connected to the gate of the seventh transistor; the third clock line is configured to transmit the third clock signal, and the third clock line is connected to the other of the source/drain of the third transistor connection; the fourth clock wiring is configured to transmit a fourth clock signal, and the fourth clock wiring is connected to the gate of the eighth transistor and the gate of the twelfth transistor.
  • the first scan signal may be the N-2th level scan signal G(N-2).
  • the second scan signal may be the N+2th level scan signal G(N+2).
  • the third clock signal may be the Nth stage clock signal CK(N).
  • the fourth clock signal may be an N+4th stage clock signal CK(N+4).
  • the Nth-level gate drive unit further includes a thirteenth transistor, the gate of the thirteenth transistor is connected to the high potential wiring, and one of the source/drain of the thirteenth transistor is connected to the thirteenth transistor. The other of the source/drain of the first transistor is connected, and one of the source/drain of the thirteenth transistor is connected to the gate of the third transistor.
  • the thirteenth transistor is useful for maintaining and isolating the potential of the other of the source/drain of the first transistor, the potential of the gate of the third transistor.
  • the thirteenth transistor may be the thirteenth thin film transistor T7.
  • the first thin film transistor T1 to the fifteenth thin film transistor T11 may be, but not limited to, N-channel thin film transistors, and may also be P-channel thin film transistors.
  • this embodiment provides a display panel, which includes the gate driving circuit in any one of the above embodiments.
  • the failure of the gate drive circuit can be alleviated, thereby improving the reliability of the gate drive circuit.
  • control the scanning direction control module 30 by the clock signal and can realize the alternate carrying out of positive and negative scanning, the output terminal of scanning direction control module 30 is connected with the output terminal of pull-up control module 10, the output terminal potential of pull-up control module 10 Alternate conversion is possible, which relieves the stress on the output terminal of the pull-up control module 10 for a long period of time to maintain the same potential, and further improves the reliability of the gate drive circuit.
  • the working phase of the display panel includes a row scanning phase; the row scanning phase includes a touch scanning phase; and the gate driving circuit works time-divisionally in the row scanning phase and the touch scanning phase.
  • the row scanning stage there will be a scanning pause stage during the row scanning stage to perform the touch scanning stage, and the row scanning stage will be performed after the touch scanning stage is completed.
  • the in-cell touch screen technology Specifically, in the in-cell (In-Cell) touch screen technology, several rows of pixels in the display area (AA, Active Area) are displayed (display) During the scanning process, the display scanning can be stopped first, and at least part of the touch (Touch) electrodes in the AA area can be scanned, and then the display scanning can be continued, and so on, and the display scanning and touch scanning can be repeated multiple times for cross operation , the number of times can be determined according to the specific product, until the display scan of a frame and the touch scan of the full screen are completed.
  • AA display area
  • Touch touch electrodes in the AA area
  • the display scanning and touch scanning can be repeated multiple times for cross operation , the number of times can be determined according to the specific product, until the display scan of a frame and the touch scan of the full screen are completed.
  • Figure 6 shows the N-2th clock signal CK (N-2), the Nth clock signal, the N+2th clock signal, the N-2th level scanning signal G (N-2), the Nth level Schematic diagram of waveforms of scanning signal G(N), scanning signal G(N+2) of stage N+2, node Q(N) and node P(N).
  • the corresponding clock signal can be used to control the gate driving circuit to stop the work of display scanning.
  • the Nth-level gate drive unit outputs the Nth-level scanning signal G(N)
  • it enters the mid-stop period stop display scanning and start touch scanning
  • no pulses can be generated through the corresponding clock signal ( Pulse)
  • realize the stop output of the gate drive circuit that is, stop the display scan.
  • the potential of the global pull-down signal GAS2 changes from a low potential to a high potential
  • the global pull-down module 130 ie the fifteenth TFT T11 is turned on, and each scan signal output by the gate driving circuit is at a low potential.
  • the N+2th clock signal starts to output corresponding pulses, and the corresponding gate driving unit can continue to perform normal display scanning.
  • the stop period will last for a long period of time, which is critical for the key nodes in the gate drive circuit, such as node Q(N) and node P(N), the potentials of the two It is easy to have leakage or maintain the same potential for a long time. Therefore, for the gate drive circuit with an interruption period, the gate drive circuit and display panel provided in this embodiment can better overcome leakage and some thin film transistors. It is prone to lower reliability conditions caused by bias voltage and temperature stress.
  • the bias voltage and temperature stress of the thin film transistor will be more obvious during the double 85 test, wherein the double 85 test refers to an aging test performed in an environment with a temperature of 85°C and a humidity of 85%. This is because the environmental conditions of temperature 85°C and humidity 85% are worse than the environment of normal temperature and normal humidity. Therefore, the bias voltage and temperature stress of the thin film transistor will also cause the gate drive circuit to appear worse. reliability performance.

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Abstract

一种栅极驱动电路及显示面板，栅极驱动电路包括多个级联的栅极驱动单元，其中，第N级栅极驱动单元包括上拉控制模块（10）、上拉输出模块（20）以及扫描方向控制模块（30）；通过时钟信号（CK（N-2）、CK（N+2））控制扫描方向控制模块（30）可以实现正反向扫描的交替进行，扫描方向控制模块（30）的输出端与上拉控制模块（10）的输出端连接，上拉控制模块（10）的输出端电位可以交替变换。

Description

栅极驱动电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种栅极驱动电路及显示面板。
 背景技术
栅极驱动（Gate Driver On Array，阵列基板行驱动）技术为利用薄膜晶体管显示面板的阵列（Array）制程，制作Gate（栅极）行扫描驱动信号电路于Array基板上，实现对Gate逐行扫描的驱动方式的一项技术。
但是，栅极驱动电路中的上拉节点存在漏电状况，容易导致栅极驱动电路的工作失效。同时，栅极驱动电路中的上拉节点在较长一段时间内保持同一电位，致使该上拉节点受到长期的应力作用，降低了栅极驱动电路的可靠性。
 技术问题
本申请提供一种栅极驱动电路及显示面板，以缓解栅极驱动电路的可靠性较低的技术问题。
 技术解决方案
第一方面，本申请提供一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动单元，其中，第N级栅极驱动单元包括高电位走线、第N级扫描走线、第一晶体管、第二晶体管以及第三晶体管；高电位走线配置为传输高电位信号；第N级扫描走线配置为传输第N级扫描信号；第一晶体管的源极/漏极中的一个与高电位走线连接；第二晶体管的源极/漏极中的一个与高电位走线连接；第三晶体管的栅极与第一晶体管的源极/漏极中的另一个和第二晶体管的源极/漏极中的另一个连接，第三晶体管的源极/漏极中的一个与第N级扫描走线连接。
在其中一些实施方式中，第N级栅极驱动单元还包括第一时钟走线、第二时钟走线、第四晶体管、第五晶体管、第六晶体管以及第七晶体管；第一时钟走线配置为传输第一时钟信号；第二时钟走线配置为传输第二时钟信号；第四晶体管的源极/漏极中的一个与第四晶体管的栅极和第一时钟走线连接；第五晶体管的源极/漏极中的一个与第四晶体管的源极/漏极中的另一个连接，第五晶体管的源极/漏极中的另一个与第一晶体管的源极/漏极中的另一个连接；第六晶体管的源极/漏极中的一个与第六晶体管的栅极和第二时钟走线连接；第七晶体管的源极/漏极中的一个与第六晶体管的源极/漏极中的另一个连接，第七晶体管的源极/漏极中的另一个与第二晶体管的源极/漏极中的另一个连接。
在其中一些实施方式中，第N级栅极驱动单元还包括低电位走线、第八晶体管、第九晶体管以及第十晶体管；低电位走线配置为传输低电位信号；第八晶体管的源极/漏极中的一个与高电位走线连接；第九晶体管的栅极与第八晶体管的源极/漏极中的另一个连接，第九晶体管的源极/漏极中的一个与低电位走线连接，第九晶体管的源极/漏极中的另一个与第N级扫描走线连接；第十晶体管的栅极与第一晶体管的源极/漏极中的另一个连接，第十晶体管的源极/漏极中的一个与低电位走线连接，第十晶体管的源极/漏极中的另一个与第九晶体管的栅极连接。
在其中一些实施方式中，第N级栅极驱动单元还包括第十一晶体管，第十一晶体管的源极/漏极中的一个与低电位走线连接，第十一晶体管的源极/漏极中的另一个与第一晶体管的源极/漏极中的另一个连接，第十一晶体管的栅极与第十晶体管的源极/漏极中的另一个连接。
在其中一些实施方式中，第N级栅极驱动单元还包括第十二晶体管，第十二晶体管的源极/漏极中的一个与低电位走线连接，第十二晶体管的源极/漏极中的另一个与第一晶体管的源极/漏极中的另一个连接。
在其中一些实施方式中，第N级栅极驱动单元还包括第一扫描走线、第二扫描走线、正向扫描控制走线、反向扫描控制走线、第三时钟走线以及第四时钟走线；第一扫描走线配置为传输第一扫描信号，第一扫描走线与第一晶体管的栅极连接；第二扫描走线配置为传输第二扫描信号，第二扫描走线与第二晶体管的栅极连接；正向扫描控制走线配置为传输正向扫描控制信号，正向扫描控制走线与第五晶体管的栅极连接；反向扫描控制走线配置为传输反向扫描控制信号，反向扫描控制走线与第七晶体管的栅极连接；第三时钟走线配置为传输第三时钟信号，第三时钟走线与第三晶体管的源极/漏极中的另一个连接；第四时钟走线配置为传输第四时钟信号，第四时钟走线与第八晶体管的栅极和第十二晶体管的栅极连接。
在其中一些实施方式中，第N级栅极驱动单元还包括第十三晶体管，第十三晶体管的栅极与高电位走线连接，第十三晶体管的源极/漏极中的一个与第一晶体管的源极/漏极中的另一个连接，第十三晶体管的源极/漏极中的一个与第三晶体管的栅极连接。
第二方面，本申请提供一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动单元，其中，第N级栅极驱动单元包括上拉控制模块、上拉输出模块以及扫描方向控制模块；上拉控制模块的输入端用于接入高电位信号，上拉控制模块的控制端用于接入第N-2级扫描信号和第N+2级扫描信号；上拉输出模块的控制端与上拉控制模块的输出端连接，上拉输出模块的输入端用于接入第N级时钟信号，上拉输出模块的输出端用于输出第N级扫描信号；扫描方向控制模块的输入端用于接入第N-2级时钟信号和第N+2级时钟信号，扫描方向控制模块的控制端用于接入正向扫描控制信号、反向扫描控制信号、第N-2级时钟信号以及第N+2级时钟信号；扫描方向控制模块的输出端与上拉控制模块的输出端连接。
在其中一些实施方式中，第N级栅极驱动单元还包括下拉控制模块和下拉输出模块；下拉控制模块的输入端用于接入高电位信号，下拉控制模块的控制端用于接入第N+4级时钟信号；下拉输出模块的控制端与下拉控制模块的输出端连接，下拉输出模块的输入端用于接入低电位信号，下拉输出模块的输出端与上拉输出模块的输出端连接。
在其中一些实施方式中，第N级栅极驱动单元还包括第一下拉模块；第一下拉模块的输入端用于接入低电位信号，第一下拉模块的控制端与上拉控制模块的输出端连接，第一下拉模块的输出端与下拉控制模块的输出端连接。
在其中一些实施方式中，第N级栅极驱动单元还包括第二下拉模块；第二下拉模块的输入端用于接入低电位信号，第二下拉模块的输出端与上拉控制模块的输出端连接，第二下拉模块的控制端与下拉控制模块的输出端连接。
在其中一些实施方式中，第N级栅极驱动单元还包括第三下拉模块；第三下拉模块的输入端用于接入低电位信号，第三下拉模块的输出端与上拉控制模块的输出端连接，第三下拉模块的控制端与第N+4级时钟信号连接。
在其中一些实施方式中，第N级栅极驱动单元还包括第一稳压模块和/或第二稳压模块；第一稳压模块的一端与上拉控制模块的输出端连接，第一稳压模块的另一端用于接入低电位信号；第二稳压模块的一端与下拉控制模块的输出端连接，第二稳压模块的另一端用于接入低电位信号。
在其中一些实施方式中，第N级栅极驱动单元还包括第三稳压模块、全局上拉模块以及全局下拉模块中的至少一个；第三稳压模块的输入端与上拉控制模块的输出端连接，第三稳压模块的控制端与高电位信号连接，第三稳压模块的输出端与上拉输出模块的控制端连接；全局上拉模块的输入端用于接入全局上拉信号，全局上拉模块的控制端用于接入全局上拉信号，全局上拉模块的输出端与上拉输出模块的输出端连接；全局下拉模块的输入端用于接入低电位信号，全局下拉模块的控制端用于接入全局下拉信号，全局下拉模块的输出端与上拉输出模块的输出端连接。
在其中一些实施方式中，上拉控制模块包括第一薄膜晶体管和第二薄膜晶体管；第一薄膜晶体管的源极/漏极中的一个用于接入高电位信号，第一薄膜晶体管的栅极用于接入第N-2级扫描信号；第二薄膜晶体管的源极/漏极中的一个用于接入高电位信号，第二薄膜晶体管的栅极用于接入第N+2级扫描信号，第二薄膜晶体管的源极/漏极中的另一个与第一薄膜晶体管的源极/漏极中的另一个和扫描方向控制模块的输出端连接。
在其中一些实施方式中，扫描方向控制模块包括正向扫描控制模块和反向扫描控制模块；正向扫描控制模块的输入端用于接入第N+2级时钟信号，正向扫描控制模块的控制端用于接入第N+2级时钟信号和正向扫描控制信号；反向扫描控制模块的输入端用于接入第N-2级时钟信号，反向扫描控制模块的控制端用于接入第N-2级时钟信号和反向扫描控制信号，反向扫描控制模块的输出端与正向扫描控制模块的输出端和上拉控制模块的输出端连接。
在其中一些实施方式中，正向扫描控制模块包括第三薄膜晶体管和第四薄膜晶体管，第三薄膜晶体管的源极/漏极中的一个用于接入第N+2级时钟信号，第三薄膜晶体管的栅极用于接入第N+2级时钟信号，第三薄膜晶体管的源极/漏极中的另一个与第四薄膜晶体管的源极/漏极中的一个连接，第四薄膜晶体管的栅极用于接入正向扫描控制信号，第四薄膜晶体管的源极/漏极中的另一个与上拉控制模块的输出端连接；和/或，反向扫描控制模块包括第五薄膜晶体管和第六薄膜晶体管，第五薄膜晶体管的源极/漏极中的一个用于接入第N-2级时钟信号，第五薄膜晶体管的栅极用于接入第N-2级时钟信号，第五薄膜晶体管的源极/漏极中的另一个与第六薄膜晶体管的源极/漏极中的一个连接，第六薄膜晶体管的栅极用于接入反向扫描控制信号，第六薄膜晶体管的源极/漏极中的另一个与上拉控制模块的输出端连接。
在其中一些实施方式中，上拉输出模块包括第七薄膜晶体管；第七薄膜晶体管的栅极与第四薄膜晶体管的源极/漏极中的另一个和/或第六薄膜晶体管的源极/漏极中的另一个连接；第七薄膜晶体管的源极/漏极中的一个用于接入第N级时钟信号；第七薄膜晶体管T8的源极/漏极中的另一个用于输出第N级扫描信号。
第三方面，本申请提供一种显示面板，其包括上述任一实施方式中的栅极驱动电路。
在其中一些实施方式中，显示面板的工作阶段包括行扫描阶段；行扫描阶段包括触控扫描阶段；栅极驱动电路分时工作于行扫描阶段和触控扫描阶段。
 有益效果
本申请提供的栅极驱动电路及显示面板，通过上拉控制模块的输入端接入高电位信号，可以缓解栅极驱动电路的工作失效，进而提高了栅极驱动电路工作的可靠性；同时，通过时钟信号控制扫描方向控制模块可以实现正反向扫描的交替进行，扫描方向控制模块的输出端与上拉控制模块的输出端连接，上拉控制模块的输出端电位可以交替变换，缓解了上拉控制模块的输出端较长时间内保持同一电位所受到的应力作用，进一步提高了栅极驱动电路的可靠性。
 附图说明
图1为本申请实施例提供的栅极驱动电路的第一种结构示意图。
图2为图1所示的栅极驱动电路的时序示意图。
图3为本申请实施例提供的栅极驱动电路的第二种结构示意图。
图4为本申请实施例提供的栅极驱动电路的第三种结构示意图。
图5为图4所示的栅极驱动电路的一种时序示意图。
图6为图4所示的栅极驱动电路的另一种时序示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
在其中一个实施例中，如图1所示，本实施例提供了一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动单元，在其中一个栅极驱动单元中，正向扫描控制信号U2D与晶体管NT1的源极/漏极中的一个和晶体管NT3的栅极连接；晶体管NT1的栅极与栅极扫描信号Gate（N-2）连接。晶体管NT1的源极/漏极中的另一个与晶体管NT7的源极/漏极中的一个、电容C1的第一端、晶体管NT2的源极/漏极中的另一个以及晶体管NT5的源极/漏极中的一个连接，并作为上拉节点Q；电容C1的第二端与低电位信号VGL连接；晶体管NT7的栅极与高电位信号VGH连接；晶体管NT7的源极/漏极中的另一个与晶体管NT9的栅极连接；晶体管NT9的源极/漏极中的一个与时钟信号CKN连接；晶体管NT9的源极/漏极中的另一个与晶体管NT10的源极/漏极中的一个、晶体管NT11的源极/漏极中的另一个以及晶体管NT13的源极/漏极中的一个连接，并输出栅极扫描信号Gate（N）。晶体管NT3的源极/漏极中的一个与时钟信号CKN+2连接；晶体管NT3的源极/漏极中的另一个与晶体管NT4的源极/漏极中的另一个、晶体管NT8的栅极以及晶体管NT14的源极/漏极中的一个连接；晶体管NT4的源极/漏极中的一个与时钟信号CKN-2连接；晶体管NT8的源极/漏极中的一个与高电位信号VGH连接。晶体管NT8的源极/漏极中的另一个与晶体管NT6的源极/漏极中的一个、晶体管NT5的栅极、电容C2的第二端、晶体管NT12的源极/漏极中的一个以及晶体管NT10的栅极连接，并作为下拉节点P；电容C2的第一端与低电位信号VGL连接。反向扫描控制信号D2U与晶体管NT4的栅极和晶体管NT2的源极/漏极中的一个连接；晶体管NT2的源极/漏极中的另一个与上拉节点Q、晶体管NT6的栅极连接。低电位信号VGL与晶体管NT5的源极/漏极中的另一个、晶体管NT6的源极/漏极中的另一个、晶体管NT12的源极/漏极中的另一个、晶体管NT14的源极/漏极中的另一个、晶体管NT10的源极/漏极中的另一个以及晶体管NT13的源极/漏极中的另一个连接。全局控制信号Gas1与晶体管NT12的栅极、晶体管NT14的栅极、晶体管NT11的栅极以及晶体管NT11的源极/漏极中的一个连接。全局控制信号Gas2与晶体管NT13的栅极连接。晶体管NT2的栅极与扫描信号Gate（N+2）连接。
基于上述描述可知，在上述的栅极驱动电路中，上拉节点Q存在的漏电路径。具体地，正向扫描时，晶体管NT1长期处于较严重的NBTS（Negative-Bias-voltage and Temperature Stress，负偏压及温度应力）状态，在此种状态下，晶体管NT1的漏极与源极之间的电压Vds等于高电位信号VGH与低电位信号VGL之间的电位差值，长期工作下，晶体管NT1的阈值电压Vth会产生负漂或者其关断电流I-off增加。进入TP（Touch Panel，触控显示面板）中停期间即栅极驱动电路需要在显示（Display）期间实现暂停扫描之功能。上拉节点Q的电位需维持在高电位信号VGH的准位，下拉节点P的电位维持低电位信号VGL的电位。正向扫描时，晶体管NT1的源极/漏极中的一个连接正向扫描控制信号U2D，此时，该正向扫描控制信号U2D为与高电位信号VGH的电位一致的高电位，上拉节点Q不能通过晶体管NT1漏电。但是，反向扫描时，正向扫描控制信号U2D变为与低电位信号VGL的电位一致的低电位，此时，上拉节点Q可以通过晶体管NT1形成漏电路径，因此，上拉节点Q的与高电位信号VGH的电位的准电位被拉低，导致栅极驱动电路在TP中停期间发生失效，进而引发栅极驱动电路的一个关于可靠性的技术问题。
如图2所述，上述栅极驱动电路在对应的初始信号STV以及时钟信号的控制下，其中，时钟信号可以为时钟信号CK（1）、时钟信号CK（3）、时钟信号CK（5）、时钟信号CK（7）等，上述栅极驱动电路可以生成对应的扫描信号，例如，该扫描信号可以为扫描信号G（1）、扫描信号G（3）、扫描信号G（N-2）、扫描信号G（N）以及扫描信号G（N+2）等，对应地，上述栅极驱动电路的第N级上拉节点Q（N）的电位和第N级下拉节点P（N）的电位如下所述。
栅极驱动电路的另一个关于可靠性的技术问题为：上述栅极驱动电路中第N级栅极驱动单元在一帧即扫描信号Gate（N-2）的上升沿至扫描信号Gate（N+2）的上升沿的期间，第N级上拉节点Q（N）的电位保持在与高电位信号VGH相一致的电位，而其余时间内，第N级上拉节点Q（N）的电位为保持在与低电位信号VGL相一致的电位，导致晶体管NT6受到长时间的NBTS。扫描信号Gate（N-2）的上升沿至扫描信号Gate（N+2）的上升沿的期间，第N级下拉节点P（N）的电位保持在与低电位信号VGL相一致的电位，其余时间内，第N级下拉节点P（N）的电位则保持在与高电位信号VGH相一致的电位，导致晶体管NT5受到长时间的PBTS（Positive-Bias-voltage and Temperature Stress，正偏压及温度应力）状态。
请参阅图3至图6，如图3和图4所示，本实施例提供了一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动单元，其中，第N级栅极驱动单元包括上拉控制模块10、上拉输出模块20以及扫描方向控制模块30；上拉控制模块10的输入端用于接入高电位信号VGH，上拉控制模块10的控制端用于接入第N-2级扫描信号G（N-2）和第N+2级扫描信号G（N+2）；上拉输出模块20的控制端与上拉控制模块10的输出端连接，上拉输出模块20的输入端用于接入第N级时钟信号CK（N），上拉输出模块20的输出端用于输出第N级扫描信号G（N）；扫描方向控制模块30的输入端用于接入第N-2级时钟信号CK（N-2）和第N+2级时钟信号CK（N+2），扫描方向控制模块30的控制端用于接入正向扫描控制信号U2D、反向扫描控制信号D2U、第N-2级时钟信号CK（N-2）以及第N+2级时钟信号CK（N+2）；扫描方向控制模块30的输出端与上拉控制模块10的输出端连接。
可以理解的是，本实施例提供的栅极驱动电路，通过上拉控制模块10的输入端接入高电位信号VGH，可以缓解栅极驱动电路的工作失效，进而提高了栅极驱动电路工作的可靠性；同时，通过时钟信号控制扫描方向控制模块30可以实现正反向扫描的交替进行，扫描方向控制模块30的输出端与上拉控制模块10的输出端连接，上拉控制模块10的输出端电位可以交替变换，缓解了上拉控制模块10的输出端较长时间内保持同一电位所受到的应力作用，进一步提高了栅极驱动电路的可靠性。
需要进行说明的是，N可以为正整数，例如，1、2、3、8等等。
如图4所示，在其中一个实施例中，上拉控制模块10包括第一薄膜晶体管T1和第二薄膜晶体管T2；第一薄膜晶体管T1的源极/漏极中的一个用于接入高电位信号VGH，第一薄膜晶体管T1的栅极用于接入第N-2级扫描信号G（N-2）；第二薄膜晶体管T2的源极/漏极中的一个用于接入高电位信号VGH，第二薄膜晶体管T2的栅极用于接入第N+2级扫描信号G（N+2），第二薄膜晶体管T2的源极/漏极中的另一个与第一薄膜晶体管T1的源极/漏极中的另一个和扫描方向控制模块30的输出端连接。
需要进行说明的是，由于第一薄膜晶体管T1的源极/漏极中的一个和第二薄膜晶体管T2源极/漏极中的一个接入的均为高电位信号VGH，可以实时减少或者防止节点Q（N）的电位通过第一薄膜晶体管T1和/或第二薄膜晶体管T2进行漏电。
其中，该节点Q（N）可以为上拉控制模块10的输出端、扫描方向控制模块30的输出端、上拉输出模块20的控制端以及第三稳压模块110的输入端中的至少一个。
在其中一个实施例中，扫描方向控制模块30包括正向扫描控制模块和反向扫描控制模块；正向扫描控制模块的输入端用于接入第N+2级时钟信号CK（N+2），正向扫描控制模块的控制端用于接入第N+2级时钟信号CK（N+2）和正向扫描控制信号U2D；反向扫描控制模块的输入端用于接入第N-2级时钟信号CK（N-2），反向扫描控制模块的控制端用于接入第N-2级时钟信号CK（N-2）和反向扫描控制信号D2U，反向扫描控制模块的输出端与正向扫描控制模块的输出端和上拉控制模块10的输出端连接。
可以理解的是，在本实施例中，通过第N+2级时钟信号CK（N+2）可以驱动第N级栅极驱动单元进行正向扫描；通过第N-2级时钟信号CK（N-2）可以驱动第N级栅极驱动单元进行反向扫描。对应地，第N+2级时钟信号CK（N+2）、第N-2级时钟信号CK（N-2）将对应传输至节点Q（N），则节点Q（N）的电位可以随着对应的时钟信号进行电位变换，可以缓解节点Q（N）需要长时间承受同一电位所受到的应力或者温度应力导致的可靠性问题。
如图4所示，在其中一个实施例中，正向扫描控制模块包括第三薄膜晶体管T12和第四薄膜晶体管T13，第三薄膜晶体管T12的源极/漏极中的一个用于接入第N+2级时钟信号CK（N+2），第三薄膜晶体管T12的栅极用于接入第N+2级时钟信号CK（N+2），第三薄膜晶体管T12的源极/漏极中的另一个与第四薄膜晶体管T13的源极/漏极中的一个连接，第四薄膜晶体管T13的栅极用于接入正向扫描控制信号U2D，第四薄膜晶体管T13的源极/漏极中的另一个与上拉控制模块10的输出端连接。
在其中一个实施例中，反向扫描控制模块包括第五薄膜晶体管T14和第六薄膜晶体管T15，第五薄膜晶体管T14的源极/漏极中的一个用于接入第N-2级时钟信号CK（N-2），第五薄膜晶体管T14的栅极用于接入第N-2级时钟信号CK（N-2），第五薄膜晶体管T14的源极/漏极中的另一个与第六薄膜晶体管T15的源极/漏极中的一个连接，第六薄膜晶体管T15的栅极用于接入反向扫描控制信号D2U，第六薄膜晶体管T15的源极/漏极中的另一个与上拉控制模块10的输出端连接。
在其中一个实施例中，上拉输出模块20包括第七薄膜晶体管T8；第七薄膜晶体管T8的栅极与第一薄膜晶体管T1的源极/漏极中的另一个连接；第七薄膜晶体管T8的源极/漏极中的一个用于接入第N级时钟信号CK（N）；第七薄膜晶体管T8的源极/漏极中的另一个用于输出第N级扫描信号G（N）。
在其中一个实施例中，第N级栅极驱动单元还包括下拉控制模块40和下拉输出模块50；下拉控制模块40的输入端用于接入高电位信号VGH，下拉控制模块40的控制端用于接入第N+4级时钟信号CK（N+4）；下拉输出模块50的控制端与下拉控制模块40的输出端连接，下拉输出模块50的输入端用于接入低电位信号VGL，下拉输出模块50的输出端与上拉输出模块20的输出端连接。
可以理解的是，下拉输出模块50的控制端和下拉控制模块40的输出端中的至少一个可以作为节点P（N）。
其中，下拉控制模块40包括第八薄膜晶体管T4；第八薄膜晶体管T4的栅极用于接入第N+4级时钟信号CK（N+4）；第八薄膜晶体管T4的源极/漏极中的一个用于接入高电位信号VGH；第八薄膜晶体管T4的源极/漏极中的另一个可以作为节点P（N）。
下拉输出模块50包括第九薄膜晶体管T9；第九薄膜晶体管T9的栅极与第八薄膜晶体管T4的源极/漏极中的另一个连接；第九薄膜晶体管T9的源极/漏极中的一个用于接入低电位信号VGL；第九薄膜晶体管T9的源极/漏极中的另一个与第七薄膜晶体管T8的源极/漏极中的另一个连接。
在其中一个实施例中，第N级栅极驱动单元还包括第一下拉模块60；第一下拉模块60的输入端用于接入低电位信号VGL，第一下拉模块60的控制端与上拉控制模块10的输出端连接，第一下拉模块60的输出端与下拉控制模块40的输出端连接。
其中，第一下拉模块60包括第十薄膜晶体管T6；第十薄膜晶体管T6的栅极与第一薄膜晶体管T1的源极/漏极中的另一个和第二薄膜晶体管T2的源极/漏极中的另一个连接；第十薄膜晶体管T6的源极/漏极中的一个用于接入低电位信号VGL；第十薄膜晶体管T6的源极/漏极中的另一个与第八薄膜晶体管T4的源极/漏极中的另一个连接。
可以理解的是，当节点Q（N）的电位可以打开第十薄膜晶体管T6时，则节点P（N）的电位被拉低至低电位信号VGL的电位，例如，当第十薄膜晶体管T6为N沟道型薄膜晶体管时，节点Q（N）的高电位可以拉低节点P（N）的电位至低电位信号VGL的电位。因此，随着节点Q（N）的电位变化，则节点P（N）的电位也会调整至对应的电位，进而可以缓解节点P（N）的电位长期保持在同一电位的状况，进而可以改善第十薄膜晶体管T6长期承受连续的NBTS状况，能够提升栅极驱动电路的可靠性。
在其中一个实施例中，第N级栅极驱动单元还包括第二下拉模块70；第二下拉模块70的输入端用于接入低电位信号VGL，第二下拉模块70的输出端与上拉控制模块10的输出端连接，第二下拉模块70的控制端与下拉控制模块40的输出端连接。
其中，第二下拉模块70包括第十一薄膜晶体管T5；第十一薄膜晶体管T5的栅极与第八薄膜晶体管T4的源极/漏极中的另一个连接；第十一薄膜晶体管T5的源极/漏极中的一个用于接入低电位信号VGL；第十一薄膜晶体管T5的源极/漏极中的另一个与第一薄膜晶体管T1的源极/漏极中的另一个和第二薄膜晶体管T2的源极/漏极中的另一个连接。
可以理解的是，当节点P（N）的电位可以打开第十一薄膜晶体管T5时，则节点Q（N）的电位被拉低至低电位信号VGL的电位，例如，当第十一薄膜晶体管T5为N沟道型薄膜晶体管时，节点P（N）的高电位可以拉低节点Q（N）的电位至低电位信号VGL的电位。因此，随着节点P（N）的电位变化，则节点Q（N）的电位也会调整至对应的电位，进而可以缓解节点Q（N）的电位长期保持在同一电位的状况，进而可以改善第十一薄膜晶体管T5长期承受连续的BTS（Bias-voltage and Temperature Stress，偏压及温度应力）状况，能够提升栅极驱动电路的可靠性。
在其中一个实施例中，第N级栅极驱动单元还包括第三下拉模块80；第三下拉模块80的输入端用于接入低电位信号VGL，第三下拉模块80的输出端与上拉控制模块10的输出端连接，第三下拉模块80的控制端与第N+4级时钟信号CK（N+4）连接。
在其中一个实施例中，第三下拉模块80包括第十二薄膜晶体管T3；第十二薄膜晶体管T3的栅极用于接入第N+4级时钟信号CK（N+4）；第十二薄膜晶体管T3的源极/漏极中的一个用于接入低电位信号VGL；第十二薄膜晶体管T3的源极/漏极中的一个与第一薄膜晶体管T1的源极/漏极中的另一个、第二薄膜晶体管T2的源极/漏极中的另一个、第四薄膜晶体管T13的源极/漏极中的另一个以及第六薄膜晶体管T15的源极/漏极中的另一个中的至少一个连接。
在其中一个实施例中，第N级栅极驱动单元还包括第一稳压模块90和/或第二稳压模块100；第一稳压模块90的一端与上拉控制模块10的输出端连接，第一稳压模块90的另一端用于接入低电位信号VGL；第二稳压模块100的一端与下拉控制模块40的输出端连接，第二稳压模块100的另一端用于接入低电位信号VGL。
在其中一个实施例中，第一稳压模块90包括第一电容C1；第一电容C1的一端与第一薄膜晶体管T1的源极/漏极中的另一个和第二薄膜晶体管T2的源极/漏极中的另一个中的至少一个连接；第一电容C1的另一端用于接入低电位信号VGL。
可以理解的是，第一稳压模块90有利于稳定节点Q（N）的电位。
在其中一个实施例中，第二稳压模块100包括第二电容C2；第二电容C2的一端与第八薄膜晶体管T4的源极/漏极中的另一个连接；第一电容C1的另一端用于接入低电位信号VGL。
可以理解的是，第二稳压模块100有利于稳定节点P（N）的电位。
在其中一个实施例中，第N级栅极驱动单元还包括第三稳压模块110、全局上拉模块120以及全局下拉模块130中的至少一个；第三稳压模块110的输入端与上拉控制模块10的输出端连接，第三稳压模块110的控制端与高电位信号VGH连接，第三稳压模块110的输出端与上拉输出模块20的控制端连接；全局上拉模块120的输入端用于接入全局上拉信号GAS1，全局上拉模块120的控制端用于接入全局上拉信号GAS1，全局上拉模块120的输出端与上拉输出模块20的输出端连接；全局下拉模块130的输入端用于接入低电位信号VGL，全局下拉模块130的控制端用于接入全局下拉信号GAS2，全局下拉模块130的输出端与上拉输出模块20的输出端连接。
其中，第三稳压模块110包括第十三薄膜晶体管T7；第十三薄膜晶体管T7的源极/漏极中的一个可以与第一薄膜晶体管T1的源极/漏极中的另一个和第二薄膜晶体管T2的源极/漏极中的另一个中的至少一个连接；第十三薄膜晶体管T7的源极/漏极中的另一个可以与第七薄膜晶体管T8的栅极连接；第十三薄膜晶体管T7的栅极用于接入高电位信号VGH。
可以理解的是，当第十三薄膜晶体管T7的源极/漏极中的一个的电位与第十三薄膜晶体管T7的源极/漏极中的另一个的电位相等时，则第十三薄膜晶体管T7断开或者截止，此时有利于保持第十三薄膜晶体管T7的源极/漏极中的一个的电位和/或第十三薄膜晶体管T7的源极/漏极中的另一个的电位。
全局上拉模块120可以包括第十四薄膜晶体管T10；第十四薄膜晶体管T10的源极/漏极中的一个用于接入全局上拉信号GAS1；第十四薄膜晶体管T10的源极/漏极中的另一个与第七薄膜晶体管T8的源极/漏极中的另一个连接；第十四薄膜晶体管T10的栅极用于接入全局上拉信号GAS1。
全局下拉模块130可以包括第十五薄膜晶体管T11；第十五薄膜晶体管T11的源极/漏极中的一个用于接入低电位信号VGL；第十五薄膜晶体管T11的源极/漏极中的另一个与第七薄膜晶体管T8的源极/漏极中的另一个连接；第十五薄膜晶体管T11的栅极用于接入全局下拉信号GAS2。
如图5所示，可以理解的是，在一些实施例中的栅极驱动电路，可以在对应的初始信号STV以及时钟信号的控制下，栅极驱动电路可以生成对应的扫描信号。其中，时钟信号可以但不限于为第一时钟信号CK（1）、第三时钟信号CK（3）、第五时钟信号CK（5）、第七时钟信号CK（7）等。例如，扫描信号可以但不限于为第一级扫描信号G（1）、第三级扫描信号G（3）、第N-2级扫描信号G（N-2）、第N级扫描信号G（N）以及第N+2级扫描信号G（N+2）等。
具体地，节点Q（N）、节点P（N）的电位状态可以为如下：
例如，在第三级扫描信号G（3）的上升沿至第五时钟信号CK（5）的第一个脉冲的上升沿之间的时间段，节点Q（N）的电位可以维持高电位；对应地，节点P（N）的电位维持在低电位。
例如，在第三时钟信号CK（3）的第二个脉冲的上升沿至第五时钟信号CK（5）的第二个脉冲的上升沿之间的时间段，节点Q（N）的电位可以维持高电位；对应地，节点P（N）的电位维持在低电位。
例如，在第N-2级扫描信号G（N-2）的上升沿至第五时钟信号CK（5）的第三个脉冲的上升沿之间的时间段，节点Q（N）的电位可以维持高电位；对应地，节点P（N）的电位维持在低电位。
又例如，在第三时钟信号CK（3）的其中一个脉冲的上升沿至第五时钟信号CK（5）的其中一个脉冲的上升沿之间的时间段，节点Q（N）的电位可以维持高电位；对应地，节点P（N）的电位维持在低电位。
而节点Q（N）在两个相邻的高电位之间，总是会存在对应的低电位。同理，节点P（N）在两个相邻的低电位之间，总是会存在对应的高电位。
由此可见，节点Q（N）和节点P（N）中任一个的电位状态总是可以以高电位、低电位的不同电位状态交替出现，其中，交替出现的频率也得到了提高，这样可以缓解对应的薄膜晶体管长期承受同一电位状态致使的偏压即温度应力，其中，偏压可以但不限于为正偏压，也可以为负偏压，进而可以提高栅极驱动电路的可靠性。
如图4所示，基于上述，本实施例提供一种栅极驱动电路，栅极驱动电路包括多个级联的栅极驱动单元，其中，第N级栅极驱动单元包括高电位走线、第N级扫描走线、第一晶体管、第二晶体管以及第三晶体管；高电位走线配置为传输高电位信号VGH；第N级扫描走线配置为传输第N级扫描信号G（N）；第一晶体管的源极/漏极中的一个与高电位走线连接；第二晶体管的源极/漏极中的一个与高电位走线连接；第三晶体管的栅极与第一晶体管的源极/漏极中的另一个和第二晶体管的源极/漏极中的另一个连接，第三晶体管的源极/漏极中的一个与第N级扫描走线连接。
可以理解的是，在本实施例中，第一晶体管的源极/漏极中的一个和第二晶体管的源极/漏极中的一个均与高电位走线连接，可以减少或者防止第三晶体管的栅极出现漏电流现象，缓解了栅极驱动电路的工作失效问题，同时提高了栅极驱动电路的可靠性。
需要进行说明的是，第一晶体管可以为第一薄膜晶体管T1。第二晶体管可以为第二薄膜晶体管T2。第三晶体管可以为第七薄膜晶体管T8。
在其中一个实施例中，第N级栅极驱动单元还包括第一时钟走线、第二时钟走线、第四晶体管、第五晶体管、第六晶体管以及第七晶体管；第一时钟走线配置为传输第一时钟信号；第二时钟走线配置为传输第二时钟信号；第四晶体管的源极/漏极中的一个与第四晶体管的栅极和第一时钟走线连接；第五晶体管的源极/漏极中的一个与第四晶体管的源极/漏极中的另一个连接，第五晶体管的源极/漏极中的另一个与第一晶体管的源极/漏极中的另一个连接；第六晶体管的源极/漏极中的一个与第六晶体管的栅极和第二时钟走线连接；第七晶体管的源极/漏极中的一个与第六晶体管的源极/漏极中的另一个连接，第七晶体管的源极/漏极中的另一个与第二晶体管的源极/漏极中的另一个连接。
可以理解的是，通过第一时钟走线和第二时钟走线控制第一晶体管的源极/漏极中的另一个的电位、第二晶体管的源极/漏极中的另一个的电位，可以交替变换第一晶体管的源极/漏极中的另一个的电位、第二晶体管的源极/漏极中的另一个的电位，缓解了第一晶体管的源极/漏极中的另一个的电位、第二晶体管的源极/漏极中的另一个的电位较长时间内保持同一电位所受到的应力作用，进一步提高了栅极驱动电路的可靠性。
需要进行说明的是，第一时钟信号可以但不限于为第N+2级时钟信号CK（N+2）。第二时钟信号可以但不限于为第N-2级时钟信号CK（N-2）。第四晶体管可以为第三薄膜晶体管T12。第五晶体管可以为第四薄膜晶体管T13。第六晶体管可以为第五薄膜晶体管T14。第七晶体管可以为第六薄膜晶体管T15。
在其中一个实施例中，第N级栅极驱动单元还包括低电位走线、第八晶体管、第九晶体管以及第十晶体管；低电位走线配置为传输低电位信号VGL；第八晶体管的源极/漏极中的一个与高电位走线连接；第九晶体管的栅极与第八晶体管的源极/漏极中的另一个连接，第九晶体管的源极/漏极中的一个与低电位走线连接，第九晶体管的源极/漏极中的另一个与第N级扫描走线连接；第十晶体管的栅极与第一晶体管的源极/漏极中的另一个连接，第十晶体管的源极/漏极中的一个与低电位走线连接，第十晶体管的源极/漏极中的另一个与第九晶体管的栅极连接。
可以理解的是，第十晶体管可以基于第一晶体管的源极/漏极中的另一个的交替变换的电位，实现第八晶体管的源极/漏极中的另一个的电位的对应交替变换，可以改善第八晶体管的源极/漏极中的另一个的电位较长时间内保持同一电位所受到的应力作用，进一步提高了栅极驱动电路的可靠性。
需要进行说明的是，第八晶体管可以为第八薄膜晶体管T4。第九晶体管可以为第九薄膜晶体管T9。第十晶体管可以为第十薄膜晶体管T6。
在其中一个实施例中，第N级栅极驱动单元还包括第十一晶体管，第十一晶体管的源极/漏极中的一个与低电位走线连接，第十一晶体管的源极/漏极中的另一个与第一晶体管的源极/漏极中的另一个连接，第十一晶体管的栅极与第十晶体管的源极/漏极中的另一个连接。
可以理解的是，第十一晶体管的源极/漏极中的另一个的电位可以基于第一晶体管的源极/漏极中的另一个的电位进行交替变换，可以改善第十一晶体管的源极/漏极中的另一个的电位较长时间内保持同一电位所受到的应力作用，进一步提高了栅极驱动电路的可靠性。
需要进行说明的是，第十一晶体管可以为第十一薄膜晶体管T5。
在其中一个实施例中，第N级栅极驱动单元还包括第十二晶体管，第十二晶体管的源极/漏极中的一个与低电位走线连接，第十二晶体管的源极/漏极中的另一个与第一晶体管的源极/漏极中的另一个连接。
可以理解的是，第十二晶体管的源极/漏极中的另一个的电位可以基于第一晶体管的源极/漏极中的另一个的电位进行交替变换，可以改善第十二晶体管的源极/漏极中的另一个的电位较长时间内保持同一电位所受到的应力作用，进一步提高了栅极驱动电路的可靠性。
需要进行说明的是，第十二晶体管可以为十二薄膜晶体管T3。
在其中一个实施例中，第N级栅极驱动单元还包括第一扫描走线、第二扫描走线、正向扫描控制走线、反向扫描控制走线、第三时钟走线以及第四时钟走线；第一扫描走线配置为传输第一扫描信号，第一扫描走线与第一晶体管的栅极连接；第二扫描走线配置为传输第二扫描信号，第二扫描走线与第二晶体管的栅极连接；正向扫描控制走线配置为传输正向扫描控制信号，正向扫描控制走线与第五晶体管的栅极连接；反向扫描控制走线配置为传输反向扫描控制信号，反向扫描控制走线与第七晶体管的栅极连接；第三时钟走线配置为传输第三时钟信号，第三时钟走线与第三晶体管的源极/漏极中的另一个连接；第四时钟走线配置为传输第四时钟信号，第四时钟走线与第八晶体管的栅极和第十二晶体管的栅极连接。
需要进行说明的是，第一扫描信号可以为第N-2级扫描信号G（N-2）。第二扫描信号可以为第N+2级扫描信号G（N+2）。第三时钟信号可以为第N级时钟信号CK（N）。第四时钟信号可以为第N+4级时钟信号CK（N+4）。
在其中一个实施例中，第N级栅极驱动单元还包括第十三晶体管，第十三晶体管的栅极与高电位走线连接，第十三晶体管的源极/漏极中的一个与第一晶体管的源极/漏极中的另一个连接，第十三晶体管的源极/漏极中的一个与第三晶体管的栅极连接。
可以理解的是，第十三晶体管有利于维持并隔离第一晶体管的源极/漏极中的另一个的电位、第三晶体管的栅极的电位。
需要进行说明的是，第十三晶体管可以为第十三薄膜晶体管T7。
在其中一个实施例中，第一薄膜晶体管T1至第十五薄膜晶体管T11可以但不限于为N沟道型薄膜晶体管，其还可以为P沟道型薄膜晶体管。
在其中一个实施例中，本实施例提供一种显示面板，其包括上述任一实施例中的栅极驱动电路。
可以理解的是，本实施例提供的显示面板，通过上拉控制模块10的输入端接入高电位信号VGH，可以缓解栅极驱动电路的工作失效，进而提高了栅极驱动电路工作的可靠性；同时，通过时钟信号控制扫描方向控制模块30可以实现正反向扫描的交替进行，扫描方向控制模块30的输出端与上拉控制模块10的输出端连接，上拉控制模块10的输出端电位可以交替变换，缓解了上拉控制模块10的输出端较长时间内保持同一电位所受到的应力作用，进一步提高了栅极驱动电路的可靠性。
在其中一个实施例中，显示面板的工作阶段包括行扫描阶段；行扫描阶段包括触控扫描阶段；栅极驱动电路分时工作于行扫描阶段和触控扫描阶段。
需要进行说明的是，行扫描阶段在进行行扫描的过程中，会存在一个扫描暂停阶段，以进行触控扫描阶段，待到该触控扫描阶段结束之后，再进行行扫描阶段。
具体地，在内嵌式（In- Cell）触摸屏技术中，对显示区（AA，Active Area）的若干行像素进行显示（display) 扫描的过程中，可以先停止显示扫描，开始对AA区中至少部分的触摸（Touch) 电极进行扫描，之后再继续显示扫描，以次类推，显示扫描与触控扫描可以反复多次进行交叉操作，次数可以依具体产品而定，直至完成一帧画面的显示扫描和全屏的触控扫描。
例如，图6中示出了第N-2时钟信号CK（N-2）、第N时钟信号、第N+2时钟信号、第N-2级扫描信号G（N-2）、第N级扫描信号G（N）、第N+2级扫描信号G（N+2）、节点Q（N）以及节点P（N）的波形示意图。
具体地，当显示面板需要进行触控扫描时，可以通过对应的时钟信号控制栅极驱动电路停止显示扫描的工作。例如，第N级栅极驱动单元输出第N级扫描信号G（N）后，进入中停（停止显示扫描，开始触控扫描）期间，中停时可以通过对应的时钟信号均不出现脉冲（Pulse），实现栅极驱动电路的停止输出即停止显示扫描。同时，全局下拉信号GAS2的电位由低电位转变为高电位，全局下拉模块130即第十五薄膜晶体管T11打开，栅极驱动电路输出的各扫描信号均为低电位。当触控扫描结束后，第N+2时钟信号开始输出对应的脉冲，对应的栅极驱动单元可以继续级传以进行正常的显示扫描。
其中，需要进行说明的是，中停期间会持续一个较长的时间段，这对于栅极驱动电路中的关键节点，例如，节点Q（N）、节点P（N），这两者的电位容易存在漏电或者长期保持在同一电位的情况，因此，对于存在中停期间的栅极驱动电路而言，本实施例中提供的栅极驱动电路及显示面板可以较好地克服漏电以及一些薄膜晶体管容易出现偏压及温度应力致使的可靠性较低的状况。
具体地，薄膜晶体管的偏压及温度应力在双85测试时将会体现的更为明显，其中，双85测试是指在温度85℃、湿度85%的环境进行的老化测试。这是因为温度85℃、湿度85%这种环境状况比常温、常规湿度的环境更为恶略，因此，薄膜晶体管的偏压及温度应力也会对应导致栅极驱动电路出现更为欠佳的可靠性表现。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种栅极驱动电路，所述栅极驱动电路包括多个级联的栅极驱动单元，其中，第N级栅极驱动单元包括：
    高电位走线，所述高电位走线配置为传输高电位信号；
    第N级扫描走线，所述第N级扫描走线配置为传输第N级扫描信号；
    第一晶体管，所述第一晶体管的源极/漏极中的一个与所述高电位走线连接；
    第二晶体管，所述第二晶体管的源极/漏极中的一个与所述高电位走线连接；以及
    第三晶体管，所述第三晶体管的栅极与所述第一晶体管的源极/漏极中的另一个和所述第二晶体管的源极/漏极中的另一个连接，所述第三晶体管的源极/漏极中的一个与所述第N级扫描走线连接。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括：
    第一时钟走线，所述第一时钟走线配置为传输第一时钟信号；
    第二时钟走线，所述第二时钟走线配置为传输第二时钟信号；
    第四晶体管，所述第四晶体管的源极/漏极中的一个与所述第四晶体管的栅极和所述第一时钟走线连接；
    第五晶体管，所述第五晶体管的源极/漏极中的一个与所述第四晶体管的源极/漏极中的另一个连接，所述第五晶体管的源极/漏极中的另一个与所述第一晶体管的源极/漏极中的另一个连接；
    第六晶体管，所述第六晶体管的源极/漏极中的一个与所述第六晶体管的栅极和所述第二时钟走线连接；以及
    第七晶体管，所述第七晶体管的源极/漏极中的一个与所述第六晶体管的源极/漏极中的另一个连接，所述第七晶体管的源极/漏极中的另一个与所述第二晶体管的源极/漏极中的另一个连接。
  3. 根据权利要求2所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括：
    低电位走线，所述低电位走线配置为传输低电位信号；
    第八晶体管，所述第八晶体管的源极/漏极中的一个与所述高电位走线连接；
    第九晶体管，所述第九晶体管的栅极与所述第八晶体管的源极/漏极中的另一个连接，所述第九晶体管的源极/漏极中的一个与所述低电位走线连接，所述第九晶体管的源极/漏极中的另一个与所述第N级扫描走线连接；以及
    第十晶体管，所述第十晶体管的栅极与所述第一晶体管的源极/漏极中的另一个连接，所述第十晶体管的源极/漏极中的一个与所述低电位走线连接，所述第十晶体管的源极/漏极中的另一个与所述第九晶体管的栅极连接。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括：
    第十一晶体管，所述第十一晶体管的源极/漏极中的一个与所述低电位走线连接，所述第十一晶体管的源极/漏极中的另一个与所述第一晶体管的源极/漏极中的另一个连接，所述第十一晶体管的栅极与所述第十晶体管的源极/漏极中的另一个连接。
  5. 根据权利要求4所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括：
    第十二晶体管，所述第十二晶体管的源极/漏极中的一个与所述低电位走线连接，所述第十二晶体管的源极/漏极中的另一个与所述第一晶体管的源极/漏极中的另一个连接。
  6. 根据权利要求5所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括：
    第一扫描走线，所述第一扫描走线配置为传输第一扫描信号，所述第一扫描走线与所述第一晶体管的栅极连接；
    第二扫描走线，所述第二扫描走线配置为传输第二扫描信号，所述第二扫描走线与所述第二晶体管的栅极连接；
    正向扫描控制走线，所述正向扫描控制走线配置为传输正向扫描控制信号，所述正向扫描控制走线与所述第五晶体管的栅极连接；
    反向扫描控制走线，所述反向扫描控制走线配置为传输反向扫描控制信号，所述反向扫描控制走线与所述第七晶体管的栅极连接；
    第三时钟走线，所述第三时钟走线配置为传输第三时钟信号，所述第三时钟走线与所述第三晶体管的源极/漏极中的另一个连接；以及
    第四时钟走线，所述第四时钟走线配置为传输第四时钟信号，所述第四时钟走线与所述第八晶体管的栅极和所述第十二晶体管的栅极连接。
  7. 根据权利要求1所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括：
    第十三晶体管，所述第十三晶体管的栅极与所述高电位走线连接，所述第十三晶体管的源极/漏极中的一个与所述第一晶体管的源极/漏极中的另一个连接，所述第十三晶体管的源极/漏极中的一个与所述第三晶体管的栅极连接。
  8. 一种栅极驱动电路，所述栅极驱动电路包括多个级联的栅极驱动单元，其中，第N级栅极驱动单元包括：
    上拉控制模块，所述上拉控制模块的输入端用于接入高电位信号，所述上拉控制模块的控制端用于接入第N-2级扫描信号和第N+2级扫描信号；
    上拉输出模块，所述上拉输出模块的控制端与所述上拉控制模块的输出端连接，所述上拉输出模块的输入端用于接入第N级时钟信号，所述上拉输出模块的输出端用于输出第N级扫描信号；以及
    扫描方向控制模块，所述扫描方向控制模块的输入端用于接入第N-2级时钟信号和第N+2级时钟信号，所述扫描方向控制模块的控制端用于接入正向扫描控制信号、反向扫描控制信号、所述第N-2级时钟信号以及所述第N+2级时钟信号；所述扫描方向控制模块的输出端与所述上拉控制模块的输出端连接。
  9. 根据权利要求8所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括：
    下拉控制模块，所述下拉控制模块的输入端用于接入所述高电位信号，所述下拉控制模块的控制端用于接入第N+4级时钟信号；和
    下拉输出模块，所述下拉输出模块的控制端与所述下拉控制模块的输出端连接，所述下拉输出模块的输入端用于接入低电位信号，所述下拉输出模块的输出端与所述上拉输出模块的输出端连接。
  10. 根据权利要求9所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括第一下拉模块；
    所述第一下拉模块的输入端用于接入所述低电位信号，第一下拉模块的控制端与所述上拉控制模块的输出端连接，所述第一下拉模块的输出端与所述下拉控制模块的输出端连接。
  11. 根据权利要求10所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括第二下拉模块；
    所述第二下拉模块的输入端用于接入所述低电位信号，所述第二下拉模块的输出端与所述上拉控制模块的输出端连接，所述第二下拉模块的控制端与所述下拉控制模块的输出端连接。
  12. 根据权利要求11所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括第三下拉模块；
    所述第三下拉模块的输入端用于接入所述低电位信号，所述第三下拉模块的输出端与所述上拉控制模块的输出端连接，所述第三下拉模块的控制端与所述第N+4级时钟信号连接。
  13. 根据权利要求9所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括：
    第一稳压模块，所述第一稳压模块的一端与所述上拉控制模块的输出端连接，所述第一稳压模块的另一端用于接入所述低电位信号；和/或
    第二稳压模块，所述第二稳压模块的一端与所述下拉控制模块的输出端连接，所述第二稳压模块的另一端用于接入所述低电位信号。
  14. 根据权利要求8所述的栅极驱动电路，其中，所述第N级栅极驱动单元还包括第三稳压模块、全局上拉模块以及全局下拉模块中的至少一个；
    所述第三稳压模块的输入端与所述上拉控制模块的输出端连接，所述第三稳压模块的控制端与所述高电位信号连接，所述第三稳压模块的输出端与所述上拉输出模块的控制端连接；
    所述全局上拉模块的输入端用于接入全局上拉信号，所述全局上拉模块的控制端用于接入所述全局上拉信号，所述全局上拉模块的输出端与所述上拉输出模块的输出端连接；
    所述全局下拉模块的输入端用于接入低电位信号，所述全局下拉模块的控制端用于接入全局下拉信号，所述全局下拉模块的输出端与所述上拉输出模块的输出端连接。
  15. 根据权利要求8所述的栅极驱动电路，其中，所述上拉控制模块包括：
    第一薄膜晶体管，所述第一薄膜晶体管的源极/漏极中的一个用于接入所述高电位信号，所述第一薄膜晶体管的栅极用于接入所述第N-2级扫描信号；和
    第二薄膜晶体管，所述第二薄膜晶体管的源极/漏极中的一个用于接入所述高电位信号，所述第二薄膜晶体管的栅极用于接入所述第N+2级扫描信号，所述第二薄膜晶体管的源极/漏极中的另一个与所述第一薄膜晶体管的源极/漏极中的另一个和所述扫描方向控制模块的输出端连接。
  16. 根据权利要求8所述的栅极驱动电路，其中，所述扫描方向控制模块包括：
    正向扫描控制模块，所述正向扫描控制模块的输入端用于接入所述第N+2级时钟信号，所述正向扫描控制模块的控制端用于接入所述第N+2级时钟信号和所述正向扫描控制信号；和
    反向扫描控制模块，所述反向扫描控制模块的输入端用于接入所述第N-2级时钟信号，所述反向扫描控制模块的控制端用于接入所述第N-2级时钟信号和所述反向扫描控制信号，所述反向扫描控制模块的输出端与所述正向扫描控制模块的输出端和所述上拉控制模块的输出端连接。
  17. 根据权利要求16所述的栅极驱动电路，其中，所述正向扫描控制模块包括第三薄膜晶体管和第四薄膜晶体管，所述第三薄膜晶体管的源极/漏极中的一个用于接入所述第N+2级时钟信号，所述第三薄膜晶体管的栅极用于接入所述第N+2级时钟信号，所述第三薄膜晶体管的源极/漏极中的另一个与所述第四薄膜晶体管的源极/漏极中的一个连接，所述第四薄膜晶体管的栅极用于接入所述正向扫描控制信号，所述第四薄膜晶体管的源极/漏极中的另一个与所述上拉控制模块的输出端连接；和/或
    所述反向扫描控制模块包括第五薄膜晶体管和第六薄膜晶体管，所述第五薄膜晶体管的源极/漏极中的一个用于接入所述第N-2级时钟信号，所述第五薄膜晶体管的栅极用于接入所述第N-2级时钟信号，所述第五薄膜晶体管的源极/漏极中的另一个与所述第六薄膜晶体管的源极/漏极中的一个连接，所述第六薄膜晶体管的栅极用于接入所述反向扫描控制信号，所述第六薄膜晶体管的源极/漏极中的另一个与所述上拉控制模块的输出端连接。
  18. 根据权利要求17所述的栅极驱动电路，其中，所述上拉输出模块包括第七薄膜晶体管；所述第七薄膜晶体管的栅极与所述第四薄膜晶体管的源极/漏极中的另一个和/或所述第六薄膜晶体管的源极/漏极中的另一个连接；所述第七薄膜晶体管的源极/漏极中的一个用于接入第N级时钟信号；第七薄膜晶体管T8的源极/漏极中的另一个用于输出所述第N级扫描信号。
  19. 一种显示面板，包括如权利要求1所述的栅极驱动电路。
  20. 根据权利要求19所述的显示面板，其中，所述显示面板的工作阶段包括行扫描阶段；所述行扫描阶段包括触控扫描阶段；所述栅极驱动电路分时工作于所述行扫描阶段和所述触控扫描阶段。
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