WO2022241626A1 - 一种载板以及转移装置 - Google Patents

一种载板以及转移装置 Download PDF

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Publication number
WO2022241626A1
WO2022241626A1 PCT/CN2021/094195 CN2021094195W WO2022241626A1 WO 2022241626 A1 WO2022241626 A1 WO 2022241626A1 CN 2021094195 W CN2021094195 W CN 2021094195W WO 2022241626 A1 WO2022241626 A1 WO 2022241626A1
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Prior art keywords
dissociation
arc
layer
carrier
microstructure
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PCT/CN2021/094195
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English (en)
French (fr)
Inventor
李海旭
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/094195 priority Critical patent/WO2022241626A1/zh
Priority to US17/760,982 priority patent/US20240047250A1/en
Priority to CN202180001170.XA priority patent/CN115643816A/zh
Publication of WO2022241626A1 publication Critical patent/WO2022241626A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67333—Trays for chips
    • H01L21/67336—Trays for chips characterized by a material, a roughness, a coating or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes

Definitions

  • the present application relates to the field of display technology, in particular to a carrier and a transfer device.
  • LED display technology As a new type of display technology, has gradually become one of the research hotspots.
  • Light Emitting Diode display technology uses an array of Light Emitting Diodes (LEDs) for display.
  • LED display technology has the advantages of high luminous intensity, fast response speed, low power consumption, low voltage demand, light and thin equipment, long service life, impact resistance, and strong anti-interference ability.
  • Micro-LEDs with smaller size can better realize high-resolution products, such as smartphones or virtual display screens with 4K or even 8K resolution.
  • the embodiment of the present invention discloses a carrier plate, including: an intermediate carrier substrate, a dissociation adjustment structure, and a dissociation adhesive layer arranged in sequence, and the dissociation adjustment structure is configured to adjust the dissociation adhesive layer
  • the dissociation precision is high, and the dissociation adhesive layer is configured to be connected with a plurality of light emitting diode chips.
  • the dissociation regulating structure includes a plurality of regulating microstructures, and each of the regulating microstructures corresponds to one of the light-emitting diode chips; wherein,
  • the orthographic projection of the adjustment microstructure on the intermediate substrate is a first projection, and the orthographic projection of the LED chip on the intermediate substrate is a second projection;
  • the first projection of each of the adjustment microstructures at least partially overlaps with the second projection of the corresponding LED chip, and the area of the first projection is smaller than or equal to the area of the second projection.
  • the adjusting microstructure includes: arc-shaped protrusions arranged on a side of the release glue layer close to the intermediate carrier substrate.
  • the intermediate carrier substrate is provided with a first arc-shaped groove at a position opposite to the arc-shaped protrusion, and the shape of the first arc-shaped groove is adapted to the shape of the arc-shaped protrusion , the arc-shaped protrusion is embedded in the first arc-shaped groove.
  • the carrier plate further includes: a dielectric layer, the dielectric layer is arranged between the intermediate carrier substrate and the release glue layer, and the dielectric layer is at a position opposite to the arc-shaped protrusion
  • a second arc-shaped groove is provided, the shape of the second arc-shaped groove is adapted to the shape of the arc-shaped protrusion, and the arc-shaped protrusion is embedded in the second arc-shaped groove.
  • the thickness of the dielectric layer is greater than the depth of the second arc-shaped groove.
  • the thickness of the release glue layer is greater than the depth of the arc-shaped protrusion.
  • the adjustment microstructure includes a grating, and an orthographic projection of the grating on the intermediate substrate at least partially overlaps a central area of an orthographic projection of the light emitting diode chip on the intermediate substrate.
  • both the slit width and the passband width of the grating are greater than the wavelength of the dissociation light
  • the height of the grating is 1000-3000A, and the slit width and passband width of the grating are both 500-1400A.
  • the orthographic projection of the grating on the intermediate substrate is a third projection
  • the orthographic projection of the LED chip on the intermediate substrate is a second projection
  • the area of the third projection is 5%-10% of the area of the second projection.
  • the carrier plate further includes: a microlens structure, the microlens structure is disposed on the side of the intermediate carrier substrate away from the release adhesive layer;
  • the orthographic projection of the microlens structure on the intermediate substrate at least partially overlaps an edge region of the orthographic projection of the light emitting diode chip on the intermediate substrate.
  • the grating is located on a side of the intermediate carrier substrate close to the release glue layer.
  • the adjusting microstructure includes: a plurality of pre-arrangement units, the orthographic projection of the plurality of pre-arrangement units on the intermediate substrate and the orthographic projection of the light emitting diode chip on the intermediate substrate At least partially overlapped, the side of the release glue layer away from the intermediate carrier substrate is formed with a plurality of protrusions, one of the protrusions corresponds to one of the pre-arrangement units, and the gap between adjacent protrusions is Form the exhaust channel.
  • the pre-arrangement unit is made of transparent material.
  • the height of the pre-arrangement unit is 15000-20000A, and the width of the pre-arrangement unit in any direction is greater than 2.5um.
  • each of the LED chips is correspondingly provided with a plurality of the pre-arrangement units, and there is a certain distance between two adjacent pre-arrangement units.
  • the release glue layer includes: a laser release layer and a viscous glue layer, the laser dissociation layer is located on the side of the intermediate carrier substrate close to the light-emitting diode chip, and the viscous glue layer is located on the Between the laser dissociation layer and the LED chip; wherein,
  • the viscous adhesive material layer is provided with a first microstructure on a side close to the laser dissociation layer, and the laser dissociation layer is provided with a second microstructure on a side close to the viscous adhesive material layer, and the second The shape of the microstructure is complementary to that of the first microstructure, and the second microstructure and the first microstructure are interfitted with each other.
  • the thickness of the laser dissociation layer is 1-3um, and the thickness of the viscous adhesive layer is 1-10um.
  • the first microstructure is a nano-microstructure, and the first microstructure is selected from at least one of conical microstructures and prismatic microstructures.
  • the first microstructure is cone-shaped, the height of the cone is 0.2-1um, the diameter of the bottom of the cone is 100-500nm, and the distance between the side and the bottom of the cone is The included angle is 15-60°.
  • the refractive index of the viscous adhesive material layer is greater than or equal to 1.5, and the light transmittance of the viscous adhesive material layer is greater than or equal to 97%.
  • the embodiment of the present application also discloses a transfer device, the transfer device includes: a plurality of light-emitting diode chips and the carrier board described in any one of the above; the plurality of light-emitting diode chips are connected to the carrier The dissociated glue layer of the board.
  • the dissociation adjustment structure can adjust the dissociation adjustment structure of the dissociation adhesive layer Dissociation precision. In this way, it is possible to avoid the positional displacement of the light emitting diode chip during the falling process, and improve the yield rate and dissociation precision of the light emitting diode chip, thereby improving the yield rate and dissociation accuracy of the light emitting diode chip in the mass transfer process. Efficiency of mass transfers.
  • FIG. 1 schematically shows a schematic diagram of an existing carrier plate used for transferring light-emitting diode chips
  • FIG. 2 schematically shows a detailed structural diagram of position A in Fig. 1;
  • FIG. 3 schematically shows a schematic structural view of a carrier board according to an embodiment of the present application
  • Fig. 4 schematically shows a schematic structural view of a dissociated glue layer in the embodiment of the present application
  • FIG. 5 schematically shows a schematic structural view of a medium carrier substrate in the carrier shown in FIG. 3;
  • FIG. 6 schematically shows a schematic structural view of another carrier of the embodiment of the present application.
  • Fig. 7 schematically shows a schematic view of the structure of the carrier plate shown in Fig. 6 with the release adhesive layer removed;
  • FIG. 8 schematically shows a schematic structural view of another carrier of the embodiment of the present application.
  • FIG. 9 schematically shows a schematic top view of the carrier shown in FIG. 8.
  • FIG. 10 schematically shows a schematic structural view of another carrier in the embodiment of the present application.
  • FIG. 11 schematically shows a schematic structural view of another carrier in the embodiment of the present application.
  • Fig. 12 schematically shows one of the processing status diagrams of the carrier shown in Fig. 11;
  • Fig. 13 schematically shows the second processing state view of the carrier shown in Fig. 11;
  • Figure 14 schematically shows a schematic structural view of another carrier of the present application.
  • Fig. 15 schematically shows a schematic structural view of another carrier according to the embodiment of the present application.
  • Figure 16 schematically shows one of the specific processing schematic diagrams of the carrier plate shown in Figure 15;
  • Fig. 17 schematically shows the second specific processing schematic diagram of the carrier plate shown in Fig. 15;
  • Fig. 18 schematically shows the third schematic diagram of the specific processing of the carrier plate shown in Fig. 15;
  • Fig. 19 schematically shows the fourth schematic diagram of the specific processing of the carrier plate shown in Fig. 15;
  • Fig. 20 schematically shows a flow chart of steps of a method for processing a carrier according to an embodiment of the present application
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.
  • the carrier board may include an intermediate carrier substrate 10 and a release adhesive layer 12 , and the release adhesive layer 12 may be configured to be connected to a plurality of LED chips 20 .
  • the dissociation light (as shown by the arrow in Figure 1) can be irradiated on the dissociation adhesive layer 12 through the mask, and the dissociation adhesive layer 12 can be vaporized and decomposed under the irradiation of the dissociation light, so that the light emitting diode chip 20 Separated from the intermediate substrate 10 , the light emitting diode chips 20 can be dropped and transferred onto the driving substrate of the display device, so as to realize mass transfer of the light emitting diode chips 20 .
  • the central area of the dissociation adhesive layer 12 will preferentially The dissociation forms a microcavity S, and the gas generated by gasification of the dissociation adhesive layer 12 also exists in the microcavity 12 .
  • the dissociation adhesive layer 12 After the dissociation adhesive layer 12 is dissociated as a whole, due to the uncertainty of the gas impact in the microcavity S, the deviation of the falling posture and position of the light-emitting diode chip 20 will be caused, and it is easy to cause the light-emitting diode chip 20 to lose its position during the falling process. Offset seriously reduces the transfer yield of the LED chip 20 and reduces the dissociation precision of the LED chip 20 .
  • the light emitting diode chip 20 may include a light emitting layer 201 with a sandwich structure and a first electrode 202 and a second electrode 203 disposed on the same side of the light emitting layer 201 .
  • the light-emitting layer 201 can be a semiconductor thin film layer, and the semiconductor thin film layer can be made of materials such as P-GaN, MQW or N-GaN, the first electrode 202 can be a positive electrode, and the second electrode 203 can be a negative electrode.
  • the side of the light-emitting diode chip 20 that is not provided with electrodes can face the dissociation adhesive layer 12, and the side of the light-emitting diode chip 20 provided with electrodes faces the driving substrate.
  • the second The first electrode 202 and the second electrode 203 can be fixedly connected with pads on the driving substrate.
  • FIG. 3 it shows a schematic structural diagram of a carrier board according to an embodiment of the present application. As shown in FIG. 3 ,
  • the carrier plate may specifically include: an intermediate carrier substrate 10, a dissociation adjustment structure, and a dissociation adhesive layer 12 arranged in sequence, and the dissociation adjustment structure may be configured to adjust the dissociation accuracy of the dissociation adhesive layer 12.
  • the glue layer 12 may be configured to be connected with a plurality of LED chips 20 .
  • the release adhesive layer 12 of the carrier board can be configured to connect with a plurality of light emitting diode chips 20, and the plurality of light emitting diode chips 20 can be distributed in arrays on the carrier board.
  • the light emitting diode chips 20 may be light emitting diode chips emitting the same color, or may be light emitting diode chips emitting different colors, which is not limited in this embodiment of the present application.
  • the dissociation adhesive layer 12 may be a laser dissociation adhesive, and by irradiating laser light to a part of the intermediate carrier substrate 10, the dissociation adhesive layer 12 in the corresponding area can be dissociated, so that the light-emitting diode chip 20 in this area falls off. , and transferred to the driver substrate.
  • the release adhesive layer 12 can also be pyrolytic adhesive; at this time, the corresponding area of the release adhesive layer 12 can be dissociated by heating a part of the intermediate substrate 10, so that the light-emitting diode chip 20 in this area falls off. , and transferred to the driver substrate.
  • the intermediate substrate 10 when it is necessary to transfer the light-emitting diode chip 20 on the intermediate substrate 10 to the driving substrate, the intermediate substrate 10 can be arranged above the driving substrate according to the direction of gravity, that is, the intermediate substrate 10 and the driving substrate are along the The direction of gravity is set in order, so that the light-emitting diode core 20 to be transferred on the intermediate substrate 10 can be transferred to the driving substrate by utilizing the gravity and coordinating with the above-mentioned release glue layer 12 .
  • the dissociation adjustment structure since the dissociation adjustment structure is set between the dissociation adhesive layer 12 and the medium-mounted substrate 10, the dissociation adjustment structure can adjust the dissociation adjustment structure of the dissociation adhesive layer 12 during the mass transfer process of the light-emitting diode chip 20. dissociation precision. In this way, it is possible to avoid the positional deviation of the light emitting diode chip 20 during the falling process, and improve the yield rate and dissociation precision of the light emitting diode chip 20, thereby improving the yield rate and the mass transfer process of the light emitting diode chip 20. The efficiency of mass transfer.
  • the dissociation regulating structure may include a plurality of regulating microstructures, and each of the regulating microstructures corresponds to a light-emitting diode chip 20; wherein, the regulating microstructures are carried in The orthographic projection on the substrate 10 is the first projection, and the orthographic projection of the light-emitting diode chip 20 on the medium-mounted substrate 10 is the second projection; the first projection of each of the adjustment microstructures and the second projection of the corresponding light-emitting diode chip 20 The projections at least partially overlap, and the area of the first projection is smaller than or equal to the area of the second projection.
  • the adjustment microstructure may be a pattern and a microstructure, or may be a grating, a microlens, or a preset structure, etc., and the microstructure may optimize the interface morphology of the debonding adhesive layer 12 .
  • the periphery can be used to automatically exhaust air.
  • the adjustment microstructure can be arranged in the central area of the light emitting diode chip 20, so that the central area of the first projection and the second projection overlap; or, the microstructure can also be arranged in the light emitting diode chip 20 The edge area of the chip 20, so that the edge area of the first projection and the second projection overlap; or, the micro-adjustment structure can also be arranged on the entire outer surface area of the entire light-emitting diode chip 20, so that The first projection completely overlaps the second projection.
  • the present application does not limit the specific position of the micro-adjustment structure relative to the LED chip 20 .
  • the adjustment of the microstructure may specifically include: arc-shaped protrusions 121 disposed on the side of the release glue layer 12 close to the intermediate carrier substrate 10 .
  • FIG. 4 it shows a schematic structural view of a dissociation glue layer according to an embodiment of the present application.
  • the thickness of the central region of the debonding glue layer 12 is greater than the thickness of the edge region, and in the case of reaching the same degree of dissociation, the energy of the dissociation light required by the central region of the debonding glue layer 12 is greater than the energy of the dissociation light required by the edge region. energy.
  • the energy of the dissociation light irradiating on the arc-shaped protrusion 121 generally decreases from the central area to the edge area.
  • the thickness of the debonding glue layer 12 can be gradually reduced from the central area to the edge area, and the energy distribution of the dissociation light can be adapted to make the debonding glue layer
  • the central area and the edge area of 12 can realize the same degree of dissociation, avoiding the microcavity and gas produced by the dissociation of the central area of the dissociation adhesive layer 12, thereby, the impact of the gas can be avoided, and the light-emitting diode chip 20 can be prevented from falling.
  • a position shift occurs during the process, which improves the yield rate and dissociation precision of the light emitting diode chip 20 . Furthermore, the yield rate and the mass transfer efficiency of the light emitting diode chip 20 during the mass transfer process can be improved.
  • the arc of the arc-shaped protrusion 121 can be set according to the energy distribution of the dissociated light, and the embodiment of the present application does not specifically limit the arc of the arc-shaped protrusion.
  • FIG. 5 it shows a schematic view of the structure of the middle carrier substrate in the carrier shown in FIG. 3 .
  • the groove 101 and the shape of the first arc-shaped groove 101 are adapted to the shape of the arc-shaped protrusion 121 , and the arc-shaped protrusion 121 is embedded in the first arc-shaped groove 101 .
  • the first arc-shaped groove 101 can be formed on the intermediate carrier substrate 10 first, and then the dissociation gel can be applied on the side where the first arc-shaped groove 101 is formed, and the dissociation glue can flow into In the first arc-shaped groove 101 , in this way, an arc-shaped protrusion 121 can be formed on the finally formed release glue layer 12 .
  • Forming the first arc-shaped groove 101 directly on the intermediate carrier substrate 10 can make the carrier substrate simpler in structure and lower in height.
  • the shape adaptation of the first arc-shaped groove 101 and the arc-shaped protrusion 121 may specifically include: the shape of the first arc-shaped groove 101 and the arc-shaped protrusion 121 are the same, or, the first arc-shaped groove 101 slightly larger than the arc-shaped protrusion 121 so as to form the arc-shaped protrusion 121 in the first arc-shaped groove 101 .
  • the carrier board may further include: a dielectric layer 11, which is disposed between the intermediate carrier substrate 10 and the release adhesive layer 12, and the dielectric layer 11 is provided with a The second arc-shaped groove 111 , the shape of the second arc-shaped groove 111 is adapted to the shape of the arc-shaped protrusion 121 , and the arc-shaped protrusion 121 is embedded in the second arc-shaped groove 111 .
  • the intermediate substrate 10 is usually made of glass
  • the process of directly forming an arc-shaped groove on the intermediate substrate 10 is generally complicated and the processing cost is relatively high.
  • a layer of dielectric layer 11 can be formed on the medium carrier substrate 10, and then a second arc-shaped groove 111 is formed on the dielectric layer 11.
  • the process is relatively simple.
  • the material of the dielectric layer 11 may be at least one of silicon oxide and silicon nitride.
  • the material of the dielectric layer 11 is silicon oxide or silicon nitride, it can facilitate the photolithography process on the dielectric layer 11.
  • a photolithography process may be used to form a correspondingly formed concave with a certain curvature at the position where the LED chip 20 needs to be connected, that is, the second curved groove 111 .
  • the side where the second arc-shaped groove 111 is formed on the dielectric layer 111 is coated with a dissociating glue, and the dissociating glue can flow into the second arc-shaped groove 111, so that the finally formed dissociating glue can Curved protrusions 121 may be formed on the layer 12 .
  • Forming the second arc-shaped groove 111 on the dielectric layer 11 by photolithography can make the processing technology of the second arc-shaped groove 111 relatively simple, and the processing cost is low.
  • the shape adaptation between the second arc-shaped groove 111 and the arc-shaped protrusion 121 may specifically include: the shape of the second arc-shaped groove 111 is the same as that of the arc-shaped protrusion 121, or, the second arc-shaped groove 111 slightly larger than the arc-shaped protrusion 121 so as to form the arc-shaped protrusion 121 in the second arc-shaped groove 111 .
  • the thickness of the dielectric layer 11 may be greater than the depth of the second arc-shaped groove 111 , so as to form a complete second arc-shaped groove 111 on the dielectric layer 11 .
  • the dielectric layer 11 being completely etched away during the photolithography process to expose the intermediate carrier substrate 10, and to improve the regularity and integrity of the second arc-shaped groove 111 on the dielectric layer 11, which is beneficial to A regular and complete arc-shaped protrusion 121 is obtained.
  • the depth of the second arc-shaped groove 111 may specifically be the depth corresponding to the deepest position of the second arc-shaped groove 111 .
  • the thickness of the second dielectric layer 11 may be 5000-10000A.
  • the depth of the second arc-shaped groove 111 is greater than or equal to 1000 ⁇ , and less than the thickness of the dielectric layer 11 .
  • the thickness of the release adhesive layer 12 is greater than the depth of the arc-shaped protrusion 121 , so as to achieve reliable bonding of the LED chip 21 on the intermediate carrier substrate 10 .
  • the depth of the arc-shaped protrusion 121 may specifically be the depth corresponding to the highest position of the arc-shaped protrusion 121 .
  • the thickness of the release adhesive layer 12 can be determined according to the actual use effect.
  • the thickness of the release glue layer 12 can be 1-5um
  • the thickness of the corresponding dielectric layer 11 can be higher than 3000A
  • the depth of the arc-shaped protrusion 121 can be 500-2500A.
  • the adjustment microstructure may include a grating 13, and the orthographic projection and light emission of the grating 13 on the medium carrier substrate 10 Central regions of the orthographic projections of the diode chips 20 on the intermediate substrate 10 are at least partially overlapped.
  • the central area of the orthographic projection of the light emitting diode chip 20 on the intermediate substrate 10 may be: the area covered by a circle drawn with a preset distance as the radius around the center of the orthographic projection of the light emitting diode chip 20, The preset distance may be 10%-50% of the distance from the center to the edge of the LED chip 20 ; or, the central area may also be an orthographic projection area close to the center of the LED chip 20 .
  • the area outside the central area may be an edge area.
  • the grating 13 may be located on a side of the intermediate carrier substrate 10 close to the release glue layer 12 .
  • the dissociation light enters from the side of the intermediate carrier substrate 10 , it can be diffracted at the grating 13 to reduce the energy of the dissociation light.
  • the center of the orthographic projection of the grating 13 on the intermediate substrate 10 and the orthographic projection of the light emitting diode chip 20 on the intermediate substrate 10 can be made The regions at least partially overlap.
  • the energy of the dissociation light irradiated to the central area of the dissociation adhesive layer 12 can be reduced, thereby, the light rays irradiated to the central area and edge areas of the dissociation adhesive layer 12 can be made relatively uniform, so that the dissociation
  • the central area and the edge area of the adhesive layer 12 can be dissociated to the same degree, so as to avoid the microcavity and gas produced by the dissociation of the central area of the adhesive layer 12 first, avoid the impact of the gas, and prevent the light-emitting diode chip 20 from falling.
  • the position shift occurs during the process, which improves the yield rate and dissociation precision of the light emitting diode chip 20, and further, can improve the yield rate and mass transfer efficiency of the light emitting diode chip 20 in the mass transfer process.
  • both the slit width and the passband width of the grating 13 are larger than the wavelength of the dissociated light, so that the dissociated light can be better diffracted at the grating 13 .
  • the slit width and passband width of the grating 13 may be 500-1400A.
  • the height of the grating 13 may be 1000-3000A. Due to the low height of the grating 13, when the grating 13 continues to be coated with the release glue, it is difficult to protrude obviously on the surface of the release glue layer 12, and the surface of the release glue layer 12 is relatively smooth, so that light can be realized Connection reliability of the diode chip.
  • FIG. 9 shows a schematic top view of the carrier plate shown in FIG. 8.
  • the orthographic projection on 10 is the second projection S2.
  • the third projection S3 may overlap the central area of the second projection S2.
  • the area of the third projection S3 is 5%-10% of the area of the second projection S2, so as to improve the uniformity of the dissociation light irradiation on the dissociation adhesive layer 20. property, so that the central area and edge area of the release adhesive layer 12 can be dissociated synchronously.
  • the area of the third projection S3 may be less than 7% of the area of the second projection S2 .
  • the carrier board shown in FIG. 10 may include: The lens structure 14, the microlens structure 14 is arranged on the side of the intermediate carrier substrate 10 away from the dissociation adhesive layer 12, the microlens structure 14 can be used for energy convergence, and adjusts the uniformity of the dissociated light incident on the intermediate carrier substrate 10, thereby , so that the central area and the edge area of the release glue layer 12 can be dissociated synchronously.
  • the microlens structure 14 can be arranged in a region where the dissociated light is relatively weak according to actual conditions.
  • the orthographic projection of the microlens structure 14 on the intermediate substrate 10 and the edge region of the orthographic projection of the light emitting diode chip 20 on the intermediate substrate 10 at least partially overlap, that is, The microlens structure 14 may be disposed at a position corresponding to the edge region of the LED chip 20 .
  • the microlens structure 14 can be used Energy concentration is performed on the dissociated light in the edge region of the LED chip 20 .
  • the arrangement area of the microlens structure 14 may be determined according to the actual situation of the dissociated light, and the embodiment of the present application does not specifically limit the arrangement area of the microlens structure 14 .
  • the material of the microlens structure 14 is a conventional lens material, such as light-transmitting resin or glass, and the radius of curvature of the microlens structure 14 depends on the actual light-gathering effect, which is not limited in this embodiment of the present application.
  • the adjustment microstructure may include: a plurality of pre-arrangement units 15 in which The orthographic projection on the carrier substrate 10 and the orthographic projection of the light emitting diode chip 20 on the intermediate carrier substrate 10 at least partially overlap, and the side of the release glue layer 12 away from the intermediate carrier substrate 10 is formed with a plurality of protrusions 122, one protrusion 122 corresponds to a pre-arrangement unit 15, and an exhaust channel L is formed between adjacent protrusions 122, so that the gas generated by the dissociation and gasification of the dissociation adhesive layer 12 can be discharged from the exhaust channel L, thereby making it possible to
  • the light-emitting diode chip 20 is protected from the impact of the gas during the falling process, avoiding the positional deviation of the light-emitting diode chip 20 during the falling process, improving the yield rate and dissociation accuracy of the light-e
  • FIG. 12 it shows one of the processing state diagrams of the carrier shown in FIG. 11 .
  • a plurality of array-distributed pre-arrangement units 15 can be provided corresponding to the positions where the light-emitting diode chips 20 need to be connected on the intermediate carrier board 10 .
  • the intermediate substrate 10 and the pre-arrangement unit 15 can be designed as an integrated structure, or the intermediate substrate 10 and the pre-arrangement unit 15 can be designed as a separate structure.
  • the connection form between the carrier substrate 10 and the pre-arrangement unit 15 may not be limited.
  • FIG. 13 it shows the second processing state diagram of the carrier shown in FIG. 11 .
  • One side of the provided pre-arrangement unit 15 is coated with release glue to form the release glue layer 12 .
  • the pre-arrangement unit 15 will prevent the dissociation glue from flowing, and the dissociation glue itself has a certain viscosity, so it is difficult for the dissociation glue to dissociate the pre-arrangement unit through its own fluidity. 15 are leveled, so that protrusions 122 will be formed at positions corresponding to the pre-arrangement unit 15, so that an exhaust passage L is formed between adjacent protrusions 122.
  • the gas generated by the dissociation and gasification of the dissociation adhesive layer 12 can be discharged from the exhaust channel L, so that the light-emitting diode chip 20 can be protected from the gas during the falling process.
  • the shock avoids the positional deviation of the light emitting diode chip 20 during the falling process, and improves the yield rate and dissociation precision of the light emitting diode chip 20 .
  • the pre-arrangement unit 15 can be made of a transparent material, so that the dissociation light can pass through the pre-arrangement unit 15 and irradiate onto the dissociation adhesive layer 12, avoiding the influence of the pre-arrangement unit 15 on the intensity of the dissociation light. influences.
  • the transparent material may be selected from at least one of silicon oxide and silicon nitride, and the embodiment of the present application does not specifically limit the transparent material.
  • the height of the pre-arrangement unit 15 can be 15000-20000 ⁇ , so that the pre-arrangement unit 15 can form an effective barrier to the release glue, and form regular protrusions 122 on the surface of the release glue layer 12 .
  • the height of the pre-arrangement unit 15 needs to be determined according to the actual thickness of the release adhesive layer 12 , the greater the thickness of the release adhesive layer 12 , the higher the height of the pre-arrangement unit 15 is.
  • the difference between the height of the pre-arrangement unit 15 and the height of the release glue layer 12 should be less than or equal to 1 um.
  • the width of any direction of the pre-arrangement unit 15 should be greater than or equal to 2.5 um, so that the pre-arrangement unit 15 has better processing performance.
  • the cross-sectional shape of the pre-arrangement unit 15 may include, but not limited to, a circle, a rectangle or other polygons, and the embodiment of the present application may not limit the specific shape of the pre-arrangement unit 15 .
  • the diameter of the circle should be greater than or equal to 2.5um; when the cross-sectional shape of the pre-arrangement unit 15 is a rectangle, the shortest side length of the rectangle Should be greater than or equal to 2.5um.
  • each light-emitting diode chip 20 is correspondingly provided with a plurality of pre-arrangement units 15, and there is a certain distance between two adjacent pre-arrangement units 15.
  • a plurality of independent exhaust channels L are formed between the chip 20 and the release glue layer 12 to further improve the stability of the exhaust.
  • the carrier may include: a dielectric layer 11 , and the dielectric layer 11 is arranged at a position opposite to the arc-shaped protrusion 121 There is a second arc-shaped groove 111 , and the side of the second arc-shaped groove 111 facing away from the intermediate carrier substrate 10 is also provided with a pre-arrangement unit 15 .
  • the material of the pre-arrangement unit 15 may be photoresist, and the pre-arrangement unit 15 in the second arc-shaped groove 111 may be made by using a mask.
  • the dissociation adhesive layer 12 may include: a laser dissociation layer 123 and a viscous adhesive material layer 124.
  • the dissociation layer 123 is located on the side of the medium-mounted substrate 10 close to the light-emitting diode chip 20, and the viscous adhesive material layer 124 is located between the laser dissociation layer 123 and the light-emitting diode chip 20;
  • a first microstructure 1241 is provided on one side of the laser dissociation layer 123, and a second microstructure 1231 is provided on the side of the laser dissociation layer 123 close to the viscous adhesive material layer 124.
  • the shape of the second microstructure 1231 is complementary to that of the first microstructure 1241, and the second The microstructure 1231 and the first microstructure 1241 are embedded with each other.
  • the laser dissociation layer 123 when the dissociation light irradiates the dissociation adhesive layer 12, under the irradiation of the dissociation light, the laser dissociation layer 123 can vaporize and dissociate, and the viscous adhesive material layer 124 can fall off together with the LED chip 20, because A first microstructure 1241 is provided on the side of the adhesive adhesive material layer 124 close to the laser dissociation layer 123, and the first microstructure 1241 can be used as a light extraction structure without removing the adhesive adhesive material layer 124 on the LED chip 20, In this way, the operation of removing the residual glue on the LED chip 20 is avoided, and the efficiency of mass transfer of the LED chip 20 is further improved.
  • the adjustment microstructure disposed between the release glue layer 12 and the intermediate carrier substrate 10 is not shown.
  • an adjustment microstructure may be provided between the release glue layer 12 and the intermediate substrate 10, and the adjustment microstructure may include but not limited to the above-mentioned embodiments. Any one of arc-shaped protrusions, gratings, and pre-arrangement units, which is not limited in this embodiment of the present application.
  • the first microstructure 1241 can be a nano-microstructure, so that the first microstructure 1241 can function as a nano-microlens to achieve a better light extraction effect.
  • the first microstructure 1241 may be selected from at least one of a conical microstructure and a prismatic microstructure, and the embodiment of the present application may not specifically limit the shape of the first microstructure 1241 .
  • the first microstructure 1241 when the first microstructure 1241 is in the shape of a cone, the height of the cone is 0.2-1um, and the diameter of the bottom surface of the cone is 100-500nm, so The included angle between the side surface and the bottom surface of the tapered shape is 15-60°, so that the first microstructure 1241 can achieve better light extraction effect.
  • the thickness of the laser dissociation layer 123 is 1-3 um, so that the laser dissociation layer 123 can achieve better bonding effect and at the same time, the dissociation efficiency is higher.
  • the thickness of the adhesive material layer 124 is 1-10 um, so that the adhesive material layer 124 can be reliably connected to the LED chip 20 and can achieve a better light extraction effect.
  • the refractive index of the adhesive adhesive material layer 124 is greater than or equal to 1.5, and the light transmittance of the adhesive adhesive material layer 124 is greater than or equal to 97%, so that the adhesive adhesive material layer 124 can transmit light to achieve better Light extraction effect.
  • a specific processing schematic diagram of the carrier plate shown in FIG. 15 can be provided.
  • a laser dissociation glue can be coated on the intermediate carrier substrate 10, for example, a layer of 1-3um thick dissociation glue layer can be coated and cured accordingly, after the curing is completed, the A second microstructure 1231 is formed on the surface of the debonding glue layer to obtain a jagged laser debonding layer 123 .
  • the second microstructure 1231 can be formed on the surface of the laser dissociation layer 123 by nanoimprinting or photolithography, and the embodiment of the present application does not limit the specific formation process of the second microstructure 1231 .
  • an adhesive material may be coated on the laser-dissociated layer 124 to form an adhesive adhesive material layer 124 . Due to the leveling property of the viscous material itself, after coating and fixing, the viscous adhesive material layer 124 will automatically produce a flat and filling effect on the side close to the laser dissociation layer 124, forming a first microstructure 1231 whose shape is complementary to that of the second microstructure 1231.
  • the microstructure 1241 , and the second microstructure 1241 can be embedded with the first microstructure 1231 .
  • the LED chip 20 can be bound on the adhesive material layer 124 , and the LED chip 20 can be bound to the intermediate substrate 20 .
  • the specific curing process can be: pressurization and heating ⁇ holding for a certain time (5min) ⁇ high temperature curing (230°C).
  • a mask can be used to ash the release adhesive layer 12 to obtain the carrier plate shown in FIG. 15 .
  • the carrier board shown in FIG. 15 is in the process of transferring the LED chip 20 to the driver chip 40 .
  • the laser dissociation layer 123 can vaporize and dissociate, while the viscous adhesive material layer 124 can fall off together with the light-emitting diode chip 20.
  • a microstructure 1241, the first microstructure 1241 can be used as a light extraction structure without removing the adhesive material layer 124 on the LED chip, thus avoiding the operation of removing the residual glue on the LED chip 20, further The mass transfer efficiency of the LED chip 20 is improved.
  • the carrier board described in the embodiment of the present application can at least include the following advantages:
  • the dissociation adjustment structure can adjust the dissociation adjustment structure of the dissociation adhesive layer Dissociation precision. In this way, it is possible to avoid the positional displacement of the light emitting diode chip during the falling process, and improve the yield rate and dissociation precision of the light emitting diode chip, thereby improving the yield rate and dissociation accuracy of the light emitting diode chip in the mass transfer process. Efficiency of mass transfers.
  • the embodiment of the present application also provides a transfer device, and the transfer device may specifically include: the above-mentioned carrier board for multiple light emitting diode chips;
  • the transfer device can be used to transfer the plurality of light emitting diode chips to the driving chip of the display device, so as to realize mass transfer of the light emitting diode chips.
  • the structure of the carrier board in the embodiment of the present application is the same as the structure of the carrier board in the foregoing embodiments, and will not be repeated here.
  • the dissociation adjustment structure is set between the dissociation adhesive layer and the medium-carrying substrate on the carrier plate, and the dissociation adjustment structure can adjust the dissociation adjustment structure during the mass transfer process of the light-emitting diode chips.
  • the dissociation accuracy of the gel layer In this way, it is possible to avoid the positional displacement of the light emitting diode chip during the falling process, and improve the yield rate and dissociation precision of the light emitting diode chip, thereby improving the yield rate and dissociation accuracy of the light emitting diode chip in the mass transfer process. Efficiency of mass transfers.
  • FIG. 20 it shows a flow chart of the steps of a processing method of a carrier board according to an embodiment of the present application.
  • the processing method can be used to process the carrier boards in the foregoing embodiments.
  • the processing method can specifically include the following steps :
  • Step S11 forming a dissociation regulating structure on the intermediate substrate.
  • the dissociation regulating structure may be formed on the intermediate carrier substrate 10 first, so as to form the dissociation regulating structure between the dissociation adhesive layer 12 and the intermediate carrier substrate 10 .
  • the dissociation regulating structure can adjust the dissociation precision of the dissociation adhesive layer 12. In this way, it is possible to avoid the positional deviation of the light emitting diode chip 20 during the falling process, and improve the yield rate and dissociation precision of the light emitting diode chip 20, thereby improving the yield rate and the mass transfer process of the light emitting diode chip 20. The efficiency of mass transfer.
  • the dissociation regulating structure may include a plurality of regulating microstructures, and each of the regulating microstructures corresponds to a light-emitting diode chip 20; wherein, the regulating microstructures are carried in The orthographic projection on the substrate 10 is the first projection, and the orthographic projection of the light-emitting diode chip 20 on the medium-mounted substrate 10 is the second projection; the first projection of each of the adjustment microstructures and the second projection of the corresponding light-emitting diode chip 20 The projections at least partially overlap, and the area of the first projection is smaller than or equal to the area of the second orthographic projection.
  • the adjustment microstructure may be a pattern and a microstructure, or may be a grating, a microlens, or a preset structure, etc., and the microstructure may optimize the interface morphology of the debonding adhesive layer 12 .
  • the periphery can be used to automatically exhaust air.
  • the adjustment microstructure can be arranged in the central area of the light emitting diode chip 20, so that the central area of the first projection and the second projection overlap; or, the microstructure can also be arranged in the light emitting diode chip 20 The edge area of the chip 20, so that the edge area of the first projection and the second projection overlap; or, the micro-adjustment structure can also be arranged on the entire outer surface area of the entire light-emitting diode chip 20, so that The first projection completely overlaps the second projection.
  • the present application does not limit the specific position of the micro-adjustment structure relative to the LED chip 20 .
  • Step S12 Coating a dissociation glue on the side of the intermediate carrier substrate on which the dissociation regulating structure is formed to form a dissociation glue layer, and the dissociation glue layer is configured to be connected to a plurality of light emitting diode chips.
  • the release glue layer 12 of the carrier board can be configured to connect with a plurality of light emitting diode chips 20, and the plurality of light emitting diode chips 20 can be distributed in an array on the carrier board.
  • the light emitting diode chips 20 may be light emitting diode chips emitting the same color, or may be light emitting diode chips emitting different colors, which is not limited in this embodiment of the present application.
  • the dissociation adhesive layer 12 may be a laser dissociation adhesive, and by irradiating laser light to a part of the intermediate carrier substrate 10, the dissociation adhesive layer 12 in the corresponding area can be dissociated, so that the light-emitting diode chip 20 in this area falls off. , and transferred to the driver substrate.
  • the release adhesive layer 12 can also be pyrolytic adhesive; at this time, the corresponding area of the release adhesive layer 12 can be dissociated by heating a part of the intermediate substrate 10, so that the light-emitting diode chip 20 in this area can be dissociated. detached and transferred to the drive substrate.
  • the dissociation adjustment structure is set between the dissociation adhesive layer and the medium-carrying substrate on the carrier plate, and the dissociation adjustment structure can adjust the dissociation adjustment structure during the mass transfer process of the light-emitting diode chips.
  • the dissociation accuracy of the gel layer In this way, it is possible to avoid the positional displacement of the light emitting diode chip during the falling process, and improve the yield rate and dissociation precision of the light emitting diode chip, thereby improving the yield rate and dissociation accuracy of the light emitting diode chip in the mass transfer process. Efficiency of mass transfers.
  • the device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative efforts.
  • references herein to "one embodiment,” “an embodiment,” or “one or more embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Additionally, please note that examples of the word “in one embodiment” herein do not necessarily all refer to the same embodiment.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
  • the invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

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Abstract

本申请实施例提供了一种载板以及转移装置，所述载板具体包括依次设置的中载基板、解离调节结构以及解离胶层，所述解离调节结构被配置为调节所述解离胶层的解离精度，所述解离胶层被配置为与多个发光二极管芯片连接。所述载板可以提高所述发光二极管芯片的良率和解离精度，从而，可以提高所述发光二极管芯片在进行巨量转移过程中的良率和巨量转移的效率。

Description

一种载板以及转移装置 技术领域
本申请涉及显示技术领域，尤其涉及一种载板以及一种转移装置。
背景技术
随着显示技术的不断发展，发光二极管显示技术作为一种新型的显示技术已逐渐成为研究的热点之一。发光二极管显示技术利用发光二极管(Light Emitting Diode，LED)组成的阵列来进行显示。相对于其他显示技术，发光二极管显示技术具有发光强度高、响应速度快、功耗低、电压需求低、设备轻薄、使用寿命长、耐冲击、抗干扰能力强等优点。而具有较小尺寸的微型发光二极管(Micro-LED)可更好地实现高分辨率的产品，例如4K甚至8K分辨率的智能手机或虚拟显示屏幕等。
在发光二极管基板的生产过程中，通常需要采用载板来实现发光二极管芯片的巨量转移。载板中的解离胶层受激发后，在解离胶层整体解离之前，解离胶层的内部会先产生气体形成微腔，这样，很容易使得发光二极管芯片在下落过程发生位置偏移，严重降低了发光二极管芯片的转移良率，并降低了发光二极管芯片的解离精度。
发明内容
第一方面，本发明实施例公开了一种载板，包括：依次设置的中载基板、解离调节结构以及解离胶层，所述解离调节结构被配置为调节所述解离胶层的解离精度，所述解离胶层被配置为与多个发光二极管芯片连接。
可选地，所述解离调节结构包括多个调节微结构，每个所述调节微结构与一个所述发光二极管芯片对应；其中，
所述调节微结构在所述中载基板上的正投影为第一投影，所述发光二极管芯片在所述中载基板上的正投影为第二投影；
每个所述调节微结构的第一投影与其对应的所述发光二极管芯片的第二投影至少部分重叠，且所述第一投影的面积小于或者等于所述第二投影的面积。
可选地，所述调节微结构包括：设置在所述解离胶层靠近所述中载基板一侧的弧形凸起。
可选地，所述中载基板在与所述弧形凸起相对的位置设置有第一弧形凹槽，所述第一弧形凹槽的形状与所述弧形凸起的形状适配，所述弧形凸起嵌设于所述第一弧形凹槽内。
可选地，所述载板还包括：介质层，所述介质层设置于所述中载基板和所述解离胶层之间，所述介质层在与所述弧形凸起相对的位置设置有第二弧形凹槽，所述第二弧形凹槽的形状与所述弧形凸起的形状适配，所述弧形凸起嵌设于所述第二弧形凹槽内。
可选地，，所述介质层的厚度大于所述第二弧形凹槽的深度。
可选地，所述解离胶层的厚度大于所述弧形凸起的深度。
可选地，所述调节微结构包括光栅，所述光栅在所述中载基板上的正投影与所述发光二极管芯片在所述中载基板上的正投影的中央区域至少部分交叠。
可选地，所述光栅的狭缝宽度和通带宽度皆大于解离光的波长；
所述光栅的高度为1000-3000A，所述光栅的狭缝宽度和通带宽度皆为500-1400A。
可选地，所述光栅在所述中载基板上的正投影为第三投影，所述发光二极管芯片在所述中载基板上的正投影为第二投影，所述第三投影的面积为所述第二投影的面积的5％-10％。
可选地，所述载板还包括：微透镜结构，所述微透镜结构设置在所述中载基板上远离所述解离胶层的一侧；
所述微透镜结构在所述中载基板上的正投影与所述发光二极管芯片在所述中载基板上的正投影的边缘区域至少部分交叠。
可选地，所述光栅位于所述中载基板靠近所述解离胶层的一侧。
可选地，所述调节微结构包括：多个预布置单元，所述多个预布置单元在所述中载基板上的正投影与所述发光二极管芯片在所述中载基板上的正投影至少部分交叠，所述解离胶层远离所述中载基板的一侧形成有多个凸起，一个所述凸起与一个所述预布置单元对应，相邻的所述凸起之间形成排气通道。
可选地，所述预布置单元采用透明材料制成。
可选地，所述预布置单元的高度为15000-20000A，所述预布置单元任一方向的宽度大于2.5um。
可选地，每个所述发光二极管芯片对应设置有多个所述预布置单元，相 邻的两个所述预布置单元之间具有一定距离。
可选地所述解离胶层包括：激光解离层和粘性胶材层，所述激光解离层位于所述中载基板靠近所述发光二极管芯片的一侧，所述粘性胶材层位于所述激光解离层与所述发光二极管芯片之间；其中，
所述粘性胶材层靠近所述激光解离层的一侧设置有第一微结构，所述激光解离层靠近所述粘性胶材层的一侧设置有第二微结构，所述第二微结构与所述第一微结构的形状互补，所述第二微结构与所述第一微结构相互嵌合。
可选地，所述激光解离层的厚度为1-3um，所述粘性胶材层的厚度为1-10um。
可选地，所述第一微结构为纳米微结构，所述第一微结构选自圆锥状微结构、棱状微结构中的至少一种。
可选地，所述第一微结构的为锥形，所述锥形的高度为0.2-1um，所述锥形的底面的直径为100-500nm，所述锥形的侧面与底面之间的夹角为15-60°。
可选地，所述粘性胶材层的折射率大于或者等于1.5，所述粘性胶材层的光透过率大于或者等于97％。
第二方面，本申请实施例还公开了一种转移装置，所述转移装置包括：多个发光二极管芯片以及上述任一项所述的载板；所述多个发光二极管芯片连接于所述载板的解离胶层。
本申请实施例中，通过在解离胶层与中载基板之间设置解离调节结构，在发光二极管芯片的巨量转移过程中，所述解离调节结构可以调节所述解离胶层的解离精度。这样，就可以避免发光二极管芯片在下落过程中发生位置偏移，提高所述发光二极管芯片的良率和解离精度，从而，可以提高所述发光二极管芯片在进行巨量转移过程中的良率和巨量转移的效率。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在 不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示意性地示出了现有的一种的载板用于发光二级管芯片的转移的示意图；
图2示意性地示出了图1中A位置的详细结构示意图；
图3示意性地示出了本申请实施例的一种载板的结构示意图；
图4示意性地示出了本申请实施例的一种解离胶层的结构示意图；
图5示意性地示出了图3所示的载板中的中载基板的结构示意图；
图6示意性地示出了本申请实施例的另一种载板的结构示意图；
图7示意性地示出了图6所示的载板去除了解离胶层的结构示意图；
图8示意性地示出了本申请实施例的另一种载板的结构示意图；
图9示意性地示出了图8所示的载板的俯视结构示意图；
图10示意性地示出了本申请实施例的再一种载板的结构示意图；
图11示意性地示出了本申请实施例的再一种载板的结构示意图；
图12示意性地示出了图11所示的载板的加工状态图之一；
图13示意性地示出了图11所示的载板的加工状态图之二；
图14示意性地示出了本申请的另一种载板的结构示意图；
图15示意性地示出了本申请实施例的又一种载板的结构示意图；
图16示意性地示出了图15所示的载板的具体加工示意图之一；
图17示意性地示出了图15所示的载板的具体加工示意图之二；
图18示意性地示出了图15所示的载板的具体加工示意图之三；
图19示意性地示出了图15所示的载板的具体加工示意图之四；
图20示意性地示出了本申请实施例的一种载板的加工方法的步骤流程图；
附图标记说明：10-中载基板，101-第一弧形凹槽，11-介质层，111-第二弧形凹槽，12-解离胶层，121-弧形凸起，122-凸起，123-激光解离层，1231-第二微结构，124-粘性胶材层，1241-第一微结构，13-光栅，14-微透镜结构，15-预布置单元，20-发光二极管芯片，201-发光层，202-第一电极，203-第二电极，30-掩模，S-微腔，S2-第二投影。S3-第三投影，L-排气通道。
具体实施例
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述， 显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
参照图1，示出了现有的一种的载板用于发光二级管芯片的转移的示意图，参照图2，示意出了图1中A位置的详细结构示意图。具体的，所述载板可以包括中载基板10和解离胶层12，解离胶层12可以被配置为与多个发光二极管芯片20连接。
如图1所示，解离光(如图1中的箭头所示)可经过掩模照射在解离胶层12上，解离胶层12在解离光的照射下可气化分解，使得发光二极管芯片20与中载基板10分离，发光二极管芯片20可以下落转移至显示装置的驱动基板上，实现发光二极管芯片20的巨量转移。
如图2所示，在解离光照射在解离胶层12后，由于解离光能量在解离胶层12的中央区域的强度高于边缘区域的强度，因此，解离胶层12的中央区域会优先解离形成微腔S，解离胶层12气化产生的气体也会存在微腔12 内。在解离胶层12整体解离后，由于微腔S内的气体冲击作用的不确定性，会导致发光二极管芯片20下落姿势和位置的偏差，很容易使得发光二极管芯片20在下落过程发生位置偏移，严重降低了发光二极管芯片20的转移良率，并降低了发光二极管芯片20的解离精度。
如图2所示，发光二极管芯片20可以包括三明治结构的发光层201以及设置在发光层201上同一侧的第一电极202和第二电极203。其中，发光层201可以为半导体薄膜层，所述半导体薄膜层可以采用P-GaN、MQW或者N-GaN等材料制成，第一电极202可以为正电极，第二电极203可以为负电极。转移过程中，可以将发光二极管芯片20中没有设置电极的一面对着解离胶层12，并将发光二极管芯片20设置有电极的一侧朝向驱动基板，在发光二极管芯片20落下后，第一电极202和第二电极203则可以与驱动基板上的焊盘固定相连。
参照图3，示出了本申请实施例的一种载板的结构示意图，如图3所示，
所述载板具体可以包括：依次设置的中载基板10、解离调节结构以及解离胶层12，所述解离调节结构可以被配置为调节解离胶层12的解离精度，解离胶层12可以被配置为与多个发光二极管芯片20连接。
具体的，所述载板的解离胶层12可以被配置连接多个发光二极管芯片20，多个发光二极管芯片20可以阵列分布在所述载板上。所述发光二极管芯片20可以为发出同一颜色的发光二极管芯片，也可以为可发出不同颜色的发光二极管芯片，本申请实施例对此不做限定。
具体的，解离胶层12可以为激光解离胶，通过向中载基板10的部分区域照射激光，可以使得对应区域的解离胶层12解离，从而使得该区域的发光二极管芯片20脱落，并转移到驱动基板上。或者，解离胶层12还可以为热解胶；此时，可通过向中载基板10的部分区域进行加热来解离胶层12对应区域解离，从而使得该区域的发光二极管芯片20脱落，并转移到驱动基板上。
例如，在需要将中载基板10上的发光二极管芯片20转移至驱动基板上时，可按照重力的方向，将中载基板10设置在驱动基板的上方，即中载基板10和驱动基板沿着重力的方向依次设置，从而可利用重力配合上述解离胶层12将中载基板10上需要转移的发光二极管芯20转移到驱动基板上。
本申请实施例中，由于解离胶层12与中载基板10之间设置解离调节结构，在发光二极管芯片20的巨量转移过程中，所述解离调节结构可以调节 解离胶层12的解离精度。这样，就可以避免发光二极管芯片20在下落过程中发生位置偏移，提高发光二极管芯片20的良率和解离精度，从而，可以提高发光二极管芯片20在进行巨量转移过程中的良率和巨量转移的效率。
在本申请的一些可选实施例中，所述解离调节结构可以包括多个调节微结构，每个所述调节微结构与一个发光二极管芯片20对应；其中，所述调节微结构在中载基板10上的正投影为第一投影，发光二极管芯片20在中载基板10上的正投影为第二投影；每个所述调节微结构的第一投影与其对应的发光二极管芯片20的第二投影至少部分重叠，且所述第一投影的面积小于或者等于所述第二投影的面积。
具体地，所述调节微结构可以为图案和微结构，也可以为光栅、微透镜或者预置结构等，所述微结构可以将解离胶层12的界面形貌做出优化。这样，解离胶层12在解离过程中，可以利用周边自动排气。通过给每个发光二极管芯片20对应设置一个所述调节微结构，可以使排气不畅导致的发光二极管芯片20偏移问题得到有效解决。
示例的，所述调节微结构可以设置在发光二极管芯片20的中央区域，以使所述第一投影与所述第二投影的中央区域交叠；或者，所述微结构还可以设置在发光二极管芯片20的边缘区域，以使所述第一投影与所述第二投影的边缘区域交叠；或者，所述微调节结构还可以设置在整个发光二极管芯片20的整个外表面区域相对，以使所述第一投影与所述第二投影完全交叠。本申请对于所述微调节结构相对于发光二极管芯片20的具体位置不做限定。
如图3所示，所述调节微结构具体可以包括：设置在解离胶层12靠近中载基板10一侧的弧形凸起121。
参照图4，示出了本申请实施例的一种解离胶层的结构示意图，如图4所示，由于解离胶层12靠近中载基板10的一侧设有弧形凸起121，因此，解离胶层12的中央区域的厚度要大于边缘区域的厚度，在达到相同的解离程度的情况下，解离胶层12的中央区域需要的解离光的能量大于边缘区域需要的解离光的能量。而解离光照射到弧形凸起121上时，解离光照射在弧形凸起121上的能量通常从中央区域往边缘区域递减。这样，通过在解离胶层12上设置弧形凸起121，可以实现解离胶层12的厚度从中央区域往边缘区域递减，和解离光的能量分布进行适配，以使得解离胶层12的中央区域和边缘区域可以实现同等程度的解离，避免解离胶层12的中央区域先行解离产生的微腔和气体，从而，可以免受气体的冲击，避免发光二极管芯片20 在下落过程中发生位置偏移，提高发光二极管芯片20的良率和解离精度。进而，可以提高发光二极管芯片20在进行巨量转移过程中的良率和巨量转移的效率。
需要说明的是，在实际应用中，弧形凸起121的弧度可以根据解离光的能量分布进行设定，本申请实施例对于弧形凸起的弧度不做具体限定。
参照图5，示出了图3所示的载板中的中载基板的结构示意图，如图5所示，中载基板10在与弧形凸起121相对的位置设置有第一弧形凹槽101，第一弧形凹槽101的形状与弧形凸起121的形状适配，弧形凸起121嵌设于第一弧形凹槽101内。
本申请实施例中，可以先在中载基板10上形成第一弧形凹槽101，然后，再在形成有第一弧形凹槽101的一侧涂覆解离胶，解离胶可以流入第一弧形凹槽101内，这样，就可以使得最后形成的解离胶层12上可以形成弧形凸起121。在中载基板10上直接形成第一弧形凹槽101，可以使得所述载板的结构较为简单，且高度较低。
具体地，第一弧形凹槽101与弧形凸起121的形状适配具体可以包括：第一弧形凹槽101与弧形凸起121的形状相同，或者，第一弧形凹槽101略大于弧形凸起121，以便于在第一弧形凹槽101内形成弧形凸起121。
参照图6，示出了本申请实施例的另一种载板的结构示意图，参照图7，示出了图6所示的载板去除了解离胶层的结构示意图。如图6所示，所述载板还可以包括：介质层11，介质层11设置于中载基板10和解离胶层12之间，介质层11在与弧形凸起121相对的位置设置有第二弧形凹槽111，第二弧形凹槽111的形状与弧形凸起121的形状适配，弧形凸起121嵌设于第二弧形凹槽111内。
在具体的应用中，由于中载基板10通常由玻璃制成，因此，在中载基板10上直接加工形成弧形凹槽的工艺通常较为复杂，且加工成本较高。为了减低工艺复杂性并减少成本，在形成解离胶层12之前，可以先在中载基板10上形成一层介质层11，然后在介质层11上形成第二弧形凹槽111，工艺较为简单，最后，再在介质层11上涂覆解离胶，以形成带有弧形凸起121的解离胶层12。这样，就可以避免在玻璃材质的中载基板10上直接加工弧形凹槽的操作。
可选地，介质层11的材质可以为：氧化硅、氮化硅中的至少一种。在实际应用中，在介质层11的材质为氧化硅或者氮化硅的情况下，可以便于 在介质层11上进行光刻的工艺。具体地，可以采用光刻的工艺在需要连接发光二极管芯片20的位置对应形成具有一定弧度的凹陷，即第二弧形凹槽111。然后，再在介质层111形成有第二弧形凹槽111的一侧涂覆解离胶，解离胶可以流入第二弧形凹槽111内，这样，就可以使得最后形成的解离胶层12上可以形成弧形凸起121。采用光刻的工艺在介质层11上形成第二弧形凹槽111，可以使得第二弧形凹槽111的加工工艺较为简单，加工成本较低。
具体地，第二弧形凹槽111与弧形凸起121的形状适配具体可以包括：第二弧形凹槽111与弧形凸起121的形状相同，或者，第二弧形凹槽111略大于弧形凸起121，以便于在第二弧形凹槽111内形成弧形凸起121。
可选地，介质层11的厚度可以大于第二弧形凹槽111的深度，以便于在介质层11上形成完整的第二弧形凹槽111。这样，就可以避免在光刻的过程中将介质层11全部刻蚀掉暴露了中载基板10，提高介质层11上的第二弧形凹槽111的规则性和完整性，进而，有利于得到形状规则且完整的弧形凸起121。
需要说明的是，第二弧形凹槽111的深度具体可以为第二弧形凹槽111凹陷的最深位置对应的深度。
示例地，在第二弧形凹槽111的深度大于或者等于1000A，第二介质层11的厚度可以为5000-10000A。第二弧形凹槽111的深度大于或者等于1000A，且小于介质层11的厚度。
在本申请的一些可选实施例中，解离胶层12的厚度大于弧形凸起121的深度，以实现发光二极管芯片21在中载基板10上的可靠粘接。
需要说明的是，弧形凸起121的深度具体可以为弧形凸起121凸起到最高位置对应的深度。
具体地，解离胶层12的厚度可以依据实际使用效果而定。例如，解离胶层12的厚度可以为1-5um，对应介质层11厚度可以高于3000A，弧形凸起121的深度可以为500-2500A。
参照图8，示出了本申请实施例的另一种载板的结构示意图，如图8所示，所述调节微结构可以包括光栅13，光栅13在中载基板10上的正投影与发光二极管芯片20在中载基板10上的正投影的中央区域至少部分交叠。
具体的，发光二极管芯片20在中载基板10上的正投影的中央区域可以为：以发光二极管芯片20的中心的正投影为中心，以预设距离为半径的范 围画圆所涵盖的区域，所述预设距离可以为发光二极管芯片20的中心到边缘的距离的10％-50％；或者，所述中央区域还可以是靠近发光二极管芯片20的中心的正投影的区域。所述发光二极管芯片20在中载基板10上的正投影中，所述中央区域之外的区域可以为边缘区域。
在实际应用中，光栅13可以位于中载基板10靠近解离胶层12的一侧。解离光从中载基板10侧射入的情况下，可以在光栅13处发生衍射，降低解离光的能量。本申请实施例中，通过将光栅13设置在解离胶层12的中央区域，可以使得光栅13在中载基板10上的正投影与发光二极管芯片20在中载基板10上的正投影的中央区域至少部分交叠。由于光栅13的衍射作用，可以使得照射至解离胶层12的中央区域的解离光的能量降低，从而，可以使得照射至解离胶层12的中央区域和边缘区域的光线较为均匀，使得解离胶层12的中央区域和边缘区域可以实现同等程度的解离，以避免解离胶层12的中央区域先行解离产生的微腔和气体，免受气体的冲击，避免发光二极管芯片20在下落过程中发生位置偏移，提高发光二极管芯片20的良率和解离精度，进而，可以提高发光二极管芯片20在进行巨量转移过程中的良率和巨量转移的效率。
本申请实施例中，光栅13的狭缝宽度和通带宽度皆大于解离光的波长，以使得所述解离光可以在光栅13处发生较好的衍射。例如，在解离光的波长为266-355nm的情况下，光栅13的狭缝宽度和通带宽度可以为500-1400A。
示例地，光栅13的高度可以为1000-3000A。由于光栅13的高度较低，在光栅13继续涂覆解离胶时，很难在解离胶层12的表面明显的凸起，解离胶层12的表面相对平整，这样，就可以实现发光二极管芯片的连接可靠性。
参照图9，示出了图8所示的载板的俯视结构示意图，如图9所示，光栅13在中载基板10上的正投影为第三投影S3，发光二极管芯片20在中载基板10上的正投影为第二投影S2。如图9所示，第三投影S3可以与第二投影S2的中央区域交叠。
在具体的应用中，在解离光的均匀性为5％的情况下，第三投影S3的面积为第二投影S2的面积的5％-10％，以提高解离光照射解离胶层20上的均匀性，使得解离胶层12的中央区域和边缘区域可以同步解离。示例地，为了兼顾解离光的均匀性以及解离胶层12的表面平整度，第三投影S3的面积可以为第二投影S2的面积的7％以下。
参照图10，示出了本申请实施例的再一种载板的结构示意图，如图10 所示，在图8所示的载板的基础上，图10所示的载板可以包括：微透镜结构14，微透镜结构14设置在中载基板10上远离解离胶层12的一侧，微透镜结构14可以用于进行能量汇聚，调节射入中载基板10的解离光的均匀性，从而，可以使得解离胶层12的中央区域和边缘区域可以同步解离。
在实际应用中，微透镜结构14可以根据实际情况设置在解离光较弱的区域。在本申请的一种可选实施例中，微透镜结构14在中载基板10上的正投影与发光二极管芯片20在中载基板10上的正投影的边缘区域至少部分交叠，也即，微透镜结构14可以设置在发光二极管芯片20的边缘区域对应的位置。
在实际应用中，由于解离光较弱的区域集中在发光二极管芯片20的边缘区域对应的位置，因此，通过将微透镜14设置在发光二极管芯片20的边缘区域对应的位置，微透镜结构14可以用于将发光二极管芯片20的边缘区域的解离光进行能量汇聚。
需要说明的是，微透镜结构14的布置面积可根据解离光的实际情况而定，本申请实施例对于微透镜结构14的布置面积不做具体限定。微透镜结构14的材料为常规的透镜材料，例如，透光树脂或者玻璃等，微透镜结构14的曲率半径依据实际聚光效果而定，本申请实施例此不做限定。
参照图11，示出了本申请实施例的再一种载板的结构示意图，如图11所示，所述调节微结构可以包括：多个预布置单元15，多个预布置单元15在中载基板10上的正投影与发光二极管芯片20在中载基板10上的正投影至少部分交叠，解离胶层12远离中载基板10的一侧形成有多个凸起122，一个凸起122与一个预布置单元15对应，相邻的凸起122之间形成排气通道L，这样，解离胶层12解离气化所产生的气体可以从排气通道L排出，从而，可以使得发光二极管芯片20在下落过程中免受该气体的冲击，避免发光二极管芯片20在下落过程中发生的位置偏移，提高发光二极管芯片20的良率和解离精度，进而，可以提高发光二极管芯片20在进行巨量转移过程中的良率和巨量转移的效率。
参照图12，示出了图11所示的载板的加工状态图之一。如图12所示，在具体的应用中，在所述载板的加工过程中，可以先在中载基板10需要连接发光二极管芯片20的位置对应设置多个阵列分布的预布置单元15。
需要说明的是，在实际应用中，可以将中载基板10和预布置单元15设计成一体式结构，也可以将中载基板10与预布置单元15设计成分体式结构， 本申请实施例对于中载基板10与预布置单元15之间的连接形式可以不做限定。
参照图13，示出了图11所示的载板的加工状态图之二，如图13所示，在中载基板10上设置了多个预布置单元15之后，可以在中载基板10上设有的预布置单元15的一侧涂覆解离胶以形成解离胶层12。
具体的，由于预布置单元15的阻挡作用，预布置单元15会阻止解离胶流动，再加上解离胶本身又具备一定的粘性，解离胶很难通过自身的流动性将预布置单元15的位置流平，这样，就会在预布置单元15对应的位置形成凸起122，以使相邻的凸起122之间形成排气通道L。在解离胶层12解离的过程中，解离胶层12解离气化所产生的气体可以从排气通道L排出，从而，可以使得发光二极管芯片20在下落过程中免受该气体的冲击，避免发光二极管芯片20在下落过程中发生的位置偏移，提高发光二极管芯片20的良率和解离精度。
本申请实施例中，预布置单元15可以采用透明材料制成，这样，就可以使得解离光可以透过预布置单元15照射至解离胶层12上，避免预布置单元15对解离光的强度造成的影响。示例地，所述透明材料可以选自氧化硅、氮化硅中的至少一种，本申请实施例对于所述透明材料不做具体地限定。
示例地，预布置单元15的高度可以为15000-20000A,以使得预布置单元15可以形成对于解离胶的有效阻挡，在解离胶层12的表面形成规则的凸起122。
当然，在实际应用中，预布置单元15的高度需要根据实际的解离胶层12的厚度来确定，解离胶层12的厚度越大，预布置单元15的高度相应也越高。通常，为了实现较好的阻挡效果，预布置单元15的高度与解离胶层12的高度之间的差值应该小于或者等于1um。
示例地，预布置单元15的任一方向的宽度应该大于或者等于2.5um，以使得预布置单元15具备较好的加工性能。
示例地，预布置单元15的截面形状可以包括但不限于圆形、矩形或者其他的多边形，本申请实施例对于预布置单元15的具体形状可以不做限定。在预布置单元15的截面形状为圆形的情况下，所述圆形的直径应该大于或者等于2.5um；在预布置单元15的截面形状为矩形的情况下，所述矩形的最短的边长应该大于或者等于2.5um。
在本申请的一些可选的实施例中，每个发光二极管芯片20对应设置有 多个预布置单元15，相邻的两个预布置单元15之间具有一定距离，这样，可以便于在发光二极管芯片20与解离胶层12之间形成多个彼此独立的排气通道L，以进一步提高排气的稳定性。
参照图14，示出了本申请的另一种载板的结构示意图，如图14所示，所述载板可以包括：介质层11，介质层11在与弧形凸起121相对的位置设置有第二弧形凹槽111，第二弧形凹槽111背离中载基板10的一侧还设置有预布置单元15。这样，既可以使得最后形成的解离胶层12上可以形成弧形凸起121，而且，便于在发光二极管芯片20与解离胶层12之间形成多个彼此独立的排气通道L，以进一步提高排气的稳定性。从而，可以避免发光二极管芯片20在下落过程中发生位置偏移，提高发光二极管芯片20的良率和解离精度。进而，可以提高发光二极管芯片20在进行巨量转移过程中的良率和巨量转移的效率。
在实际应用中，预布置单元15的材质可以为光刻胶，第二弧形凹槽111内的预布置单元15可以采用掩模制成。
参照图15，示出了本申请实施例的又一种载板的结构示意图，如图15所示，所述解离胶层12可以包括：激光解离层123和粘性胶材层124，激光解离层123位于中载基板10靠近发光二极管芯片20的一侧，粘性胶材层124位于激光解离层123与发光二极管芯片20之间；其中，粘性胶材层124靠近激光解离层123的一侧设置有第一微结构1241，激光解离层123靠近粘性胶材层124的一侧设置有第二微结构1231，第二微结构1231与第一微结构1241的形状互补，第二微结构1231与第一微结构1241相互嵌合。
本申请实施例中，在解离光照射到解离胶层12时，在解离光的照射下，激光解离层123可以气化解离，而粘性胶材层124则可以与发光二极管芯片20一起脱落，由于粘性胶材层124靠近激光解离层123的一侧设置有第一微结构1241，第一微结构1241可以用于充当光提取结构，无需去除发光二极管芯片20上的粘接胶材层124，这样，就避免了去除发光二极管芯片20上的残胶的操作，进一步提升的发光二极管芯片20的巨量转移的效率。
需要说明的是，图15所示的载板中，为了示意简单，没有示意出设置在解离胶层12与中载基板10中间的调节微结构。而在实际应用中，图15所示的载板中，在解离胶层12与中载基板10之间可以设置有调节微结构，所述调节微结构可以包括但不局限于上述各实施例中的弧形凸起、光栅、预布置单元中的任意一种，本申请实施例对此不做限定。
可选地，第一微结构1241可以为纳米微结构，以使得第一微结构1241可以充当纳米微透镜的功能，实现较好的光提取的效果。
示例地，第一微结构1241可以选自圆锥状微结构、棱状微结构中的至少一种，本申请实施例对于第一微结构1241的形状可以不做具体限定。
在本申请的一种可选实施例中，在第一微结构1241为锥形的形状下，所述锥形的高度为0.2-1um，所述锥形的底面的直径为100-500nm，所述锥形的侧面与底面之间的夹角为15-60°，以使得第一微结构1241实现较好的光提取效果。
示例地，激光解离层123的厚度为1-3um，以使得激光解离层123既可实现较好的粘接效果，同时，解离效率又较高。粘性胶材层124的厚度为1-10um，以使得粘接胶材层124既可可靠的连接在发光二极管芯片20上，又可以实现较好的光提取效果。
本申请实施例中，粘性胶材层124的折射率大于或者等于1.5，粘性胶材层124的光透过率大于或者等于97％，以使得粘性胶材层124可以透光，实现较好的光提取效果。
参照图16至19，可以提供一种图15所示的载板的具体加工示意图。如图16所示，首先，可以在中载基板10上涂覆激光解离胶，示例地，可以涂覆一层1-3um厚的解离胶层比进行相应固化，在固化完成后，可以在解离胶层的表面加工形成第二微结构1231，以得到锯齿状的激光解离层123。示例地，可以采用纳米压印或者光刻刻蚀的工艺在激光解离层123的表面形成第二微结构1231，本申请实施例对于第二微结构1231的具体形成工艺可以不做限定。
如图17所示，在激光解离层123上形成了第二微结构1231的情况下，可以在激光解离层124上涂覆粘性材料，以形成粘性胶材层124。由于粘性材料本身具备流平性，在涂覆固定后，粘性胶材层124在靠近激光解离层124的一侧会自动产生平坦和填充效果，形成形状与第二微结构1231互补的第一微结构1241，而且，第二微结构1241可以与第一微结构1231相互嵌合。
如图18所示，在粘性胶材层124完成之后，可以在粘性胶材层124上绑定发光二极管芯片20，将发光二极管芯片20绑定至中载基板20上。需要说明的是，在绑定发光二极管芯片20的过程中，需要对粘性教材层124进行固化。具体的固化工艺可以为：加压加温→保持一定时间(5min)→高温固化(230℃)。
在实际应用中，在形成图18的结构之后，可以采用掩模对解离胶层12进行灰化处理，以得到图15所示的载板。
如图19所示，在图15所示的载板在向驱动芯片40转移发光二极管芯片20的过程中。在解离光的照射下，激光解离层123可以气化解离，而粘性胶材层124则可以与发光二极管芯片20一起脱落，由于粘性胶材层124靠近激光解离层123的一侧设置有第一微结构1241，第一微结构1241可以用于充当光提取结构，无需去除发光二极管芯片上的粘接胶材层124，这样，就避免了去除发光二极管芯片20上的残胶的操作，进一步提升的发光二极管芯片20的巨量转移的效率。
综上，本申请实施例所述的载板至少可以包括以下优点：
本申请实施例中，通过在解离胶层与中载基板之间设置解离调节结构，在发光二极管芯片的巨量转移过程中，所述解离调节结构可以调节所述解离胶层的解离精度。这样，就可以避免发光二极管芯片在下落过程中发生位置偏移，提高所述发光二极管芯片的良率和解离精度，从而，可以提高所述发光二极管芯片在进行巨量转移过程中的良率和巨量转移的效率。
本申请实施例还提供了一种转移装置，所述转移装置具体可以包括：多个发光二极管芯片前述的载板；所述多个发光二极管芯片连接于所述载板的解离胶层，所述转移装置可以用于将所述多个发光二极管芯片转移至显示装置的驱动芯片上，实现发光二极管芯片的巨量转移。
需要说明的是，本申请实施例中的所述载板的结构与前述各实施例中的载板的结构相同，在此不做赘述。
本申请实施例中，所述载板通过在解离胶层与中载基板之间设置解离调节结构，在发光二极管芯片的巨量转移过程中，所述解离调节结构可以调节所述解离胶层的解离精度。这样，就可以避免发光二极管芯片在下落过程中发生位置偏移，提高所述发光二极管芯片的良率和解离精度，从而，可以提高所述发光二极管芯片在进行巨量转移过程中的良率和巨量转移的效率。
参照图20，示出了本申请实施例的一种载板的加工方法的步骤流程图，所述加工方法可以用于加工前述各实施例中的载板，所述加工方法具体可以包括以下步骤：
步骤S11：在中载基板上形成解离调节结构。
本申请实施例中，可以先在中载基板10上形成解离调节结构，以便于将解离调节结构形成于解离胶层12与中载基板10之间。在发光二极管芯片 20的巨量转移过程中，所述解离调节结构可以调节解离胶层12的解离精度。这样，就可以避免发光二极管芯片20在下落过程中发生位置偏移，提高发光二极管芯片20的良率和解离精度，从而，可以提高发光二极管芯片20在进行巨量转移过程中的良率和巨量转移的效率。
在本申请的一些可选实施例中，所述解离调节结构可以包括多个调节微结构，每个所述调节微结构与一个发光二极管芯片20对应；其中，所述调节微结构在中载基板10上的正投影为第一投影，发光二极管芯片20在中载基板10上的正投影为第二投影；每个所述调节微结构的第一投影与其对应的发光二极管芯片20的第二投影至少部分重叠，且所述第一投影的面积小于或者等于所述第二正投影的面积。
具体地，所述调节微结构可以为图案和微结构，也可以为光栅、微透镜或者预置结构等，所述微结构可以将解离胶层12的界面形貌做出优化。这样，解离胶层12在解离过程中，可以利用周边自动排气。通过给每个发光二极管芯片20对应设置一个所述调节微结构，可以使排气不畅导致的发光二极管芯片20偏移问题得到有效解决。
示例的，所述调节微结构可以设置在发光二极管芯片20的中央区域，以使所述第一投影与所述第二投影的中央区域交叠；或者，所述微结构还可以设置在发光二极管芯片20的边缘区域，以使所述第一投影与所述第二投影的边缘区域交叠；或者，所述微调节结构还可以设置在整个发光二极管芯片20的整个外表面区域相对，以使所述第一投影与所述第二投影完全交叠。本申请对于所述微调节结构相对于发光二极管芯片20的具体位置不做限定。
步骤S12：在所述中载基板形成有所述解离调节结构的一侧涂覆解离胶，形成解离胶层，所述解离胶层被配置为与多个发光二极管芯片连接。
本申请实施例中，所述载板的解离胶层12可以被配置连接多个发光二极管芯片20，多个发光二极管芯片20可以阵列分布在所述载板上。所述发光二极管芯片20可以为发出同一颜色的发光二极管芯片，也可以为可发出不同颜色的发光二极管芯片，本申请实施例对此不做限定。
具体的，解离胶层12可以为激光解离胶，通过向中载基板10的部分区域照射激光，可以使得对应区域的解离胶层12解离，从而使得该区域的发光二极管芯片20脱落，并转移到驱动基板上。或者，解离胶层12还可以为为热解胶；此时，可通过向中载基板10的部分区域进行加热来解离胶层12对应区域解离，从而使得该区域的发光二极管芯片20脱落，并转移到驱动 基板上。
本申请实施例中，所述载板通过在解离胶层与中载基板之间设置解离调节结构，在发光二极管芯片的巨量转移过程中，所述解离调节结构可以调节所述解离胶层的解离精度。这样，就可以避免发光二极管芯片在下落过程中发生位置偏移，提高所述发光二极管芯片的良率和解离精度，从而，可以提高所述发光二极管芯片在进行巨量转移过程中的良率和巨量转移的效率。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本发明的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (22)

  1. 一种载板，其特征在于，包括：依次设置的中载基板、解离调节结构以及解离胶层，所述解离调节结构被配置为调节所述解离胶层的解离精度，所述解离胶层被配置为与多个发光二极管芯片连接。
  2. 根据权利要求1所述的载板，其特征在于，所述解离调节结构包括多个调节微结构，每个所述调节微结构与一个所述发光二极管芯片对应；其中，
    所述调节微结构在所述中载基板上的正投影为第一投影，所述发光二极管芯片在所述中载基板上的正投影为第二投影；
    每个所述调节微结构的第一投影与其对应的所述发光二极管芯片的第二投影至少部分重叠，且所述第一投影的面积小于或者等于所述第二投影的面积。
  3. 根据权利要求2所述的载板，其特征在于，所述调节微结构包括：设置在所述解离胶层靠近所述中载基板一侧的弧形凸起。
  4. 根据权利要求3所述载板，其特征在于，所述中载基板在与所述弧形凸起相对的位置设置有第一弧形凹槽，所述第一弧形凹槽的形状与所述弧形凸起的形状适配，所述弧形凸起嵌设于所述第一弧形凹槽内。
  5. 根据权利要求3所述的载板，所述载板还包括：介质层，所述介质层设置于所述中载基板和所述解离胶层之间，所述介质层在与所述弧形凸起相对的位置设置有第二弧形凹槽，所述第二弧形凹槽的形状与所述弧形凸起的形状适配，所述弧形凸起嵌设于所述第二弧形凹槽内。
  6. 根据权利要求5所述的载板，其特征在于，所述介质层的厚度大于所述第二弧形凹槽的深度。
  7. 根据权利要求3至6任一项所述的载板，其特征在于，所述解离胶层的厚度大于所述弧形凸起的深度。
  8. 根据权利要求2所述的载板，其特征在于，所述调节微结构包括光栅，所述光栅在所述中载基板上的正投影与所述发光二极管芯片在所述中载基板上的正投影的中央区域至少部分交叠。
  9. 根据权利要求8所述的载板，其特征在于，所述光栅的狭缝宽 度和通带宽度皆大于解离光的波长；
    所述光栅的高度为1000-3000A，所述光栅的狭缝宽度和通带宽度皆为500-1400A。
  10. 根据权利要求8所述的载板，其特征在于，所述光栅在所述中载基板上的正投影为第三投影，所述发光二极管芯片在所述中载基板上的正投影为第二投影，所述第三投影的面积为所述第二投影的面积的5％-10％。
  11. 根据权利要求8所述的载板，其特征在于，所述载板还包括：微透镜结构，所述微透镜结构设置在所述中载基板上远离所述解离胶层的一侧；
    所述微透镜结构在所述中载基板上的正投影与所述发光二极管芯片在所述中载基板上的正投影的边缘区域至少部分交叠。
  12. 根据权利要求10至15任一项所述的载板，其特征在于，所述光栅位于所述中载基板靠近所述解离胶层的一侧。
  13. 根据权利要求2所述的载板，其特征在于，所述调节微结构包括：多个预布置单元，所述多个预布置单元在所述中载基板上的正投影与所述发光二极管芯片在所述中载基板上的正投影至少部分交叠，所述解离胶层远离所述中载基板的一侧形成有多个凸起，一个所述凸起与一个所述预布置单元对应，相邻的所述凸起之间形成排气通道。
  14. 根据权利要求13所述的载板，其特征在于，所述预布置单元采用透明材料制成。
  15. 根据权利要求14所述的载板，其特征在于，所述预布置单元的高度为15000-20000A，所述预布置单元任一方向的宽度大于或者等于2.5um。
  16. 根据权利要求13至15任一项所述的载板，其特征在于，每个所述发光二极管芯片对应设置有多个所述预布置单元，相邻的两个所述预布置单元之间具有一定距离
  17. 根据权利要求1至16任一项所述的载板，其特征在于，所述解离胶层包括：激光解离层和粘性胶材层，所述激光解离层位于所述中载基板靠近所述发光二极管芯片的一侧，所述粘性胶材层位于所述激光解离层与所述发光二极管芯片之间；其中，
    所述粘性胶材层靠近所述激光解离层的一侧设置有第一微结构，所述激光解离层靠近所述粘性胶材层的一侧设置有第二微结构，所述第二微结构与所述第一微结构的形状互补，所述第二微结构与所述第一微结构相互嵌合。
  18. 根据权利要求17所述的载板，其特征在于，所述激光解离层的厚度为1-3um，所述粘性胶材层的厚度为1-10um。
  19. 根据权利要求17所述的载板，其特征在于，所述第一微结构为纳米微结构，所述第一微结构选自圆锥状微结构、棱状微结构中的至少一种。
  20. 根据权利要求17所述的载板，其特征在于，所述第一微结构为锥形，所述锥形的高度为0.2-1um，所述锥形的底面的直径为100-500nm，所述锥形的侧面与底面之间的夹角为15-60°。
  21. 根据权利要求17至20任一项所述的载板，其特征在于，所述粘性胶材层的折射率大于或者等于1.5，所述粘性胶材层的光透过率大于或者等于97％。
  22. 一种转移装置，其特征在于，所述转移装置包括：多个发光二极管芯片以及权利要求21任一项所述的载板；所述多个发光二极管芯片连接于所述载板的解离胶层。
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