WO2022204921A1 - 显示基板、显示装置 - Google Patents

显示基板、显示装置 Download PDF

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Publication number
WO2022204921A1
WO2022204921A1 PCT/CN2021/083856 CN2021083856W WO2022204921A1 WO 2022204921 A1 WO2022204921 A1 WO 2022204921A1 CN 2021083856 W CN2021083856 W CN 2021083856W WO 2022204921 A1 WO2022204921 A1 WO 2022204921A1
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WO
WIPO (PCT)
Prior art keywords
power supply
display substrate
substrate
layer
orthographic projection
Prior art date
Application number
PCT/CN2021/083856
Other languages
English (en)
French (fr)
Inventor
易宏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/083856 priority Critical patent/WO2022204921A1/zh
Priority to US17/753,214 priority patent/US20240040866A1/en
Priority to DE112021001218.5T priority patent/DE112021001218T5/de
Priority to CN202180000631.1A priority patent/CN115669273A/zh
Publication of WO2022204921A1 publication Critical patent/WO2022204921A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • Active Matrix Organic Light Emitting Diode (English: Active Matrix Organic Light Emitting Diode, AMOLED for short) display panel has become one of the hot spots in the field of flat panel display research.
  • the AMOLED display panel Compared with the traditional thin film transistor liquid crystal display panel (English: Thin Film Transistor Liquid Crystal Display, TFTLCD for short), the AMOLED display panel has faster response speed, higher contrast ratio and wider viewing angle.
  • more and more electronic devices have higher and higher requirements on the size of the frame of the AMOLED display panel, which makes the AMOLED display panel gradually develop towards a narrow frame.
  • the purpose of the present disclosure is to provide a display substrate and a display device.
  • a first aspect of the present disclosure provides a display substrate including: a display area and a non-display area surrounding the display area; the display substrate further includes:
  • a plurality of data fan-out lines at least part of the data fan-out lines are located in the non-display area, and the data fan-out lines are coupled with corresponding data lines;
  • the plurality of data fan-out lines include a plurality of first data fan-out lines and A plurality of second data fan-out lines, the first data fan-out lines and the scan lines are provided on the same layer and the same material, and the second data fan-out lines and the data lines are provided on the same layer and the same material.
  • At least part of the orthographic projection of the first data fan-out line on the base of the display substrate at least partially overlaps the orthographic projection of the second data fan-out line on the base.
  • At least part of the first data fan-out line includes a first line segment
  • at least part of the second data fan-out line includes a second line segment
  • the orthographic projection of the first line segment on the substrate is the same as the The orthographic projections of the second line segment on the substrate coincide.
  • the display substrate further includes:
  • the power supply line includes a first power supply layer, and in a direction perpendicular to the base of the display substrate, at least part of the first power supply layer is located on the first data fan-out line and the second data fan between the lines.
  • the power line further includes a second power layer, and the second power layer is coupled to the first power layer;
  • At least part of the first power supply layer and at least part of the second power supply layer are both located in the non-display area, the first power supply layer and the second power supply layer are stacked and arranged, and the first power supply layer is at least partially between the second power supply layer and the base of the display substrate.
  • At least part of the second data fan-out line is located between the first power supply layer and the second power supply layer.
  • the display substrate further includes a conductive connection part, at least a part of the conductive connection part is located between the first power supply layer and the second power supply layer, and the conductive connection part is respectively connected to the first power supply layer.
  • the power supply layer is coupled to the second power supply layer.
  • the display substrate includes a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer that are stacked in sequence along a direction away from the base of the display substrate;
  • the scan line and the first gate metal layer are arranged in the same layer and the same material, and the data line and the first source-drain metal layer are arranged in the same layer and the same material;
  • the first power supply layer and the second gate metal layer are provided in the same layer and the same material
  • the second power supply layer and the second source-drain metal layer are provided in the same layer and the same material
  • the conductive connection portion and the first power supply layer are provided with the same material
  • a source-drain metal layer is provided with the same material and the same layer.
  • the power line includes a positive power line
  • the first power layer includes a first positive power layer
  • the second power layer includes a second positive power layer
  • At least a portion of the first positive power layer extends along a first direction, the first positive power layer includes a first middle portion and two first end portions, and the first middle portion is located in the first direction along the first direction. between the two first ends, the two first ends are symmetrical with respect to a central axis extending along a second direction in the display substrate, and the second direction intersects the first direction;
  • the maximum width of the first end portion in the second direction is smaller than the maximum width of the first intermediate portion in the second direction.
  • the first end portion includes a first target portion, the first target portion has a first width in the second direction, and the first width gradually increases in a direction away from the first intermediate portion get bigger.
  • the first end portion further includes a second target portion, the first target portion is located between the second target portion and the first intermediate portion along the first direction, and the second target portion is located between the second target portion and the first intermediate portion along the first direction.
  • the target portion has a second width along the second direction, the second width gradually decreasing in a direction away from the first intermediate portion.
  • the non-display area includes a bending area, and the orthographic projection of the first middle portion on the base of the display substrate does not overlap with the orthographic projection of the bending area on the base.
  • the second positive power supply layer includes: a second middle portion and two second end portions, and at least part of the second middle portion is located between the two second end portions along the first direction. In between, the two second end portions are symmetrical with respect to the central axis extending along the second direction in the display substrate;
  • the orthographic projection of the second end portion on the base of the display substrate at least partially overlaps with the orthographic projection of the first end portion on the base; the second middle portion on the base an orthographic projection that at least partially overlaps an orthographic projection of the first intermediate portion on the substrate.
  • the second end portion includes a third target portion
  • the third target portion has a third width in the second direction
  • the third width gradually increases in a direction away from the second intermediate portion get bigger.
  • the second end portion further includes a fourth target portion, and the third target portion is located between the fourth target portion and the second intermediate portion along the first direction, and the fourth target portion is located between the fourth target portion and the second intermediate portion.
  • the width of the target portion in the second direction is equal to the maximum value of the third width.
  • the second end portion further includes a fifth target portion, and the fourth target portion is located between the fifth target portion and the second intermediate portion along the first direction, and the fifth target portion is located between the fifth target portion and the second intermediate portion.
  • the target portion has a fifth width in the second direction, and the fifth width gradually decreases in a direction away from the second intermediate portion.
  • the second intermediate portion includes:
  • a second transmission part at least a part of the second transmission part extends along the first direction, the first transmission part is located between the display area and the second transmission part;
  • connection part located between the first transmission part and the second transmission part, the connection part is respectively coupled with the first transmission part and the second transmission part;
  • orthographic projection of the connecting portion on the base of the display substrate at least partially overlaps with the orthographic projection of the bending region of the display substrate on the base;
  • Two first wire inlets at least part of the first wire inlets extend along the second direction, and the two first wire inlets are coupled to two ends of the second transmission part in a one-to-one correspondence .
  • the conductive connection part includes two first conductive connection parts, and the two first conductive connection parts are symmetrical about the central axis; the first conductive connection parts are respectively connected with the first end part and the The second end is coupled.
  • the first conductive connection portion extends from the lower frame of the display substrate to the side frame of the display substrate.
  • the orthographic projection of the first conductive connection portion on the base and the orthographic projection of the first end portion on the base of the display substrate have a first overlapping area, and the first conductive connection a portion is coupled to the first end portion through a first via hole, the orthographic projection of the first via hole on the substrate at least partially overlaps the first overlapping region;
  • the orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the second end portion on the substrate have a second overlapping area, and the first conductive connection portion is connected to the substrate through the second via hole.
  • the second end portion is coupled, and the orthographic projection of the second via hole on the substrate at least partially overlaps the second overlapping region.
  • the first via hole and the second via hole are arranged along the first direction.
  • the display substrate further includes:
  • the orthographic projection of the first via hole on the substrate is located between the orthographic projection of the plurality of first signal lines on the substrate and the orthographic projection of the plurality of data fan-out lines on the substrate ;
  • the orthographic projection of the second via hole on the substrate partially overlaps the orthographic projection of at least part of the first signal line on the substrate.
  • the power supply line includes a negative power supply line
  • the first power supply layer includes a first negative power supply layer
  • the second power supply layer includes a second negative power supply layer
  • the first negative power supply layer includes two first negative power supply patterns, the two first negative power supply patterns are symmetrical about the central axis, and at least a part of the first end is located between the display area and the first negative power supply. A negative power supply between the graphics.
  • the first negative power pattern includes a sixth target portion and a seventh target portion, the sixth target portion is located between the seventh target portion and the central axis, and the sixth target portion is located between the seventh target portion and the central axis.
  • the width in the second direction is greater than the maximum width of the first end portion in the second direction.
  • the seventh target portion has a seventh width in the second direction, and the seventh width gradually decreases along a direction away from the central axis.
  • the second negative power supply layer includes:
  • annular portion surrounds the display area, the annular portion has an opening in the lower frame of the display substrate, and at least a portion of the second end portion is located between the annular portion and the display area;
  • Two second wire inlets at least part of the second wire inlets extend along the second direction, and the two second wire inlets are coupled with the two ends of the annular portion at the opening in a one-to-one correspondence catch.
  • the second wire entry portion is provided with an opening, and the orthographic projection of the opening on the base of the display substrate is the same as the orthographic projection of the bending area in the display substrate on the base. at least partially overlap.
  • the conductive connection part includes a second conductive connection part, the second conductive connection part surrounds the display area, and the second conductive connection part has an opening in the lower frame of the display substrate; the first conductive connection part has an opening; Two conductive connection parts are respectively coupled to the first negative power supply layer and the second negative power supply layer.
  • the second conductive connection part includes: a surrounding part, two first parts and two second parts;
  • At least a part of the display area is surrounded by the surrounding part, two ends of the surrounding part are coupled with the first ends of the two second parts in a one-to-one correspondence, and the first ends of the two second parts are in a one-to-one correspondence.
  • the two ends are coupled to the two first parts in a one-to-one correspondence, and an opening of the second conductive connection part is formed between the two first parts;
  • the extension direction of the first part intersects both the first direction and the second direction, and the orthographic projection of the first part on the base of the display substrate is the same as the first negative power layer on the base
  • the orthographic projection on the substrate has a third overlapping region, the first portion is coupled with the first negative power supply layer through a third via hole, and the orthographic projection of the third via hole on the substrate and the third the overlapping regions at least partially overlap;
  • At least part of the second portion extends along the first direction, the orthographic projection of the second portion on the base and/or the orthographic projection of the surround on the base, and the second The orthographic projection of the negative power supply layer on the substrate has a fourth overlapping region, the second portion and/or the surrounding portion is coupled to the second negative power supply layer through a fourth via hole, the fourth The orthographic projection of the via hole on the substrate at least partially overlaps the fourth overlapping region.
  • an extension direction of an orthographic projection of the third via hole on the substrate intersects both the first direction and the second direction.
  • a second aspect of the present disclosure provides a display device including the above-mentioned display substrate.
  • FIG. 1 is a schematic diagram of an overall structure of a power supply line in a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a first layout of a data fan-out line according to an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view of a data fan-out line provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a second layout of a data fan-out line according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of coupling between a data fan-out line and a fan-out extension line according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a third layout of a data fan-out line according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a fourth layout of a data fan-out line according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a portion of a positive power supply line and a negative power supply line at the lower left corner of the display substrate according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a first layout of a lower left corner of a display substrate according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a second layout of the lower left corner of the display substrate provided by the embodiment of the present disclosure.
  • FIG. 11 is a schematic layout diagram of an active layer at the lower left corner of a display substrate according to an embodiment of the present disclosure
  • FIG. 12 is a schematic layout diagram of a first gate metal layer at the lower left corner of a display substrate according to an embodiment of the present disclosure
  • FIG. 13 is a schematic layout diagram of a second gate metal layer at the lower left corner of a display substrate according to an embodiment of the present disclosure
  • FIG. 14 is a schematic layout diagram of an interlayer insulating layer at the lower left corner of a display substrate according to an embodiment of the present disclosure
  • FIG. 15 is a schematic layout diagram of a first source-drain metal layer at the lower left corner of a display substrate according to an embodiment of the present disclosure
  • 16 is a schematic layout diagram of a second source-drain metal layer at the lower left corner of the display substrate according to an embodiment of the present disclosure
  • 17 is a schematic layout diagram of the second gate metal layer and the first source-drain metal layer at the lower left corner of the display substrate according to an embodiment of the present disclosure
  • FIG. 18 is a schematic layout diagram of a first source-drain metal layer and a second source-drain metal layer in the lower left corner of the display substrate according to an embodiment of the present disclosure
  • FIG. 19 is a schematic layout diagram of a passivation layer at the lower left corner of a display substrate according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic layout diagram of the first flat layer at the lower left corner of the display substrate according to an embodiment of the present disclosure.
  • 21 is a schematic cross-sectional view of a display area in a display substrate provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a display substrate, including: a display area 10 and a non-display area 20 surrounding the display area 10 ; the display substrate further includes:
  • a plurality of data lines 102 at least part of the data lines 102 is located in the display area 10;
  • a plurality of data fan-out lines 21, at least part of the data fan-out lines 21 are located in the non-display area 20, and the data fan-out lines 21 are coupled with the corresponding data lines 102;
  • the plurality of data fan-out lines 21 include a plurality of A first data fan-out line 210 and a plurality of second data fan-out lines 211, the first data fan-out line 210 and the scan line 101 are provided with the same layer and material, the second data fan-out line 211 and the data line 102 Same layer and same material setting.
  • the display substrate includes a display area and a non-display area 20 surrounding the display area 10.
  • the display area 10 includes a plurality of sub-pixels for realizing the display function of the display substrate; Side frames arranged oppositely in one direction, such as a left frame and a frame, the display substrate further includes an upper frame and a lower frame oppositely arranged along the second direction.
  • the first direction includes a horizontal direction
  • the second direction includes a vertical direction.
  • the plurality of scan lines 101 are arranged along the second direction, the scan lines 101 include portions extending along the first direction, and at least a portion of the scan lines 101 is located in the second direction. the display area.
  • the scan lines 101 are used to provide scan signals for the sub-pixel driving circuits 60 included in the sub-pixels in the display area.
  • the plurality of data lines 102 are arranged along the first direction, the data lines 102 include portions extending along the second direction, and the data lines 102 are at least partially in the display area.
  • the data lines 102 are used to provide data signals for the sub-pixel driving circuits 60 included in the sub-pixels in the display area.
  • the plurality of data fan-out lines 21 are in one-to-one correspondence with the plurality of data lines 102, and the data fan-out lines 21 are coupled to the corresponding data lines 102, It is used to provide data signals for the corresponding data lines 102 .
  • the plurality of data fan-out lines are located on the lower border of the display substrate.
  • the data fan-out line and the corresponding data line 102 are coupled through a conductive part A, and the conductive part A is made of a first gate metal layer.
  • the display substrate further includes a plurality of fan-out extension lines 212 , and at least some of the fan-out extension lines 212 are in one-to-one correspondence with the plurality of data fan-out lines 21 , so
  • the fan-out extension lines 212 are respectively coupled to the corresponding data fan-out lines 21 and corresponding pins in the driver chip, and the fan-out extension lines 212 are used to transmit data signals provided by the driver chip to the corresponding data fan-out lines 21 .
  • the display substrate includes a base, and along a direction away from the base, an active layer, a first gate insulating layer, a first gate metal layer, and a second gate are sequentially stacked on the base.
  • the display substrate may further include a passivation layer PVX, where the passivation layer PVX is located between the first source-drain metal layer and the first planarization layer PLN1. It should be noted that FIG. 11 is a schematic diagram showing the layout of the active layer in the lower left corner of the display substrate.
  • the fan-out extension line 212 extends along the second direction, the plurality of fan-out extension lines 212 are arranged at intervals along the first direction, and the fan-out extension line 212 is spaced along the first direction.
  • the extension line 212 and the second source-drain metal layer are provided in the same layer and the same material, and the orthographic projection of the fan-out extension line 212 on the base is the same as the normal projection of the bending region 30 of the display substrate on the base. The projections overlap at least partially.
  • the side of the second source-drain metal layer facing the substrate is adjacent to the first flat layer
  • the side of the second source-drain metal layer facing away from the substrate is adjacent to the second flat layer
  • the first flat layer is adjacent to the side of the second source-drain metal layer facing away from the substrate.
  • Both the flat layer and the second flat layer are made of organic materials. Therefore, the fan-out extension line 212 and the second source-drain metal layer are arranged in the same layer and the same material, which is beneficial to the fan-out extension line 212 in the bending area. 30 places of reliability.
  • the plurality of data fan-out lines include a plurality of first data fan-out lines 210 and a plurality of second data fan-out lines 211 , the plurality of first data lines 102 are evenly distributed, and the plurality of second data lines 102 evenly distributed.
  • the first data fan-out lines 210 and the scan lines 101 are provided in the same layer and material, so that the first data fan-out lines 210 and the scan lines 101 can be formed in the same patterning process.
  • the second data fan-out line 211 and the data line 102 are arranged in the same layer and material, so that the second data fan-out line 211 and the data line 102 can be formed in the same patterning process, so that the The manufacturing process of the display substrate is better simplified, and the manufacturing cost of the display substrate is reduced.
  • the fan-out extension line 212 and the corresponding data line 102 coupled thereto are disposed in different layers, and the fan-out extension line 212 is directly connected to the corresponding data line through at least one via hole 102; or, the fan-out extension line 212 is coupled to the corresponding data line 102 through at least one via hole and a conductive portion.
  • the fan-out extension line 212 and the second data fan-out line 211 are directly coupled through at least one via hole, and the fan-out extension line 212 and the first data fan-out line 210 pass through via holes and conductive parts
  • the conductive part is made of the first source-drain metal layer.
  • the plurality of data fan-out lines to include a plurality of first data fan-out lines 210 and a plurality of second data fan-out lines 211 , the first data fan-out lines 211 .
  • a data fan-out line 210 and the scan line 101 are formed in the same layer and material, and the second data fan-out line 211 and the data line 102 are formed in the same layer and material; so that the first data fan-out line 210 and the The two data fan-out lines 211 are arranged in different layers, so that the distance between the orthographic projection of the first data fan-out line 210 on the substrate and the orthographic projection of the second data fan-out line 211 on the substrate can be shortened. distance, reducing the overall space occupied by the plurality of data fan-out lines, and reducing the overall width of the plurality of data fan-out lines in the second direction, thereby effectively narrowing the width of the lower border of the display substrate and improving the display substrate. Formed to show the competitiveness of products.
  • At least part of the orthographic projection of the first data fan-out line 210 on the base 80 of the display substrate is set, and the second data fan-out line 211 is set on the base 80 .
  • the above arrangement shortens the distance between the orthographic projection of the first data fan-out line 210 on the substrate and the orthographic projection of the second data fan-out line 211 on the substrate, reducing the number of The space occupied by the data fan-out line as a whole effectively narrows the width of the lower frame of the display substrate and improves the competitiveness of the display products formed by the display substrate.
  • At least part of the first data fan-out line 210 is set to include a first line segment, at least part of the second data fan-out line 211 includes a second line segment, and the first data fan-out line 211 includes a second line segment.
  • the orthographic projection of the line segment on the substrate coincides with the orthographic projection of the second line segment on the substrate.
  • the extending direction of the first line segment intersects both the first direction and the second direction.
  • the first data fan-out line is improved 210 and the second data fan-out line 211 have uneven line widths, further shortening the orthographic projection of the first data fan-out line 210 on the substrate and the second data fan-out line 211 on the
  • the distance between the orthographic projections on the substrate reduces the overall space occupied by the plurality of data fan-out lines, thereby effectively narrowing the width of the lower frame of the display substrate and improving the competitiveness of display products formed by the display substrate.
  • the display substrate further includes:
  • a power supply line includes a first power supply layer (such as a first positive power supply layer 220, a first negative power supply layer 240), and in a direction perpendicular to the base of the display substrate, at least one of the first power supply layer A portion is located between the first data fan-out line 210 and the second data fan-out line 211 .
  • a first power supply layer such as a first positive power supply layer 220, a first negative power supply layer 240
  • the orthographic projection of the first power supply layer on the substrate at least partially overlaps with the orthographic projection of the first data fan-out line 210 on the substrate.
  • the orthographic projection of the first power supply layer on the substrate at least partially overlaps with the orthographic projection of the second data fan-out line 211 on the substrate.
  • the first power supply layer is located between the first data fan-out line 210 and the second data fan-out line 211, so that in the direction perpendicular to the substrate
  • the first power supply layer can separate the first data fan-out line 210 from the second data fan-out line 211. Since static DC signals are transmitted on the first power supply layer, the Crosstalk between a data fan-out line 210 and the second data fan-out line 211 .
  • the power supply line further includes a second power supply layer (eg, the second positive power supply layer 221 , the Two negative power supply layers 241), the second power supply layer is coupled to the first power supply layer;
  • a second power supply layer eg, the second positive power supply layer 221 , the Two negative power supply layers 241, the second power supply layer is coupled to the first power supply layer;
  • At least part of the first power supply layer and at least part of the second power supply layer are both located in the non-display area 20, the first power supply layer and the second power supply layer are stacked and arranged, and the first power supply layer At least part of the is located between the second power supply layer and the base of the display substrate.
  • the power lines include a positive power line 22 and a negative power line 24 .
  • the first power supply layer and the second power supply layer are stacked and disposed, and in a direction perpendicular to the substrate, at least part of the first power supply layer is located between the second power supply layer and the display. between the bases of the substrates.
  • the orthographic projection of the first power supply layer on the substrate at least partially overlaps the orthographic projection of the second power supply layer on the substrate.
  • the area of the power supply line is effectively increased, and the power transmission on the power supply line is reduced.
  • the voltage drop (loading) of the power supply signal by setting the power supply line to include the first power supply layer and the second power supply layer, the area of the power supply line is effectively increased, and the power transmission on the power supply line is reduced. The voltage drop (loading) of the power supply signal.
  • At least part of the second data fan-out line 211 is located at the first power supply layer (eg, the first positive power supply layer). 220, the first negative power supply layer 240) and the second power supply layer (eg, the second positive power supply layer 221, the second negative power supply layer 241).
  • the orthographic projection of the second data fan-out line 211 on the substrate at least partially overlaps the orthographic projection of the first power supply layer on the substrate, where the second data fan-out line 211 is located.
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the second power layer on the substrate.
  • the crosstalk between 211 also ensures the stability of the data signal transmitted on the second data fan-out line 211.
  • the display substrate further includes conductive connection parts (eg, the first conductive connection part 23 and the second conductive connection part 25 ), At least part of the conductive connection part is located in the first power supply layer (eg, the first positive power supply layer 220, the first negative power supply layer 240) and the second power supply layer (eg, the second positive power supply layer 221, the second negative power supply layer Between the power supply layers 241), the conductive connection parts are respectively coupled to the first power supply layer and the second power supply layer.
  • first power supply layer eg, the first positive power supply layer 220, the first negative power supply layer 240
  • the second power supply layer eg, the second positive power supply layer 221, the second negative power supply layer Between the power supply layers 241
  • the orthographic projection of the conductive connection portion on the substrate at least partially overlaps with the orthographic projection of the first power supply layer on the substrate; the orthographic projection of the conductive connection portion on the substrate a projection that at least partially overlaps the orthographic projection of the second power layer on the substrate.
  • the conductive connection portion is disposed in a uniform layer with the first power supply layer and the second power supply layer, and in a direction perpendicular to the substrate, at least part of the conductive connection portion is located in the first power supply layer. Between a power supply layer and the second power supply layer, the conductive connection parts are respectively coupled to the first power supply layer and the second power supply layer through corresponding via holes.
  • the above-mentioned arrangement of the display substrate further includes a conductive connection portion, and the conductive connection portion is respectively coupled to the first power supply layer and the second power supply layer, which ensures that the first power supply layer and the second power supply layer are well connected.
  • the display substrate includes a first gate metal layer 96 and a second gate metal layer 97 which are sequentially stacked along a direction away from the base of the display substrate. , the first source-drain metal layer SD1 and the second source-drain metal layer SD2;
  • the scan line 101 and the first gate metal layer 96 are provided in the same layer and the same material, and the data line 102 and the first source-drain metal layer SD1 are provided in the same layer and the same material;
  • the first power supply layer and the second gate metal layer 97 are provided on the same layer and the same material
  • the second power supply layer and the second source-drain metal layer SD2 are provided on the same layer and the same material
  • the conductive connection portion is connected to the same material.
  • the first source-drain metal layer SD1 is provided with the same layer and the same material.
  • the first gate metal layer 96 includes the gate electrode of the thin film transistor in the sub-pixel driving circuit 60 and the electrode plate of the capacitor; the second gate metal layer 97 includes the sub-pixel driving circuit 60 The electrode plate of the middle capacitor, and some signal lines in the display substrate; the first source-drain metal layer SD1 includes some signal lines in the display substrate and some conductive connection patterns; the second source-drain metal layer SD2 includes the display substrate. Some signal lines in the substrate, and some conductive connection patterns.
  • FIG. 21 also shows the substrate 90, the active layer 98, the first flat layer PLN1, the second flat layer PLN2, the pixel defining layer PDL, the anode layer 91, the light-emitting functional layer EL, the cathode layer 92, the first inorganic layer
  • the scan line 101 and the first gate metal layer 96 are set in the same layer and the same material, so that the scan line 101 and the first gate metal layer 96 can be formed in the same patterning process;
  • the line 102 and the first source-drain metal layer SD1 are set in the same layer and the same material, so that the data line 102 and the first source-drain metal layer SD1 can be formed in the same patterning process;
  • the first power layer The same material as the second gate metal layer 97 is set, so that the first power supply layer and the second gate metal layer 97 can be formed in the same patterning process;
  • the second source-drain metal layer SD2 is provided with the same layer and material, so that the second power supply layer and the second source-drain metal layer SD2 can be formed in the same patterning process;
  • the first conductive connection portion 23 The first source-drain metal layer SD1 and the first source-drain metal layer SD1 are provided in the same layer and the same material, so that the first conductive connection portion 23 and the first source-drain
  • the "same layer" in the embodiments of the present disclosure may refer to a film layer on the same structural layer.
  • the film layers in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through one patterning process.
  • one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These particular graphics may also be at different heights or have different thicknesses.
  • the power supply line includes a positive power supply line 22
  • the first power supply layer includes a first positive power supply layer 220
  • the The second power supply layer includes a second positive power supply layer 221;
  • At least part of the first positive power supply layer 220 extends along a first direction
  • the first positive power supply layer 220 includes a first middle portion 2202 and two first end portions 2201
  • the first positive power supply layer 220 extends along the first direction
  • the middle portion 2202 is located between the two first end portions 2201, and the two first end portions 2201 are symmetrical with respect to the central axis 40 of the display substrate extending along a second direction, the second direction being the same as the the first direction intersects;
  • the maximum width of the first end portion 2201 in the second direction is smaller than the maximum width of the first middle portion 2202 in the second direction.
  • the power supply line includes a positive power supply line 22, and the positive power supply line 22 is used for transmitting a positive power supply signal VDD.
  • the first power supply layer includes a first positive power supply layer 220
  • the second power supply layer includes a second positive power supply layer 221
  • the first positive power supply layer 220 is coupled to the second positive power supply layer 221 .
  • the first positive power supply layer 220 includes a first middle portion 2202 and two first end portions 2201, and the first middle portion 2202 and the two first end portions 2201 form an integral structure.
  • the width of the first middle portion 2202 in the second direction is uniform or non-uniform.
  • the first middle portion 2202 is symmetrical with respect to the central axis 40 of the display substrate extending along the second direction, and the two first end portions 2201 are symmetrical with respect to the middle axis extending along the second direction in the display substrate.
  • the axis 40 is symmetrical.
  • the voltage of the first positive power supply layer 220 is effectively reduced.
  • the layout difficulty ensures the uniformity and stability of the signal transmitted by the positive power line 22 .
  • the first end portion 2201 includes a first target portion 2201a, and the first target portion 2201a has a first width D1 in the second direction, along the direction away from the The first width D1 gradually becomes larger in the direction of the first middle portion 2202 .
  • the value range of the first width D1 is between 71 micrometers and 157 micrometers, which may include end points.
  • the first end portion 2201 by setting the first end portion 2201 to include the first target portion 2201a, it not only ensures a good connection between the first positive power supply layer 220 and the second positive power supply layer 221 .
  • the connection performance is improved, and the layout difficulty of the first positive power supply layer 220 is effectively reduced, and the uniformity and stability of the signals transmitted by the positive power supply line 22 are ensured.
  • the first end portion 2201 further includes a second target portion 2201b, and the first target portion 2201a is located at the second target portion along the first direction Between 2201b and the first intermediate portion 2202, the second target portion 2201b has a second width D2 along the second direction, and the second width D2 gradually changes in the direction away from the first intermediate portion 2202 Small.
  • the second target portion 2201b and the first target portion 2201a form an integral structure.
  • the value range of the second width D2 is less than or equal to 157 microns.
  • the first end portion 2201 by setting the first end portion 2201 to further include the second target portion 2201b, it not only ensures that the first positive power supply layer 220 and the second positive power supply layer 221 have a good connection between them.
  • the connection performance is improved, and the layout difficulty of the first positive power supply layer 220 is effectively reduced, and the uniformity and stability of the transmission signal of the positive power supply line 22 are ensured.
  • the non-display area 20 includes a bending area 30 , the orthographic projection of the first middle portion 2202 on the base of the display substrate, and the bending area 30 The orthographic projections on the substrate do not overlap.
  • the non-display area 20 includes a bending area 30, the bending area 30 is located at the lower frame of the display substrate, and the bending area 30 extends along the first direction.
  • the above-mentioned setting of the orthographic projection of the first middle portion 2202 on the base of the display substrate does not overlap with the orthographic projection of the bending region 30 on the base, thereby avoiding the occurrence of the first middle portion 2202 Bending, so as to ensure the reliability of the first middle part 2202.
  • the second positive power supply layer 221 includes: a second middle part 2210 and two second end parts 2211 , along the first At least part of the second middle portion 2210 is located between the two second end portions 2211, and the two second end portions 2211 are symmetrical with respect to the central axis 40 of the display substrate extending along the second direction;
  • the orthographic projection of the second end portion 2211 on the base of the display substrate at least partially overlaps with the orthographic projection of the first end portion 2201 on the base;
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the first intermediate portion 2202 on the substrate.
  • the second positive power supply layer 221 includes a second middle portion 2210 and two second end portions 2211 , and the second middle portion 2210 and the two second end portions 2211 form an integral structure.
  • the second middle portion 2210 is symmetrical with respect to the central axis 40 of the display substrate extending along the second direction, and the two second end portions 2211 are about the middle portion of the display substrate extending along the second direction.
  • the axis 40 is symmetrical.
  • the layout difficulty of the second positive power supply layer 221 is effectively reduced, and the guarantee of The uniformity and stability of the signal transmitted by the positive power line 22 are improved.
  • the second end portion 2211 includes a third target portion 2211a, the third target portion 2211a has a third width D3 in the second direction, The third width D3 gradually becomes larger in the direction of the second middle portion 2210 .
  • the value range of the third width D3 is between 73 micrometers and 175 micrometers, which may include end points.
  • the second end portion 2211 by setting the second end portion 2211 to include the third target portion 2211a, it not only ensures that the first positive power supply layer 220 and the second positive power supply layer 221 have a good connection between them.
  • the connection performance is improved, and the layout difficulty of the second positive power supply layer 221 is effectively reduced, and the uniformity and stability of the signals transmitted by the positive power supply line 22 are ensured.
  • the second end portion 2211 further includes a fourth target portion 2211b, and the third target portion 2211a is located between the fourth target portion 2211b and the fourth target portion 2211b along the first direction. Between the second middle portion 2210, the width D4 of the fourth target portion 2211b in the second direction is equal to the maximum value of the third width D3.
  • the width of the fourth target portion 2211b in the second direction is uniform.
  • the value of the width D4 includes 175 microns.
  • the value range of the width D4 is between 170 micrometers and 180 micrometers, which may include the end points.
  • the second end portion 2211 further includes the fourth target portion 2211b, and the width of the fourth target portion 2211b in the second direction is equal to the third width. maximum value, not only ensures good connection performance between the first positive power supply layer 220 and the second positive power supply layer 221, but also effectively reduces the layout difficulty of the second positive power supply layer 221, ensuring that all The uniformity and stability of the signal transmitted by the positive power line 22 are described.
  • the second end portion 2211 further includes a fifth target portion 2211c, and the fourth target portion 2211b is located between the fifth target portion 2211c and the fifth target portion 2211c along the first direction.
  • the fifth target portion 2211c has a fifth width D5 in the second direction, and the fifth width D5 gradually decreases along the direction away from the second middle portion 2210 .
  • the value range of the fifth width D5 is between 84 micrometers and 175 micrometers, which may include end points.
  • the fifth target portion 2211c, the fourth target portion 2211b and the third target portion 2211a form an integral structure.
  • the second end portion 2211 further includes the fifth target portion 2211c, and the fifth target portion 2211c has a fifth width in the second direction, along the direction away from the The fifth width gradually decreases in the direction of the second middle portion 2210, which not only ensures good connection performance between the first positive power supply layer 220 and the second positive power supply layer 221, but also effectively reduces the The difficulty of the layout of the second positive power supply layer 221 ensures the uniformity and stability of the signals transmitted by the positive power supply line 22 .
  • the second intermediate portion 2210 includes:
  • first transmission part 2210a two ends of the first transmission part 2210a are coupled to the two second end parts 2211 in a one-to-one correspondence;
  • a second transmission part 2210b at least a part of the second transmission part 2210b extends along the first direction, and the first transmission part 2210a is located between the display area and the second transmission part 2210b;
  • connection part 2210c the at least one connection part 2210c is located between the first transmission part 2210a and the second transmission part 2210b, the connection part 2210c is respectively connected with the first transmission part 2210a and the second transmission part 2210b.
  • the two transmission parts 2210b are coupled; the orthographic projection of the connecting part 2210c on the base of the display substrate at least partially overlaps with the orthographic projection of the bending region 30 of the display substrate on the base;
  • Two first wire feed portions 2210d at least a part of the first wire feed portion 2210d extends along the second direction, and the two first wire feed portions 2210d are one with two ends of the second transmission portion 2210b. A corresponding coupling.
  • the first transmission part 2210a, the second transmission part 2210b, the at least one connection part 2210c and the two first wire entry parts 2210d form an integral structure.
  • a grid-shaped power supply layer 103 is provided in the display area of the display substrate, and the first transmission part 2210 a is coupled to the grid-shaped power supply layer 103 .
  • the length of the first transmission part 2210a in the first direction is smaller than the length of the second transmission part 2210b in the first direction.
  • the second middle part 2210 includes a plurality of connecting parts 2210c, the plurality of connecting parts 2210c are located between the first transmission part 2210a and the second transmission part 2210b, the plurality of connecting parts 2210c are arranged at intervals along the first direction, and each of the connecting parts 2210c is respectively coupled to the first transmission part 2210a and the second transmission part 2210b.
  • the orthographic projection of the connection portion 2210c on the base of the display substrate at least partially overlaps with the orthographic projection of the bending region 30 of the display substrate on the base. at least partially bent.
  • the two first wire entry portions 2210d extend away from the display area along the second direction.
  • the two first wire entry portions 2210d are coupled to the driver chip, and receive a positive power signal provided by the driver chip.
  • the conductive connection part includes two first conductive connection parts 23 , and the two first conductive connection parts 23 are related to The central axis 40 is symmetrical; the first conductive connection portion 23 is coupled to the first end portion 2201 and the second end portion 2211 respectively.
  • the two first conductive connection parts 23 correspond to the two first end parts 2201 one-to-one, and the two first conductive connection parts 23 correspond to the two second end parts 2211 one-to-one Correspondingly, the first conductive connection portions 23 are respectively coupled to the corresponding first end portion 2201 and the corresponding second end portion 2211 .
  • the conductive connection portion by setting the conductive connection portion to include the two first conductive connection portions 23 , it not only ensures that the first positive power supply layer 220 and the second positive power supply layer 221 are in good condition.
  • the connection performance is improved, the layout difficulty of the conductive connection portion is effectively reduced, and the uniformity and stability of the signal transmitted by the positive power line 22 are ensured.
  • the first conductive connection portion 23 is arranged to extend from the lower frame of the display substrate to the side frame of the display substrate.
  • one first conductive connection part 23 extends from the lower frame of the display substrate to the left frame of the display substrate, and the other first conductive connection part 23 extends from the lower frame of the display substrate to the left frame of the display substrate.
  • the lower frame of the display substrate extends to the right frame of the display substrate.
  • the first conductive connection portion 23 extends along the corner of the display area and is in an arc shape.
  • the above arrangement can better reduce the voltage drop generated by the positive power line 22 when transmitting the power signal.
  • the orthographic projection of the first conductive connection portion 23 on the substrate is where the first end portion 2201 is located.
  • the orthographic projection on the base of the display substrate has a first overlapping region, and the first conductive connection portion 23 is coupled to the first end portion 2201 through a first via hole Via1, where the first via hole Via1 is located.
  • an orthographic projection on the substrate at least partially overlaps the first overlapping region;
  • the orthographic projection of the first conductive connection portion 23 on the substrate and the orthographic projection of the second end portion 2211 on the substrate have a second overlapping area, and the first conductive connection portion 23 passes through the second
  • the via hole Via2 is coupled to the second end portion 2211 , and the orthographic projection of the second via hole Via2 on the substrate at least partially overlaps the second overlapping region.
  • the first via hole Via1 penetrates the interlayer insulating layer
  • the second via hole Via2 penetrates the passivation layer and the first flat layer.
  • the second via hole Via2 only penetrates the first flat layer.
  • the first via hole Via1 and the second via hole Via2 are arranged along the first direction.
  • the above arrangement is beneficial to narrow the width of the lower frame of the display substrate.
  • the display substrate further includes:
  • the orthographic projection of the second via hole Via2 on the substrate partially overlaps with the orthographic projection of at least part of the first signal line 50 on the substrate.
  • the gate driving circuit GOA is arranged on the left side frame and the right side frame of the display substrate, and the plurality of first signal lines 50 are arranged on the left side and the right side of the lower frame of the display substrate.
  • the first signal line 50 is coupled to the driving chip through a connecting line.
  • the connecting line is located at the position marked 70 in FIG. 16 , and a touch connecting line or the like may also be provided at this position for transmitting touch signals.
  • the gate driving circuit GOA can provide scan signals for the scan lines through the signal transmission line B. As shown in FIG.
  • the above arrangement can effectively narrow the width of the lower frame of the display substrate while avoiding the short circuit between the positive power line 22 and the first signal line 50 .
  • the power line includes a negative power line 24
  • the first power layer includes a first negative power line 24
  • the second power supply layer includes a second negative power supply layer 241;
  • the first negative power supply layer 240 includes two first negative power supply patterns 2401, the two first negative power supply patterns 2401 are symmetrical about the central axis 40, and at least a part of the first end portion 2201 is located in the display. area and the first negative power pattern 2401.
  • the power supply line includes a negative power supply line 24, and the negative power supply line 24 is used to transmit the negative power supply signal VSS.
  • the first power supply layer includes a first negative power supply layer 240
  • the second power supply layer includes a second negative power supply layer 241
  • the first negative power supply layer 240 is coupled to the second negative power supply layer 241 .
  • the orthographic projection of at least part of the first negative power pattern 2401 on the substrate is located where the orthographic projection of the first signal line 50 on the substrate and the first end portion 2201 are located. between the orthographic projections on the substrate.
  • the above-mentioned arrangement of the first negative power supply layer 240 includes two first negative power supply patterns 2401 , and the two first negative power supply patterns 2401 are symmetrical about the central axis 40 , which effectively reduces the voltage of the first negative power supply layer 240
  • the layout difficulty ensures the uniformity and stability of the signal transmitted by the negative power line 24 .
  • the first negative power pattern 2401 includes a sixth target portion 2401a and a seventh target portion 2401b, and the sixth target portion 2401a is located between the seventh target portion 2401b and the seventh target portion 2401b. Between the central axes 40, the width D6 of the sixth target portion 2401a in the second direction is greater than the maximum width (eg, D2) of the first end portion 2201 in the second direction.
  • the sixth target portion 2401a and the seventh target portion 2401b form an integral structure.
  • the width of the sixth target portion 2401a in the second direction is uniform or non-uniform.
  • the value of the width D6 includes 392 microns.
  • the value range of the width D6 includes between 387 ⁇ m and 397 ⁇ m, and may include end points.
  • the above-mentioned setting of the width of the sixth target portion 2401a in the second direction is greater than the maximum width of the first end portion 2201 in the second direction, which well ensures the transmission performance of the negative power line 24 and reduces the The voltage drop generated when the negative power line 24 transmits the signal is eliminated.
  • the seventh target portion 2401b is set to have a seventh width D7 in the second direction, and the seventh width D7 gradually decreases along the direction away from the central axis 40 . Small.
  • the value range of the seventh width D7 is between 73 microns and 392 microns, which may include end points.
  • the above arrangement not only ensures good connection performance between the first negative power supply layer 240 and the second negative power supply layer 241, but also effectively reduces the layout difficulty of the first negative power supply pattern 2401, ensuring that The negative power line 24 transmits signal uniformity and stability.
  • the second negative power supply layer 241 includes:
  • the annular portion 2411 surrounds the display area, the annular portion 2411 has an opening at the lower frame of the display substrate, and at least part of the second end portion 2211 is located between the annular portion 2411 and the between display areas;
  • Two second wire inlets 2412, at least part of the second wire inlets 2412 extend along the second direction, the two second wire inlets 2412 and the two ends of the annular portion 2411 at the opening One-to-one correspondence coupling.
  • annular portion 2411 and the two second wire inlet portions 2412 are formed as an integral structure.
  • At least a portion of the second wire entry portion 2412 extends away from the display area along the second direction.
  • both the annular portion 2411 and the two second wire inlet portions 2412 are symmetrical with respect to the central axis 40 .
  • At least parts of the second transmission part 2210b , the first wire inlet part 2210d and the connection part 2210c are all located between the two second wire inlet parts 2412 .
  • one end of the second wire entry portion 2412 away from the display area is coupled to a driving chip, and receives a negative power supply signal provided by the driving chip.
  • the second wire inlet portion 2412 is provided with an opening 2412a, and the orthographic projection of the opening 2412a on the base of the display substrate is different from that of the display substrate.
  • the orthographic projections of the middle bend region 30 on the substrate at least partially overlap.
  • the above arrangement can better ensure the reliability of the second wire inlet portion 2412 when the bending region 30 is bent.
  • disposing the conductive connection portion includes a second conductive connection portion 25 surrounding the display area, the second conductive connection part 25 has an opening in the lower frame of the display substrate; the second conductive connection part 25 is respectively coupled to the first negative power supply layer 240 and the second negative power supply layer 241 .
  • the second conductive connection portion 25 is symmetrical about the central axis 40 .
  • the above arrangement well ensures the connection performance between the first negative power supply layer 240 and the second negative power supply layer 241 , and ensures the uniformity and stability of the signal transmitted by the negative power supply line 24 .
  • the second conductive connection part 25 includes: a surrounding part 251 , two first parts 252 and two second parts 253 ;
  • At least part of the display area is surrounded by the surrounding portion 251 , two ends of the surrounding portion 251 are coupled to the first ends of the two second portions 253 in a one-to-one correspondence, and the two second The second end of the portion 253 is coupled to the two first portions 252 in a one-to-one correspondence, and an opening of the second conductive connection portion 25 is formed between the two first portions 252;
  • the extending direction of the first part 252 intersects both the first direction and the second direction, and the first part 252 is at the base of the display substrate
  • the orthographic projection on the substrate has a third overlapping area with the orthographic projection of the first negative power supply layer 240 on the substrate, and the first portion 252 is coupled to the first negative power supply layer 240 through the third via hole Via3 Then, the orthographic projection of the third via hole Via3 on the substrate at least partially overlaps the third overlapping region;
  • the orthographic projection of the second portion 253 on the substrate and /or the orthographic projection of the surrounding portion on the substrate has a fourth overlapping area with the orthographic projection of the second negative power supply layer 241 on the substrate, the second portion 253 and/or the The surrounding portion is coupled to the second negative power supply layer 241 through a fourth via hole Via4, and the orthographic projection of the fourth via hole Via4 on the substrate at least partially overlaps the fourth overlapping region.
  • the surrounding portion 251 , the two first portions 252 and the two second portions 253 are formed into an integral structure.
  • the surrounding portion 251 is symmetrical about the central axis 40
  • the two first portions 252 are symmetrical about the central axis 40
  • the two second portions 253 are symmetrical about the central axis 40 .
  • the surrounding portion 251 is not closed at the lower frame of the display substrate, and has two ends.
  • the two first parts 252 are not directly connected, and an opening of the second conductive connection part 25 is formed between the two first parts 252 .
  • the third via hole Via3 penetrates the interlayer insulating layer
  • the fourth via hole Via4 penetrates the passivation layer and the first flat layer.
  • the fourth via hole Via4 only penetrates the first flat layer.
  • At least part of the orthographic projection of the fourth via hole Via4 on the substrate extends along the first direction.
  • at least part of the orthographic projection of the fourth via hole Via4 on the substrate extends along a corner area of the display substrate.
  • Second conductive connection part 25 can well ensure the connection performance between the first negative power supply layer 240 and the second negative power supply layer 241 , and ensure the negative power supply line 24 Uniformity and stability of the transmitted signal.
  • the extending direction of the orthographic projection of the third via hole Via3 on the substrate intersects both the first direction and the second direction.
  • the above arrangement not only helps to reduce the layout difficulty of the negative power supply line 24 and the second conductive connection part 25 , but also can well ensure the first negative power supply layer 240 and the second negative power supply layer 241 connection performance.
  • Embodiments of the present disclosure further provide a display device including the display substrate provided by the above embodiments.
  • the plurality of data fan-out lines include a plurality of first data fan-out lines 210 and a plurality of second data fan-out lines 211 by setting the first data fan-out lines 210 and the scan lines.
  • 101 is set on the same layer and the same material
  • the second data fan-out line 211 and the data line 102 are set on the same layer and the same material; so that the first data fan-out line 210 and the second data fan-out line 211 are set in different layers, so that Therefore, by shortening the distance between the orthographic projection of the first data fan-out line 210 on the substrate and the orthographic projection of the second data fan-out line 211 on the substrate, the number of The overall space occupied by the data fan-out lines reduces the overall width of the plurality of data fan-out lines in the second direction, thereby effectively narrowing the width of the lower frame of the display substrate and improving the competitiveness of display products formed by the display substrate.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, and a tablet computer.
  • An embodiment of the present disclosure further provides a method for fabricating a display substrate, and the fabrication method is used for fabricating the display substrate provided in the above-mentioned embodiments, the display substrate includes: a display area and a non-display area 20 surrounding the display area;
  • the fabrication method includes: fabricating a plurality of scan lines 101, a plurality of data lines 102 and a plurality of data fan-out lines;
  • At least part of the data line 102 is located in the display area
  • At least part of the data fan-out lines are located in the non-display area 20, and the data fan-out lines are coupled to the corresponding data lines 102;
  • the plurality of data fan-out lines include a plurality of first data fan-out lines 210 and a plurality of first data fan-out lines
  • Two data fan-out lines 211 , the first data fan-out line 210 and the scan line 101 are provided in the same layer and the same material, and the second data fan-out line 211 and the data line 102 are provided in the same layer and the same material.
  • the plurality of data fan-out lines include a plurality of first data fan-out lines 210 and a plurality of second data fan-out lines 211 , the plurality of first data lines 102 are evenly distributed, and the plurality of second data lines 102 evenly distributed.
  • the first data fan-out lines 210 and the scan lines 101 are provided in the same layer and material, so that the first data fan-out lines 210 and the scan lines 101 can be formed in the same patterning process.
  • the second data fan-out line 211 and the data line 102 are arranged in the same layer and material, so that the second data fan-out line 211 and the data line 102 can be formed in the same patterning process, so that the The manufacturing process of the display substrate is better simplified, and the manufacturing cost of the display substrate is reduced.
  • the plurality of data fan-out lines include a plurality of first data fan-out lines 210 and a plurality of second data fan-out lines 211 by setting the first data fan-out lines.
  • 210 and the scan line 101 are set on the same layer and material
  • the second data fan-out line 211 and the data line 102 are set on the same layer and the same material; so that the first data fan-out line 210 and the second data fan-out line are 211 are arranged in different layers, so that the distance between the orthographic projection of the first data fan-out line 210 on the substrate and the orthographic projection of the second data fan-out line 211 on the substrate can be reduced.
  • the overall space occupied by the plurality of data fan-out lines is reduced, and the overall width of the plurality of data fan-out lines in the second direction is reduced, thereby effectively narrowing the width of the lower frame of the display substrate and improving the display formed by the display substrate. product competitiveness.
  • sequence numbers of the steps are not used to limit the sequence of the steps.
  • the sequence of the steps can be changed without creative work. Also within the scope of protection of the present disclosure.

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Abstract

一种显示基板、显示装置，该显示基板包括：显示区域（10）和围绕显示区域（10）的非显示区域（20）；显示基板还包括：多条扫描线（101），多条数据线（102）和多条数据扇出线（21），扫描线（101）的至少部分位于显示区域；数据线（102）的至少部分位于显示区域；数据扇出线（21）的至少部分位于非显示区域（10），数据扇出线（21）与对应的数据线（102）耦接；多条数据扇出线（21）包括多条第一数据扇出线（210）和多条第二数据扇出线（211），第一数据扇出线（210）与扫描线（101）同层同材料设置，第二数据扇出线（211）与数据线（102）同层同材料设置。

Description

显示基板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示装置。
背景技术
近年来，随着显示技术的进步，有源矩阵有机发光二极管(英文：Active Matrix Organic Light Emitting Diode，简称AMOLED)显示面板成为当今平板显示器研究领域的热点之一。AMOLED显示面板相对于传统的薄膜晶体管液晶显示面板(英文：Thin Film Transistor Liquid Crystal Display，简称：TFTLCD)具有更快的反应速度，更高的对比度以及更广大的视角。且随着显示技术的发展，越来越多的电子设备对AMOLED显示面板边框的尺寸要求越来越高，使得AMOLED显示面板逐渐向窄边框方向发展。
发明内容
本公开的目的在于提供一种显示基板、显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种显示基板，包括：显示区域和围绕所述显示区域的非显示区域；所述显示基板还包括：
多条扫描线，所述扫描线的至少部分位于所述显示区域；
多条数据线，所述数据线的至少部分位于所述显示区域；
多条数据扇出线，所述数据扇出线的至少部分位于所述非显示区域，所述数据扇出线与对应的数据线耦接；所述多条数据扇出线包括多条第一数据扇出线和多条第二数据扇出线，所述第一数据扇出线与所述扫描线同层同材料设置，所述第二数据扇出线与所述数据线同层同材料设置。
可选的，至少部分所述第一数据扇出线在所述显示基板的基底上的正投影，与所述第二数据扇出线在所述基底上的正投影至少部分交叠。
可选的，至少部分所述第一数据扇出线包括第一线段，至少部分所述第 二数据扇出线包括第二线段，所述第一线段在所述基底上的正投影与所述第二线段在所述基底上的正投影重合。
可选的，所述显示基板还包括：
电源线，所述电源线包括第一电源层，在垂直于所述显示基板的基底的方向上，所述第一电源层的至少部分位于所述第一数据扇出线和所述第二数据扇出线之间。
可选的，所述电源线还包括第二电源层，所述第二电源层与所述第一电源层耦接；
所述第一电源层的至少部分和所述第二电源层的至少部分均位于所述非显示区域，所述第一电源层与所述第二电源层层叠设置，所述第一电源层的至少部分位于所述第二电源层与所述显示基板的基底之间。
可选的，在垂直于所述显示基板的基底的方向上，所述第二数据扇出线的至少部分位于所述第一电源层和所述第二电源层之间。
可选的，所述显示基板还包括导电连接部，所述导电连接部的至少部分位于所述第一电源层和所述第二电源层之间，所述导电连接部分别与所述第一电源层和所述第二电源层耦接。
可选的，所述显示基板包括沿远离所述显示基板的基底的方向依次层叠设置的第一栅金属层，第二栅金属层，第一源漏金属层和第二源漏金属层；
所述扫描线与所述第一栅金属层同层同材料设置，所述数据线与所述第一源漏金属层同层同材料设置；
所述第一电源层与所述第二栅金属层同层同材料设置，所述第二电源层与所述第二源漏金属层同层同材料设置，所述导电连接部与所述第一源漏金属层同层同材料设置。
可选的，所述电源线包括正电源线，所述第一电源层包括第一正电源层，所述第二电源层包括第二正电源层；
所述第一正电源层的至少部分沿第一方向延伸，所述第一正电源层包括第一中间部分和两个第一端部，沿所述第一方向所述第一中间部分位于所述两个第一端部之间，所述两个第一端部关于所述显示基板中沿第二方向延伸的中轴线对称，所述第二方向与所述第一方向相交；
所述第一端部在所述第二方向上的最大宽度，小于所述第一中间部分在所述第二方向上的最大宽度。
可选的，所述第一端部包括第一目标部分，所述第一目标部分在所述第二方向上具有第一宽度，沿远离所述第一中间部分的方向所述第一宽度逐渐变大。
可选的，所述第一端部还包括第二目标部分，沿所述第一方向所述第一目标部分位于所述第二目标部分与所述第一中间部分之间，所述第二目标部分沿所述第二方向具有第二宽度，沿远离所述第一中间部分的方向所述第二宽度逐渐变小。
可选的，所述非显示区域包括弯折区，所述第一中间部分在所述显示基板的基底上的正投影，与所述弯折区在所述基底上的正投影不交叠。
可选的，所述第二正电源层包括：第二中间部分和两个第二端部，沿所述第一方向所述第二中间部分的至少部分位于所述两个第二端部之间，所述两个第二端部关于所述显示基板中沿第二方向延伸的中轴线对称；
所述第二端部在所述显示基板的基底上的正投影，与所述第一端部在所述基底上的正投影至少部分交叠；所述第二中间部分在所述基底上的正投影，与所述第一中间部分在所述基底上的正投影至少部分交叠。
可选的，所述第二端部包括第三目标部分，所述第三目标部分在所述第二方向上具有第三宽度，沿远离所述第二中间部分的方向所述第三宽度逐渐变大。
可选的，所述第二端部还包括第四目标部分，沿所述第一方向所述第三目标部分位于所述第四目标部分与所述第二中间部分之间，所述第四目标部分在所述第二方向的宽度等于所述第三宽度的最大值。
可选的，所述第二端部还包括第五目标部分，沿所述第一方向所述第四目标部分位于所述第五目标部分与所述第二中间部分之间，所述第五目标部分在所述第二方向具有第五宽度，沿远离所述第二中间部分的方向所述第五宽度逐渐变小。
可选的，所述第二中间部分包括：
第一传输部，所述第一传输部的两端与所述两个第二端部一一对应耦接；
第二传输部，所述第二传输部的至少部分沿所述第一方向延伸，所述第一传输部位于所述显示区域与所述第二传输部之间；
至少一个连接部，所述至少一个连接部位于所述第一传输部与所述第二传输部之间，所述连接部分别与所述第一传输部和所述第二传输部耦接；所述连接部在所述显示基板的基底上的正投影，与所述显示基板的弯折区在所述基底上的正投影至少部分交叠；
两个第一进线部，所述第一进线部的至少部分沿所述第二方向延伸，所述两个第一进线部与所述第二传输部的两端一一对应耦接。
可选的，所述导电连接部包括两个第一导电连接部，所述两个第一导电连接部关于所述中轴线对称；所述第一导电连接部分别与所述第一端部和所述第二端部耦接。
可选的，所述第一导电连接部从所述显示基板的下边框延伸至显示基板的侧边框。
可选的，所述第一导电连接部在所述基底上的正投影与所述第一端部在所述显示基板的基底上的正投影具有第一交叠区，所述第一导电连接部通过第一过孔与所述第一端部耦接，所述第一过孔在所述基底上的正投影与所述第一交叠区至少部分交叠；
所述第一导电连接部在所述基底上的正投影与所述第二端部在所述基底上的正投影具有第二交叠区，所述第一导电连接部通过第二过孔与所述第二端部耦接，所述第二过孔在所述基底上的正投影与所述第二交叠区至少部分交叠。
可选的，所述第一过孔和所述第二过孔沿所述第一方向排列。
可选的，所述显示基板还包括：
多个栅极驱动电路和用于为所述多个栅极驱动电路提供相应信号的多条第一信号线；
所述第一过孔在所述基底上的正投影，位于所述多条第一信号线在所述基底上的正投影与所述多条数据扇出线在所述基底上的正投影之间；
所述第二过孔在所述基底上的正投影与至少部分所述第一信号线在所述基底上的正投影部分交叠。
可选的，所述电源线包括负电源线，所述第一电源层包括第一负电源层，所述第二电源层包括第二负电源层；
所述第一负电源层包括两个第一负电源图形，所述两个第一负电源图形关于所述中轴线对称，所述第一端部的至少部分位于所述显示区域与所述第一负电源图形之间。
可选的，所述第一负电源图形包括第六目标部分和第七目标部分，所述第六目标部分位于所述第七目标部分与所述中轴线之间，所述第六目标部分在所述第二方向的宽度，大于所述第一端部在所述第二方向的最大宽度。
可选的，所述第七目标部分在所述第二方向具有第七宽度，沿远离所述中轴线的方向，所述第七宽度逐渐减小。
可选的，所述第二负电源层包括：
环形部，所述环形部围绕所述显示区域，所述环形部在所述显示基板的下边框具有开口，所述第二端部的至少部分位于所述环形部与所述显示区域之间；
两个第二进线部，所述第二进线部的至少部分沿所述第二方向延伸，所述两个第二进线部与所述环形部在开口处的两端一一对应耦接。
可选的，所述第二进线部上设置有开孔，所述开孔在所述显示基板的基底上的正投影，与所述显示基板中弯折区在所述基底上的正投影至少部分交叠。
可选的，所述导电连接部包括第二导电连接部，所述第二导电连接部围绕所述显示区域，所述第二导电连接部在所述显示基板的下边框具有开口；所述第二导电连接部分别与所述第一负电源层和所述第二负电源层耦接。
可选的，所述第二导电连接部包括：环绕部，两个第一部分和两个第二部分；
所述显示区域的至少部分被所述环绕部环绕，所述环绕部的两个端部与所述两个第二部分的第一端一一对应耦接，所述两个第二部分的第二端与所述两个第一部分一一对应耦接，所述两个第一部分之间形成所述第二导电连接部的开口；
所述第一部分的延伸方向与所述第一方向和所述第二方向均相交，所述 第一部分在所述显示基板的基底上的正投影，与所述第一负电源层在所述基底上的正投影具有第三交叠区，所述第一部分通过第三过孔与所述第一负电源层耦接，所述第三过孔在所述基底上的正投影与所述第三交叠区至少部分交叠；
所述第二部分的至少部分沿所述第一方向延伸，所述第二部分在所述基底上的正投影和/或所述环绕部在所述基底上的正投影，与所述第二负电源层在所述基底上的正投影具有第四交叠区，所述第二部分和/或所述环绕部通过第四过孔与所述第二负电源层耦接，所述第四过孔在所述基底上的正投影与所述第四交叠区至少部分交叠。
可选的，所述第三过孔在所述基底上的正投影的延伸方向与所述第一方向和所述第二方向均相交。
基于上述显示基板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示基板。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的显示基板中电源线整体结构示意图；
图2为本公开实施例提供的数据扇出线的第一布局示意图；
图3为本公开实施例提供的数据扇出线的截面示意图；
图4为本公开实施例提供的数据扇出线的第二布局示意图；
图5为本公开实施例提供的数据扇出线与扇出延长线耦接的示意图；
图6为本公开实施例提供的数据扇出线的第三布局示意图；
图7为本公开实施例提供的数据扇出线的第四布局示意图；
图8为本公开实施例提供的正电源线和负电源线在显示基板左下角的部分的结构示意图；
图9为本公开实施例提供的显示基板的左下角的第一布局示意图；
图10为本公开实施例提供的显示基板的左下角的第二布局示意图；
图11为本公开实施例提供的显示基板的左下角的有源层的布局示意图；
图12为本公开实施例提供的显示基板的左下角的第一栅金属层的布局示意图；
图13为本公开实施例提供的显示基板的左下角的第二栅金属层的布局示意图；
图14为本公开实施例提供的显示基板的左下角的层间绝缘层的布局示意图；
图15为本公开实施例提供的显示基板的左下角的第一源漏金属层的布局示意图；
图16为本公开实施例提供的显示基板的左下角的第二源漏金属层的布局示意图；
图17为本公开实施例提供的显示基板的左下角的第二栅金属层和第一源漏金属层的布局示意图；
图18为本公开实施例提供的显示基板的左下角的第一源漏金属层和第二源漏金属层的布局示意图；
图19为本公开实施例提供的显示基板的左下角的钝化层的布局示意图；
图20为本公开实施例提供的显示基板的左下角的第一平坦层的布局示意图。
图21本公开实施例提供的显示基板中显示区域的截面示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示基板、显示装置，下面结合说明书附图进行详细描述。
随着显示技术的发展，越来越多的电子设备对显示面板边框的尺寸要求越来越高，使得显示面板逐渐向窄边框方向发展，这样就需要在满足电学和工艺的情况下，缩小显示面板中设置于边框处的结构的尺寸，以减小显示面板的边框宽度。
请参阅图1至图7、图12和图15，本公开实施例提供了一种显示基板， 包括：显示区域10和围绕所述显示区域10的非显示区域20；所述显示基板还包括：
多条扫描线101，所述扫描线101的至少部分位于所述显示区域10；
多条数据线102，所述数据线102的至少部分位于所述显示区域10；
多条数据扇出线21，所述数据扇出线21的至少部分位于所述非显示区域20，所述数据扇出线21与对应的数据线102耦接；所述多条数据扇出线21包括多条第一数据扇出线210和多条第二数据扇出线211，所述第一数据扇出线210与所述扫描线101同层同材料设置，所述第二数据扇出线211与所述数据线102同层同材料设置。
示例性的，所述显示基板包括显示区域和围绕所述显示区域10的非显示区域20，所述显示区域10包括多个子像素，用于实现显示基板的显示功能；所述显示基板包括沿第一方向相对设置的侧边框，如：左边框和有边框，所述显示基板还包括沿第二方向相对设置的上边框和下边框。示例性的，所述第一方向包括水平方向，所述第二方向包括竖直方向。
如图7所示，示例性的，所述多条扫描线101沿所述第二方向排列，所述扫描线101包括沿所述第一方向延伸的部分，所述扫描线101的至少部分位于所述显示区域。所述扫描线101用于为显示区中子像素包括的子像素驱动电路60提供扫描信号。
如图6和图7所示，示例性的，所述多条数据线102沿所述第一方向排列，所述数据线102包括沿所述第二方向延伸的部分，所述数据线102的至少部分位于所述显示区域。所述数据线102用于为显示区中子像素包括的子像素驱动电路60提供数据信号。
如图6和图7所示，示例性的，所述多条数据扇出线21与所述多条数据线102一一对应，所述数据扇出线21与对应的所述数据线102耦接，用于为对应的所述数据线102提供数据信号。示例性的，所述多条数据扇出线位于所述显示基板的下边框。示例性的，所述数据扇出线与对应的所述数据线102之间通过导电部A耦接，所述导电部A采用第一栅金属层制作。
如图4和图5所示，示例性的，所述显示基板还包括多条扇出延长线212，至少部分所述扇出延长线212与所述多条数据扇出线21一一对应，所述扇出 延长线212分别与对应的数据扇出线21和驱动芯片中对应的引脚耦接，所述扇出延长线212用于将驱动芯片提供的数据信号传输至对应的数据扇出线21。
示例性的，所述显示基板包括基底，以及沿远离所述基底的方向，依次层叠设置于所述基底上的有源层，第一栅极绝缘层，第一栅金属层，第二栅极绝缘层GI2，第二栅金属层，层间绝缘层ILD，第一源漏金属层，第一平坦层PLN1，第二源漏金属层，第二平坦层，阳极层，发光功能层，阴极层等。示例性的，所述显示基板还可以包括钝化层PVX，该钝化层PVX位于所述第一源漏金属层和所述第一平坦层PLN1之间。需要说明，图11示意了显示基板左下角有源层的布局示意图。
如图10所示，示例性的，所述扇出延长线212的至少部分沿所述第二方向延伸，所述多条扇出延长线212沿所述第一方向间隔排列，所述扇出延长线212与所述第二源漏金属层同层同材料设置，所述扇出延长线212在所述基底上的正投影与所述显示基板的弯折区30在所述基底上的正投影至少部分交叠。由于所述第二源漏金属层朝向基底的一侧紧挨的是第一平坦层，所述第二源漏金属层背向基底的一侧紧挨的是第二平坦层，所述第一平坦层和所述第二平坦层均采用有机材料制作，因此将所述扇出延长线212与所述第二源漏金属层同层同材料设置，有利于扇出延长线212在弯折区30处的信赖性。
示例性的，所述多条数据扇出线包括多条第一数据扇出线210和多条第二数据扇出线211，所述多条第一数据线102均匀分布，所述多条第二数据线102均匀分布。将所述第一数据扇出线210与所述扫描线101同层同材料设置，使得所述第一数据扇出线210与所述扫描线101能够在同一次构图工艺中形成。同样的，将所述第二数据扇出线211与所述数据线102同层同材料设置，使得所述第二数据扇出线211与所述数据线102能够在同一次构图工艺中形成，这样能够更好的简化显示基板的制作流程，降低显示基板的制作成本。
如图4和图5所示，示例性的，所述扇出延长线212与其对应耦接的数据线102异层设置，所述扇出延长线212通过至少一个过孔直接与对应的数 据线102耦接；或者，所述扇出延长线212通过至少一个过孔和导电部与对应的数据线102耦接。需要说明，所述扇出延长线212与所述第二数据扇出线211通过至少一个过孔直接耦接，所述扇出延长线212与所述第一数据扇出线210通过过孔和导电部实现耦接，所述导电部采用第一源漏金属层制作。
根据上述显示基板的具体结构可知，本公开实施例提供的显示基板中，通过设置所述多条数据扇出线包括多条第一数据扇出线210和多条第二数据扇出线211，所述第一数据扇出线210与所述扫描线101同层同材料设置，所述第二数据扇出线211与所述数据线102同层同材料设置；使得所述第一数据扇出线210与所述第二数据扇出线211异层设置，这样就可以通过缩短所述第一数据扇出线210在所述基底上的正投影与所述第二数据扇出线211在所述基底上的正投影之间的距离，减小了所述多条数据扇出线整体占用的空间，缩小所述多条数据扇出线在第二方向上的整体宽度，从而有效缩窄了显示基板的下边框宽度，提升了显示基板形成的显示产品的竞争力。
如图3所示，在一些实施例中，设置至少部分所述第一数据扇出线210在所述显示基板的基底80上的正投影，与所述第二数据扇出线211在所述基底80上的正投影至少部分交叠。
上述设置方式缩短了所述第一数据扇出线210在所述基底上的正投影与所述第二数据扇出线211在所述基底上的正投影之间的距离，减小了所述多条数据扇出线整体占用的空间，从而有效缩窄了显示基板的下边框宽度，提升了显示基板形成的显示产品的竞争力。
如图2至图7所示，在一些实施例中，设置至少部分所述第一数据扇出线210包括第一线段，至少部分所述第二数据扇出线211包括第二线段，所述第一线段在所述基底上的正投影与所述第二线段在所述基底上的正投影重合。
示例性的，所述第一线段的延伸方向与所述第一方向和所述第二方向均相交。
上述实施例提供的显示基板中，通过设置所述第一线段在所述基底上的正投影与所述第二线段在所述基底上的正投影重合，改善了所述第一数据扇出线210与所述第二数据扇出线211的线宽尺寸不均的问题，进一步缩短了 所述第一数据扇出线210在所述基底上的正投影与所述第二数据扇出线211在所述基底上的正投影之间的距离，减小了所述多条数据扇出线整体占用的空间，从而有效缩窄了显示基板的下边框宽度，提升了显示基板形成的显示产品的竞争力。
如图3，图8、图9、图13、图16、图17和图18所示，在一些实施例中，所述显示基板还包括：
电源线，所述电源线包括第一电源层(如第一正电源层220，第一负电源层240)，在垂直于所述显示基板的基底的方向上，所述第一电源层的至少部分位于所述第一数据扇出线210和所述第二数据扇出线211之间。
示例性的，所述第一电源层在所述基底上的正投影，与所述第一数据扇出线210在所述基底上的正投影至少部分交叠。示例性的，所述第一电源层在所述基底上的正投影，与所述第二数据扇出线211在所述基底上的正投影至少部分交叠。
上述实施例提供的显示基板中，通过设置所述第一电源层的至少部分位于所述第一数据扇出线210和所述第二数据扇出线211之间，使得在垂直于所述基底的方向上，所述第一电源层能够将所述第一数据扇出线210和所述第二数据扇出线211隔开，由于所述第一电源层上传输静态直流信号，从而有效降低了所述第一数据扇出线210和所述第二数据扇出线211之间的串扰。
如图3，图8、图9、图13、图16、图17和图18所示，在一些实施例中，所述电源线还包括第二电源层(如第二正电源层221，第二负电源层241)，所述第二电源层与所述第一电源层耦接；
所述第一电源层的至少部分和所述第二电源层的至少部分均位于所述非显示区域20，所述第一电源层与所述第二电源层层叠设置，所述第一电源层的至少部分位于所述第二电源层与所述显示基板的基底之间。
示例性的，所述电源线包括正电源线22和负电源线24。
示例性的，所述第一电源层与所述第二电源层层叠设置，在垂直于所述基底的方向上，所述第一电源层的至少部分位于所述第二电源层与所述显示基板的基底之间。
示例性的，所述第一电源层在所述基底上的正投影与所述第二电源层在 所述基底上的正投影至少部分交叠。
上述实施例提供的显示基板中，通过设置所述电源线包括所述第一电源层和所述第二电源层，有效增加了所述电源线的面积，降低了在所述电源线上传输的电源信号的压降(loading)。
如图3所示，在一些实施例中，在垂直于所述显示基板的基底的方向上，所述第二数据扇出线211的至少部分位于所述第一电源层(如第一正电源层220，第一负电源层240)和所述第二电源层(如第二正电源层221，第二负电源层241)之间。
示例性的，所述第二数据扇出线211在所述基底上的正投影与所述第一电源层在所述基底上的正投影至少部分交叠，所述第二数据扇出线211在所述基底上的正投影与所述第二电源层在所述基底上的正投影至少部分交叠。
上述设置所述第二数据扇出线211的至少部分位于所述第一电源层和所述第二电源层之间，不仅有效降低了所述第一数据扇出线210和所述第二数据扇出线211之间的串扰，还很好的保证了所述第二数据扇出线211上传输的数据信号的稳定性。
如图8、图9、图15、图17和图18所示，在一些实施例中，所述显示基板还包括导电连接部(如第一导电连接部23和第二导电连接部25)，所述导电连接部的至少部分位于所述第一电源层(如第一正电源层220，第一负电源层240)和所述第二电源层(如第二正电源层221，第二负电源层241)之间，所述导电连接部分别与所述第一电源层和所述第二电源层耦接。
示例性的，所述导电连接部在所述基底上的正投影，与所述第一电源层在所述基底上的正投影至少部分交叠；所述导电连接部在所述基底上的正投影，与所述第二电源层在所述基底上的正投影至少部分交叠。
示例性的，所述导电连接部与所述第一电源层和所述第二电源层均异层设置，在垂直于所述基底的方向上，所述导电连接部的至少部分位于所述第一电源层和所述第二电源层之间，所述导电连接部通过相应的过孔分别与所述第一电源层和所述第二电源层耦接。
上述设置所述显示基板还包括导电连接部，所述导电连接部分别与所述第一电源层和所述第二电源层耦接，很好的保证了所述第一电源层与所述第 二电源层之间的连接性能。
如图6、图7和图20所示，在一些实施例中，所述显示基板包括沿远离所述显示基板的基底的方向依次层叠设置的第一栅金属层96，第二栅金属层97，第一源漏金属层SD1和第二源漏金属层SD2；
所述扫描线101与所述第一栅金属层96同层同材料设置，所述数据线102与所述第一源漏金属层SD1同层同材料设置；
所述第一电源层与所述第二栅金属层97同层同材料设置，所述第二电源层与所述第二源漏金属层SD2同层同材料设置，所述导电连接部与所述第一源漏金属层SD1同层同材料设置。
如图6所示，示例性的，所述第一栅金属层96包括子像素驱动电路60中薄膜晶体管的栅极和电容的极板；所述第二栅金属层97包括子像素驱动电路60中电容的极板，以及显示基板中的一些信号线；所述第一源漏金属层SD1包括显示基板中的一些信号线，以及一些导电连接图形；所述第二源漏金属层SD2包括显示基板中的一些信号线，以及一些导电连接图形。
需要说明，图21中还示意了基底90，有源层98，第一平坦层PLN1，第二平坦层PLN2，像素界定层PDL，阳极层91，发光功能层EL，阴极层92，第一无机封装层93，有机封装层94，第二无机封装层95。
上述将所述扫描线101与所述第一栅金属层96同层同材料设置，使得所述扫描线101与所述第一栅金属层96能够在同一次构图工艺中形成；将所述数据线102与所述第一源漏金属层SD1同层同材料设置，使得所述数据线102与所述第一源漏金属层SD1能够在同一次构图工艺中形成；将所述第一电源层与所述第二栅金属层同层97同材料设置，使得所述第一电源层与所述第二栅金属层97同层能够在同一次构图工艺中形成；将所述第二电源层与所述第二源漏金属层SD2同层同材料设置，使得所述第二电源层与所述第二源漏金属层SD2能够在同一次构图工艺中形成；将所述第一导电连接部23与所述第一源漏金属层SD1同层同材料设置，使得所述第一导电连接部23与所述第一源漏金属层SD1能够在同一次构图工艺中形成；因此，上述实施例提供的显示基板采用上述设置方式时，能够有效简化显示基板的制作流程，降低显示基板的制作成本。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
如图8、图9、图13、图15、图16所示，在一些实施例中，所述电源线包括正电源线22，所述第一电源层包括第一正电源层220，所述第二电源层包括第二正电源层221；
所述第一正电源层220的至少部分沿第一方向延伸，所述第一正电源层220包括第一中间部分2202和两个第一端部2201，沿所述第一方向所述第一中间部分2202位于所述两个第一端部2201之间，所述两个第一端部2201关于所述显示基板中沿第二方向延伸的中轴线40对称，所述第二方向与所述第一方向相交；
如图8所示，所述第一端部2201在所述第二方向上的最大宽度，小于所述第一中间部分2202在所述第二方向上的最大宽度。
示例性的，所述电源线包括正电源线22，所述正电源线22用于传输正电源信号VDD。所述第一电源层包括第一正电源层220，所述第二电源层包括第二正电源层221，所述第一正电源层220与所述第二正电源层221耦接。
示例性的，所述第一正电源层220包括第一中间部分2202和两个第一端部2201，所述第一中间部分2202和两个第一端部2201形成为一体结构。
示例性的，所述第一中间部分2202在所述第二方向的宽度均匀或者不均匀。
示例性的，所述第一中间部分2202关于所述显示基板中沿第二方向延伸的中轴线40对称，所述两个第一端部2201关于所述显示基板中沿第二方向延伸的中轴线40对称。
上述实施例提供的显示基板中，通过设置所述第一正电源层220包括所述第一中间部分2202和所述两个第一端部2201，有效降低了所述第一正电源层220的布局难度，保证了所述正电源线22传输信号的均一性和稳定性。
如图13所示，在一些实施例中，所述第一端部2201包括第一目标部分2201a，所述第一目标部分2201a在所述第二方向上具有第一宽度D1，沿远离所述第一中间部分2202的方向所述第一宽度D1逐渐变大。
示例性的，所述第一宽度D1的取值范围在71微米至157微米之间，可以包括端点值。
上述实施例提供的显示基板中，通过设置所述第一端部2201包括第一目标部分2201a，不仅保证了所述第一正电源层220与所述第二正电源层221之间很好的连接性能，而且有效降低了所述第一正电源层220的布局难度，保证了所述正电源线22传输信号的均一性和稳定性。
如图8和图13所示，在一些实施例中，所述第一端部2201还包括第二目标部分2201b，沿所述第一方向所述第一目标部分2201a位于所述第二目标部分2201b与所述第一中间部分2202之间，所述第二目标部分2201b沿所述第二方向具有第二宽度D2，沿远离所述第一中间部分2202的方向所述第二宽度D2逐渐变小。
示例性的，所述第二目标部分2201b与所述第一目标部分2201a形成为一体结构。
示例性的，所述第二宽度D2的取值范围为小于或等于157微米。
上述实施例提供的显示基板中，通过设置所述第一端部2201还包括第二目标部分2201b，不仅保证了所述第一正电源层220与所述第二正电源层221之间很好的连接性能，而且有效降低了所述第一正电源层220的布局难度，保证了所述正电源线22传输信号的均一性和稳定性。
如图8所示，在一些实施例中，所述非显示区域20包括弯折区30，所述第一中间部分2202在所述显示基板的基底上的正投影，与所述弯折区30在所述基底上的正投影不交叠。
示例性的，所述非显示区域20包括弯折区30，所述弯折区30位于所述显示基板的下边框，所述弯折区30沿所述第一方向延伸。
上述设置所述第一中间部分2202在所述显示基板的基底上的正投影，与所述弯折区30在所述基底上的正投影不交叠，避免了所述第一中间部分2202发生弯折，从而很好的保证了所述第一中间部分2202的信赖性。
如图8、图9、图16和图18所示，在一些实施例中，所述第二正电源层221包括：第二中间部分2210和两个第二端部2211，沿所述第一方向所述第二中间部分2210的至少部分位于所述两个第二端部2211之间，所述两个第二端部2211关于所述显示基板中沿第二方向延伸的中轴线40对称；
所述第二端部2211在所述显示基板的基底上的正投影，与所述第一端部2201在所述基底上的正投影至少部分交叠；所述第二中间部分2210在所述基底上的正投影，与所述第一中间部分2202在所述基底上的正投影至少部分交叠。
示例性的，所述第二正电源层221包括第二中间部分2210和两个第二端部2211，所述第二中间部分2210和所述两个第二端部2211形成为一体结构。
示例性的，所述第二中间部分2210关于所述显示基板中沿第二方向延伸的中轴线40对称，所述两个第二端部2211关于所述显示基板中沿第二方向延伸的中轴线40对称。
上述实施例提供的显示基板中，通过设置所述第二正电源层221包括第二中间部分2210和两个第二端部2211，有效降低了所述第二正电源层221的布局难度，保证了所述正电源线22传输信号的均一性和稳定性。
如图16所示，在一些实施例中，所述第二端部2211包括第三目标部分2211a，所述第三目标部分2211a在所述第二方向上具有第三宽度D3，沿远离所述第二中间部分2210的方向所述第三宽度D3逐渐变大。
示例性的，所述第三宽度D3的取值范围在73微米至175微米之间，可以包括端点值。
上述实施例提供的显示基板中，通过设置所述第二端部2211包括第三目标部分2211a，不仅保证了所述第一正电源层220与所述第二正电源层221之间很好的连接性能，而且有效降低了所述第二正电源层221的布局难度，保证了所述正电源线22传输信号的均一性和稳定性。
如图16所示，在一些实施例中，所述第二端部2211还包括第四目标部分2211b，沿所述第一方向所述第三目标部分2211a位于所述第四目标部分2211b与所述第二中间部分2210之间，所述第四目标部分2211b在所述第二方向的宽度D4等于所述第三宽度D3的最大值。
示例性的，所述第四目标部分2211b在所述第二方向的宽度均一。
示例性的，宽度D4的取值包括175微米。示例性的，宽度D4的取值范围在170微米至180微米之间，可以包括端点值。
上述实施例提供的显示基板中，通过设置所述第二端部2211还包括所述第四目标部分2211b，所述第四目标部分2211b在所述第二方向的宽度等于所述第三宽度的最大值，不仅保证了所述第一正电源层220与所述第二正电源层221之间很好的连接性能，而且有效降低了所述第二正电源层221的布局难度，保证了所述正电源线22传输信号的均一性和稳定性。
如图16所示，在一些实施例中，所述第二端部2211还包括第五目标部分2211c，沿所述第一方向所述第四目标部分2211b位于所述第五目标部分2211c与所述第二中间部分2210之间，所述第五目标部分2211c在所述第二方向具有第五宽度D5，沿远离所述第二中间部分2210的方向所述第五宽度D5逐渐变小。
示例性的，所述第五宽度D5的取值范围在84微米至175微米之间，可以包括端点值。
示例性的，所述第五目标部分2211c，所述第四目标部分2211b和所述第三目标部分2211a形成为一体结构。
上述实施例提供的显示基板中，通过设置所述第二端部2211还包括所述第五目标部分2211c，所述第五目标部分2211c在所述第二方向具有第五宽度，沿远离所述第二中间部分2210的方向所述第五宽度逐渐变小，不仅保证了所述第一正电源层220与所述第二正电源层221之间很好的连接性能，而且有效降低了所述第二正电源层221的布局难度，保证了所述正电源线22传输信号的均一性和稳定性。
如图8所示，在一些实施例中，所述第二中间部分2210包括：
第一传输部2210a，所述第一传输部2210a的两端与所述两个第二端部2211一一对应耦接；
第二传输部2210b，所述第二传输部2210b的至少部分沿所述第一方向延伸，所述第一传输部2210a位于所述显示区域与所述第二传输部2210b之间；
至少一个连接部2210c，所述至少一个连接部2210c位于所述第一传输部2210a与所述第二传输部2210b之间，所述连接部2210c分别与所述第一传输部2210a和所述第二传输部2210b耦接；所述连接部2210c在所述显示基板的基底上的正投影，与所述显示基板的弯折区30在所述基底上的正投影至少部分交叠；
两个第一进线部2210d，所述第一进线部2210d的至少部分沿所述第二方向延伸，所述两个第一进线部2210d与所述第二传输部2210b的两端一一对应耦接。
示例性的，所述第一传输部2210a，所述第二传输部2210b，所述至少一个连接部2210c和所述两个第一进线部2210d形成为一体结构。
如图1所示，示例性的，所述显示基板的显示区域设置有网格状的电源层103，所述第一传输部2210a与所述网格状的电源层103耦接。
示例性的，所述第一传输部2210a在所述第一方向上的长度小于述第二传输部2210b在所述第一方向上的长度。
示例性的，所述第二中间部分2210包括多个连接部2210c，所述多个连接部2210c位于所述第一传输部2210a与所述第二传输部2210b之间，所述多个连接部2210c沿所述第一方向间隔排列，每个所述连接部2210c分别与所述第一传输部2210a和所述第二传输部2210b耦接。
示例性的，所述连接部2210c在所述显示基板的基底上的正投影，与所述显示基板的弯折区30在所述基底上的正投影至少部分交叠，所述连接部2210c的至少部分发生弯折。
示例性的，所述两个第一进线部2210d沿所述第二方向向远离所述显示区域的方向延伸。所述两个第一进线部2210d与驱动芯片耦接，接收所述驱动芯片提供的正电源信号。
将所述第二中间部分2210设置为上述结构，不仅保证了所述第二正电源层221在弯折时的信赖性，保证了第二正电源层221良好的传输性能，而且，有效降低了所述第二正电源层221的布局难度，保证了所述正电源线22传输信号的均一性和稳定性。
如图8、图9、图15、图17和图18所示，在一些实施例中，所述导电 连接部包括两个第一导电连接部23，所述两个第一导电连接部23关于所述中轴线40对称；所述第一导电连接部23分别与所述第一端部2201和所述第二端部2211耦接。
示例性的，所述两个第一导电连接部23与所述两个第一端部2201一一对应，所述两个第一导电连接部23与所述两个第二端部2211一一对应，所述第一导电连接部23分别与对应的所述第一端部2201和对应的所述第二端部2211耦接。
上述实施例提供的显示基板中，通过设置所述导电连接部包括所述两个第一导电连接部23，不仅保证了所述第一正电源层220和所述第二正电源层221良好的连接性能，而且有效降低了所述导电连接部的布局难度，保证了所述正电源线22传输信号的均一性和稳定性。
如图8、图9、图15、图17和图18所示，在一些实施例中，设置所述第一导电连接部23从所述显示基板的下边框延伸至显示基板的侧边框。
示例性的，所述两个第一导电连接部23中，一个第一导电连接部23从所述显示基板的下边框延伸至显示基板的左侧边框，另一个第一导电连接部23从所述显示基板的下边框延伸至显示基板的右侧边框。
示例性的，所述第一导电连接部23沿所述显示区域的拐角延伸，呈弧线状。
上述设置方式能够更好的降低所述正电源线22在传输电源信号时产生的压降。
如图9、图10、图14、图17至图20所示，在一些实施例中，所述第一导电连接部23在所述基底上的正投影与所述第一端部2201在所述显示基板的基底上的正投影具有第一交叠区，所述第一导电连接部23通过第一过孔Via1与所述第一端部2201耦接，所述第一过孔Via1在所述基底上的正投影与所述第一交叠区至少部分交叠；
所述第一导电连接部23在所述基底上的正投影与所述第二端部2211在所述基底上的正投影具有第二交叠区，所述第一导电连接部23通过第二过孔Via2与所述第二端部2211耦接，所述第二过孔Via2在所述基底上的正投影与所述第二交叠区至少部分交叠。
示例性的，所述第一过孔Via1贯穿所述层间绝缘层，所述第二过孔Via2贯穿所述钝化层和所述第一平坦层。示例性的，在所述显示基板不包括钝化层时，所述第二过孔Via2仅贯穿所述第一平坦层。
在一些实施例中，设置所述第一过孔Via1和所述第二过孔Via2沿所述第一方向排列。
上述设置方式有利于缩窄所述显示基板的下边框宽度。
如图9、图10、图14、图17至图20所示，在一些实施例中，所述显示基板还包括：
多个栅极驱动电路GOA和用于为所述多个栅极驱动电路GOA提供相应信号的多条第一信号线50；
所述第一过孔Via1在所述基底上的正投影，位于所述多条第一信号线50在所述基底上的正投影与所述多条数据扇出线在所述基底上的正投影之间；
所述第二过孔Via2在所述基底上的正投影与至少部分所述第一信号线50在所述基底上的正投影部分交叠。
示例性的，所述栅极驱动电路GOA布局在所述显示基板的左侧边框和右侧边框，所述多条第一信号线50布局在所述显示基板下边框的左侧和右侧。所述第一信号线50通过连接线与驱动芯片耦接。需要说明连接线位于图16中标记70的位置，该位置还可以设置有触控连接线等，用于传输触控信号。此外，如图6所示，所述栅极驱动电路GOA可以通过信号传输线B为扫描线提供扫描信号。
上述设置方式能够在避免所述正电源线22与所述第一信号线50之间发生短路的同时，有效缩窄所述显示基板的下边框宽度。
如图1、图8、图9、图13、图16、图17和图18所示，在一些实施例中，所述电源线包括负电源线24，所述第一电源层包括第一负电源层240，所述第二电源层包括第二负电源层241；
所述第一负电源层240包括两个第一负电源图形2401，所述两个第一负电源图形2401关于所述中轴线40对称，所述第一端部2201的至少部分位于所述显示区域与所述第一负电源图形2401之间。
示例性的，所述电源线包括负电源线24，所述负电源线24用于传输负 电源信号VSS。所述第一电源层包括第一负电源层240，所述第二电源层包括第二负电源层241，所述第一负电源层240与所述第二负电源层241耦接。
示例性的，所述第一负电源图形2401的至少部分在所述基底上的正投影，位于所述第一信号线50在所述基底上的正投影与所述第一端部2201在所述基底上的正投影之间。
上述设置所述第一负电源层240包括两个第一负电源图形2401，所述两个第一负电源图形2401关于所述中轴线40对称，有效降低了所述第一负电源层240的布局难度，保证了所述负电源线24传输信号的均一性和稳定性。
如图13所示，在一些实施例中，所述第一负电源图形2401包括第六目标部分2401a和第七目标部分2401b，所述第六目标部分2401a位于所述第七目标部分2401b与所述中轴线40之间，所述第六目标部分2401a在所述第二方向的宽度D6，大于所述第一端部2201在所述第二方向的最大宽度(如D2)。
示例性的，所述第六目标部分2401a和所述第七目标部分2401b形成为一体结构。
示例性的，所述第六目标部分2401a在所述第二方向的宽度均一或不均一。
示例性的，宽度D6的取值包括392微米。示例性的，宽度D6的取值范围包括387微米至397微米之间，可以包括端点值。
上述设置所述第六目标部分2401a在所述第二方向的宽度，大于所述第一端部2201在所述第二方向的最大宽度，很好的保证了负电源线24的传输性能，降低了负电源线24传输信号时产生的压降。
如图13所示，在一些实施例中，设置所述第七目标部分2401b在所述第二方向具有第七宽度D7，沿远离所述中轴线40的方向，所述第七宽度D7逐渐减小。
示例性的，所述第七宽度D7的取值范围在73微米至392微米之间，可以包括端点值。
上述设置方式，不仅保证了所述第一负电源层240与所述第二负电源层241之间很好的连接性能，而且有效降低了所述第一负电源图形2401的布局难度，保证了所述负电源线24传输信号的均一性和稳定性。
如图8和图16所示，在一些实施例中，所述第二负电源层241包括：
环形部2411，所述环形部2411围绕所述显示区域，所述环形部2411在所述显示基板的下边框具有开口，所述第二端部2211的至少部分位于所述环形部2411与所述显示区域之间；
两个第二进线部2412，所述第二进线部2412的至少部分沿所述第二方向延伸，所述两个第二进线部2412与所述环形部2411在开口处的两端一一对应耦接。
示例性的，所述环形部2411和所述两个第二进线部2412形成为一体结构。
示例性的，所述第二进线部2412的至少部分沿所述第二方向向远离所述显示区域的方向延伸。
示例性的，所述环形部2411和所述两个第二进线部2412均关于所述中轴线40对称。
示例性的，所述第二传输部2210b，所述第一进线部2210d和所述连接部2210c的至少部分均位于所述两个第二进线部2412之间。
示例性的，所述第二进线部2412远离所述显示区域的一端与驱动芯片耦接，接收所述驱动芯片提供的负电源信号。
将所述第二负电源层241设置为上述结构，不仅降低了所述负电源线24的布局难度，还保证了所述负电源线24对信号传输的稳定性和均一性。
如图8所示，在一些实施例中，设置所述第二进线部2412上设置有开孔2412a，所述开孔2412a在所述显示基板的基底上的正投影，与所述显示基板中弯折区30在所述基底上的正投影至少部分交叠。
上述设置方式能够更好的保证所述第二进线部2412在所述弯折区30发生弯折时的信赖性。
如图8、图9、图15、图17和图18所示，在一些实施例中，设置所述导电连接部包括第二导电连接部25，所述第二导电连接部25围绕所述显示区域，所述第二导电连接部25在所述显示基板的下边框具有开口；所述第二导电连接部25分别与所述第一负电源层240和所述第二负电源层241耦接。
示例性的，所述第二导电连接部25关于所述中轴线40对称。
上述设置方式很好的保证了所述第一负电源层240与所述第二负电源层241之间的连接性能，保证了所述负电源线24传输信号的均一性和稳定性。
如图9、图13至图20所示，在一些实施例中，所述第二导电连接部25包括：环绕部251，两个第一部分252和两个第二部分253；
所述显示区域的至少部分被所述环绕部251环绕，所述环绕部251的两个端部与所述两个第二部分253的第一端一一对应耦接，所述两个第二部分253的第二端与所述两个第一部分252一一对应耦接，所述两个第一部分252之间形成所述第二导电连接部25的开口；
如图9、图13、图15和图17所示，所述第一部分252的延伸方向与所述第一方向和所述第二方向均相交，所述第一部分252在所述显示基板的基底上的正投影，与所述第一负电源层240在所述基底上的正投影具有第三交叠区，所述第一部分252通过第三过孔Via3与所述第一负电源层240耦接，所述第三过孔Via3在所述基底上的正投影与所述第三交叠区至少部分交叠；
如图9、图15、图16、图18至图20所示，所述第二部分253的至少部分沿所述第一方向延伸，所述第二部分253在所述基底上的正投影和/或所述环绕部在所述基底上的正投影，与所述第二负电源层241在所述基底上的正投影具有第四交叠区，所述第二部分253和/或所述环绕部通过第四过孔Via4与所述第二负电源层241耦接，所述第四过孔Via4在所述基底上的正投影与所述第四交叠区至少部分交叠。
示例性的，所述环绕部251，所述两个第一部分252和所述两个第二部分253形成为一体结构。
示例性的，所述环绕部251关于所述中轴线40对称，所述两个第一部分252关于所述中轴线40对称，所述两个第二部分253关于所述中轴线40对称。
示例性的，所述环绕部251在所述显示基板的下边框不闭合，具有两个端部。示例性的，所述两个第一部分252之间不直接连接，在所述两个第一部分252之间形成所述第二导电连接部25的开口。
示例性的，所述第三过孔Via3贯穿所述层间绝缘层，所述第四过孔Via4贯穿所述钝化层和所述第一平坦层。示例性的，在所述显示基板不包括钝化 层时，所述第四过孔Via4仅贯穿所述第一平坦层。
示例性的，所述第四过孔Via4在所述基底上的正投影的至少部分沿所述第一方向延伸。示例性的，所述第四过孔Via4在所述基底上的正投影的至少部分沿所述显示基板的拐角区延伸。
将所述第二导电连接部25设置为上述结构，很好的保证了所述第一负电源层240与所述第二负电源层241之间的连接性能，保证了所述负电源线24传输信号的均一性和稳定性。
如图14所示，在一些实施例中，设置所述第三过孔Via3在所述基底上的正投影的延伸方向与所述第一方向和所述第二方向均相交。
上述设置方式，不仅有利于降低所述负电源线24和所述第二导电连接部25的布局难度，还能够很好的保证所述第一负电源层240和所述第二负电源层241之间的连接性能。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
上述实施例提供的显示基板中，通过设置所述多条数据扇出线包括多条第一数据扇出线210和多条第二数据扇出线211，所述第一数据扇出线210与所述扫描线101同层同材料设置，所述第二数据扇出线211与所述数据线102同层同材料设置；使得所述第一数据扇出线210与所述第二数据扇出线211异层设置，这样就可以通过缩短所述第一数据扇出线210在所述基底上的正投影与所述第二数据扇出线211在所述基底上的正投影之间的距离，来减小了所述多条数据扇出线整体占用的空间，缩小所述多条数据扇出线在第二方向上的整体宽度，从而有效缩窄了显示基板的下边框宽度，提升了显示基板形成的显示产品的竞争力。
因此，本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
本公开实施例还提供了一种显示基板的制作方法，所述制作方法用于制作上述实施例提供的显示基板，所述显示基板包括：显示区域和围绕所述显示区域的非显示区域20；所述制作方法包括：制作多条扫描线101，多条数 据线102和多条数据扇出线；
所述扫描线101的至少部分位于所述显示区域；
所述数据线102的至少部分位于所述显示区域；
所述数据扇出线的至少部分位于所述非显示区域20，所述数据扇出线与对应的数据线102耦接；所述多条数据扇出线包括多条第一数据扇出线210和多条第二数据扇出线211，所述第一数据扇出线210与所述扫描线101同层同材料设置，所述第二数据扇出线211与所述数据线102同层同材料设置。
示例性的，所述多条数据扇出线包括多条第一数据扇出线210和多条第二数据扇出线211，所述多条第一数据线102均匀分布，所述多条第二数据线102均匀分布。将所述第一数据扇出线210与所述扫描线101同层同材料设置，使得所述第一数据扇出线210与所述扫描线101能够在同一次构图工艺中形成。同样的，将所述第二数据扇出线211与所述数据线102同层同材料设置，使得所述第二数据扇出线211与所述数据线102能够在同一次构图工艺中形成，这样能够更好的简化显示基板的制作流程，降低显示基板的制作成本。
采用本公开实施例提供的制作方法制作的显示基板中，通过设置所述多条数据扇出线包括多条第一数据扇出线210和多条第二数据扇出线211，所述第一数据扇出线210与所述扫描线101同层同材料设置，所述第二数据扇出线211与所述数据线102同层同材料设置；使得所述第一数据扇出线210与所述第二数据扇出线211异层设置，这样就可以通过缩短所述第一数据扇出线210在所述基底上的正投影与所述第二数据扇出线211在所述基底上的正投影之间的距离，来减小了所述多条数据扇出线整体占用的空间，缩小所述多条数据扇出线在第二方向上的整体宽度，从而有效缩窄了显示基板的下边框宽度，提升了显示基板形成的显示产品的竞争力。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实 施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (31)

  1. 一种显示基板，包括：显示区域和围绕所述显示区域的非显示区域；所述显示基板还包括：
    多条扫描线，所述扫描线的至少部分位于所述显示区域；
    多条数据线，所述数据线的至少部分位于所述显示区域；
    多条数据扇出线，所述数据扇出线的至少部分位于所述非显示区域，所述数据扇出线与对应的数据线耦接；所述多条数据扇出线包括多条第一数据扇出线和多条第二数据扇出线，所述第一数据扇出线与所述扫描线同层同材料设置，所述第二数据扇出线与所述数据线同层同材料设置。
  2. 根据权利要求1所述的显示基板，其中，至少部分所述第一数据扇出线在所述显示基板的基底上的正投影，与所述第二数据扇出线在所述基底上的正投影至少部分交叠。
  3. 根据权利要求2所述的显示基板，其中，至少部分所述第一数据扇出线包括第一线段，至少部分所述第二数据扇出线包括第二线段，所述第一线段在所述基底上的正投影与所述第二线段在所述基底上的正投影重合。
  4. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：
    电源线，所述电源线包括第一电源层，在垂直于所述显示基板的基底的方向上，所述第一电源层的至少部分位于所述第一数据扇出线和所述第二数据扇出线之间。
  5. 根据权利要求4所述的显示基板，其中，所述电源线还包括第二电源层，所述第二电源层与所述第一电源层耦接；
    所述第一电源层的至少部分和所述第二电源层的至少部分均位于所述非显示区域，所述第一电源层与所述第二电源层层叠设置，所述第一电源层的至少部分位于所述第二电源层与所述显示基板的基底之间。
  6. 根据权利要求5所述的显示基板，其中，在垂直于所述显示基板的基底的方向上，所述第二数据扇出线的至少部分位于所述第一电源层和所述第二电源层之间。
  7. 根据权利要求5或6所述的显示基板，其中，所述显示基板还包括导 电连接部，所述导电连接部的至少部分位于所述第一电源层和所述第二电源层之间，所述导电连接部分别与所述第一电源层和所述第二电源层耦接。
  8. 根据权利要求7所述的显示基板，其中，所述显示基板包括沿远离所述显示基板的基底的方向依次层叠设置的第一栅金属层，第二栅金属层，第一源漏金属层和第二源漏金属层；
    所述扫描线与所述第一栅金属层同层同材料设置，所述数据线与所述第一源漏金属层同层同材料设置；
    所述第一电源层与所述第二栅金属层同层同材料设置，所述第二电源层与所述第二源漏金属层同层同材料设置，所述导电连接部与所述第一源漏金属层同层同材料设置。
  9. 根据权利要求7所述的显示基板，其中，所述电源线包括正电源线，所述第一电源层包括第一正电源层，所述第二电源层包括第二正电源层；
    所述第一正电源层的至少部分沿第一方向延伸，所述第一正电源层包括第一中间部分和两个第一端部，沿所述第一方向所述第一中间部分位于所述两个第一端部之间，所述两个第一端部关于所述显示基板中沿第二方向延伸的中轴线对称，所述第二方向与所述第一方向相交；
    所述第一端部在所述第二方向上的最大宽度，小于所述第一中间部分在所述第二方向上的最大宽度。
  10. 根据权利要求9所述的显示基板，其中，所述第一端部包括第一目标部分，所述第一目标部分在所述第二方向上具有第一宽度，沿远离所述第一中间部分的方向所述第一宽度逐渐变大。
  11. 根据权利要求10所述的显示基板，其中，所述第一端部还包括第二目标部分，沿所述第一方向所述第一目标部分位于所述第二目标部分与所述第一中间部分之间，所述第二目标部分沿所述第二方向具有第二宽度，沿远离所述第一中间部分的方向所述第二宽度逐渐变小。
  12. 根据权利要求9所述的显示基板，其中，所述非显示区域包括弯折区，所述第一中间部分在所述显示基板的基底上的正投影，与所述弯折区在所述基底上的正投影不交叠。
  13. 根据权利要求9所述的显示基板，其中，所述第二正电源层包括： 第二中间部分和两个第二端部，沿所述第一方向所述第二中间部分的至少部分位于所述两个第二端部之间，所述两个第二端部关于所述显示基板中沿第二方向延伸的中轴线对称；
    所述第二端部在所述显示基板的基底上的正投影，与所述第一端部在所述基底上的正投影至少部分交叠；所述第二中间部分在所述基底上的正投影，与所述第一中间部分在所述基底上的正投影至少部分交叠。
  14. 根据权利要求13所述的显示基板，其中，所述第二端部包括第三目标部分，所述第三目标部分在所述第二方向上具有第三宽度，沿远离所述第二中间部分的方向所述第三宽度逐渐变大。
  15. 根据权利要求14所述的显示基板，其中，所述第二端部还包括第四目标部分，沿所述第一方向所述第三目标部分位于所述第四目标部分与所述第二中间部分之间，所述第四目标部分在所述第二方向的宽度等于所述第三宽度的最大值。
  16. 根据权利要求15所述的显示基板，其中，所述第二端部还包括第五目标部分，沿所述第一方向所述第四目标部分位于所述第五目标部分与所述第二中间部分之间，所述第五目标部分在所述第二方向具有第五宽度，沿远离所述第二中间部分的方向所述第五宽度逐渐变小。
  17. 根据权利要求13所述的显示基板，其中，所述第二中间部分包括：
    第一传输部，所述第一传输部的两端与所述两个第二端部一一对应耦接；
    第二传输部，所述第二传输部的至少部分沿所述第一方向延伸，所述第一传输部位于所述显示区域与所述第二传输部之间；
    至少一个连接部，所述至少一个连接部位于所述第一传输部与所述第二传输部之间，所述连接部分别与所述第一传输部和所述第二传输部耦接；所述连接部在所述显示基板的基底上的正投影，与所述显示基板的弯折区在所述基底上的正投影至少部分交叠；
    两个第一进线部，所述第一进线部的至少部分沿所述第二方向延伸，所述两个第一进线部与所述第二传输部的两端一一对应耦接。
  18. 根据权利要求13所述的显示基板，其中，所述导电连接部包括两个第一导电连接部，所述两个第一导电连接部关于所述中轴线对称；所述第一 导电连接部分别与所述第一端部和所述第二端部耦接。
  19. 根据权利要求18所述的显示基板，其中，所述第一导电连接部从所述显示基板的下边框延伸至显示基板的侧边框。
  20. 根据权利要求18所述的显示基板，其中，所述第一导电连接部在所述基底上的正投影与所述第一端部在所述显示基板的基底上的正投影具有第一交叠区，所述第一导电连接部通过第一过孔与所述第一端部耦接，所述第一过孔在所述基底上的正投影与所述第一交叠区至少部分交叠；
    所述第一导电连接部在所述基底上的正投影与所述第二端部在所述基底上的正投影具有第二交叠区，所述第一导电连接部通过第二过孔与所述第二端部耦接，所述第二过孔在所述基底上的正投影与所述第二交叠区至少部分交叠。
  21. 根据权利要求20所述的显示基板，其中，所述第一过孔和所述第二过孔沿所述第一方向排列。
  22. 根据权利要求20所述的显示基板，其中，所述显示基板还包括：
    多个栅极驱动电路和用于为所述多个栅极驱动电路提供相应信号的多条第一信号线；
    所述第一过孔在所述基底上的正投影，位于所述多条第一信号线在所述基底上的正投影与所述多条数据扇出线在所述基底上的正投影之间；
    所述第二过孔在所述基底上的正投影与至少部分所述第一信号线在所述基底上的正投影部分交叠。
  23. 根据权利要求13所述的显示基板，其中，所述电源线包括负电源线，所述第一电源层包括第一负电源层，所述第二电源层包括第二负电源层；
    所述第一负电源层包括两个第一负电源图形，所述两个第一负电源图形关于所述中轴线对称，所述第一端部的至少部分位于所述显示区域与所述第一负电源图形之间。
  24. 根据权利要求23所述的显示基板，其中，所述第一负电源图形包括第六目标部分和第七目标部分，所述第六目标部分位于所述第七目标部分与所述中轴线之间，所述第六目标部分在所述第二方向的宽度，大于所述第一端部在所述第二方向的最大宽度。
  25. 根据权利要求24所述的显示基板，其中，所述第七目标部分在所述第二方向具有第七宽度，沿远离所述中轴线的方向，所述第七宽度逐渐减小。
  26. 根据权利要求23所述的显示基板，其中，所述第二负电源层包括：
    环形部，所述环形部围绕所述显示区域，所述环形部在所述显示基板的下边框具有开口，所述第二端部的至少部分位于所述环形部与所述显示区域之间；
    两个第二进线部，所述第二进线部的至少部分沿所述第二方向延伸，所述两个第二进线部与所述环形部在开口处的两端一一对应耦接。
  27. 根据权利要求26所述的显示基板，其中，所述第二进线部上设置有开孔，所述开孔在所述显示基板的基底上的正投影，与所述显示基板中弯折区在所述基底上的正投影至少部分交叠。
  28. 根据权利要求23所述的显示基板，其中，所述导电连接部包括第二导电连接部，所述第二导电连接部围绕所述显示区域，所述第二导电连接部在所述显示基板的下边框具有开口；所述第二导电连接部分别与所述第一负电源层和所述第二负电源层耦接。
  29. 根据权利要求28所述的显示基板，其中，所述第二导电连接部包括：环绕部，两个第一部分和两个第二部分；
    所述显示区域的至少部分被所述环绕部环绕，所述环绕部的两个端部与所述两个第二部分的第一端一一对应耦接，所述两个第二部分的第二端与所述两个第一部分一一对应耦接，所述两个第一部分之间形成所述第二导电连接部的开口；
    所述第一部分的延伸方向与所述第一方向和所述第二方向均相交，所述第一部分在所述显示基板的基底上的正投影，与所述第一负电源层在所述基底上的正投影具有第三交叠区，所述第一部分通过第三过孔与所述第一负电源层耦接，所述第三过孔在所述基底上的正投影与所述第三交叠区至少部分交叠；
    所述第二部分的至少部分沿所述第一方向延伸，所述第二部分在所述基底上的正投影和/或所述环绕部在所述基底上的正投影，与所述第二负电源层在所述基底上的正投影具有第四交叠区，所述第二部分和/或所述环绕部通过 第四过孔与所述第二负电源层耦接，所述第四过孔在所述基底上的正投影与所述第四交叠区至少部分交叠。
  30. 根据权利要求29所述的显示基板，其中，所述第三过孔在所述基底上的正投影的延伸方向与所述第一方向和所述第二方向均相交。
  31. 一种显示装置，包括如权利要求1～30中任一项所述的显示基板。
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CN109407436A (zh) * 2018-12-10 2019-03-01 武汉华星光电半导体显示技术有限公司 阵列基板
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CN210349260U (zh) * 2019-11-15 2020-04-17 京东方科技集团股份有限公司 显示面板、显示装置
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