WO2023159868A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023159868A1
WO2023159868A1 PCT/CN2022/108255 CN2022108255W WO2023159868A1 WO 2023159868 A1 WO2023159868 A1 WO 2023159868A1 CN 2022108255 W CN2022108255 W CN 2022108255W WO 2023159868 A1 WO2023159868 A1 WO 2023159868A1
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WIPO (PCT)
Prior art keywords
circuit
display panel
sub
pixel
display area
Prior art date
Application number
PCT/CN2022/108255
Other languages
English (en)
French (fr)
Inventor
楼均辉
吴勇
葛林
何泽尚
Original Assignee
昆山国显光电有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to KR1020237037497A priority Critical patent/KR20230158123A/ko
Priority to JP2023566880A priority patent/JP2024516254A/ja
Publication of WO2023159868A1 publication Critical patent/WO2023159868A1/zh
Priority to US18/474,304 priority patent/US20240016015A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/128—Active-matrix OLED [AMOLED] displays comprising two independent displays, e.g. for emitting information from two major sides of the display
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components

Definitions

  • the present application relates to the display field, in particular to a display panel and a display device.
  • the pixel circuits used to drive the sub-pixels in the bezel display area or the light-transmitting display area are arranged in other areas, which leads to problems such as uneven display effects of the display panel.
  • Embodiments of the present application provide a display panel and a display device, aiming at improving the display effect of the display panel.
  • the embodiment of the first aspect of the present application provides a display panel.
  • the display panel has a first display area and a second display area.
  • the display panel includes: sub-pixels, including a first sub-pixel located in the first display area and a sub-pixel located in the second display area.
  • the pixel driving circuit, located in the second display area, the pixel driving circuit includes a first circuit and a second circuit, the first circuit is used to drive the first sub-pixel, and the second circuit is used to drive the second sub-pixel
  • the connection line includes a first connection line for connecting the first circuit and the first sub-pixel; wherein at least part of the first connection line extends along the first direction and is located on one side of the first circuit.
  • the embodiment of the second aspect of the present application provides a display device, which includes the display panel of any one of the above-mentioned embodiments of the first aspect.
  • the display panel includes sub-pixels, a pixel driving circuit and connection lines.
  • the sub-pixels include a first sub-pixel located in the first display area and a second sub-pixel located in the second display area, the first sub-pixel is used to realize the display in the first display area, and the second sub-pixel is used to realize the display in the second display area display.
  • the pixel driving circuit includes a first circuit and a second circuit located in the second display area. The first circuit is used to drive the first sub-pixels located in the first display area, so the pixel driving circuit used to drive the sub-pixels in the first display area is located in the second display area.
  • the first display area is a frame display area
  • other driving circuits can be arranged in the first display area, so as to realize setting of a narrow frame of the display panel.
  • the first display area is a light-transmitting display area
  • the light transmittance of the first display area can be increased, so that the photosensitive component can obtain light information through the first display area, which is beneficial to the under-screen integration of the photosensitive component.
  • connection line includes a first connection line for connecting the first circuit and the first sub-pixel, at least part of the first connection line extends along the first direction and is located on one side of the first circuit, so that the first connection line is located at the first circuit pre- In the remaining space, at least part of the first connection line will not overlap with the first circuit, which can reduce the mutual influence between the first connection line and the first circuit, and improve the display effect of the display panel.
  • Fig. 1 is a schematic structural diagram of a display panel provided by an embodiment of the first aspect of the present application
  • Fig. 2 is a partial enlarged view of the arrangement structure of the sub-pixels of the Q area display pattern in Fig. 1;
  • FIG. 3 is a partial enlarged view of some pixel driving circuits of the Q-region display panel in FIG. 1;
  • Fig. 4 is the sectional view of B-B place among Fig. 2;
  • Fig. 5 is a partial enlarged structural schematic diagram of Fig. 3;
  • Fig. 6 is a sectional view of B-B in another embodiment in Fig. 2;
  • FIG. 7 is a partial enlarged view of some pixel driving circuits of the Q-region display panel in FIG. 1 in another embodiment
  • Fig. 8 is a partially enlarged view of the arrangement structure of the sub-pixels of the Q area display pattern in Fig. 1 in another embodiment
  • Fig. 9 is a schematic structural diagram of a display device provided by an embodiment of the second aspect of the present application.
  • Fig. 10 is a cross-sectional view at C-C in Fig. 9 .
  • a light-transmitting display area may be provided on the above-mentioned electronic device, and a photosensitive component may be arranged on the back of the light-transmitting display area, so as to realize full-screen display of the electronic device while ensuring normal operation of the photosensitive component.
  • the driving circuit in the light-transmitting area is often arranged in the non-light-transmitting area.
  • the connection line between the driving circuit and the sub-pixel is usually above the driving circuit layer.
  • there is a parasitic capacitance between the driving circuit and the connection line and the parasitic capacitance will affect the transmission of signals in the connection line or the driving circuit.
  • a shift register is arranged in the border display area of the display panel, and pixel circuits for driving sub-pixels in the border display area are arranged in other areas, which leads to problems such as uneven display effect of the display panel.
  • An embodiment of the present application provides a display panel, and the display panel may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel.
  • OLED Organic Light Emitting Diode
  • FIG. 1 shows a schematic top view of a display panel provided by an embodiment of the first aspect of the present application.
  • the display panel 100 has a first display area AA1 , a second display area AA2 and a non-display area NA surrounding the first display area AA1 and the second display area AA2 .
  • the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2.
  • the second display area AA2 is arranged around at least part of the first display area AA1.
  • the first display area AA1 may also be arranged around at least part of the second display area AA2.
  • the light transmittance of the first display area AA1 is greater than or equal to 15%.
  • the light transmittance of some functional film layers of the display panel 100 in this embodiment is greater than 80%. Even the light transmittance of at least some of the functional film layers is greater than 90%.
  • the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2, so that the display panel 100 can integrate photosensitive components on the back of the first display area AA1 to realize, for example, a camera.
  • the photosensitive components are integrated under the screen, and at the same time, the first display area AA1 can display images, which increases the display area of the display panel 100 and realizes a full-screen design of the display device.
  • the first display area AA1 is a light-transmitting display area
  • the number of the first display area AA1 and the second display area AA2 is 1 One, used to realize the under-screen integration of photosensitive components or to realize fingerprint recognition.
  • the number of the first display area AA1 is two, one of the first display area AA1 is used to realize the under-screen integration of photosensitive components, and the other first display area AA1 is used for Realize fingerprint recognition.
  • driving components such as a shift register can also be set in the first display area AA1, and then can The frame size of the display panel 100 is reduced to realize a narrow frame design.
  • the first display area AA1 may also include both a light-transmitting display area and a frame display area, which can not only realize the under-screen integration of photosensitive components, but also realize the design of a narrow frame.
  • FIG. 2 is a partially enlarged schematic diagram of the arrangement structure of sub-pixels 101 in the Q region in FIG. 1
  • FIG. 3 is a partially enlarged schematic diagram of a part of the pixel driving circuit in the Q region in FIG.
  • the display panel 100 includes a sub-pixel 101 , a pixel driving circuit 102 and a connection line 103 .
  • the sub-pixel 101 includes a first sub-pixel 110 located in the first display area AA1 and a second sub-pixel 120 located in the second display area AA2; the pixel driving circuit 102 is located in the second display area AA2, and the pixel driving circuit 102 includes a first circuit 210 and the second circuit 220, the first circuit 210 is used to drive the first sub-pixel 110, and the second circuit 220 is used to drive the second sub-pixel 120;
  • the first connection line 310 At least a part of the first connecting wires 310 extends along the first direction X and is located on one side of the first circuit 210 along the second direction Y.
  • the first display area AA1 can be a light-transmitting display area or a frame display area.
  • the first display area AA1 is a light-transmitting display area, that is, the second display area AA2 surrounds at least part of the first display area AA1 as an example. illustrate.
  • the first sub-pixel 110 in the first display area A1 is reserved in FIG. 3 . Moreover, only part of the pixel driving circuit 102 in the Q region is shown in FIG. 3 .
  • the display panel 100 includes a sub-pixel 101 , a pixel driving circuit 102 and a connection line 103 .
  • the sub-pixel 101 includes a first sub-pixel 110 located in the first display area AA1 and a second sub-pixel 120 located in the second display area AA2, the first sub-pixel 110 is used to realize the display of the first display area AA1, and the second sub-pixel 120 is used to realize the display of the second display area AA2.
  • the pixel driving circuit 102 includes a first circuit 210 and a second circuit 220 located in the second display area AA2. The first circuit 210 is used to drive the first sub-pixel 110 located in the first display area AA1 to emit light.
  • the pixel driving circuit 102 used to drive the sub-pixel 101 in the first display area AA1 is located in the second display area AA2, which can improve the performance of the second display area AA2.
  • the light transmittance of the first display area AA1 enables the photosensitive element 200 to obtain light information through the first display area AA1 , which is beneficial to the off-screen integration of the photosensitive element 200 .
  • the connection line 103 includes a first connection line 310 for connecting the first circuit 210 and the first sub-pixel 110 , the first connection line 310 is formed extending along the first direction X, at least part of the first connection line 310 is located on the first circuit 210 On one side of the second direction Y, on the one hand, the first connection line 310 is located in the space reserved between the first circuits 210, and on the other hand, the overlapping area between the first connection line 310 and the first circuit 210 can be reduced , to improve the interaction between the first connection line 310 and the first circuit 210 . Therefore, the embodiment of the present application can not only realize the under-screen integration of the photosensitive module, but also improve the mutual influence between the first connection line 310 and the first circuit 210 .
  • the first circuit 210 is compressed in the second direction Y.
  • the space size of the first circuit 210 can be reduced;
  • the arrangement of the wires 310 leaves enough space and reduces the overlapping area of the first connection wires 310 and the first circuit 210 .
  • FIG. 4 is a cross-sectional view at B-B in FIG. 2 .
  • the display panel 100 further includes: a first signal line layer 105, the first signal line layer 105 includes a first signal line 510, at least part of the first connection line 310 is located on the first signal line layer 105,
  • the first signal line 510 includes at least one of a data line, a scan line, a power line, a voltage reference line and a ground line.
  • the first signal line 510 may be prepared by photolithography.
  • steps such as film formation, coating, exposure, development, etching and stripping need to be performed sequentially, and a mask plate is also required to expose the photoresist layer in the exposure step. deal with.
  • the first connection line 310 is located on the first signal line layer 105, and the first signal line 510 includes at least one of a data line, a scan line, a power line, a voltage reference line and a ground line , so that at least part of the first connecting line 310 can be prepared synchronously with at least one of the data line, scanning line, power line, voltage reference line and grounding line, without increasing the manufacturing process steps to prepare the first connecting line 310, and will not increase
  • the number and manufacturing process of the mask can simplify the manufacturing process of the display panel 100 and improve the manufacturing efficiency of the display panel 100 .
  • the display panel 100 may further include a substrate 11 , an array substrate layer 12 and a pixel definition layer 13 disposed on the substrate.
  • the pixel driving circuit 102 can be disposed on the array substrate layer 12 .
  • Both the first circuit 210 and the second circuit 220 may include thin film transistors (Thin Film Transistor; TFT).
  • the array substrate layer 12 may also include structures such as capacitors.
  • the pixel definition layer 13 includes pixel openings, and the pixel openings include a first pixel opening K1 located in the first display area AA1 and a second pixel opening K2 located in the second display area AA2.
  • the first sub-pixel 110 includes a first electrode 111, a second electrode 112 and a first light emitting structure 113 located between the first electrode 111 and the second electrode 112, and the first light emitting structure 113 is located in the first pixel opening K1.
  • the first electrode 111 is connected to the TFT of the first circuit 210 through the first connection line 310 .
  • the second sub-pixel 120 includes a third electrode 121 , a fourth electrode 122 and a second light emitting structure 123 located between the third electrode 121 and the fourth electrode 122 , and the second light emitting structure 123 is located in the second pixel opening K2 .
  • Supporting pillars 14 may also be arranged on the pixel definition layer 13 .
  • the first electrode 111 and the third electrode 121 may be pixel electrodes, and the second electrode 112 and the fourth electrode 122 may be interconnected to form whole-surface electrodes.
  • FIG. 5 is a partially enlarged structural diagram of FIG. 3
  • FIG. 6 is a partially enlarged schematic structural diagram of B-B in FIG. 2 in another embodiment.
  • the display panel 100 further includes a light-transmitting signal line layer 106
  • the first connection line 310 includes a first segment 311 located in the first display area AA1 and a second segment located in the second display area AA2.
  • Segment 312 the first segment 311 is located at the transparent signal line layer 106
  • the second segment 312 is located at the first signal line layer 105 and/or the transparent signal line layer 106 .
  • the first segment 311 of the first connection line 310 is located in the light-transmitting signal line layer 106 , which can further increase the light transmittance of the first display area AA1 .
  • the second segment 312 can be prepared synchronously with the first signal line 510 .
  • the second segment 311 is located in the transparent signal line layer 106 of the first display area AA1.
  • the second segment 312 can be prepared synchronously with the light-transmitting signal line layer 106 , without increasing the manufacturing process steps to prepare the first connection line 310 , and without increasing the number of masks and the manufacturing process.
  • first segment 311 and the second segment 312 are located on the transparent signal line layer 106, the first segment 311 and the second segment 312 do not need to be connected through via holes, which can simplify the shape of the first connecting line 310 , improving the stability of signal transmission on the first connection line 310 .
  • connection line 103 further includes a second connection line 320 for connecting the second circuit 220 and the second sub-pixel 120 .
  • FIG. 7 is a partially enlarged structural schematic diagram of the Q region in FIG. 1 in another example.
  • a first circuit 210 and a second circuits 220 form a first circuit block 200a, where a is an integer greater than 1, and at least part of the first circuit block extending along the first direction X
  • a connection line 310 is located at one side of the first circuit block 200 a in the second direction Y where the first circuit 210 connected thereto is located.
  • 7 shows the first circuit block 200a with a dotted line box, the first circuit 210 and the second circuit 220 located in the same dotted line box 200a belong to the same first circuit block 200a, and the dotted line box does not constitute the structure of the display panel 100 of the present application. on the limit.
  • the first connection line 310 is located on one side of the first circuit block 200a in the second direction Y where the first circuit 210 connected thereto is located, so that the first connection line 310 is located on the first circuit block In the space reserved by 200a, at least part of the first connection line 310 does not overlap with the first circuit block 200a, which can prevent the formation of parasitic capacitance between the first connection line 310 and the first circuit block 200a and affect signal transmission.
  • a number of adjacent second sub-pixels 120 form a pixel block 100a, and a number of second circuits 220 in the first circuit block 200a are used to drive the same There are a number of second sub-pixels 120 in the pixel block 100a, the number of the first circuit block 200a is multiple, and the relative position between each first circuit block 200a and the pixel block 100a driven by the first circuit block 200a same.
  • the pixel block 100a driven by the first circuit block 200a is the pixel block 100a where a adjacent second sub-pixels 120 driven by a second circuits 220 in the first circuit block 200a are located.
  • the pixel block 100a is illustrated by a dotted line frame, and the second sub-pixels 120 whose area in the dotted line frame accounts for more than 50% of its own area are the second sub-pixels 120 included in the pixel block 100a indicated by the dotted line frame.
  • the dotted frame is not enough to limit the structure of the display panel in the embodiment of the present application.
  • each first circuit block 200a and the pixel block 100a driven by the first circuit block 200a means that, for example, the display panel 100 includes a plurality of first circuit blocks 200a, and each first circuit block 200a is connected to The pixel blocks 100a driven by them are displaced in the thickness direction, and the displacement size and direction of each first circuit block 200a are the same as those of the pixel blocks 100a driven by the first circuit blocks 200a.
  • the relative position between each first circuit block 200a and the pixel block 100a driven by the first circuit block 200a is the same, on the one hand, the second circuit in the first circuit block 200a can be reduced 220 and the second sub-pixel 120 driven by it, reduce the length of wiring between the second circuit 220 and the second sub-pixel 120 driven by it, improve the stability of signal transmission, and reduce the
  • the small first circuit 210 is disposed on the influence of the first circuit block 200 a on the second circuit 220 .
  • the relative positions between the second circuits 220 and the second sub-pixels 120 driven by them are the same, so that the lengths of the wires connecting the second circuits 220 and the second sub-pixels 120 are all the same. Therefore, the rate of signal transmission between multiple sets of second circuits 220 and the second sub-pixels 120 in the second display area AA2 can tend to be consistent, and the display uniformity of the second display area AA2 can be further improved.
  • each second circuit 220 and the second sub-pixel 120 driven by it is the same, which also makes the mutual influence between each second circuit 220 and the second sub-pixel 120 driven by it tend to be consistent,
  • the environment where the plurality of second sub-pixels 120 are located tends to be consistent, which can further improve the display uniformity of the second display area AA2.
  • the distance between each first circuit block 200a and the pixel block 100a driven by the first circuit block 200a can be reduced by reducing the size of the first circuit 210 and the second circuit 220.
  • the relative positions between them are the same.
  • setting the dummy area 230 can make the layout of the second circuit block 200b consistent with the layout of the first circuit block 200a as much as possible, improve the display difference, and further improve the display uniformity of the second display area AA2.
  • At least part of the second circuit block 200b is provided with a dummy wire 104 on one side of the second direction Y, and the dummy wire 104 extends along the first direction X.
  • the dummy wires are shown schematically in dashed lines in FIG. 7 .
  • the display unevenness of the second display area AA2 caused by the arranging of the first connection wire 310 can be improved.
  • the dummy wire 104 is located on one side of the second circuit block 200b in the second direction Y, so that overlapping of the dummy wire 104 and the second circuit block 200b can be avoided.
  • the plurality of second circuit blocks 200b includes a second circuit block 200b located on one side of the first circuit block 200a in the second direction Y (for example, the second circuit block located below the first circuit block 200a in FIG. 7 Block 200b), the dummy wire 104 includes a first dummy wire 410, and the first dummy wire 410 is located on one side of the first connection line 310 in the second direction Y (for example, in FIG.
  • the first dummy wire 410 is located on the first connection line 310 below), that is, the first dummy wire 410 is located on at least one side of the first circuit block 200a in the second direction Y, and the relative position of the second circuit block 200b and its corresponding first dummy wire 410 is the same as that of the first circuit block 200a
  • the relative position of the corresponding first connecting line is the same.
  • the first dummy wire 410 corresponding to the second circuit block 200b is the first dummy wire 410 located on one side of the second circuit block 200b in the second direction Y.
  • the first connection line 310 corresponding to the first circuit block 200a is the first connection line 310 connected to the first circuit 210 in the first circuit block 200a, and the first connection line 310 is located in the second direction Y of the first circuit block 200a side.
  • the consistency of the routing density in the second direction Y can be improved, and the second display can be improved.
  • the relative position of the second circuit block 200b and its corresponding first dummy wire 410 is the same as the relative position of the first circuit block 200a and its corresponding first connecting line 310, for example as shown in FIG.
  • the first dummy wire 410 corresponding to the second circuit block 200b is also located below the second circuit block 200b, which can avoid the gap between the second circuit block 200b and the first circuit block 200a.
  • multiple rows of second circuit blocks 200b are provided on at least one side of the first circuit block 200a in the second direction Y, and each row of second circuit blocks 200b is provided with first connecting lines on the same side in the second direction Y 410.
  • the row direction is the first direction X, and multiple rows of second circuit blocks 200b are arranged along the second direction Y.
  • one side of the second circuit block 200b in each row is provided with a first dummy wire 410, which can further improve the consistency of the wiring density in the second direction Y, and improve the second display area AA2. display uniformity.
  • the dummy wire 104 includes a second dummy wire 420 , and the second dummy wire 420 is located on at least one side of the first connection wire 310 in the first direction X.
  • the uniformity of the trace density in the first direction X in the second display area AA2 can be improved, and the display uniformity of the second display area AA2 can be improved.
  • a second circuits 220 in the second circuit block 200b are used to drive a second sub-pixels 120 in the same pixel block 100a, each second circuit block 200b and the second circuit block driven by the second circuit block 200b
  • the relative positions between the pixel blocks 100a are the same, so as to reduce the influence of setting the dummy region 230 in the second circuit block 200b on the connection between the second circuit 220 and the second sub-pixel 120, and reduce the connection between the second circuit block 200b and the sub-pixels 120.
  • the distance between the pixel blocks 100a driven by it that is, the distance between the second circuit 210 in the second circuit block 200b and the second sub-pixel 120 driven by it is reduced, the length of wiring is reduced, and the stability of signal transmission is improved. sex.
  • the size of the orthographic projection of the first circuit 210 is the same as the size of the dummy area 230, which can further improve the display uniformity of the second display area AA2.
  • the first signal wire 510 of the display panel 100 includes a first wire extending along the first direction X and a second wire extending along the second direction Y.
  • the first wires are, for example, scan lines, light emission control signal lines, voltage reference lines and the like.
  • the second wires are, for example, data signal wires, power wires and the like.
  • the distance between the first wires connected to a circuit 210 may be a dimension L of the first circuit 210 in the second direction Y.
  • the distance from the center of the first wire connected to the previous first circuit 210 in the second direction Y to the center of the first wire connected to the next first circuit 210 in the second direction Y may be Dimension L in two directions Y.
  • the second wire connected to the previous first circuit 210 is connected to the next first circuit 210.
  • the distance between the second wires connected to the circuit 210 may be a dimension H of the first circuit 210 in the first direction X.
  • the distance between the center of the second wire connected to the previous first circuit 210 in the first direction X and the center of the second wire connected to the next first circuit 210 in the first direction X is Dimension H in the first direction X.
  • the center of the first wire connected to the first circuit 210 in the second direction Y is connected to the first wire connected to the second circuit 220 at the second A distance between centers in the direction Y may be a size L of the first circuit 210 in the second direction.
  • the distance between the second wire connected to the first circuit 210 and the second wire connected to the second circuit 220 may be Dimension H in one direction X.
  • the orthographic dimension of the first circuit 210 may be H ⁇ L.
  • the number of first circuits 210 in the first circuit block 200a is the same as the number of dummy areas 230 in the second circuit block 200b, so that the display effect of the dummy area 230 and the area where the first circuits 210 are located are the same, which can further improve the The uniformity displayed by the second display area AA2.
  • the size of the orthographic projection of the first circuit block 200a and the size of the orthographic projection of the second circuit block 200b are the same, then the a-th of the first circuit block 200a and the second circuit block 200b
  • the size of the two circuits 220 is the same, which can further improve the display uniformity of the second display area AA2.
  • the orthographic projection size of the first circuit block 200a is the sum of the orthographic projection dimensions of the first circuit 210 and a second circuits 220 in the first circuit block 200a.
  • the orthographic projection size of the second circuit block 200b is the sum of the orthographic projection sizes of the virtual area 230 in the second circuit block 200b and a second circuits 220 .
  • the center of the first wire connected to the first circuit 210 in the second direction Y is connected to the first wire connected to the second circuit 220 at the second
  • the distance between centers in the direction Y may be a dimension L′ of the second circuit 210 in the second direction Y.
  • the distance between the second wire connected to the first circuit 210 and the second wire connected to the second circuit 220 may be A dimension H' in one direction X.
  • the orthographic projection size of the second circuit 220 is L' ⁇ H'.
  • the relative positional relationship between the first circuit 210 and the second circuit 220 in the first circuit block 200a is the same as the relative positional relationship between the dummy area 230 and the second circuit 220 in the second circuit block 200b, further simplifying pixel driving
  • the layout and preparation of the circuit 102 can further improve the display uniformity of the second display area AA2.
  • a virtual circuit is set in the virtual area 230, and the structure of the virtual circuit is the same as that of the first circuit 210, so that the display effect of the area where the virtual area 230 and the first circuit 210 are located is the same, and the second display area AA2 can be further improved. Uniformity of display.
  • the second display area AA2 includes a main display area and a transition area, the transition area is located between the main display area and the first display area AA1, the first circuit 210 is located in the transition area, and the virtual area 230 is located in the main display area, so that the second The distance between the first circuit 210 and the first display area AA1 is small, which can shorten the wiring length between the first circuit 210 and the first sub-pixel 110 .
  • connection lines 103 connected to the sub-pixels 101 of the same color are made of the same material.
  • the sub-pixels 101 of the same color use the connecting wire 103 of the same material, which can reduce the difference in pixel brightness caused by the different resistance of the connecting wire 103, and can further improve the display uniformity of the second display area AA2. sex.
  • the first sub-pixels 110 and the second sub-pixels 120 are arranged in rows and columns along the first direction X and the second direction Y, and the first circuit 210 and the second circuit 220 are arranged along the first direction X Arranged in rows and columns with the second direction Y, at least part of the first circuit 210 and the second circuit 220 are arranged side by side and in the same row along the first direction X, and the first circuit 210 and the second circuit 220 in the same row are used for The first sub-pixel 110 and the second sub-pixel 120 of the same row are driven.
  • the first circuit 210 is connected to the first sub-pixel 110 through the first connection line 310
  • the second circuit 220 is connected to the second sub-pixel 120 through the second connection line 320.
  • the shape of the scanning line can be simplified, so that the scanning line can drive the first sub-pixel and the second sub-pixel in the same row, Improve the stability of signal transmission.
  • the first display area AA1 is arranged symmetrically with respect to the first axis of symmetry M, the first axis of symmetry M extends along the second direction Y, and the first axis of symmetry M passes through the center of the first display area AA1,
  • a plurality of first circuits 210 are distributed symmetrically about the first symmetry axis M, and the first circuits 210 and the first sub-pixels 110 driven by them are located on the same side of the first symmetry axis M, so as to further reduce the number of first circuits 210 and their The distance between the driven first sub-pixels 110 reduces the wiring distance.
  • FIG. 9 is a schematic structural diagram of a display device provided by an embodiment of the present application
  • FIG. 10 is a cross-sectional view at D-D in FIG. 9 .
  • the display device provided in the embodiment of the second aspect of the present application may include the display panel 100 in any of the foregoing implementation manners.
  • the display panel 100 may be the display panel 100 of one of the above-mentioned embodiments, and the display panel 100 has a first display area AA1 and a second display area AA2.
  • the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2. That is, when the first display area AA1 is a light-transmitting display area, the display device further includes a photosensitive element 200 located in the first display area AA1 .
  • the display panel 100 includes a first surface S1 and a second surface S2 opposite to each other, wherein the first surface S1 is a display surface.
  • the display device further includes a photosensitive component 200 located on the second surface S2 side of the display panel 100 , and the photosensitive component 200 corresponds to the position of the first display area AA1 .
  • the light transmittance of the first display area AA1 is greater than the light transmittance of the second display area AA2, so that the display panel 100 can integrate the photosensitive component 200 on the back of the first display area AA1 to realize, for example, an image
  • the photosensitive component 200 of the acquisition device is integrated under the screen, and at the same time, the first display area AA1 can display images, thereby increasing the display area of the display panel 100 and realizing a full-screen design of the display device.
  • the photosensitive component 200 may be an image acquisition device for acquiring external image information.
  • the photosensitive component 200 is a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image acquisition device, and in some other embodiments, the photosensitive component 200 can also be a charge-coupled device (Charge-coupled Device, CCD) Image acquisition devices and other forms of image acquisition devices.
  • CMOS Complementary Metal Oxide Semiconductor
  • CCD Charge-coupled Device
  • the photosensitive component 200 may not be limited to an image acquisition device, for example, in some embodiments, the photosensitive component 200 may also be an infrared sensor, a proximity sensor, an infrared lens, a flood sensing element, an ambient light sensor, and a dot matrix projection light sensors such as
  • the display device can also integrate other components on the second surface S2 of the display panel 100 , such as an earpiece, a speaker, and the like.
  • driving components such as shift registers can also be set in the first display area AA1 , which can further reduce the size of the frame of the display panel 100 and realize the narrow frame design of the display device.
  • the first display area AA1 may also include both a light-transmitting display area and a frame display area, which can not only realize the under-screen integration of photosensitive components, but also realize the design of a narrow frame.

Abstract

本申请公开了一种显示面板及显示装置，显示面板包括子像素、像素驱动电路和连接线。子像素包括位于第一显示区的第一子像素和位于第二显示区的第二子像素。像素驱动电路包括位于第二显示区的第一电路和第二电路。第一电路用于驱动位于第一显示区的第一子像素，第一电路位于第二显示区，能够提高第一显示区的透光率，有利于感光组件的屏下集成。连接线包括第一连接线，至少部分第一连接线沿第一方向延伸且位于第一电路的一侧，简化了第一连接线的布置，使得第一连接线位于第一电路之间预留的空间内，能够降低第一连接线和第一电路之间的相互影响。

Description

显示面板及显示装置
相关申请的交叉引用
本申请要求享有于2022年02月28日提交的名称为“显示面板及显示装置”的中国专利申请第202210193420.0号的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请涉及显示领域，具体涉及一种显示面板及显示装置。
背景技术
随着电子设备的快速发展，用户对屏占比的要求越来越高，使得电子设备的全面屏显示受到业界越来越多的关注。
为了实现感光组件的屏下集成或者为了实现窄边框，会将用于驱动边框显示区或透光显示区内子像素的像素电路设置于其他区域，这就导致显示面板的显示效果不均一等问题。
发明内容
本申请实施例提供一种显示面板及显示装置，目的在于提高显示面板的显示效果。
本申请第一方面的实施例提供一种显示面板，显示面板具有第一显示区和第二显示区，显示面板包括：子像素，包括位于第一显示区的第一子像素和位于第二显示区的第二子像素；像素驱动电路，位于第二显示区，像素驱动电路包括第一电路和第二电路，第一电路用于驱动第一子像素，第二电路用于驱动第二子像素；连接线，包括用于连接第一电路和第一子像素的第一连接线；其中，至少部分第一连接线沿第一方向延伸且位于第一电路的一侧。
本申请第二方面的实施例提供一种显示装置，其包括上述任一第一方面实施例的显示面板。
在本申请第一方面实施例提供的显示面板中，显示面板包括子像素、像素驱动电路和连接线。子像素包括位于第一显示区的第一子像素和位于第二显示区的第二子像素，第一子像素用于实现第一显示区的显示，第二子像素用于实现第二显示区的显示。像素驱动电路包括位于第二显示区的第一电路和第二电路。第一电路用于驱动位于第一显示区的第一子像素，因此用于驱动第一显示区的子像素的像素驱动电路位于第二显示区。当第一显示区为边框显示区时，使得第一显示区内能够布置其他驱动电路，实现显示面板的窄边框设置。当第一显示区为透光显示区时，能够提高第一显示区的透光率，使得感光组件能够透过第一显示区获取光线信息，有利于感光组件的屏下集成。连接线包括用于连接第一电路和第一子像素的第一连接线，至少部分第一连接线沿第一方向延伸且位于第一电路的一侧，使得第一连接线位于第一电路预留的空间内，至少部分第一连接线不会与第一电路交叠，能够减少第一连接线和第一电路之间的相互影响，提高显示面板的显示效果。
附图说明
通过阅读以下参照附图对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显，其中，相同或相似的附图标记表示相同或相似的特征，附图并未按照实际的比例绘制。
图1本申请第一方面实施例提供的一种显示面板的结构示意图；
图2是图1中Q区域显示面案的子像素的排布结构的局部放大图；
图3是图1中Q区域显示面板的部分像素驱动电路的局部放大图；
图4是图2中B-B处的剖视图；
图5是图3的局部放大结构示意图；
图6是图2中B-B处在另一实施例中的剖视图；
图7是另一实施例中图1中Q区域显示面板的部分像素驱动电路的局部放大图；
图8是另一实施例中图1中Q区域显示面案的子像素的排布结构的局部放大图
图9是本申请第二方面实施例提供的一种显示装置的结构示意图；
图10是图9中C-C处的剖视图。
具体施方式
下面将详细描述本申请的各个方面的特征和示例性实施例，为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及具体实施例，对本申请进行进一步详细描述。应理解，此处所描述的具体实施例仅被配置为解释本申请，并不被配置为限定本申请。对于本领域技术人员来说，本申请可以在不需要这些具体细节中的一些细节的情况下实施。下面对实施例的描述仅仅是为了通过示出本申请的示例来提供对本申请更好的理解。
在诸如手机和平板电脑等电子设备上，需要在显示面板的一侧集成诸如前置摄像头、红外光传感器、接近光传感器等感光组件。在一些实施例中，可以在上述电子设备上设置透光显示区，将感光组件设置在透光显示区背面，在保证感光组件正常工作的情况下，实现电子设备的全面屏显示。
为提高透光显示区的透光率，往往将透光区域的驱动电路设置于非透光区域，现有技术中，驱动电路和子像素之间的连接线通常是在驱动电路层的上方，这就导致驱动电路和连接线之间存在寄生电容，寄生电容会影响连接线或驱动电路内信号的传输。
在还一些相关的实施例中，为了实现显示装置的窄边框设计，需要尽量压缩封装区域的宽度和电路的尺寸，从而对封装的可靠性、抗跌能力、电路的驱动能力都造成了不利的影响。在一些相关技术中，显示面板的边框显示区内设置有移位寄存器，而用于驱动边框显示区内子像素的像素电路设置于其他区域，这就导致显示面板的显示效果不均一等问题。
为解决上述问题，本申请实施例提供了一种显示面板及显示装置，以下将结合附图对显示面板及显示装置的各实施例进行说明。
本申请实施例提供一种显示面板，该显示面板可以是有机发光二极管(Organic Light Emitting Diode，OLED)显示面板。
图1示出本申请第一方面实施例提供一种显示面板的俯视示意图。
如图1所示，显示面板100具有第一显示区AA1、第二显示区AA2以及围绕第一显示区AA1、第二显示区AA2的非显示区NA。可选的，第一显示区AA1的透光率大于第二显示区AA2的透光率。可选的，第二显示区AA2环绕至少部分第一显示区AA1设置。在另一些实施例中，第一显示区AA1还可以环绕至少部分第二显示区AA2设置。
本文中，当第二显示区AA2环绕至少部分第一显示区AA1设置，第一显示区AA1为透光显示区时，优选第一显示区AA1的透光率大于或等于15％。为确保第一显示区AA1的透光率大于15％，甚至大于40％，甚至具有更高的透光率，本实施例中显示面板100的部分功能膜层的透光率均大于80％，甚至至少部分功能膜层的透光率均大于90％。
根据本申请实施例的显示面板100，第一显示区AA1的透光率大于第二显示区AA2的透光率，使得显示面板100在第一显示区AA1的背面可以集成感光组件，实现例如摄像头的感光组件的屏下集成，同时第一显示区AA1能够显示画面，提高显示面板100的显示面积，实现显示装置的全面屏设计。
当第一显示区AA1为透光显示区时，第一显示区AA1和第二显示区AA2的个数设置方式有多种，例如第一显示区AA1和第二显示区AA2的个数为1个，用于实现感光组件的屏下集成或者用于实现指纹识别。或者，在另一些可选的实施例中，第一显示区AA1的个数为两个，其中一第一显示区AA1用于实现感光组件的屏下集成，另一第一显示区AA1用于实现指纹识别。
可选的，当第一显示区AA1环绕至少部分第二显示区AA2设置，即第一显示区AA1为边框显示区时，第一显示区AA1内还可以设置移位寄存器等驱动部件，进而能够减小显示面板100的边框尺寸，实现窄边框的设计。
可选的，第一显示区AA1还可以既包括透光显示区也包括边框显示区，既能够实现感光组件的屏下集成，也能够实现窄边框的设计。
请一并参阅图1至图3，图2是图1中Q区域的子像素101排布结构 的局部放大示意图，图3是图1中Q区域部分像素驱动电路的局部放大示意图示意图。
如图1至图3所示，本申请实施例提供的显示面板100包括子像素101、像素驱动电路102和连接线103。子像素101包括位于第一显示区AA1的第一子像素110和位于第二显示区AA2的第二子像素120；像素驱动电路102位于第二显示区AA2，像素驱动电路102包括第一电路210和第二电路220，第一电路210用于驱动第一子像素110，第二电路220用于驱动第二子像素120；连接线103包括用于连接第一电路210和第一子像素110的第一连接线310。至少部分第一连接线310沿第一方向X延伸且位于第一电路210在第二方向Y上的一侧。
第一显示区AA1可以为透光显示区或者边框显示区，本申请实施例以第一显示区AA1为透光显示区，即第二显示区AA2环绕至少部分第一显示区AA1为例进行举例说明。
为了更好的展示第一电路210和第一子像素110的连接关系，图3中保留了第一显示区A1的第一子像素110。且图3中仅展示了Q区域的部分像素驱动电路102。
在本申请第一方面实施例提供的显示面板100中，显示面板100包括子像素101、像素驱动电路102和连接线103。子像素101包括位于第一显示区AA1的第一子像素110和位于第二显示区AA2的第二子像素120，第一子像素110用于实现第一显示区AA1的显示，第二子像素120用于实现第二显示区AA2的显示。像素驱动电路102包括位于第二显示区AA2的第一电路210和第二电路220。第一电路210用于驱动位于第一显示区AA1的第一子像素110发光，因此，用于驱动第一显示区AA1的子像素101的像素驱动电路102位于第二显示区AA2，能够提高第一显示区AA1的透光率，使得感光组件200能够透过第一显示区AA1获取光线信息，有利于感光组件200的屏下集成。
连接线103包括用于连接第一电路210和第一子像素110的第一连接线310，第一连接线310沿第一方向X延伸成型，至少部分第一连接线310位于第一电路210在第二方向Y上的一侧，一方面使得第一连接线310位 于第一电路210之间预留的空间内，另一方面能够减小第一连接线310与第一电路210的交叠面积，改善第一连接线310和第一电路210之间的相互影响。因此，本申请实施例不仅能够实现感光模组的屏下集成，还能够改善第一连接线310和第一电路210之间的相互影响。
此外，本申请实施例提供的显示面板100中，在第二方向Y上对第一电路210进行了压缩，一方面能够减小第一电路210的空间尺寸，另一方面还能够为第一连接线310的布置留有足够的空间，并减小第一连接线310与第一电路210的交叠面积。
请参阅图4，图4是图2中B-B处的剖视图。
在一些可选的实施例中，显示面板100还包括：第一信号线层105，第一信号线层105包括第一信号线510，至少部分第一连接线310位于第一信号线层105，第一信号线510包括数据线、扫描线、电源线、电压参考线和接地线中的至少一者。
可选的，第一信号线510可以选用光刻蚀的制备工艺进行制备。利用光刻蚀工艺制备第一信号线510时，需要依次进行成膜、涂布、曝光、显影、刻蚀和剥离等步骤，在曝光步骤中还需要使用掩膜板对光刻胶层进行曝光处理。
在这些可选的实施例中，至少部分第一连接线310位于第一信号线层105，第一信号线510包括数据线、扫描线、电源线、电压参考线和接地线中的至少一者，使得至少部分第一连接线310能够与数据线、扫描线、电源线、电压参考线和接地线中的至少一者同步制备，无需增加制备工艺步骤制备第一连接线310，也不会增加掩膜板的数量和制程，能够简化显示面板100的制备工艺并提高显示面板100的制备效率。
请继续参阅图3和图4，显示面板100还可以包括衬底11、设置于衬底的阵列基板层12和像素定义层13。像素驱动电路102可以设置于阵列基板层12。第一电路210和第二电路220均可以包括薄膜晶体管(Thin Film Transistor；TFT)。阵列基板层12还可以包括电容等结构。像素定义层13包括像素开口，像素开口包括位于第一显示区AA1的第一像素开口K1和位于第二显示区AA2的第二像素开口K2。第一子像素110包括第一电极 111、第二电极112和位于第一电极111和第二电极112之间的第一发光结构113，第一发光结构113位于第一像素开口K1。第一电极111通过第一连接线310连接于第一电路210的TFT。第二子像素120包括第三电极121、第四电极122和位于第三电极121和第四电极122之间的第二发光结构123，第二发光结构123位于第二像素开口K2。像素定义层13上还可以设置支撑柱14。第一电极111和第三电极121可以为像素电极，第二电极112和第四电极122可以互连为整面电极。
请一并参阅图4至图6，图5是图3的局部放大结构示意图，图6是图2中B-B处在另一实施例中的局部放大结构示意图。
在一些可选的实施例中，显示面板100还包括透光信号线层106，第一连接线310包括位于第一显示区AA1的第一分段311和位于第二显示区AA2的第二分段312，第一分段311位于透光信号线层106，第二分段312位于第一信号线层105和/或透光信号线层106。
在这些可选的实施例中，第一连接线310的第一分段311位于透光信号线层106，能够进一步提高第一显示区AA1的透光率。当第二分段312位于第二显示区AA2的第一信号线层105时，第二分段312可以与第一信号线510同步制备。当第二分段311位于第一显示区AA1的透光信号线层106时。第二分段312可以与透光信号线层106同步制备，无需增加制备工艺步骤制备第一连接线310，也不会增加掩膜版的数量和制程。此外，当第一分段311和第二分段312均位于透光信号线层106时，第一分段311和第二分段312无需通过过孔连接，能够简化第一连接线310的形状，提高第一连接线310上信号传输的稳定性。
可选的，参见图4所示，连接线103还包括用于连接第二电路220和第二子像素120的第二连接线320。
请参阅图7，图7是另一种示例中图1中Q区域的局部放大结构示意图。
如图7所示，在一些可选的实施例中，第一电路210和a个第二电路220形成第一电路块200a，a为大于1的整数，沿第一方向X延伸的至少部分第一连接线310位于与其连接的第一电路210所在的第一电路块200a在 第二方向Y上的一侧。图7中以虚线框示意出了第一电路块200a，位于同一虚线框200a内的第一电路210和第二电路220属于同一第一电路块200a，虚线框并不构成对本申请显示面板100结构上的限定。
在这些可选的实施例中，第一连接线310位于与其连接的第一电路210所在的第一电路块200a在第二方向Y上的一侧，使得第一连接线310位于第一电路块200a预留的空间内，至少部分第一连接线310不会与第一电路块200a交叠，能够避免第一连接线310和第一电路块200a之间形成寄生电容而影响信号传输。
请继续参阅图7和图8，在一些可选的实施例中，a个相邻的第二子像素120形成像素块100a，第一电路块200a内的a个第二电路220用于驱动同一像素块100a内的a个第二子像素120，第一电路块200a的个数为多个，且各第一电路块200a和被该第一电路块200a驱动的像素块100a之间的相对位置相同。
被第一电路块200a驱动的像素块100a即被第一电路块200a内a个第二电路220驱动的a个相邻的第二子像素120所在的像素块100a。
图8中以虚线框示意出了像素块100a，在虚线框内面积占自身面积比例超过50％的第二子像素120为该虚线框表示的像素块100a所包括的第二子像素120。虚线框并不够成对本申请实施例显示面板结构上的限定。
各第一电路块200a和被该第一电路块200a驱动的像素块100a之间的相对位置相同是指：例如，显示面板100包括多个第一电路块200a，每个第一电路块200a与被其驱动的像素块100a在厚度方向上错位，各第一电路块200a与被该第一电路块200a驱动的像素块100a的错位尺寸和错位方向相同。
在这些可选的实施例中，各第一电路块200a和被该第一电路块200a驱动的像素块100a之间的相对位置相同，一方面能够减小第一电路块200a内的第二电路220和被其驱动的第二子像素120之间的间距，减小第二电路220和被其驱动的第二子像素120之间布线的长度，提高信号传输的稳定性，另一方面能够减小第一电路210设置于第一电路块200a对第二电路220的影响。
可选的，各第二电路220和被其驱动的第二子像素120之间的相对位置相同，使得连接第二电路220和第二子像素120之间的走线长度均相同。因此第二显示区AA2中多组第二电路220和第二子像素120之间的信号传输的速率能够趋于一致，能够进一步提高第二显示区AA2显示的均一性。
此外，各第二电路220和被其驱动的第二子像素120之间的相对位置相同，还使得各第二电路220和被其驱动的第二子像素120之间的相互影响趋于一致，多个第二子像素120所处的环境趋于一致，能够进一步提高第二显示区AA2显示的均一性。
当第一电路210设置于第一电路块200a内时，可以通过缩小第一电路210和第二电路220的尺寸使得各第一电路块200a和被该第一电路块200a驱动的像素块100a之间的相对位置相同。
像素驱动电路102的排布方式有多种，在一些可选的实施例中，请继续参阅图7，像素驱动电路102还包括虚拟区域230，虚拟区域230和a个第二电路220形成第二电路块200b。
在这些实施例中，设置虚拟区域230能够使得第二电路块200b的布置与第一电路块200a的布置尽量保持一致，改善显示差异，能够进一步改善第二显示区AA2显示的均一性。
在一些可选的实施例中，请继续参阅图7，至少部分第二电路块200b在第二方向Y的一侧设置有虚拟导线104，虚拟导线104沿第一方向X延伸成型。图7中以虚线示意出了虚拟导线。
在这些可选的实施例中，通过设置虚拟导线104，能够改善由于设置第一连接线310导致的第二显示区AA2的显示不均。且虚拟导线104位于第二电路块200b在第二方向Y上的一侧，能够避免虚拟导线104与第二电路块200b交叠。
虚拟导线104的设置方式有多种，不同位置的第二电路块200b可以对应于不同的虚拟导线104设置。
在一些实施例中，多个第二电路块200b包括位于第一电路块200a在第二方向Y上一侧的第二电路块200b(例如图7中位于第一电路块200a下方的第二电路块200b)，虚拟导线104包括第一虚拟导线410，第一虚拟 导线410位于第一连接线310在第二方向Y上的一侧(例如图7中第一虚拟导线410位于第一连接线310下方)，即第一虚拟导线410位于第一电路块200a在第二方向Y上的至少一侧，且第二电路块200b和与其对应的第一虚拟导线410的相对位置与第一电路块200a和与其对应的第一连接线的相对位置相同。
第二电路块200b对应的第一虚拟导线410即位于第二电路块200b在第二方向Y上的一侧的第一虚拟导线410。第一电路块200a对应的第一连接线310即第一电路块200a内第一电路210连接的第一连接线310，且第一连接线310位于第一电路块200a在第二方向Y上的一侧。
在这些可选的实施例中，通过在第二电路块200b在第二方向Y上的一侧设置第一虚拟导线410，能够提高第二方向Y上走线密度的一致性，提高第二显示区AA2在第二方向Y上显示的均一性。第二电路块200b和与其对应的第一虚拟导线410的相对位置与第一电路块200a和与其对应的第一连接线310的相对位置相同，例如如图7所示，当第一连接线310位于其对应的第一电路块200a的下方时，第二电路块200b对应的第一虚拟导线410也位于该第二电路块200b的下方，能够避免第二电路块200b和第一电路块200a之间同时存在第一虚拟导线410和第一连接线310导致的走线密度不均的问题。
可选的，第一电路块200a在第二方向Y上的至少一侧设置有多行第二电路块200b，各行第二电路块200b在第二方向Y上的同侧设置有第一连接线410。其中，行方向为第一方向X，多行第二电路块200b沿第二方向Y排布。
在这些可选的实施例中，每一行的第二电路块200b的一侧均设置有第一虚拟导线410，能够进一步提高第二方向Y上的走线密度一致性，提高第二显示区AA2的显示均一性。
可选的，虚拟导线104包括第二虚拟导线420，第二虚拟导线420位于第一连接线310在第一方向X上的至少一侧。可以改善第二显示区AA2内第一方向X上走线密度的一致性，提高第二显示区AA2的显示均一性。
可选的，第二电路块200b内的a个第二电路220用于驱动同一像素块 100a内的a个第二子像素120，各第二电路块200b和被该第二电路块200b驱动的像素块100a之间的相对位置相同，以减小在第二电路块200b内设置虚拟区域230对第二电路220和第二子像素120之间连接的影响，减小第二电路块200b和被其驱动的像素块100a之间的间距，即减小第二电路块200b内第二电路210和被其驱动的第二子像素120之间的间距，减小布线的长度，提高信号传输的稳定性。
可选的，沿显示面板的厚度方向Z，第一电路210的正投影尺寸和虚拟区域230的尺寸相同，能够进一步改善第二显示区AA2显示的均一性。
可选的，显示面板100的第一信号线510包括沿第一方向X延伸的第一导线和沿第二方向Y延伸的第二导线。第一导线例如为扫描线、发光控制信号线、电压参考线等。第二导线例如为数据信号线、电源线等。
假设两个第一电路210沿第二方向Y相邻设置，那么在沿第二方向Y上相邻的两个第一电路210中，上一第一电路210连接的第一导线至下一第一电路210连接的第一导线的距离可以为第一电路210在第二方向Y上的尺寸L。例如上一第一电路210连接的第一导线在第二方向Y上的中心至下一第一电路210连接的第一导线在第二方向Y上的中心的距离可以为第一电路210在第二方向Y上的尺寸L。
假设两个第一电路210沿第一方向X相邻设置，在沿第一方向X上相邻的两个第一电路210中，前一第一电路210连接的第二导线至后一第一电路210连接的第二导线之间的距离可以为第一电路210在第一方向X上的尺寸H。例如前一第一电路210连接的第二导线在第一方向X上的中心至后一第一电路210连接的第二导线在第一方向X上的中心之间的距离为第一电路210在第一方向X上的尺寸H。
当第一电路210和第二电路220沿第二方向Y相邻设置，且第一电路210位于第一电路210连接的第一导线和第二电路220连接的第一导线之间时，那么在沿第二方向Y上相邻的第一电路210和第二电路220中，第一电路210连接的第一导线在第二方向Y上的中心至第二电路220连接的第一导线在第二方向Y上的中心之间的距离可以为第一电路210在第二方向上的尺寸L。
当第一电路210和第二电路220沿第一方向X相邻设置，且第一电路210位于第一电路210连接的第二导线和第二电路220连接的第二导线之间时，在沿第一方向X上相邻的第一电路210和第二电路220中，第一电路210连接的第二导线至第二电路220连接的第二导线之间的距离可以为第一电路210在第一方向X上的尺寸H。
沿显示面板的厚度方向Z，第一电路210的正投影尺寸可以为H×L。
可选的，第一电路块200a内第一电路210的数量和第二电路块200b内虚拟区域230的数量相同，使得虚拟区域230和第一电路210所在区域的显示效果相同，能够进一步改善第二显示区AA2显示的均一性。
可选的，沿显示面板的厚度方向Z，第一电路块200a的正投影尺寸和第二电路块200b的正投影尺寸相同，那么第一电路块200a和第二电路块200b中的a个第二电路220的尺寸相同，能够进一步改善第二显示区AA2显示的均一性。
第一电路块200a的正投影尺寸为第一电路块200a内第一电路210和a个第二电路220的正投影尺寸之和。第二电路块200b的正投影尺寸为第二电路块200b内虚拟区域230和a个第二电路220的正投影尺寸之和。
当第一电路210和第二电路220沿第二方向Y相邻设置，且第二电路210位于第一电路210连接的第一导线和第二电路220连接的第一导线之间时，那么在沿第二方向Y上相邻的第一电路210和第二电路220中，第一电路210连接的第一导线在第二方向Y上的中心至第二电路220连接的第一导线在第二方向Y上的中心之间的距离可以为第二电路210在第二方向Y上的尺寸L’。
当第一电路210和第二电路220沿第一方向X相邻设置，且第二电路210位于第一电路210连接的第二导线和第二电路220连接的第二导线之间时，在沿第一方向X上相邻的第一电路210和第二电路220中，第一电路210连接的第二导线至第二电路220连接的第二导线之间的距离可以为第二电路210在第一方向X上的尺寸H’。
沿显示面板的厚度方向Z，第二电路220的正投影尺寸为L’×H’。
可选的，第一电路块200a内的第一电路210和第二电路220的相对位 置关系与第二电路块200b内的虚拟区域230和第二电路220的相对位置关系相同，进一步简化像素驱动电路102的布局和制备，能够进一步改善第二显示区AA2显示的均一性。
可选的，虚拟区域230内设置有虚拟电路，虚拟电路的结构与第一电路210的结构相同，使得虚拟区域230和第一电路210所在区域的显示效果相同，能够进一步改善第二显示区AA2显示的均一性。
可选的，第二显示区AA2包括主显示区和过渡区，过渡区位于主显示区和第一显示区AA1之间，第一电路210位于过渡区，虚拟区域230位于主显示区，使得第一电路210与第一显示区AA1之间的间距较小，能够减短第一电路210与第一子像素110之间的布线长度。
在一些可选的实施例中，相同颜色的子像素101连接的连接线103使用相同的材料制备成型。
在这些可选的实施例中，同种颜色的子像素101采用同种材料的连接线103，可以降低连接线103电阻不同导致的像素亮度的差异，能够进一步改善第二显示区AA2显示的均一性。
在一些可选的实施例中，第一子像素110和第二子像素120沿第一方向X和第二方向Y成行成列排布，第一电路210和第二电路220沿第一方向X和第二方向Y成行成列排布，至少部分第一电路210和第二电路220沿第一方向X并排设置并位于同一行，且位于同一行的第一电路210和第二电路220用于驱动同行的第一子像素110和第二子像素120。
在这些可选的实施例中，第一电路210通过第一连接线310和第一子像素110连接，第二电路220通过第二连接线320和第二子像素120连接，当同一行的第一电路210和第二电路220和其驱动的第一子像素110和第二子像素120同行设置时，能够简化扫描线的形状，便于扫描线驱动同行的第一子像素和第二子像素，提高信号传输的稳定性。
在一些可选的实施例中，第一显示区AA1关于第一对称轴线M对称设置，第一对称轴线M沿第二方向Y延伸，且第一对称轴线M经过第一显示区AA1的中心，多个第一电路210关于第一对称轴线M对称分布，且第一电路210和被其驱动的第一子像素110位于第一对称轴线M的同侧， 以进一步减小第一电路210和其驱动的第一子像素110之间的距离，减小走线距离。
请参阅图9和图10，图9是本申请实施例提供的一种显示装置的结构示意图，图10是图9中D-D处的剖视图。
本申请第二方面实施例提供的显示装置可以包括上述任一实施方式的显示面板100。本实施例的显示装置中，显示面板100可以是上述其中一个实施例的显示面板100，显示面板100具有第一显示区AA1以及第二显示区AA2。
可选的，第一显示区AA1的透光率大于第二显示区AA2的透光率。即第一显示区AA1为透光显示区时，显示装置还包括位于第一显示区AA1的感光组件200。
显示面板100包括相对的第一表面S1和第二表面S2，其中第一表面S1为显示面。显示装置还包括感光组件200，该感光组件200位于显示面板100的第二表面S2侧，感光组件200与第一显示区AA1位置对应。
根据本发明实施例的显示装置，第一显示区AA1的透光率大于第二显示区AA2的透光率，使得显示面板100在第一显示区AA1的背面可以集成感光组件200，实现例如图像采集装置的感光组件200的屏下集成，同时第一显示区AA1能够显示画面，提高显示面板100的显示面积，实现显示装置的全面屏设计。
感光组件200可以是图像采集装置，用于采集外部图像信息。本实施例中，感光组件200为互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)图像采集装置，在其它一些实施例中，感光组件200也可以是电荷耦合器件(Charge-coupled Device，CCD)图像采集装置等其它形式的图像采集装置。可以理解的是，感光组件200可以不限于是图像采集装置，例如在一些实施例中，感光组件200也可以是红外传感器、接近传感器、红外镜头、泛光感应元件、环境光传感器以及点阵投影器等光传感器。此外，显示装置在显示面板100的第二表面S2还可以集成其它部件，例如是听筒、扬声器等。
在另一些实施例中，当第一显示区AA1环绕至少部分第二显示区AA2 设置，即第一显示区AA1为边框显示区时，第一显示区AA1内还可以设置移位寄存器等驱动部件，进而能够减小显示面板100的边框尺寸，实现显示装置的窄边框设计。
在还一些实施例中，第一显示区AA1还可以既包括透光显示区也包括边框显示区，既能够实现感光组件的屏下集成，也能够实现窄边框的设计。
依照本申请如上文的实施例，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本申请的原理和实际应用，从而使所属技术领域技术人员能很好地利用本申请以及在本申请基础上的修改使用。本申请仅受权利要求书及其全部范围和等效物的限制。

Claims (20)

  1. 一种显示面板，所述显示面板具有第一显示区和第二显示区，所述显示面板包括：
    子像素，包括位于所述第一显示区的第一子像素和位于所述第二显示区的第二子像素；
    像素驱动电路，位于所述第二显示区，所述像素驱动电路包括第一电路和第二电路，所述第一电路用于驱动所述第一子像素，所述第二电路用于驱动所述第二子像素，
    连接线，包括用于连接所述第一电路和所述第一子像素的第一连接线；
    其中，至少部分所述第一连接线沿第一方向延伸且位于所述第一电路的一侧。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括第一信号线层，所述第一信号线层包括第一信号线，至少部分所述第一连接线位于所述第一信号线层，所述第一信号线包括数据线、扫描线、电源线、电压参考线和接地线中的至少一者。
  3. 根据权利要求2所述的显示面板，其中，所述显示面板还包括透光信号线层，所述第一连接线包括位于所述第一显示区的第一分段和位于所述第二显示区的第二分段，所述第一分段位于所述透光信号线层，所述第二分段位于所述第一信号线层和/或所述透光信号线层。
  4. 根据权利要求1所述的显示面板，其中，所述第一电路和a个所述第二电路形成第一电路块，a为大于1的整数，沿所述第一方向延伸的所述至少部分第一连接线位于与其连接的所述第一电路所在的所述第一电路块的一侧。
  5. 根据权利要求4所述的显示面板，其中，a个相邻的所述第二子像素形成像素块，所述第一电路块内的a个所述第二电路用于驱动同一所述像素块内的a个所述第二子像素，所述第一电路块为多个，且各所述第一电路块和被该所述第一电路块驱动的所述像素块之间的相对位置相同。
  6. 根据权利要求5所述的显示面板，其中，所述像素驱动电路还包括 虚拟区域，所述虚拟区域和a个所述第二电路形成第二电路块。
  7. 根据权利要求6所述的显示面板，其中，所述第二电路块内的a个所述第二电路用于驱动同一所述像素块内的a个所述第二子像素，所述第二电路块为多个，且各所述第二电路块和被该所述第二电路块驱动的所述像素块之间的相对位置相同。
  8. 根据权利要求6所述的显示面板，其中，沿所述显示面板的厚度方向，所述第一电路的正投影尺寸和所述虚拟区域的尺寸相同；所述第一电路块的正投影尺寸和所述第二电路块的正投影尺寸相同。
  9. 根据权利要求6所述的显示面板，其中，所述第一电路块内所述第一电路的数量和所述第二电路块内所述虚拟区域的数量相同。
  10. 根据权利要求1所述的显示面板，其中，沿所述第一方向延伸的所述至少部分第一连接线位于所述第一电路在第二方向上的一侧，所述第一方向与所述第二方向相交。
  11. 根据权利要求6所述的显示面板，其中，所述第一电路块内所述第一电路和所述第二电路的相对位置关系与所述第二电路块内所述虚拟区域和所述第二电路的相对位置关系相同。
  12. 根据权利要求6所述的显示面板，其中，所述虚拟区域内设置有虚拟电路，所述虚拟电路的结构与所述第一电路的结构相同。
  13. 根据权利要求1所述的显示面板，其中，所述第二显示区包括主显示区和过渡区，所述过渡区位于所述主显示区和所述第一显示区之间，所述第一电路位于所述过渡区。
  14. 根据权利要求6所述的显示面板，其中，至少部分所述第二电路块在第二方向上的一侧设置有虚拟导线，所述虚拟导线沿所述第一方向延伸成型，所述第一方向与所述第二方向相交。
  15. 根据权利要求14所述的显示面板，其中，所述虚拟导线包括第一虚拟导线，所述第一虚拟导线位于所述第二电路块在所述第二方向上的至少一侧，且所述第二电路块和与其对应的所述第一虚拟导线的相对位置与所述第一电路块和与其对应的所述第一连接线的相对位置相同。
  16. 根据权利要求15所述的显示面板，其中，所述第一电路块在所述 第二方向上的至少一侧设置有多行所述第二电路块，各行所述第二电路块在所述第二方向上的同侧设置有所述第一虚拟导线。
  17. 根据权利要求14所述的显示面板，其中，所述虚拟导线包括第二虚拟导线，所述第二虚拟导线位于所述第一连接线在所述第一方向上的至少一侧。
  18. 根据权利要求1所述的显示面板，其中，相同颜色的所述子像素连接的所述连接线使用相同的材料制备成型。
  19. 根据权利要求1所述的显示面板，其中，所述第一子像素和所述第二子像素成行成列排布，所述第一电路和所述第二电路成行成列排布，至少部分所述第一电路和所述第二电路沿所述第一方向并排设置并位于同一行，且位于同一行的所述第一电路和所述第二电路用于驱动同行的所述第一子像素和所述第二子像素。
  20. 一种显示装置，包括根据权利要求1至19任一项所述的显示面板。
PCT/CN2022/108255 2022-02-28 2022-07-27 显示面板及显示装置 WO2023159868A1 (zh)

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