WO2022202322A1 - Substrat de câblage, substrat en couches et procédé de fabrication de substrat de câblage - Google Patents

Substrat de câblage, substrat en couches et procédé de fabrication de substrat de câblage Download PDF

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Publication number
WO2022202322A1
WO2022202322A1 PCT/JP2022/010268 JP2022010268W WO2022202322A1 WO 2022202322 A1 WO2022202322 A1 WO 2022202322A1 JP 2022010268 W JP2022010268 W JP 2022010268W WO 2022202322 A1 WO2022202322 A1 WO 2022202322A1
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Prior art keywords
insulating layer
via portion
sub
layer
wiring board
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PCT/JP2022/010268
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English (en)
Japanese (ja)
Inventor
和久 早川
直貴 南谷
英一 高田
Original Assignee
株式会社村田製作所
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Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to CN202290000285.7U priority Critical patent/CN220915521U/zh
Publication of WO2022202322A1 publication Critical patent/WO2022202322A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

Definitions

  • the present invention relates to a wiring board, a laminated board, and a method for manufacturing a wiring board.
  • Patent Document 1 discloses that connectivity between vias is improved in order to minimize loss during signal transmission in a high frequency band.
  • An improved printed circuit board is disclosed.
  • Patent Document 1 a first insulating layer, a plated via formed through the first insulating layer, a second insulating layer laminated on the first insulating layer, and a second insulating layer in contact with the plated via and a paste via formed through the plated via and the paste via, wherein the contact interface between the plated via and the paste via is located within the first insulating layer.
  • the connectivity between the plated via and the paste via is improved by providing the interface between the plated via and the paste via within the first insulating layer.
  • the interface between the two types of via portions provided in the first insulating layer is flat and extends in a direction perpendicular to the thickness direction of the first insulating layer. Therefore, when a printed circuit board is manufactured or bent, if a force is applied in a direction perpendicular to the interfaces of these via portions, cracks may occur at the interfaces.
  • the present invention has been made to solve the above problems, and an object of the present invention is to provide a wiring board having high connectivity between via portions provided in an insulating layer. Another object of the present invention is to provide a laminated substrate including the wiring substrate and a method for manufacturing the wiring substrate.
  • a wiring board of the present invention is a wiring board including an insulating layer and a conductor layer formed on one main surface of the insulating layer, wherein the insulating layer has the conductor layer as a bottom and the other side of the insulating layer. having a hole opening toward the main surface, the hole being provided with a first via portion connected to the conductor layer and a second via portion connected to the first via portion;
  • the first via portion includes a conductive member and does not include a resin member, and the end surface of the first via portion on the second via portion side protrudes toward the second via portion. part of the second via part extends between the protrusion of the first via part and the insulating layer and is connected to the first via part. It is characterized in that it does not come into contact with the conductor layer.
  • the laminated substrate of the present invention includes at least one layer of the wiring substrate of the present invention, another insulating layer laminated on the insulating layer of the wiring substrate, and the other insulating layer provided so as to penetrate the other insulating layer in the thickness direction. and an interlayer connection conductor.
  • a method for manufacturing a wiring board according to the present invention comprises: a step of preparing an insulating layer with a conductor foil in which a conductor foil is formed on one main surface of an insulating layer; In contrast, a hole forming step of forming a hole having the conductor foil as a bottom and opening toward the other main surface of the insulating layer, and plating the hole provided in the insulating layer, the above a first via portion forming step of forming a first via portion connected to a conductor foil in a portion of the hole; and forming the first via portion in a portion of the hole where the first via portion is not formed.
  • a second via portion forming step of forming a connected second via portion wherein in the first via portion forming step, the end face opposite to the conductor foil protrudes toward the opening of the hole; forming a first via portion having a portion, and forming a second via portion between the projecting portion of the first via portion and the inner wall surface of the hole in which the first via portion is formed; It is characterized in that a part of the via portion is extended.
  • the present invention it is possible to provide a wiring board having high connectivity between via portions provided in the insulating layer. Further, according to the present invention, it is possible to provide a laminated substrate including the wiring substrate and a method for manufacturing the wiring substrate.
  • FIG. 1 is a cross-sectional view schematically showing a wiring board according to Embodiment 1 of the present invention.
  • 2 is a top view of the wiring board according to FIG. 1.
  • FIG. 3 is a cross-sectional view schematically showing a wiring board according to Embodiment 2 of the present invention.
  • FIG. 4 is a cross-sectional view schematically showing a wiring board according to Embodiment 3 of the present invention.
  • FIG. 5 is a cross-sectional view schematically showing a wiring board according to Embodiment 4 of the present invention.
  • FIG. 6 is a perspective view schematically showing the laminated substrate of Embodiment 1 of the present invention.
  • 7 is a cross-sectional view taken along the line BB in FIG. 6.
  • FIG. 8 is a cross-sectional view taken along the line CC in FIG. 6.
  • FIG. 9A schematically shows an example of a step of preparing an insulating layer with conductor foil.
  • FIG. 9B schematically shows an example of a process of etching the conductor foil.
  • FIG. 9C schematically shows an example of the hole forming process.
  • FIG. 9D schematically shows an example of the step of forming the first via portion.
  • FIG. 9E schematically shows an example of the second via portion forming process.
  • FIG. 10A is a cross-sectional view schematically showing an example of a stacking step of stacking a plurality of insulating layers.
  • 10B is a cross-sectional view schematically showing a step of heating and pressurizing the laminate obtained in the step shown in FIG. 10A.
  • the wiring board of the present invention will be described below. It should be noted that the present invention is not limited to the following configurations, and may be modified as appropriate without departing from the gist of the present invention.
  • the present invention also includes a combination of a plurality of individual preferred configurations described below.
  • a wiring board of the present invention is a wiring board including an insulating layer and a conductor layer formed on one main surface of the insulating layer, wherein the insulating layer has the conductor layer as a bottom and the other side of the insulating layer. having a hole opening toward the main surface, the hole being provided with a first via portion connected to the conductor layer and a second via portion connected to the first via portion;
  • the first via portion includes a conductive member and does not include a resin member, and the end surface of the first via portion on the second via portion side protrudes toward the second via portion. part of the second via part extends between the protrusion of the first via part and the insulating layer and is connected to the first via part. It is characterized in that it does not come into contact with the conductor layer.
  • FIG. 1 is a cross-sectional view schematically showing a wiring board according to Embodiment 1 of the present invention.
  • 2 is a top view of the wiring board according to FIG. 1.
  • FIG. 1 is a cross-sectional view schematically showing a wiring board according to Embodiment 1 of the present invention.
  • the wiring board 1 is composed of an insulating layer 10 and a conductor layer 20 .
  • Conductive layer 20 is formed on one main surface 10 a of insulating layer 10 .
  • the insulating layer may contain a thermoplastic resin and/or a thermosetting resin, and preferably the insulating layer contains a thermoplastic resin.
  • thermoplastic resins include liquid crystal polymer (LCP), fluororesin, thermoplastic polyimide resin, polyetheretherketone resin (PEEK), polyphenylene sulfide resin (PPS), and the like.
  • Thermosetting resins include epoxy resins, phenolic resins, polyimide resins, silicon resins or modified resins thereof, and acrylic resins.
  • the insulating layer may contain an inorganic material such as a ceramic filler.
  • Ceramic fillers include, for example, boron nitride, talc, fused silica, and the like.
  • the thickness (length in the stacking direction) of the insulating layer 10 is preferably 10 ⁇ m or more and 50 ⁇ m or less.
  • the insulating layer 10 has holes 80 .
  • the hole 80 has the conductive layer 20 as its bottom and opens toward the other main surface 10 b of the insulating layer 10 . That is, the hole 80 penetrates the insulating layer 10 in the thickness direction.
  • a first via portion 30 and a second via portion 40 are provided in the hole 80 .
  • the first via portion 30 and the second via portion 40 are also collectively referred to as an interlayer connection conductor 50 .
  • the interlayer connection conductor 50 has a tapered shape. That is, when viewing the cross section of the interlayer connection conductor 50 in the direction orthogonal to the thickness direction of the insulating layer 10, the cross-sectional area of the end portion 50a of the interlayer connection conductor 50 on the side of the conductor layer 20 is It is smaller than the cross-sectional area of the end 50b opposite to the end 50a on the 20 side.
  • the first via portion 30 has one end surface connected to the conductor layer 20 and the other end surface connected to the second via portion 40 .
  • the second via portion 40 has one end surface connected to the first via portion 30 and the other end surface exposed to the other main surface 10 b of the insulating layer 10 .
  • the first via portion 30 has a projecting portion 35 .
  • the projecting portion 35 is provided on the end face of the first via portion 30 on the second via portion 40 side, and is a portion from which the first via portion 30 projects toward the second via portion 40 .
  • a portion 40 a of the second via portion 40 extends between the projecting portion 35 of the first via portion 30 and the insulating layer 10 .
  • a side surface of the first via portion 30 excluding the projecting portion 35 is in contact with the insulating layer 10 . Therefore, the portion 40a of the second via portion 40 extending between the projecting portion 35 of the first via portion 30 and the insulating layer 10 is not in contact with the conductor layer 20 connected to the first via portion 30. .
  • the connecting portion between the one-via portion 30 and the conductor layer 20 may be broken.
  • the second via portion 40 is a paste via containing a conductive member and a resin member
  • the first via portion 30 which is a plated via that does not contain a resin member
  • it is relatively mechanical. strength tends to be low.
  • the paste via with relatively low mechanical strength reaches the conductor layer 20 connected to the first via portion 30, the paste via with relatively low strength is likely to break. Then, there is a problem that the connecting portion between the first via portion 30 and the conductor layer 20 is broken due to the impact when the paste via having relatively low strength is broken.
  • the portion 40a of the second via portion 40 extending between the projecting portion 35 of the first via portion 30 and the insulating layer 10 is in contact with the conductor layer 20 connected to the first via portion 30. not Therefore, there is little possibility that the connecting portion between the first via portion 30 and the conductor layer 20 will be broken due to the breakage of the second via portion 40 as described above.
  • the first via portion 30 has the protruding portion 35, and the part 40a of the second via portion 40 is formed between the protruding portion 35 of the first via portion 30 and the insulating layer 10. extends between Therefore, compared to the case where the part 40 a of the second via portion 40 does not extend between the protruding portion 35 of the first via portion 30 and the insulating layer 10 , the first via portion 30 and the second via portion 40 are separated from each other. contact area can be increased. Therefore, the connectivity between the first via portion 30 and the second via portion 40 is high.
  • the shape of the protruding portion is such that the end surface of the first via portion on the second via portion side protrudes in an arc shape toward the second via portion side.
  • the arc shape means that the interface between the protruding portion of the first via portion and the second via portion forms a curved surface protruding toward the second via portion side. If the shape of the protruding portion is an arc-like protruding shape, it is possible to suppress concentration of press pressure on the end portion of the protruding portion when the wiring substrates of the present invention are laminated and pressed.
  • the second via portion is divided into three second via portions each having a length of 1 ⁇ 3 in the direction passing through the center of the hole and perpendicular to the thickness direction of the insulating layer.
  • the density of the second via portions arranged in the center of the division in the length direction is higher than the density of the second via portions arranged at both ends of the division in the length direction. 2
  • the direction passing through the center of the hole 80 (the position indicated by P in FIG. 2) and perpendicular to the thickness direction of the insulating layer 10 (the direction indicated by the arrow A in FIG.
  • the density of the second via portion 402 arranged in the center of the division in the length direction is less than that of the second via portions 401 and 403 arranged at both ends. higher than the density of It is considered that this is because the pressure during pressing concentrates on the portion of the first via portion 30 that most protrudes toward the second via portion 40 .
  • the magnitude of the density of each of the divided second via portions 401, 402, 403 can be measured with a scanning electron microscope (SEM). Specifically, first, each of the second via portions 401, 402, and 403 is further cut in half lengthwise, and the porosity of the obtained cross section is measured. Subsequently, by calculating back the area occupied by the solid components (the area of the portion other than the voids) from the porosity, the relative density relationship between the divided second via portions 401, 402, and 403 can be obtained. can ask.
  • SEM scanning electron microscope
  • the first via portion 30 is a plated via that contains a conductive member and does not contain a resin member.
  • the conductive member forming the first via portion 30 include Cu, Sn, Ag, and alloys containing at least one of these metals.
  • the conductive member forming the first via portion 30 is, for example, Cu.
  • "not including" the resin member means that the content of the resin member is 0.1% by volume or less.
  • the content of the conductive member in the first via portion 30 is preferably 90.0% by volume or more and 100% by volume or less.
  • the second via part 40 is preferably a paste via containing a conductive member and a resin member.
  • the same conductive member as the conductive member forming the first via portion 30 can be preferably used as the conductive member forming the second via portion 40 .
  • the conductive member forming the second via portion 40 may be the same as or different from the conductive member forming the first via portion 30 .
  • the conductive member forming the second via portion 40 is, for example, an alloy containing Cu and Sn.
  • the content of the conductive member in the second via portion 40 is preferably less than the content of the conductive member in the first via portion 30 . Moreover, the content of the conductive member in the second via portion 40 is preferably higher than the content of the resin member in the second via portion 40 .
  • the second via portion 40 may be a plated via that contains a conductive member and does not contain a resin member.
  • examples of the conductive member forming the second via portion 40 include Sn, Ni, Zn, Al, Au, and the like.
  • the second via portion 40 is a plated via, for example, the conductive member forming the first via portion 30 is Cu and the conductive member forming the second via portion is Sn. It may be a combination.
  • GC-MS gas chromatography-mass spectrometry
  • the resin member forming the second via portion 40 is selected from the group consisting of epoxy resin, phenol resin, polyimide resin, silicon resin or modified resin thereof, and acrylic resin. or at least one thermoplastic resin selected from the group consisting of polyamide resins, polystyrene resins, polymethacrylic resins, polycarbonate resins, and cellulosic resins.
  • the first via portion when comparing the area ratio of the first via portion and the area ratio of the second via portion in a cross section passing through the center of the hole and parallel to the thickness direction of the insulating layer, is preferably larger than the area ratio of the second via portion.
  • the second via portion is a paste via
  • the area ratio of the first via portion is larger than the area ratio of the second via portion, the ratio of plated vias with high conductivity will increase. resistance can be achieved.
  • the above area ratios are the area of the first via portion, the area of the second via portion, and the area of the first via portion on a cross section of the insulating layer cut in a direction parallel to the thickness direction of the insulating layer through the center of the hole. It can be calculated by calculating the total area of the portion and the second via portion and dividing the area of the first via portion or the second via portion by the total area of the first via portion and the second via portion.
  • the shape of the hole is preferably circular in a cross section perpendicular to the thickness direction of the insulating layer.
  • an ellipse, an ellipse, etc. are also included in a circle.
  • the shape of the hole may be a tapered shape in which the diameter decreases from the other main surface side of the insulating layer toward the one main surface side, as shown in FIG.
  • An alloy layer having a composition different from that of both the first via portion and the second via portion may be formed on at least a portion of the interface between the first via portion and the second via portion.
  • the connectivity between the first via portion and the second via portion is improved.
  • an alloy layer 60 having a composition different from that of both the first via portion 30 and the second via portion 40 is formed between the first via portion 30 and the second via portion 40.
  • the alloy layer 60 may be formed on the entire interface between the first via portion 30 and the second via portion 40, or may be formed on a portion thereof.
  • the alloy layer 60 may be one layer, or two or more layers.
  • the alloy layer is formed at the interface between the first via portion and the second via portion can be confirmed by observing a cross section of the insulating layer cut in a direction parallel to the thickness direction with an SEM. . Since the alloy layer has a different composition from both the first via portion and the second via portion, it is displayed in a different color tone from the first via portion and the second via portion in the SEM photograph.
  • compositions of Cu 5 Sn, Cu 3 Sn, Cu 6 Sn 5 , etc. are all compositions containing Cu and Sn as metal species, but the content ratios of the metal species are different, so the compositions are different from each other. It can be said.
  • FIG. 3 is a cross-sectional view schematically showing a wiring board according to Embodiment 2 of the present invention.
  • the insulating layer 10 includes a first sub-insulating layer 13 and a second sub-insulating layer 15 .
  • the first sub-insulating layer 13 has one main surface in contact with the conductor layer 20 and the other main surface in contact with the second sub-insulating layer 15 .
  • One main surface of the second sub-insulating layer 15 is in contact with the first sub-insulating layer 13 , and the other main surface constitutes the other main surface 10 b of the insulating layer 10 .
  • Holes 81 are formed in the first sub-insulating layer 13 and the second sub-insulating layer 15 to penetrate the insulating layer 10 in the thickness direction.
  • a first via portion 31 and a second via portion 41 are provided in the hole 81 .
  • the first via portion 31 and the second via portion 41 are also collectively referred to as an interlayer connection conductor 51 .
  • the first via portion 31 has a projecting portion 36 .
  • the projecting portion 36 is provided on the end face of the first via portion 31 on the second via portion 41 side, and is a portion where the first via portion 31 projects toward the second via portion 41 .
  • a portion 41 a of the second via portion 41 extends between the insulating layer 10 and the projecting portion 36 of the first via portion 31 .
  • a cavity 70 is provided between the side surface of the first via portion 31 provided in the first sub-insulating layer 13 and the first sub-insulating layer 13 .
  • the first sub-insulating layer 13 may be formed inside the cavity 70 in the manufacturing process of the wiring board.
  • Part of the two-via portion 41 can enter.
  • Part of the second via portion 41 enters the cavity 70, thereby increasing the contact area between the first via portion 31 and the second via portion 41, thereby further enhancing connectivity.
  • Cavity 70 may be provided entirely between the side surface of first via portion 31 provided in first sub-insulating layer 13 and first sub-insulating layer 13, but may be provided only partially. good too. Moreover, it is preferable that the cavity 70 is provided on the second sub-insulating layer 15 side of the side surface of the first via portion 31 provided in the first sub-insulating layer 13 . That is, it is preferable that the conductor layer 20 is not exposed in the cavity 70 provided in the first sub-insulating layer 13 .
  • the coefficient of linear expansion of the first sub-insulating layer 13 is smaller than the coefficient of linear expansion of the second sub-insulating layer 15 .
  • the linear expansion coefficients of the first sub-insulating layer and the second sub-insulating layer are the linear expansion coefficients of each layer in the in-plane direction.
  • the second sub-insulating layer 13 will not reach the second sub-insulating layer when the insulating layer is cooled after hot pressing in manufacturing the wiring board.
  • the insulating layer 15 shrinks more than the first sub-insulating layer 13 .
  • Part of the interface between the first sub-insulating layer 13 and the first via portion 31 is peeled off by the shrinkage force of the first sub-insulating layer 13 , so that a gap between the first via portion 31 and the first sub-insulating layer 13 is formed.
  • a cavity 70 is formed.
  • thermomechanical analysis (TMA) method The coefficients of linear expansion in the in-plane direction of the first sub-insulating layer and the second sub-insulating layer are measured, for example, by a thermomechanical analysis (TMA) method.
  • the in-plane direction of each layer means the direction along the main surface of each layer.
  • the in-plane direction of the first sub-insulating layer 13 and the second sub-insulating layer 15 can be said to be the direction perpendicular to the stacking direction.
  • both the first sub-insulation layer and the second sub-insulation layer preferably contain a thermoplastic resin.
  • the first sub-insulating layer contains a fluororesin as a main component
  • the second sub-insulating layer contains a liquid crystal polymer as a main component.
  • the second sub-insulating layer containing liquid crystal polymer as a main component has a smaller coefficient of linear expansion in the in-plane direction than the first sub-insulating layer containing fluororesin as a main component.
  • the main component means the component with the largest content (volume percentage) in each layer or each member.
  • the alloy layer when an alloy layer is provided between the first via portion and the second via portion, the alloy layer is formed in the first sub-insulation in the thickness direction of the insulation layer. It is preferably located at a position different from the interface between the layer and the second sub-insulating layer. When the alloy layer is located at a position different from the interface between the first sub-insulating layer and the second sub-insulating layer, stress is less likely to concentrate on the interface between the first sub-insulating layer and the second sub-insulating layer.
  • the alloy layer may be on the first sub-insulating layer side or on the second sub-insulating layer side of the interface between the first sub-insulating layer and the second sub-insulating layer in the thickness direction of the insulating layer. good too.
  • an alloy layer 61 is provided between the first via portion 31 and the second via portion 41 .
  • alloy layer 61 is located closer to second sub-insulating layer 15 than the interface between first sub-insulating layer 13 and second sub-insulating layer 15 .
  • the alloy layer 61 is positioned closer to the second sub-insulating layer 15 than the interface between the first sub-insulating layer 13 and the second sub-insulating layer 15.
  • the alloy layer may be located closer to the first sub-insulating layer than the interface between the first sub-insulating layer and the second sub-insulating layer.
  • FIG. 4 is a cross-sectional view schematically showing a wiring board according to Embodiment 3 of the present invention.
  • the insulating layer 10 includes a first sub-insulating layer 14 and a second sub-insulating layer 16 .
  • Holes 82 are formed in the first sub-insulating layer 14 and the second sub-insulating layer 16 to penetrate the insulating layer 10 in the thickness direction. and are provided.
  • the first via portion 32 and the second via portion 42 are also collectively referred to as an interlayer connection conductor 52 .
  • the first via portion 32 has a projecting portion 37 .
  • the projecting portion 37 is provided on the end face of the first via portion 32 on the second via portion 42 side, and is a portion from which the first via portion 32 projects toward the second via portion 42 .
  • a portion 42 a of the second via portion 42 extends between the projecting portion 37 of the first via portion 32 and the insulating layer 10 .
  • a side surface of the first via portion 32 excluding the projecting portion 37 is in contact with the insulating layer 10 . Therefore, the portion 42a of the second via portion 42 extending between the projecting portion 37 of the first via portion 32 and the insulating layer 10 is not in contact with the conductor layer 20 connected to the first via portion 32. .
  • the first via portion 32 has a constricted portion 32c.
  • the cross-sectional area of the constricted portion 32c is smaller than the cross-sectional area of the end portion 32a of the first via portion 32 on the conductor layer side. Moreover, it is smaller than the cross-sectional area of the end portion 32b of the first via portion 32 on the second via portion 42 side, excluding the projecting portion 37 . If the first via portion 32 has the constricted portion 32c, the stress applied when the wiring board 3 is pressed and the resin flows is concentrated on the connection surface between the conductor layer 20 and the first via portion 32. can be suppressed.
  • a first via portion having a constricted portion can be obtained by using, as insulating layers, a first sub-insulating layer and a second sub-insulating layer having a lower laser absorptance than the first sub-insulating layer.
  • the other main surface of the second sub-insulating layer (the main surface not in contact with the first sub-insulating layer) is irradiated with a laser to evaporate the second sub-insulating layer. to form a hole.
  • the laser travels in the thickness direction of the insulating layer toward the first sub-insulating layer.
  • the shape of the hole formed by the laser is usually a tapered shape that tapers toward the tip.
  • the laser absorptivity of the second sub-insulating layer is lower than that of the first sub-insulating layer, the amount of heat generated by the laser increases the moment the laser reaches the first sub-insulating layer. Therefore, a hole having a diameter larger than that of the second sub-insulating layer is formed in the first sub-insulating layer. Therefore, a constricted portion is formed in the vicinity of the interface between the second sub-insulating layer and the first sub-insulating layer so that the diameter of the hole formed by the laser is the smallest.
  • the laser absorptances of the first sub-insulating layer and the second sub-insulating layer are obtained as absorptances of light having the same wavelength as the laser wavelength.
  • the light absorptance can be measured, for example, with a spectrophotometer.
  • the laser wavelength include 10600 nm for CO 2 laser, 1064 nm for YAG laser, 532 nm for SHG line obtained by wavelength conversion of YAG laser, and 355 nm for THG line.
  • XeF laser of 351 nm, XeCl laser of 308 nm, KrF laser of 248 nm, ArF laser of 193 nm, F2 laser of 157 nm, and the like can be used.
  • the first sub-insulating layer contains a fluororesin as a main component
  • the second sub-insulating layer contains a liquid crystal polymer as a main component.
  • the second sub-insulating layer containing liquid crystal polymer as a main component has a lower laser absorptance than the first sub-insulating layer containing fluororesin as a main component.
  • the interface between the first sub-insulating layer and the second sub-insulating layer is located at a different position from the constricted portion in the thickness direction of the insulating layer. If the interface between the first sub-insulating layer and the second sub-insulating layer is located at a position different from the constricted portion in the thickness direction of the insulating layer, stress is generated at the interface between the first sub-insulating layer and the second sub-insulating layer. can be dispersed.
  • the constricted portion may be located on the first sub-insulating layer side or on the second sub-insulating layer side of the interface between the first sub-insulating layer and the second sub-insulating layer. may be located.
  • the interface between the first sub-insulating layer and the second sub-insulating layer, the constricted portion, and the alloy layer are preferably at different positions.
  • the first sub-insulating layer preferably contains fluororesin as a main component. Since the fluororesin has a smaller dielectric constant than the liquid crystal polymer, the first sub-insulating layer containing the fluororesin as a main component facilitates improving the dielectric properties of the wiring board in a high frequency band. In addition, since the fluororesin has a lower hygroscopicity than the liquid crystal polymer, the first sub-insulating layer containing the fluororesin as a main component makes it difficult for the wiring board to change its dielectric characteristics due to moisture absorption. On the other hand, the first sub-insulating layer functions as an adhesive layer that bonds the second sub-insulating layer and the conductor layer. Adhesive function is easily improved.
  • fluororesins examples include perfluoroalkoxyalkane (PFA), perfluoroethylene propene copolymer (FEP), polytetrafluoroethylene (PTFE), and the like.
  • PFA perfluoroalkoxyalkane
  • FEP perfluoroethylene propene copolymer
  • PTFE polytetrafluoroethylene
  • the second sub-insulating layer preferably contains a liquid crystal polymer as a main component. Since the liquid crystal polymer has a low dielectric constant among thermoplastic resins, the second sub-insulating layer containing the liquid crystal polymer as a main component facilitates improving the dielectric properties of the wiring board in a high frequency band. In addition, since the liquid crystal polymer has low hygroscopicity, the second sub-insulating layer containing the liquid crystal polymer as a main component makes it difficult for the wiring substrate to change its dielectric characteristics due to moisture absorption.
  • Liquid crystal polymers are usually classified into type I, type II, and type III aromatic polyesters.
  • the liquid crystal polymer contained in the second sub-insulating layer is preferably type I or type II wholly aromatic polyester.
  • the type I and type II wholly aromatic polyesters are more resistant to hydrolysis than the type III partially aromatic polyesters, and are therefore preferred as materials for wiring substrates.
  • the wiring board according to the fourth embodiment of the present invention is the same as the wiring board according to the first embodiment except for the shape of the projecting portion.
  • FIG. 5 is a cross-sectional view schematically showing a wiring board according to Embodiment 4 of the present invention.
  • wiring board 4 includes insulating layer 10 and conductor layer 20 .
  • Conductive layer 20 is formed on one main surface 10 a of insulating layer 10 .
  • the insulating layer 10 has holes 83 .
  • the hole 83 has the conductor layer 20 as its bottom and opens toward the other main surface 10 b of the insulating layer 10 . That is, the hole 83 penetrates the insulating layer 10 in the thickness direction.
  • a first via portion 33 and a second via portion 43 are provided in the hole 83 .
  • the first via portion 33 and the second via portion 43 are also collectively referred to as an interlayer connection conductor 53 .
  • the first via portion 33 has one end surface connected to the conductor layer 20 and the other end surface connected to the second via portion 43 .
  • One end surface of the second via portion 43 is connected to the first via portion 33 , and the other end surface constitutes the other main surface 10 b of the insulating layer 10 .
  • the first via portion 33 has a projecting portion 38 .
  • the projecting portion 38 is provided on the end face of the first via portion 33 on the second via portion 43 side, and is a portion from which the first via portion 33 projects toward the second via portion 43 .
  • the protruding portion 38 protrudes toward the second via portion 43 from the end face of the first via portion 33 on the second via portion 43 side. It has a shape in which only a part of the end face on the side of the via portion 43 is extended substantially uniformly toward the second via portion 43 . Therefore, the interface where the protruding portion 38 and the second via portion 43 are in contact has a stepped shape.
  • a portion 43 a of the second via portion 43 extends between the projecting portion 38 of the first via portion 33 and the insulating layer 10 .
  • a side surface of the first via portion 33 excluding the projecting portion 38 is in contact with the insulating layer 10 . Therefore, a portion 43a of the second via portion 43 extending between the projecting portion 38 of the first via portion 33 and the insulating layer 10 is not in contact with the conductor layer 20 connected to the first via portion 33. .
  • an alloy layer may be provided between the first via portion and the second via portion.
  • an alloy layer 63 having a composition different from that of both the first via portion 33 and the second via portion 43 is formed at the interface between the first via portion 33 and the second via portion 43 .
  • the alloy layer 63 may be formed on the entire interface between the first via portion 33 and the second via portion 43, or may be formed on a portion thereof.
  • the alloy layer 63 may be one layer, or two or more layers.
  • the laminated substrate of the present invention includes at least one layer of the wiring substrate of the present invention, another insulating layer laminated on the insulating layer of the wiring substrate, and the other insulating layer provided so as to penetrate the other insulating layer in the thickness direction. and an interlayer connection conductor.
  • another insulating layer is an insulating layer different from the insulating layer constituting the wiring board of the present invention.
  • Another insulating layer is provided with an interlayer connection conductor. The interlayer connection conductor penetrates the other insulating layer in the thickness direction.
  • the interlayer connection conductors provided in other insulating layers may be plated vias or paste vias.
  • the above-described first via portion and second via portion may be included.
  • the first via portion may have a projecting portion, and a part of the second via portion may extend between the projecting portion of the first via portion and the insulating layer.
  • the laminated substrate of the present invention includes at least one layer of the wiring substrate of the present invention, the via portions provided in the insulating layer have high connectivity.
  • the laminated substrate of the present invention preferably has a conductor layer as a signal line for transmitting signals and constitutes a transmission line.
  • the conductor layer is provided as a signal line for transmitting a signal and constitutes a transmission line
  • the conductor layer functioning as the signal line is connected by an interlayer connection conductor with high connectivity between via portions. Therefore, loss during signal transmission can be reduced.
  • FIG. 6 is a perspective view schematically showing the laminated substrate of Embodiment 1 of the present invention.
  • 7 is a cross-sectional view taken along the line BB in FIG. 6.
  • FIG. 8 is a cross-sectional view taken along the line CC in FIG. 6.
  • the laminated substrate 100 of Embodiment 1 of the present invention includes a protective layer 180, a first layer 110, a second layer 120, a third layer 130 and a fourth layer 140.
  • the laminated substrate is composed of a ground wiring 160 arranged on one main surface of the fourth layer 140, between the first layer 110 and the second layer 120, and between the second layer 120 and the third layer 130. and a signal line 170 disposed therebetween.
  • the first layer 110 and the second layer 120 each have interlayer connection conductors 50 .
  • the interlayer connection conductors 50 provided on the first layer 110 and the second layer 120 the interlayer connection conductors 50 connected to the conductor layer 20 serving as the signal line 170 just overlap in the stacking direction. Therefore, the signal lines 170 are connected to each other by the interlayer connection conductors 50 provided on the first layer 110 and the interlayer connection conductors 50 provided on the second layer 120 to form a transmission line.
  • the interlayer connection conductor 50 is composed of a first via portion having a projecting portion and a second via portion. That is, the first layer 110 and the second layer 120 forming the laminated board 100 are insulating layers forming the wiring board of the present invention.
  • an alloy layer 65 having a composition different from that of the second via portion and the conductor layer 20 is formed between the second via portion forming the interlayer connection conductor 50 and the conductor layer 20 forming the signal line 170 good. Formation of the alloy layer 65 can enhance the connectivity between the second via portion and the conductor layer 20 .
  • the third layer 130 and the fourth layer 140 are insulating layers other than the wiring board of the present invention, and interlayer connection conductors 55 are provided so as to penetrate the insulating layers in the thickness direction.
  • the interlayer connection conductor 55 is composed of a first via portion having a projecting portion and a second via portion.
  • the ground wiring 160 includes an interlayer connection conductor 50 provided on the first layer 110, an interlayer connection conductor 50 provided on the second layer 120, an interlayer connection conductor 55 provided on the third layer 130, and an interlayer connection conductor 55 provided on the third layer 130. It is connected to the conductor pattern 190 by an interlayer connection conductor 55 provided at 140 .
  • Conductor patterns 195 are provided between the interlayer connection conductors 55 provided.
  • An alloy layer 65 having a composition different from that of both the second via portion and the conductor pattern 195 may be formed between the second via portion and the conductor pattern 195 that constitute the interlayer connection conductor 50 .
  • a conductor pattern may be provided between the interlayer connection conductors 55.
  • a conductor pattern may or may not be provided between the interlayer connection conductors 50 or between the interlayer connection conductors 50 and the interlayer connection conductors 55 .
  • interlayer connection conductor 50 or 55 connected to the ground wiring 160 may simply be a paste via. In this case, it is possible to reduce the number of man-hours in manufacturing the laminated substrate.
  • a method for manufacturing a wiring board according to the present invention comprises: a step of preparing an insulating layer with a conductor foil in which a conductor foil is formed on one main surface of an insulating layer; In contrast, a hole forming step of forming a hole having the conductor foil as a bottom and opening toward the other main surface of the insulating layer, and plating the hole provided in the insulating layer, the above a first via portion forming step of forming a first via portion connected to a conductor foil in a portion of the hole; and forming the first via portion in a portion of the hole where the first via portion is not formed.
  • a second via portion forming step of forming a connected second via portion wherein in the first via portion forming step, the end face opposite to the conductor foil protrudes toward the opening of the hole; forming a first via portion having a portion, and forming a second via portion between the projecting portion of the first via portion and the inner wall surface of the hole in which the first via portion is formed; It is characterized in that a part of the via portion is extended.
  • FIGS. 9A, 9B, 9C, 9D, and 9E An embodiment of the wiring board manufacturing method of the present invention will be described with reference to FIGS. 9A, 9B, 9C, 9D, and 9E.
  • FIG. 9A schematically shows an example of a step of preparing an insulating layer with conductor foil.
  • an insulating layer with conductor foil is prepared in the step of preparing an insulating layer with conductor foil.
  • the insulating layer with conductor foil is obtained by attaching a conductor foil 90 to one main surface 10 a of the insulating layer 10 .
  • the insulating layer 10 constituting the insulating layer with conductor foil may be composed of one insulating layer, or may be composed of two or more insulating layers. When the insulating layer is composed of two insulating layers, the insulating layers are referred to as a first sub-insulating layer and a second sub-insulating layer in order from the conductor foil side.
  • FIG. 9B schematically shows an example of a process of etching the conductor foil.
  • the conductor foil 90 is etched to form a conductor pattern, if necessary.
  • the formed conductor pattern is also called conductor layer 20 .
  • the portion of the conductor foil 90 where the hole formed in the hole forming step is exposed is not removed by etching.
  • FIG. 9C schematically shows an example of the hole forming process.
  • a hole 80 is formed through the insulating layer 10 in the thickness direction with the conductor layer 20 as the bottom.
  • the method for forming the holes is not particularly limited, laser irradiation is preferred.
  • the laser diameter, laser output and irradiation time can be appropriately adjusted according to the shape of the hole to be formed and the thickness and material of the insulating layer.
  • FIG. 9D schematically shows an example of the step of forming the first via portion.
  • the hole 80 is plated to form the first via portion 30 connected to the conductor foil 90 (conductor layer 20 ) in a portion of the hole 80 .
  • the first via portion 30 having the protruding portion 35 protruding toward the opening of the hole is formed on the end face opposite to the conductor foil 90 (the conductor layer 20). For example, by adjusting the current during plating, it is possible to form the first via portion having a projecting portion. Note that the method of forming a protrusion by etching the first via portion, which has been formed by plating once and has no protrusion, with a chemical or the like is not included in the first via portion forming step of the present invention.
  • FIG. 9E schematically shows an example of the second via portion forming process.
  • the second via portion 40 connected to the first via portion 30 is formed in the portion of the hole 80 where the first via portion 30 is not formed.
  • the first via portion 30 and the second via portion 40 are also collectively referred to as an interlayer connection conductor 50 .
  • a portion of the second via portion 40 extends between the projecting portion 35 of the first via portion 30 and the inner wall surface of the hole 80 in which the first via portion 30 is formed.
  • a conductive paste is a paste containing a conductive member and a resin member.
  • a plating process using Cu in the first via portion forming step, and to fill a conductive paste containing Cu and Sn in the second via portion forming step.
  • a step of filling conductive paste into a portion where no portion is formed is also referred to as a “second via portion forming step”.
  • the second via portion 40 may be formed by plating the portion of the hole 80 where the first via portion 30 is not formed.
  • a heating and pressurizing step of heating and pressurizing the insulating layer with the conductor foil may be performed as necessary.
  • the second via portion forming step is performed by filling the conductive paste in the portion of the hole where the first via portion is not formed, heating is performed to form the conductive paste into the second via portion.
  • a pressure step may be required.
  • the wiring board of the present invention is manufactured through the above steps.
  • FIGS. 10A and 10B are schematic diagrams showing an example of the method for manufacturing the laminated substrate of the present invention.
  • FIG. 10A is a cross-sectional view schematically showing an example of a lamination step of laminating a plurality of insulating layers.
  • 10B is a cross-sectional view schematically showing a step of heating and pressurizing the laminate obtained in the step shown in FIG. 10A.
  • the protective layer 180, the insulating layer L1, the insulating layer L2, the insulating layer L3, and the insulating layer L4 are laminated in this order to produce a laminate.
  • the insulating layer L1 and the insulating layer L2 can be obtained by the method described with reference to FIGS. 9A to 9E.
  • the insulating layer L3 is formed by, for example, an etching step of forming a conductor pattern, a hole forming step of forming holes, and and an interlayer connection conductor forming step of forming an interlayer connection conductor in the hole.
  • the insulating layer L4 is formed by, for example, forming a hole in an insulating layer with a conductive foil attached to one main surface of the fourth layer 140, and forming an interlayer connection conductor in the hole. It can be obtained by a connection conductor process.
  • the conductor foil 160 attached to the fourth layer 140 serves as ground wiring.
  • the insulating layer L1 and the insulating layer L2 correspond to the wiring board 5, respectively.
  • the insulating layers included in the insulating layer L3 and the insulating layer L4 are other insulating layers.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un substrat de câblage comprenant une couche isolante 10 et une couche conductrice 20 formées sur une surface principale 10a de la couche isolante 10 : la couche isolante 10 ayant un trou 80 dont le fond est la couche semi-conductrice 20 et qui s'ouvre vers une autre surface principale 10b de la couche isolante 10 ; le trou 80 étant pourvu d'une première section de trou d'interconnexion 30 connectée à la couche conductrice 20 et d'une seconde section de trou d'interconnexion 40 reliée à la première section de trou d'interconnexion 30 ; la première section de trou d'interconnexion 30 comprenant un élément conducteur et ne comprenant pas un élément en résine ; la première section d'interconnexion 30 comprenant une section en saillie 35 où une surface d'extrémité, sur la seconde section d'interconnexion 40, de la première section d'interconnexion 30 fait saillie vers la seconde section d'interconnexion 40 ; et une section 40a de la seconde section d'interconnexion s'étendant jusqu'à entre la section en saillie 35 de la première section d'interconnexion 30 et la couche isolante 10, mais ne venant pas en contact avec la couche conductrice 20 connectée à la première section de trou d'interconnexion 30.
PCT/JP2022/010268 2021-03-26 2022-03-09 Substrat de câblage, substrat en couches et procédé de fabrication de substrat de câblage WO2022202322A1 (fr)

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JP2021-053437 2021-03-26

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10190232A (ja) * 1996-12-27 1998-07-21 Shinko Electric Ind Co Ltd 多層配線基板及びその製造方法
WO2001039267A1 (fr) * 1999-11-26 2001-05-31 Ibiden Co., Ltd. Carte de circuit imprime multicouches et dispositif semi-conducteur
JP2004297053A (ja) * 2003-03-10 2004-10-21 Sumitomo Bakelite Co Ltd 層間接合部及びそれを有する多層配線板
JP2007299943A (ja) * 2006-04-28 2007-11-15 Fujikura Ltd 多層配線基板及びその製造方法
JP2009289900A (ja) * 2008-05-28 2009-12-10 Kyocera Corp 配線基板及びその製造方法、並びにこれを用いた電子装置
JP2017174997A (ja) * 2016-03-24 2017-09-28 株式会社村田製作所 多層基板、および、多層基板の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10190232A (ja) * 1996-12-27 1998-07-21 Shinko Electric Ind Co Ltd 多層配線基板及びその製造方法
WO2001039267A1 (fr) * 1999-11-26 2001-05-31 Ibiden Co., Ltd. Carte de circuit imprime multicouches et dispositif semi-conducteur
JP2004297053A (ja) * 2003-03-10 2004-10-21 Sumitomo Bakelite Co Ltd 層間接合部及びそれを有する多層配線板
JP2007299943A (ja) * 2006-04-28 2007-11-15 Fujikura Ltd 多層配線基板及びその製造方法
JP2009289900A (ja) * 2008-05-28 2009-12-10 Kyocera Corp 配線基板及びその製造方法、並びにこれを用いた電子装置
JP2017174997A (ja) * 2016-03-24 2017-09-28 株式会社村田製作所 多層基板、および、多層基板の製造方法

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