WO2022198882A1 - 芯片检测方法及芯片检测装置 - Google Patents
芯片检测方法及芯片检测装置 Download PDFInfo
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- WO2022198882A1 WO2022198882A1 PCT/CN2021/112035 CN2021112035W WO2022198882A1 WO 2022198882 A1 WO2022198882 A1 WO 2022198882A1 CN 2021112035 W CN2021112035 W CN 2021112035W WO 2022198882 A1 WO2022198882 A1 WO 2022198882A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
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- the present application relates to the technical field of integrated circuit failure analysis, and in particular, to a chip detection method and a chip detection device.
- DRAM Dynamic Random Access Memory
- DRAM Dynamic Random Access Memory
- the gate of the transistor is electrically connected to the word line
- the source is electrically connected to the bit line
- the drain is electrically connected to the capacitor.
- the word line voltage on the word line can control the opening and closing of the transistor, so that the stored in the capacitor can be read through the bit line. data information in, or write data information into the capacitor.
- Chips such as DRAM usually include several one-time programmable memories (e-fuses), and the one-time programmable memories are used for information storage. If the one-time programmable memory leaks, it will cause various abnormal situations in the chip, such as entering 4G mode or dual memory cell (twin cell) mode, which will affect the performance and yield of the chip. It is very important to detect the leakage situation.
- the method for detecting the leakage of the one-time programmable memory in the chip is to transmit a test command to all the one-time programmable memories in the chip through a testing machine, and then read the state of all the one-time programmable memories.
- this method is low, because although this method can detect the one-time programmable memory with serious leakage (for example, burn-through by mistake), it is easy to miss the one-time programmable memory with mild leakage. Programmable memory, so that defective products with potential burn-through risk flow into subsequent production lines, resulting in a waste of resources.
- Some embodiments of the present application provide a chip detection method and a chip detection device, which are used to solve the problem of low accuracy of chip detection, so as to avoid potential risk of defective products from flowing into subsequent production lines, and to improve the quality of final chip products. Rate.
- the present application provides a chip detection method, comprising the following steps:
- the chip has several one-time programmable memories;
- the present application also provides a chip detection device, comprising:
- test module configured to transmit a test signal to the chip to be tested, so that the one-time programmable memory in the chip is kept in a latched state
- a detection module for detecting the micro-light signal emitted by the chip
- a judgment module is used for judging whether the detection module detects the low-light signal, and if so, confirms that the one-time programmable memory has a leakage defect.
- the chip detection method and the chip detection device provided by the present application judge whether the one-time programmable memory in the chip has leakage by detecting the situation that the chip emits a micro-optical signal when the one-time programmable memory in the chip is in a latched state. , not only can detect the one-time programmable memory that has been burned through by mistake, but also can detect the one-time programmable memory with relatively slight leakage, avoiding the bad products with potential burn-through risk from flowing into the subsequent production line, saving production resources and help improve the yield of the final chip product.
- FIG. 2 is a schematic diagram of a chip in a specific embodiment of the present application.
- FIG. 3 is a schematic diagram of a device in a specific embodiment of the present application when a chip is detected
- FIG. 4 is a schematic diagram of a micro-optical signal detected by a specific embodiment of the present application.
- FIG. 5 is a structural block diagram of a chip detection device in a specific embodiment of the present application.
- FIG. 1 is a flowchart of the chip detection method in the specific embodiment of the present application
- FIG. 2 is a schematic diagram of the chip in the specific embodiment of the present application
- FIG. 3 is a specific embodiment of the present application.
- FIG. 4 is a schematic diagram of the low-light signal detected by the specific embodiment of the present application.
- the chip detection method provided by this specific embodiment includes the following steps:
- step S11 a chip 20 to be tested is provided, and the chip 20 has several one-time programmable memories 21 , as shown in FIG. 2 .
- the chip 20 may be a DRAM chip, or may be another chip with a one-time programmable memory 21 .
- the chip 20 may have a plurality of the one-time programmable memories 21, and the plurality of the one-time programmable memories 21 are arranged in an array in the chip 20, as shown in FIG. 2 .
- the one-time programmable memory 21 is used for information storage.
- the one-time programmable memory 21 may be an electrical fuse (Electrical Fuse, E-Fuse) structure.
- the one-time programmable memory 21 having an electric fuse structure includes an active area (Active Area, AA) 211, a conductive area 212, and the active area 211 and AA.
- the dielectric layer region 213 between the conductive regions 212 is used for transmitting control signals to the active region 211 .
- the active region 211 , the dielectric layer region 213 and the conductive region 212 form a capacitor-like structure.
- the material of the conductive region 212 may be, but not limited to, polysilicon material.
- the material of the dielectric layer 213 may be, but not limited to, oxide materials, such as silicon dioxide.
- the active region 211 includes electrical structures such as transistors, bit line contacts, and capacitor contacts.
- the one-time programmable memory 21 with the electric fuse structure adjusts the resistance of the one-time programmable memory 21 by fusing the fuse (ie, the dielectric layer region 213 ): when the fuse is not blown When the fuse is in a high resistance state, the active region 211 and the conductive region 212 are in a state of electrical isolation; when the fuse is blown, the fuse is in a low resistance state, and the active region 211 and the conductive region 212 are in an electrically isolated state; The source region 211 and the conductive region 212 are in a state of electrical conduction.
- the fuse According to whether the fuse is blown or not, functions such as self-healing and mode switching inside the chip 20 can be realized.
- the fuse When the fuse has a leakage defect, it will affect the electrical signal transmission between the active region 211 and the conductive region 212 .
- Those skilled in the art can also set up other structures of one-time programmable memory structures according to actual needs, as long as the one-time programmable memory 21 with leakage defect can emit a low-light signal when it is in a voltage-difference leakage state.
- Step S12 transmitting a test signal to the chip 20 , so that the one-time programmable memory 21 in the chip 20 is kept in a latched state.
- the specific steps of keeping the one-time programmable memory 21 in the chip 20 in a latched state include:
- cycle steps are repeatedly performed, so that the one-time programmable memory 21 maintains the differential voltage leakage state, and the cycle steps include:
- the specific embodiment does not limit the specific content of the test signal, as long as the one-time programmable memory 21 in the chip 20 can be kept in a latched state.
- a DFT Design For Test, design for testability
- the DFT includes a plurality of test modes, so that the chip 20 can be driven to be in different working modes later, so that various performances or structures of the chip 20 can be tested to determine the chip 20 Whether it meets the design requirements or provides a reference for the technical improvement of subsequent chips. As shown in FIG.
- the chip 20 can be placed in the detection machine 30 , and the chip 20 is electrically connected to the test machine 31 outside the detection machine 30 through a cable 33 .
- the test machine 31 transmits a test signal to the chip 20 to activate a specific test mode in the DFT, so that the chip 32 is in the preset working mode, and the preset test procedure has been completed.
- the multiple mentioned in this specific embodiment refers to two or more.
- Keeping the one-time programmable memory 21 in the chip 20 in a latched state means keeping the one-time programmable memory 21 in the chip in a voltage-difference leakage state.
- the first cycle step is performed, that is, the test signal is transmitted to the chip 20 through the test machine 31, so that the chip 20 enters a preset test mode, and a corresponding test program is executed.
- the one-time programmable memory 21 is in a differential voltage leakage state, for example, the voltage of the active region 211 in the one-time programmable memory 21 is 0V, and the voltage of the conductive region 212 is 1.2V, The dielectric layer region 213 in the one-time programmable memory 21 is in a voltage leakage state of 1.2V.
- the voltage difference inside the one-time programmable memory 21 will return to 0V.
- the second cycle step is started, that is, the test machine 31 is used to send the chip to the chip again.
- the test signal is transmitted, so that the chip enters the preset test mode again, and the corresponding test program is executed again, so that the one-time programmable memory 21 is in a voltage-difference leakage state again.
- the cycle steps are repeatedly performed, so that the one-time programmable memory 21 is always kept in a differential voltage leakage state.
- the preset test mode may be any test mode in the DFT, as long as the one-time programmable memory 21 in the chip can be kept in a differential voltage leakage state.
- Step S13 detecting whether the chip 20 emits a low-light signal 40 , and if so, confirming that the one-time programmable memory 21 has a leakage defect.
- the low-light signal 40 is a low-light signal sent by the failure area in the one-time programmable memory 21 in a latched state.
- a suitable low-light detection method or detection lens can be selected in advance, so that the detected low-light emitted in the chip 20 can be detected in advance.
- the signal 40 is only sent out when the one-time programmable memory 21 leaks, thereby further improving the accuracy of chip detection.
- it can be detected whether the position of the one-time programmable memory 21 in the chip 20 emits the low-light signal 40 .
- the specific step of detecting whether the chip 20 emits a low-light signal includes:
- the chip 20 is placed on the transparent stage 302 with the front surface 201 facing upward, and a low-light detection lens 301 is placed toward the back surface 3022 of the transparent stage 302 .
- the chip 20 includes a front side 201 of the chip 20 and a back side of the chip 20 that are relatively distributed, and the surface of the chip 20 facing the transparent stage 302 is the back side of the chip 20 .
- the transparent stage 302 includes a front surface 3021 of the transparent stage and a back surface 3022 of the transparent stage that are relatively distributed.
- the surface of the transparent stage 302 facing the chip 20 is the front surface of the transparent stage. 3021.
- the chip 20 can be placed on the transparent stage 302 inside the detection machine 30 with the front side facing up, and the low-light detection lens 301 used for detecting low-light signals is directed toward the The back side of the transparent stage 302 is removed, so that the micro-optical signal emitted by the one-time programmable memory 21 in the chip 20 due to electric leakage can be detected timely and accurately.
- the size of the transparent stage 302 should be much larger than the size of the chip 20 , so that the micro-optical signal emitted from any position in the chip 20 can be detected.
- the low-light signal detected by the low-light detection lens 301 can intuitively reflect the location of the one-time programmable memory 21 in the chip 20 that emits low-light signals and the location of the one-time programmable memory 21 in the chip 20 that emits low-light signals.
- the number of one-time programmable memories 21 can intuitively reflect the location of the one-time programmable memory 21 in the chip 20 that emits low-light signals and the location of the one-time programmable memory 21 in the chip 20 that emits low-light signals.
- the one-time programmable memory 21 includes an active region 211 , a conductive region 212 located outside the active region 211 , and a conductive region 212 located between the active region 211 and the conductive region 212 .
- a dielectric layer region 213, one end of the dielectric layer region 213 is connected to the active region 211, and the other end is connected to the conductive region 212;
- the low-light detection lens 301 is capable of detecting low-light with wavelengths ranging from 700 nm to 1400 nm.
- the low-light detection lens 301 is an InGaAs lens.
- the InGaAs lens includes a near-infrared photodetector, which can capture micro-optical signals with wavelengths ranging from 700 nm to 1400 nm. Therefore, the InGaAs lens can capture micro-optical signals emitted by the one-time programmable memory 21 with leakage defects.
- Those skilled in the art can select a corresponding micro-optical detector according to the wavelength range of the micro-optical signal emitted by the one-time programmable memory 21 in the differential pressure leakage state, so as to further improve the detection accuracy of the chip 20 .
- the chip 20 has a plurality of one-time programmable memories 21 arranged in an array; the specific steps of transmitting the test signal to the chip 20 include:
- a test signal is transmitted to the chip 20 so that all the one-time programmable memories 21 in the chip 20 are kept in a latched state.
- the specific step of detecting whether the chip 20 emits a low-light signal includes:
- the chip 20 has 1024 one-time programmable memories 21 arranged in an array.
- all the one-time programmable memories 21 in the chip 20 can be kept in a latched state by transmitting a test signal to the chip 20 .
- the mapping relationship between the coordinate system on the image plane detected by the low-light detection lens 301 and the coordinate system on the chip 20 is established in advance.
- the low-light detection lens 301 detects the low-light signal
- the location of the one-time programmable memory 20 with leakage defects in the chip 20 can be located at one time, quickly and accurately according to the mapping relationship. Location.
- FIG. 5 is a structural block diagram of a chip detection device in a specific embodiment of the present application.
- the chip detection device provided by this specific embodiment can use the method shown in FIG. 1 to FIG. 4 to detect the chip.
- the chip detection device provided by this specific embodiment includes:
- the test module 50 is used for transmitting a test signal to the chip 20 to be tested, so that the one-time programmable memory 21 in the chip 20 is kept in a latched state;
- the detection module 51 is used to detect the low-light signal emitted by the chip 20;
- the judgment module 52 is used for judging whether the detection module detects the low-light signal, and if so, confirms that the one-time programmable memory 21 has a leakage defect.
- the testing module 50 may include the testing machine 31 shown in FIG. 3
- the detection module 51 may include the testing machine 30 shown in FIG. 3 .
- the test module 50 repeatedly performs the following cycle steps, so that the one-time programmable memory 21 maintains a voltage-difference leakage state.
- the cycle steps include: transmitting a test signal to the chip 20 to drive the The chip 20 is tested in a preset test mode; it is determined whether the test is completed, and if so, the next cycle step is performed.
- the detection module 51 is used to detect the micro-optical signal emitted by the chip 20 from the back of the chip 20 .
- the detection module 51 includes a transparent stage 302 and a low-light detection lens 301 , the chip 20 is placed on the transparent stage 302 facing upward, and the low-light detection lens 301 faces The back of the transparent stage 302 is placed.
- the one-time programmable memory 21 includes an active region 211 , a conductive region 212 located outside the active region 211 , and a conductive region 212 located between the active region 211 and the conductive region 212 .
- a dielectric layer region 213, one end of the dielectric layer region 213 is connected to the active region 211, and the other end is connected to the conductive region 212;
- the low-light detection lens 301 is capable of detecting low-light with wavelengths ranging from 700 nm to 1400 nm.
- the low-light detection lens 301 is an InGaAs lens.
- the chip 20 has a plurality of one-time programmable memories 21 arranged in an array;
- the test module 50 is used for transmitting test signals to the chip 20 , so that all the one-time programmable memories 21 in the chip 20 are kept in a latched state.
- the judging module 52 is configured to acquire the one-time programmable memory in the chip 20 in which the low-light signal appears after confirming that the detection module 51 detects that the chip 20 sends out the low-light signal 21 location.
- the judging module 52 can quickly obtain the one-time optical signal emitted from the chip 20 according to the low-light signal detected by the low-light detection lens 301 in the detection module 51 .
- the chip detection method and the chip detection device provided by this specific embodiment determine whether the one-time programmable memory in the chip exists by detecting the situation that the chip emits a low-light signal when the one-time programmable memory in the chip is in a latched state. Leakage, not only can detect the one-time programmable memory that has been burned through by mistake, but also can detect the one-time programmable memory with relatively slight leakage, which prevents bad products with potential burn-through risk from flowing into the subsequent production line, It saves production resources and helps to improve the yield of the final chip product.
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Abstract
一种芯片检测方法及芯片检测装置,芯片检测方法包括如下步骤:提供待测试的芯片(20),芯片(20)中具有若干一次性可编程存储器(21)(S11);传输测试信号至芯片(20),使得芯片(20)中的一次性可编程存储器(21)保持在锁存状态(S12);探测芯片(20)是否发出微光信号(40),若是,则确认一次性可编程存储器(21)存在漏电缺陷(S13)。本方法不仅能检测出已出现误烧穿的一次性可编程存储器(21),而且还能够检测出漏电情况相对较为轻微的一次性可编程存储器(21),避免了存在潜在烧穿风险的不良产品流入后续生产线。
Description
相关申请引用说明
本申请要求于2021年3月25日递交的中国专利申请号202110318085.8、申请名为“芯片检测方法及芯片检测装置”的优先权,其全部内容以引用的形式附录于此。
本申请涉及集成电路失效分析技术领域,尤其涉及一种芯片检测方法及芯片检测装置。
动态随机存储器(Dynamic Random Access Memory,DRAM)是计算机等电子设备中常用的半导体结构,其由多个存储单元构成,每个存储单元通常包括晶体管和电容器。晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接,字线上的字线电压能够控制晶体管的开启与关闭,从而通过位线能够读取存储在电容器中的数据信息,或者将数据信息写入到电容器中。
DRAM等芯片中通常包括若干个一次性可编程存储器(e-fuse),所述一次性可编程存储器用于信息的存储。若一次性可编程存储器出现漏电,会导致芯片出现各种异常情况,例如进入4G模式或者双存储单元(twin cell)模式,从而影响芯片的性能和良率,因此,对芯片中一次性可编程存储器的漏电情况进行检测显得至关重要。对芯片中一次性可编程存储器的漏电情况进行检测的方法是通过测试机台向所述芯片中的所有一次性可编程存储器传输测试指令,之后读取所有一次性可编程存储器的状态。但是,这种方法检测的准确度较低,这是因为:该方法虽然能够检测出漏电情况较为严重(例如出现误烧穿)的一次性可编程存储器,但是容易遗漏漏电情况较轻微的一次性可编程存储器,从而导致存在潜在烧穿风险的不良产品流入后续生产线,造成资源的浪费。
因此,如何提高芯片检测的准确性,避免存在潜在风险的不良产品流入后续生产线,是当前亟待解决的技术问题。
发明内容
本申请中的一些实施例提供了一种芯片检测方法及芯片检测装置,用于解 决芯片检测的准确度较低的问题,以避免存在潜在风险的不良产品流入后续生产线,提高最终芯片产品的良率。
根据一些实施例,本申请提供了一种芯片检测方法,包括如下步骤:
提供待测试的芯片,所述芯片中具有若干一次性可编程存储器;
传输测试信号至所述芯片,使得所述芯片中的所述一次性可编程存储器保持在锁存状态;
探测所述芯片是否发出微光信号,若是,则确认所述一次性可编程存储器存在漏电缺陷。
根据另一些实施例,本申请还提供了一种芯片检测装置,包括:
测试模块,用于传输测试信号至待测试的芯片,使得所述芯片中的所述一次性可编程存储器保持在锁存状态;
探测模块,用于探测所述芯片发出的微光信号;
判断模块,用于判断所述探测模块是否探测到所述微光信号,若是,则确认所述一次性可编程存储器存在漏电缺陷。
本申请提供的芯片检测方法及芯片检测装置,通过在芯片中的一次性可编程存储器处于锁存状态时探测芯片发出微光信号的情况,来判断芯片中的一次性可编程存储器是否存在漏电情况,不仅能检测出已出现误烧穿的一次性可编程存储器,而且还能够检测出漏电情况相对较为轻微的一次性可编程存储器,避免了存在潜在烧穿风险的不良产品流入后续生产线,节约了生产资源,并且有助于提高最终芯片产品的良率。
附图1是本申请具体实施方式中芯片检测方法的流程图;
附图2是本申请具体实施方式中芯片的示意图;
附图3是本申请具体实施方式在对芯片进行检测时的装置示意图;
附图4是本申请具体实施方式探测到的微光信号示意图;
附图5是本申请具体实施方式中芯片检测装置的结构框图。
下面结合附图对本申请提供的芯片检测方法及芯片检测装置的具体实施 方式做详细说明。
本具体实施方式提供了一种芯片检测方法,附图1是本申请具体实施方式中芯片检测方法的流程图,附图2是本申请具体实施方式中芯片的示意图,附图3是本申请具体实施方式在对芯片进行检测时的装置示意图,附图4是本申请具体实施方式探测到的微光信号示意图。如图1-图4所示,本具体实施方式提供的芯片检测方法,包括如下步骤:
步骤S11,提供待测试的芯片20,所述芯片20中具有若干一次性可编程存储器21,如图2所示。
具体来说,所述芯片20可以是DRAM芯片,也可以是其他具有一次性可编程存储器21的芯片。所述芯片20中可以具有多个所述一次性可编程存储器21,且多个所述一次性可编程存储器21在所述芯片20中呈阵列排布,如图2所示。所述一次性可编程存储器21用于信息的存储。
所述的一次性可编程存储器21可以为电熔丝(Electrical Fuse,E-Fuse)结构。以所述芯片20为DRAM芯片为例,具有电熔丝结构的所述一次性可编程存储器21包括有源区(Active Area,AA)211、导电区212、以及位于所述有源区211和所述导电区212之间的介质层区213,所述导电区212用于向所述有源区211传输控制信号。所述有源区211、所述介质层区213和所述导电区212形成一个类似电容的结构。所述导电区212的材料可以是但不限于多晶硅材料。所述介质层213的材料可以是但不限于氧化物材料,例如二氧化硅。所述有源区211中包括晶体管、位线接触部、电容接触部等电性结构。具有所述电熔丝结构的所述一次性可编程存储器21通过熔丝(即所述介质层区213)的熔断来调整所述一次性可编程存储器21的电阻:当所述熔丝未熔断时,所述熔丝呈现高电阻状态,所述有源区211与所述导电区212处于电性隔离的状态;当所述熔丝熔断时,所述熔丝呈现低电阻状态,所述有源区211与所述导电区212之间处于电性导通的状态。通过所述熔丝的熔断与否,可以实现所述芯片20内部的自修复、模式转换等功能。当所述熔丝出现漏电缺陷时,则会影响所述有源区211与所述导电区212之间的电信号传输。本领域技术人员也可以根据实际需要设置其他结构的一次性可编程存储器结构,只要存在漏电缺 陷的所述一次性可编程存储器21在处于压差漏电状态时能够发射出微光信号即可。
步骤S12,传输测试信号至所述芯片20,使得所述芯片20中的所述一次性可编程存储器21保持在锁存状态。
在一些实施例中,使得所述芯片20中的所述一次性可编程存储器21保持在锁存状态的具体步骤包括:
重复执行如下循环步骤,使得所述一次性可编程存储器21保持压差漏电状态,所述循环步骤包括:
传输测试信号至所述芯片20,驱动所述芯片20在预设的测试模式下进行测试;
判断所述测试是否执行完成,若是,则进行下一次循环步骤。
本具体实施方式对所述测试信号的具体内容不作限定,只要能使得所述芯片20中的所述一次性可编程存储器21保持在锁存状态即可。举例来说,在所述芯片20设计过程中,为了满足后续对所述芯片20性能测试的需要,会在所述芯片20中设置DFT(Design For Test,可测试性设计)。所述DFT中包括多个测试模式,以便于后续能够驱动所述芯片20处于不同的工作模式下,从而能够对所述芯片20的多种性能或者多个结构进行测试,以判断所述芯片20是否满足设计需求或者为后续芯片的技术改进提供参考。如图3所示,本具体实施方式可以将所述芯片20置于探测机台30内,并通过线缆33将所述芯片20与位于所述探测机台30外部的测试机台31电连接。通过所述测试机台31向所述芯片20传输测试信号,启动所述DFT中的特定测试模式,从而使得所述芯片32处于所述预设工作模式,已完成预设的测试程序。本具体实施方式中所述的多个是指两个及两个以上。
使得所述芯片20中的所述一次性可编程存储器21保持在锁存状态是指,使得所述芯片中的所述一次性可编程存储器21保持在压差漏电状态。具体来说,执行第一次循环步骤,即通过所述测试机台31向所述芯片20传输测试信号,使得所述芯片20进入一种预设的测试模式,并执行相应的测试程序。此时,所述一次性可编程存储器21处于压差漏电状态,例如所述一次性可编程 存储器21中的所述有源区211的电压为0V、所述导电区212的电压为1.2V,所述一次性可编程存储器21中的所述介质层区213则处于1.2V的压差漏电状态。当所述测试程序执行完成之后,所述一次性可编程存储器21内部的压差会恢复到0V,此时,开始执行第二次循环步骤,即通过所述测试机台31再次向所述芯片传输所述测试信号,使得所述芯片再次进入所述预设的测试模式,并再次执行相应的所述测试程序,从而使得所述一次性可编程存储器21再次处于压差漏电状态。以此类推,重复执行所述循环步骤,使得所述一次性可编程存储器21始终保持在压差漏电状态。所述预设的测试模式可以是DFT中任意的测试模式,只要能够使得所述芯片中的所述一次性可编程存储器21保持在压差漏电状态即可。
步骤S13,探测所述芯片20是否发出微光信号40,若是,则确认所述一次性可编程存储器21存在漏电缺陷。
所述微光信号40为所述一次性可编程存储器21中的失效区域在锁存状态下发出的微光信号。可以预先根据所述一次性可编程存储器21发生漏电缺陷时发射的微光信号的波长范围,选择合适的微光探测方法或者探测镜头,使得探测到的所述芯片20中发出的所述微光信号40仅为一次性可编程存储器21漏电时发出的,从而进一步提高芯片检测的准确度。或者,可以根据所述一次性可编程存储器21在所述芯片20中的位置,探测所述芯片20中所述一次性可编程存储器21所在的位置是否发出所述微光信号40。
在一些实施例中,探测所述芯片20是否发出微光信号的具体步骤包括:
自所述芯片20的背面探测所述芯片20是否发出微光信号。
在一些实施例中,传输测试信号至所述芯片20之前,还包括如下步骤:
将所述芯片20正面201朝上放置于透明载物台302上,并使得一微光探测镜头301朝向所述透明载物台302的背面3022放置。
具体来说,所述芯片20包括相对分布的所述芯片20的正面201和所述芯片20的背面,所述芯片20朝向所述透明载物台302的表面为所述芯片20的背面。所述透明载物台302包括相对分布的透明载物台的正面3021和透明载物台的背面3022,所述透明载物台302朝向所述芯片20的表面为所述透明载 物台的正面3021。本具体实施方式可以将所述芯片20正面朝上置于所述探测机台30内部的所述透明载物台302上,并使得用于探测微光信号的所述微光探测镜头301朝向所述透明载物台302的背面,从而可以及时、准确的对所述芯片20中的所述一次性可编程存储器21因漏电发出的微光信号进行探测。所述透明载物台302的尺寸应远大于所述芯片20的尺寸,以便能够对所述芯片20中任意位置发射的微光信号进行检测。所述微光探测镜头301探测到的微光信号能够直观的反映出所述芯片20中发射微光的所述一次性可编程存储器21的位置以及所述芯片20中发射微光信号的所述一次性可编程存储器21的数量。
在一些实施例中,所述一次性可编程存储器21包括有源区211、位于所述有源区211外部的导电区212、以及位于所述有源区211和所述导电区212之间的介质层区213,所述介质层区213一端连接所述有源区211、另一端连接所述导电区212;
所述微光探测镜头301能够探测波长为700nm~1400nm范围的微光。
在一些实施例中,所述微光探测镜头301为InGaAs镜头。
具体来说,所述一次性可编程存储器20中的所述介质层区213处于压差漏电状态时,被误烧的所述介质层区213中的局部失效区域会有大量的电子与空穴复合,电子的动能转化为光能,从而产生波段为1100nm左右的微光信号。InGaAs镜头包括近红外光电探测器,能够捕捉到波长为700nm~1400nm范围内的微光信号,因此,通过InGaAs镜头能够捕捉到存在漏电缺陷的所述一次性可编程存储器21发射的微光信号。
本领域技术人员可以根据所述一次性可编程存储器21在压差漏电状态下所发射的微光信号的波长范围选择相应的微光探测器,以进一步提高所述芯片20检测的准确度。
在一些实施例中,所述芯片20中具有呈阵列排布的多个一次性可编程存储器21;传输测试信号至所述芯片20的具体步骤包括:
传输测试信号至所述芯片20,使得所述芯片20中的所有所述一次性可编程存储器21均保持在锁存状态。
在一些实施例中,探测所述芯片20是否发出微光信号的具体步骤包括:
探测所述芯片20是否发出微光信号,若是,则获取所述芯片20中出现微光信号的所述一次性可编程存储器的位置。
举例来说,所述芯片20中具有呈阵列排布的1024个所述一次性可编程存储器21。在对所述芯片20进行检测时,可以通过向所述芯片20传输测试信号,使得所述芯片20中的所有的所述一次性可编程存储器21均保持在锁存状态。同时,通过预先建立所述微光探测镜头301探测到的图像平面上的坐标系与所述芯片20上的坐标系之间的映射关系。当所述微光探测镜头301探测到所述微光信号时,根据所述映射关系可以一次性、快速、准确的定位到所述芯片20中存在漏电缺陷的所述一次性可编程存储器20的位置。
不仅如此,本具体实施方式还提供了一种芯片检测装置。附图5是本申请具体实施方式中芯片检测装置的结构框图。本具体实施方式提供的芯片检测装置可以采用如图1-图4所示的方法对芯片进行检测。如图1-图5所示,本具体实施方式提供的芯片检测装置,包括:
测试模块50,用于传输测试信号至待测试的芯片20,使得所述芯片20中的所述一次性可编程存储器21保持在锁存状态;
探测模块51,用于探测所述芯片20发出的微光信号;
判断模块52,用于判断所述探测模块是否探测到所述微光信号,若是,则确认所述一次性可编程存储器21存在漏电缺陷。
具体来说,所述测试模块50可以包括图3中的测试机台31,所述探测模块51可以包括图3中的探测机台30。
在一些实施例中,所述测试模块50重复执行如下循环步骤,使得所述一次性可编程存储器21保持压差漏电状态,所述循环步骤包括:传输测试信号至所述芯片20,驱动所述芯片20在预设的测试模式下进行测试;判断所述测试是否执行完成,若是,则进行下一次循环步骤。
在一些实施例中,所述探测模块51用于自所述芯片20的背面探测所述芯片20发出的微光信号。
在一些实施例中,所述探测模块51包括透明载物台302和微光探测镜头 301,所述芯片20正面朝上放置于所述透明载物台302上,所述微光探测镜头301朝向所述透明载物台302的背面放置。
在一些实施例中,所述一次性可编程存储器21包括有源区211、位于所述有源区211外部的导电区212、以及位于所述有源区211和所述导电区212之间的介质层区213,所述介质层区213一端连接所述有源区211、另一端连接所述导电区212;
所述微光探测镜头301能够探测波长为700nm~1400nm范围的微光。
在一些实施例中,所述微光探测镜头301为InGaAs镜头。
在一些实施例中,所述芯片20中具有呈阵列排布的多个一次性可编程存储器21;
所述测试模块50用于传输测试信号至所述芯片20,使得所述芯片20中的所有所述一次性可编程存储器21均保持在锁存状态。
在一些实施例中,所述判断模块52用于在确认所述探测模块51探测到所述芯片20发出微光信号之后,获取所述芯片20中出现微光信号的所述一次性可编程存储器21的位置。
举例来说,所述判断模块52根据所述探测模块51中的所述微光探测镜头301探测到的微光信号,能够快速的获取出所述芯片20中发射微光的所述一次性可编程存储器21的位置以及所述芯片20中发射微光信号的所述一次性可编程存储器21的数量。
本具体实施方式提供的芯片检测方法及芯片检测装置,通过在芯片中的一次性可编程存储器处于锁存状态时探测芯片发出微光信号的情况,来判断芯片中的一次性可编程存储器是否存在漏电情况,不仅能检测出已出现误烧穿的一次性可编程存储器,而且还能够检测出漏电情况相对较为轻微的一次性可编程存储器,避免了存在潜在烧穿风险的不良产品流入后续生产线,节约了生产资源,并且有助于提高最终芯片产品的良率。
以上所述仅是本申请的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本申请原理的前提下,还可以做出若干改进和润饰,这些 改进和润饰也应视为本申请的保护范围。
Claims (16)
- 一种芯片检测方法,包括如下步骤:提供待测试的芯片,所述芯片中具有若干一次性可编程存储器;传输测试信号至所述芯片,使得所述芯片中的所述一次性可编程存储器保持在锁存状态;探测所述芯片是否发出微光信号,若是,则确认所述一次性可编程存储器存在漏电缺陷。
- 根据权利要求1所述的芯片检测方法,其中,使得所述芯片中的所述一次性可编程存储器保持在锁存状态的具体步骤包括:重复执行如下循环步骤,使得所述一次性可编程存储器保持压差漏电状态,所述循环步骤包括:传输测试信号至所述芯片,驱动所述芯片在预设的测试模式下进行测试;判断所述测试是否执行完成,若是,则进行下一次循环步骤。
- 根据权利要求1所述的芯片检测方法,其中,探测所述芯片是否发出微光信号的具体步骤包括:自所述芯片的背面探测所述芯片是否发出微光信号。
- 根据权利要求3所述的芯片检测方法,其中,传输测试信号至所述芯片之前,还包括如下步骤:将所述芯片正面朝上放置在透明载物台上,并使得一微光探测镜头朝向所述透明载物台的背面放置。
- 根据权利要求4所述的芯片检测方法,其中,所述一次性可编程存储器包括有源区、位于所述有源区外部的导电区、以及位于所述有源区和所述导电区之间的介质层区,所述介质层区一端连接所述有源区、另一端连接所述导电区;所述微光探测镜头能够探测波长为700nm~1400nm范围的微光。
- 根据权利要求5所述的芯片检测方法,其中,所述微光探测镜头为InGaAs镜头。
- 根据权利要求1所述的芯片检测方法,其中,所述芯片中具有呈阵列排布 的多个一次性可编程存储器;传输测试信号至所述芯片的具体步骤包括:传输测试信号至所述芯片,使得所述芯片中的所有所述一次性可编程存储器均保持在锁存状态。
- 根据权利要求7所述的芯片检测方法,其中,探测所述芯片是否发出微光信号的具体步骤包括:探测所述芯片是否发出微光信号,若是,则获取所述芯片中出现微光信号的所述一次性可编程存储器的位置。
- 一种芯片检测装置,包括:测试模块,用于传输测试信号至待测试的芯片,使得所述芯片中的所述一次性可编程存储器保持在锁存状态;探测模块,用于探测所述芯片发出的微光信号;判断模块,用于判断所述探测模块是否探测到所述微光信号,若是,则确认所述一次性可编程存储器存在漏电缺陷。
- 根据权利要求9所述的芯片检测装置,其中,所述测试模块重复执行如下循环步骤,使得所述一次性可编程存储器保持压差漏电状态,所述循环步骤包括:传输测试信号至所述芯片,驱动所述芯片在预设的测试模式下进行测试;判断所述测试是否执行完成,若是,则进行下一次循环步骤。
- 根据权利要求9所述的芯片检测装置,其中,所述探测模块用于自所述芯片的背面探测所述芯片发出的微光信号。
- 根据权利要求11所述的芯片检测装置,其中,所述探测模块包括透明载物台和微光探测镜头,所述芯片正面朝上放置于所述透明载物台上,所述微光探测镜头朝向所述透明载物台的背面放置。
- 根据权利要求12所述的芯片检测装置,其中,所述一次性可编程存储器包括有源区、位于所述有源区外部的导电区、以及位于所述有源区和所述导电区之间的介质层区,所述介质层区一端连接所述有源区、另一端连接所述导电区;所述微光探测镜头能够探测波长为700nm~1400nm范围的微光。
- 根据权利要求13所述的芯片检测装置,其中,所述微光探测镜头为InGaAs镜头。
- 根据权利要求9所述的芯片检测装置,其中,所述芯片中具有呈阵列排布的多个一次性可编程存储器;所述测试模块用于传输测试信号至所述芯片,使得所述芯片中的所有所述一次性可编程存储器均保持在锁存状态。
- 根据权利要求15所述的芯片检测装置,其中,所述判断模块用于在确认所述探测模块探测到所述芯片发出的微光信号之后,获取所述芯片中出现微光信号的所述一次性可编程存储器的位置。
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