WO2022198882A1

WO2022198882A1 - Chip detection method and chip detection apparatus

Info

Publication number: WO2022198882A1
Application number: PCT/CN2021/112035
Authority: WO
Inventors: 周舰波
Original assignee: 长鑫存储技术有限公司
Priority date: 2021-03-25
Filing date: 2021-08-11
Publication date: 2022-09-29
Also published as: CN113075532A

Abstract

A chip detection method and a chip detection apparatus. The chip detection method comprises the following steps: providing a chip (20) to be tested, wherein the chip (20) is provided with a plurality of e-fuses (21) (S11); transmitting a test signal to the chip (20), so that the e-fuses (21) in the chip (20) are kept in a latching state (S12); and detecting whether the chip (20) emits a weak light signal (40), and if so, determining that there is an electrical leakage defect in the e-fuses (21) (S13). By means of the method, not only can an e-fuse (21) that has been falsely burnt through be detected, but an e-fuse (21) that has minor electrical leakage can also be detected, thereby preventing a defective product that has a potential burn-through risk from flowing into a subsequent production line.

Description

Chip detection method and chip detection device

Citations for related applications

This application claims the priority of Chinese Patent Application No. 202110318085.8 filed on March 25, 2021, with the application title "Chip Detection Method and Chip Detection Device", the entire contents of which are appended herewith by reference.

technical field

The present application relates to the technical field of integrated circuit failure analysis, and in particular, to a chip detection method and a chip detection device.

Background technique

Dynamic Random Access Memory (DRAM) is a semiconductor structure commonly used in electronic equipment such as computers, and is composed of multiple memory cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the stored in the capacitor can be read through the bit line. data information in, or write data information into the capacitor.

Chips such as DRAM usually include several one-time programmable memories (e-fuses), and the one-time programmable memories are used for information storage. If the one-time programmable memory leaks, it will cause various abnormal situations in the chip, such as entering 4G mode or dual memory cell (twin cell) mode, which will affect the performance and yield of the chip. It is very important to detect the leakage situation. The method for detecting the leakage of the one-time programmable memory in the chip is to transmit a test command to all the one-time programmable memories in the chip through a testing machine, and then read the state of all the one-time programmable memories. However, the detection accuracy of this method is low, because although this method can detect the one-time programmable memory with serious leakage (for example, burn-through by mistake), it is easy to miss the one-time programmable memory with mild leakage. Programmable memory, so that defective products with potential burn-through risk flow into subsequent production lines, resulting in a waste of resources.

Therefore, how to improve the accuracy of chip detection and prevent potentially risky defective products from flowing into subsequent production lines is a technical problem that needs to be solved urgently.

SUMMARY OF THE INVENTION

Some embodiments of the present application provide a chip detection method and a chip detection device, which are used to solve the problem of low accuracy of chip detection, so as to avoid potential risk of defective products from flowing into subsequent production lines, and to improve the quality of final chip products. Rate.

According to some embodiments, the present application provides a chip detection method, comprising the following steps:

Provide a chip to be tested, the chip has several one-time programmable memories;

transmitting a test signal to the chip so that the one-time programmable memory in the chip remains in a latched state;

It is detected whether the chip emits a low-light signal, and if so, it is confirmed that the one-time programmable memory has a leakage defect.

According to other embodiments, the present application also provides a chip detection device, comprising:

a test module, configured to transmit a test signal to the chip to be tested, so that the one-time programmable memory in the chip is kept in a latched state;

a detection module for detecting the micro-light signal emitted by the chip;

A judgment module is used for judging whether the detection module detects the low-light signal, and if so, confirms that the one-time programmable memory has a leakage defect.

The chip detection method and the chip detection device provided by the present application judge whether the one-time programmable memory in the chip has leakage by detecting the situation that the chip emits a micro-optical signal when the one-time programmable memory in the chip is in a latched state. , not only can detect the one-time programmable memory that has been burned through by mistake, but also can detect the one-time programmable memory with relatively slight leakage, avoiding the bad products with potential burn-through risk from flowing into the subsequent production line, saving production resources and help improve the yield of the final chip product.

Description of drawings

Accompanying drawing 1 is the flow chart of the chip detection method in the specific embodiment of the present application;

2 is a schematic diagram of a chip in a specific embodiment of the present application;

FIG. 3 is a schematic diagram of a device in a specific embodiment of the present application when a chip is detected;

4 is a schematic diagram of a micro-optical signal detected by a specific embodiment of the present application;

FIG. 5 is a structural block diagram of a chip detection device in a specific embodiment of the present application.

Detailed ways

The specific embodiments of the chip detection method and the chip detection device provided by the present application will be described in detail below with reference to the accompanying drawings.

This specific embodiment provides a chip detection method. FIG. 1 is a flowchart of the chip detection method in the specific embodiment of the present application, FIG. 2 is a schematic diagram of the chip in the specific embodiment of the present application, and FIG. 3 is a specific embodiment of the present application. A schematic diagram of the device when the embodiment is used to detect the chip, and FIG. 4 is a schematic diagram of the low-light signal detected by the specific embodiment of the present application. As shown in FIG. 1-FIG. 4, the chip detection method provided by this specific embodiment includes the following steps:

In step S11 , a chip 20 to be tested is provided, and the chip 20 has several one-time programmable memories 21 , as shown in FIG. 2 .

Specifically, the chip 20 may be a DRAM chip, or may be another chip with a one-time programmable memory 21 . The chip 20 may have a plurality of the one-time programmable memories 21, and the plurality of the one-time programmable memories 21 are arranged in an array in the chip 20, as shown in FIG. 2 . The one-time programmable memory 21 is used for information storage.

The one-time programmable memory 21 may be an electrical fuse (Electrical Fuse, E-Fuse) structure. Taking the chip 20 as a DRAM chip as an example, the one-time programmable memory 21 having an electric fuse structure includes an active area (Active Area, AA) 211, a conductive area 212, and the active area 211 and AA. The dielectric layer region 213 between the conductive regions 212 is used for transmitting control signals to the active region 211 . The active region 211 , the dielectric layer region 213 and the conductive region 212 form a capacitor-like structure. The material of the conductive region 212 may be, but not limited to, polysilicon material. The material of the dielectric layer 213 may be, but not limited to, oxide materials, such as silicon dioxide. The active region 211 includes electrical structures such as transistors, bit line contacts, and capacitor contacts. The one-time programmable memory 21 with the electric fuse structure adjusts the resistance of the one-time programmable memory 21 by fusing the fuse (ie, the dielectric layer region 213 ): when the fuse is not blown When the fuse is in a high resistance state, the active region 211 and the conductive region 212 are in a state of electrical isolation; when the fuse is blown, the fuse is in a low resistance state, and the active region 211 and the conductive region 212 are in an electrically isolated state; The source region 211 and the conductive region 212 are in a state of electrical conduction. According to whether the fuse is blown or not, functions such as self-healing and mode switching inside the chip 20 can be realized. When the fuse has a leakage defect, it will affect the electrical signal transmission between the active region 211 and the conductive region 212 . Those skilled in the art can also set up other structures of one-time programmable memory structures according to actual needs, as long as the one-time programmable memory 21 with leakage defect can emit a low-light signal when it is in a voltage-difference leakage state.

Step S12 , transmitting a test signal to the chip 20 , so that the one-time programmable memory 21 in the chip 20 is kept in a latched state.

In some embodiments, the specific steps of keeping the one-time programmable memory 21 in the chip 20 in a latched state include:

The following cycle steps are repeatedly performed, so that the one-time programmable memory 21 maintains the differential voltage leakage state, and the cycle steps include:

transmitting a test signal to the chip 20, and driving the chip 20 to test in a preset test mode;

It is judged whether the execution of the test is completed, and if so, the next cycle step is performed.

The specific embodiment does not limit the specific content of the test signal, as long as the one-time programmable memory 21 in the chip 20 can be kept in a latched state. For example, in the design process of the chip 20, in order to meet the needs of subsequent performance testing of the chip 20, a DFT (Design For Test, design for testability) will be set in the chip 20. The DFT includes a plurality of test modes, so that the chip 20 can be driven to be in different working modes later, so that various performances or structures of the chip 20 can be tested to determine the chip 20 Whether it meets the design requirements or provides a reference for the technical improvement of subsequent chips. As shown in FIG. 3 , in this specific embodiment, the chip 20 can be placed in the detection machine 30 , and the chip 20 is electrically connected to the test machine 31 outside the detection machine 30 through a cable 33 . . The test machine 31 transmits a test signal to the chip 20 to activate a specific test mode in the DFT, so that the chip 32 is in the preset working mode, and the preset test procedure has been completed. The multiple mentioned in this specific embodiment refers to two or more.

Keeping the one-time programmable memory 21 in the chip 20 in a latched state means keeping the one-time programmable memory 21 in the chip in a voltage-difference leakage state. Specifically, the first cycle step is performed, that is, the test signal is transmitted to the chip 20 through the test machine 31, so that the chip 20 enters a preset test mode, and a corresponding test program is executed. At this time, the one-time programmable memory 21 is in a differential voltage leakage state, for example, the voltage of the active region 211 in the one-time programmable memory 21 is 0V, and the voltage of the conductive region 212 is 1.2V, The dielectric layer region 213 in the one-time programmable memory 21 is in a voltage leakage state of 1.2V. After the execution of the test program is completed, the voltage difference inside the one-time programmable memory 21 will return to 0V. At this time, the second cycle step is started, that is, the test machine 31 is used to send the chip to the chip again. The test signal is transmitted, so that the chip enters the preset test mode again, and the corresponding test program is executed again, so that the one-time programmable memory 21 is in a voltage-difference leakage state again. By analogy, the cycle steps are repeatedly performed, so that the one-time programmable memory 21 is always kept in a differential voltage leakage state. The preset test mode may be any test mode in the DFT, as long as the one-time programmable memory 21 in the chip can be kept in a differential voltage leakage state.

Step S13 , detecting whether the chip 20 emits a low-light signal 40 , and if so, confirming that the one-time programmable memory 21 has a leakage defect.

The low-light signal 40 is a low-light signal sent by the failure area in the one-time programmable memory 21 in a latched state. According to the wavelength range of the low-light signal emitted when the leakage defect occurs in the one-time programmable memory 21, a suitable low-light detection method or detection lens can be selected in advance, so that the detected low-light emitted in the chip 20 can be detected in advance. The signal 40 is only sent out when the one-time programmable memory 21 leaks, thereby further improving the accuracy of chip detection. Alternatively, according to the position of the one-time programmable memory 21 in the chip 20 , it can be detected whether the position of the one-time programmable memory 21 in the chip 20 emits the low-light signal 40 .

In some embodiments, the specific step of detecting whether the chip 20 emits a low-light signal includes:

It is detected from the back of the chip 20 whether the chip 20 emits a low-light signal.

In some embodiments, before transmitting the test signal to the chip 20, the following steps are further included:

The chip 20 is placed on the transparent stage 302 with the front surface 201 facing upward, and a low-light detection lens 301 is placed toward the back surface 3022 of the transparent stage 302 .

Specifically, the chip 20 includes a front side 201 of the chip 20 and a back side of the chip 20 that are relatively distributed, and the surface of the chip 20 facing the transparent stage 302 is the back side of the chip 20 . The transparent stage 302 includes a front surface 3021 of the transparent stage and a back surface 3022 of the transparent stage that are relatively distributed. The surface of the transparent stage 302 facing the chip 20 is the front surface of the transparent stage. 3021. In this specific embodiment, the chip 20 can be placed on the transparent stage 302 inside the detection machine 30 with the front side facing up, and the low-light detection lens 301 used for detecting low-light signals is directed toward the The back side of the transparent stage 302 is removed, so that the micro-optical signal emitted by the one-time programmable memory 21 in the chip 20 due to electric leakage can be detected timely and accurately. The size of the transparent stage 302 should be much larger than the size of the chip 20 , so that the micro-optical signal emitted from any position in the chip 20 can be detected. The low-light signal detected by the low-light detection lens 301 can intuitively reflect the location of the one-time programmable memory 21 in the chip 20 that emits low-light signals and the location of the one-time programmable memory 21 in the chip 20 that emits low-light signals. The number of one-time programmable memories 21 .

In some embodiments, the one-time programmable memory 21 includes an active region 211 , a conductive region 212 located outside the active region 211 , and a conductive region 212 located between the active region 211 and the conductive region 212 . a dielectric layer region 213, one end of the dielectric layer region 213 is connected to the active region 211, and the other end is connected to the conductive region 212;

The low-light detection lens 301 is capable of detecting low-light with wavelengths ranging from 700 nm to 1400 nm.

In some embodiments, the low-light detection lens 301 is an InGaAs lens.

Specifically, when the dielectric layer region 213 in the one-time programmable memory 20 is in a voltage-difference leakage state, there will be a large number of electrons and holes in the local failure region in the dielectric layer region 213 that has been burned by mistake. Recombination, the kinetic energy of the electrons is converted into light energy, thereby generating a low-light signal with a wavelength of about 1100 nm. The InGaAs lens includes a near-infrared photodetector, which can capture micro-optical signals with wavelengths ranging from 700 nm to 1400 nm. Therefore, the InGaAs lens can capture micro-optical signals emitted by the one-time programmable memory 21 with leakage defects.

Those skilled in the art can select a corresponding micro-optical detector according to the wavelength range of the micro-optical signal emitted by the one-time programmable memory 21 in the differential pressure leakage state, so as to further improve the detection accuracy of the chip 20 .

In some embodiments, the chip 20 has a plurality of one-time programmable memories 21 arranged in an array; the specific steps of transmitting the test signal to the chip 20 include:

A test signal is transmitted to the chip 20 so that all the one-time programmable memories 21 in the chip 20 are kept in a latched state.

It is detected whether the chip 20 sends out a low-light signal, and if so, the position of the one-time programmable memory in which the low-light signal appears in the chip 20 is acquired.

For example, the chip 20 has 1024 one-time programmable memories 21 arranged in an array. When testing the chip 20 , all the one-time programmable memories 21 in the chip 20 can be kept in a latched state by transmitting a test signal to the chip 20 . At the same time, the mapping relationship between the coordinate system on the image plane detected by the low-light detection lens 301 and the coordinate system on the chip 20 is established in advance. When the low-light detection lens 301 detects the low-light signal, the location of the one-time programmable memory 20 with leakage defects in the chip 20 can be located at one time, quickly and accurately according to the mapping relationship. Location.

Not only that, this specific embodiment also provides a chip detection device. FIG. 5 is a structural block diagram of a chip detection device in a specific embodiment of the present application. The chip detection device provided by this specific embodiment can use the method shown in FIG. 1 to FIG. 4 to detect the chip. As shown in FIG. 1 to FIG. 5 , the chip detection device provided by this specific embodiment includes:

The test module 50 is used for transmitting a test signal to the chip 20 to be tested, so that the one-time programmable memory 21 in the chip 20 is kept in a latched state;

The detection module 51 is used to detect the low-light signal emitted by the chip 20;

The judgment module 52 is used for judging whether the detection module detects the low-light signal, and if so, confirms that the one-time programmable memory 21 has a leakage defect.

Specifically, the testing module 50 may include the testing machine 31 shown in FIG. 3 , and the detection module 51 may include the testing machine 30 shown in FIG. 3 .

In some embodiments, the test module 50 repeatedly performs the following cycle steps, so that the one-time programmable memory 21 maintains a voltage-difference leakage state. The cycle steps include: transmitting a test signal to the chip 20 to drive the The chip 20 is tested in a preset test mode; it is determined whether the test is completed, and if so, the next cycle step is performed.

In some embodiments, the detection module 51 is used to detect the micro-optical signal emitted by the chip 20 from the back of the chip 20 .

In some embodiments, the detection module 51 includes a transparent stage 302 and a low-light detection lens 301 , the chip 20 is placed on the transparent stage 302 facing upward, and the low-light detection lens 301 faces The back of the transparent stage 302 is placed.

In some embodiments, the low-light detection lens 301 is an InGaAs lens.

In some embodiments, the chip 20 has a plurality of one-time programmable memories 21 arranged in an array;

The test module 50 is used for transmitting test signals to the chip 20 , so that all the one-time programmable memories 21 in the chip 20 are kept in a latched state.

In some embodiments, the judging module 52 is configured to acquire the one-time programmable memory in the chip 20 in which the low-light signal appears after confirming that the detection module 51 detects that the chip 20 sends out the low-light signal 21 location.

For example, the judging module 52 can quickly obtain the one-time optical signal emitted from the chip 20 according to the low-light signal detected by the low-light detection lens 301 in the detection module 51 . The location of the programming memory 21 and the number of the one-time programmable memories 21 in the chip 20 that emit micro-optical signals.

The chip detection method and the chip detection device provided by this specific embodiment determine whether the one-time programmable memory in the chip exists by detecting the situation that the chip emits a low-light signal when the one-time programmable memory in the chip is in a latched state. Leakage, not only can detect the one-time programmable memory that has been burned through by mistake, but also can detect the one-time programmable memory with relatively slight leakage, which prevents bad products with potential burn-through risk from flowing into the subsequent production line, It saves production resources and helps to improve the yield of the final chip product.

The above are only the preferred embodiments of the present application. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can also be made, and these improvements and modifications should also be regarded as The protection scope of this application.

Claims

A chip detection method, comprising the following steps:

Provide a chip to be tested, the chip has several one-time programmable memories;

transmitting a test signal to the chip so that the one-time programmable memory in the chip remains in a latched state;

It is detected whether the chip emits a low-light signal, and if so, it is confirmed that the one-time programmable memory has a leakage defect.
The chip detection method according to claim 1, wherein the specific step of keeping the one-time programmable memory in the chip in a latched state comprises:

Repeatedly executing the following cycle steps, so that the one-time programmable memory maintains a differential voltage leakage state, and the cycle steps include:

transmitting a test signal to the chip, and driving the chip to test in a preset test mode;

It is judged whether the execution of the test is completed, and if so, the next cycle step is performed.
The chip detection method according to claim 1, wherein the specific step of detecting whether the chip emits a low-light signal comprises:

Whether the chip emits a micro-light signal is detected from the back of the chip.
The chip detection method according to claim 3, wherein before transmitting the test signal to the chip, it further comprises the following steps:

The chip is placed on the transparent stage with the front side facing up, and a low-light detection lens is placed towards the back of the transparent stage.
The chip inspection method of claim 4, wherein the one-time programmable memory includes an active area, a conductive area located outside the active area, and a conductive area located between the active area and the conductive area The dielectric layer region, one end of the dielectric layer region is connected to the active region, and the other end is connected to the conductive region;

The low-light detection lens can detect low-light with wavelengths ranging from 700 nm to 1400 nm.
The chip detection method according to claim 5, wherein the low-light detection lens is an InGaAs lens.
The chip detection method according to claim 1, wherein, the chip has a plurality of one-time programmable memories arranged in an array; The concrete steps of transmitting the test signal to the chip include:

A test signal is transmitted to the chip such that all of the one-time programmable memories in the chip remain in a latched state.
The chip detection method according to claim 7, wherein the specific step of detecting whether the chip emits a low-light signal comprises:

Detect whether the chip emits a low-light signal, and if so, acquire the position of the one-time programmable memory in the chip where the low-light signal appears.
A chip detection device, comprising:

a test module, configured to transmit a test signal to the chip to be tested, so that the one-time programmable memory in the chip is kept in a latched state;

a detection module for detecting the micro-light signal emitted by the chip;

A judgment module is used for judging whether the detection module detects the low-light signal, and if so, confirms that the one-time programmable memory has a leakage defect.
The chip testing device according to claim 9, wherein the test module repeatedly executes the following cycle steps, so that the one-time programmable memory maintains a differential voltage leakage state, the cycle steps comprising:

transmitting a test signal to the chip, and driving the chip to test in a preset test mode;

It is judged whether the execution of the test is completed, and if so, the next cycle step is performed.
The chip detection device according to claim 9, wherein the detection module is used to detect the micro-optical signal emitted by the chip from the back side of the chip.
The chip detection device according to claim 11, wherein the detection module comprises a transparent stage and a low-light detection lens, the chip is placed on the transparent stage with its front side facing upward, and the low-light detection lens Place towards the back of the transparent stage.
The chip inspection apparatus of claim 12, wherein the one-time programmable memory includes an active area, a conductive area located outside the active area, and a conductive area located between the active area and the conductive area The dielectric layer region, one end of the dielectric layer region is connected to the active region, and the other end is connected to the conductive region;

The low-light detection lens can detect low-light with wavelengths ranging from 700 nm to 1400 nm.
The chip detection device according to claim 13, wherein the low-light detection lens is an InGaAs lens.
The chip detection device according to claim 9, wherein the chip has a plurality of one-time programmable memories arranged in an array;

The test module is used for transmitting test signals to the chip, so that all the one-time programmable memories in the chip are kept in a latched state.
The chip detection device according to claim 15, wherein the judging module is configured to acquire the first occurrence of the low-light signal in the chip after confirming that the detection module detects the low-light signal emitted by the chip the location of the programmable memory.