CN110706732B

CN110706732B - Failure analysis method of memory chip

Info

Publication number: CN110706732B
Application number: CN201910972844.5A
Authority: CN
Inventors: 李辉
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-10-14
Filing date: 2019-10-14
Publication date: 2021-04-13
Anticipated expiration: 2039-10-14
Also published as: CN110706732A

Abstract

The invention relates to a failure analysis method of a memory chip, which comprises the following steps: determining a hot spot area where a failure point is located; confirming the word line with leakage; applying bias voltage to the word line with the leakage, and observing the voltage contrast of the bit line in the hot spot area at the same time until finding out a failed bit line with abnormal voltage contrast in the hot spot area; and carrying out failure analysis on the failed bit line. The method can improve the failure analysis efficiency.

Description

Failure analysis method of memory chip

Technical Field

The invention relates to the technical field of semiconductors, in particular to a failure analysis method of a memory chip.

Background

In recent years, Flash Memory (Flash Memory) memories have been developed particularly rapidly. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up, and it has the advantages of high integration level, fast access speed, easy erasing and rewriting, so it is widely used in microcomputer, automation control and other fields. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), the three-dimensional flash memory (3D NAND) technology has been rapidly developed.

Since the memory comprises a plurality of memory cells with repeated structures, when the failure point exists in the memory, how to locate the failure point becomes the most important step in the failure analysis of the memory.

In a 3D NAND memory chip, leakage occurs between the Word Line (WL) and the Bit Line (BL), which is a common failure condition. In the prior art, the positioning accuracy of the failure point between the word line and the bit line is generally low, and the success rate of failure analysis needs to be further improved.

Disclosure of Invention

The invention aims to solve the technical problem of providing a failure analysis method of a memory chip, and improving the failure analysis method.

In order to solve the above problems, an embodiment of the present invention provides a failure analysis method for a memory chip, including: determining a hot spot area where a failure point is located; confirming the word line with leakage; applying bias voltage to the word line with the leakage, and observing the voltage contrast of the bit line in the hot spot area at the same time until finding out a failed bit line with abnormal voltage contrast in the hot spot area; and carrying out failure analysis on the failed bit line.

Optionally, the method further includes: in the process of finding the failed bit line, the bias voltage is adjusted.

Optionally, the bias voltage is in a range of-3V to 3V.

Optionally, the bias voltage is less than 0.

The method of claim 1, wherein the abnormal voltage contrast is a voltage contrast with a luminance greater than other bit lines.

Optionally, an electronic scanning lens is used to observe the voltage contrast of the bit line in the hot spot region.

Optionally, the method further includes: and after the failed bit line is found, storing the position of the failed bit line.

Optionally, the position of the failed bit line is stored by taking a picture through an electronic scanning lens.

Optionally, the electrical parameter of the word line is detected by the nanoprobe, so as to confirm the word line with leakage.

Optionally, the performing failure analysis on the failed bit line includes: and cutting the memory chip by using a focused ion beam to form a test sample including the failure bit line.

Optionally, a contact hole is formed on each word line of the memory chip; and applying the bias voltage to the contact hole on the word line with the leakage current through a nano probe.

Optionally, the hot spot region is determined by one or more of a light emission method or a photoresistance method.

Optionally, the memory chip is a 3D NAND chip.

According to the failure analysis method, the failure bit line with abnormal voltage contrast is observed by adopting the Active Voltage Contrast (AVC), so that accurate positioning can be realized, the failure bit line can be accurately and conveniently observed even for small electric leakage, and the success rate of failure analysis is greatly improved.

In addition, in the positioning process, a memory chip does not need to be masked to a word line layer with current leakage, and only contact holes at the tops of word lines and bit lines need to be exposed, so that the positioning of the failure point is more convenient.

Drawings

FIG. 1 is a schematic structural diagram of a failure analysis method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of biasing a word line that leaks in a hot spot region and observing an abnormal voltage substrate for a failed bit line in accordance with one embodiment of the present invention.

Detailed Description

In some embodiments, it is possible to try to check the abnormal voltage contrast in the hot spot region where the failure point exists or to check whether there is an abnormality in the hot spot region under a high scanning voltage by means of an electronic scanning electron microscope or the like based on the principle of the passive voltage contrast. If an anomaly is seen, a transmission sample is prepared at the exact spot using the focused ion beam. If no abnormity can be seen, the whole hotspot region is wrapped by adopting a focused ion beam, a plane transmission sample is firstly made, and then a section transmission sample is made as required, so that the time consumption is high, and once the sample does not cover the failure point, the whole failure analysis work fails.

To improve the above problem, the following embodiments propose a new failure analysis method. The following describes in detail a specific embodiment of a failure analysis method for a memory chip according to a subsequent embodiment of the present invention with reference to the drawings.

Fig. 1 is a schematic flow chart illustrating a failure analysis method of a memory chip according to an embodiment of the invention.

The failure analysis method of the memory chip comprises the following steps:

step S101: and determining a hot spot area where the failure point is located.

The hot spot region is determined by one or more of the methods of light Emission (EMMI) or optically variable resistance (OBIRCH).

The hot spot area is the area where the failure point in the chip is located. In general, in a memory chip, particularly a 3D NAND memory chip, a short circuit is likely to occur between a Bit Line (BL) and a Word Line (WL), in this embodiment, the failure analysis method is a method for locating a failure point generating a leakage current between the bit line and the word line, and the hot spot region can be understood as a region where the Bit Line (BL) and the Word Line (WL) are short-circuited, and the size of the hot spot region is usually large, in the range of several micrometers, and usually includes one or more logic memory block regions.

The hot spot test can be performed using the EMMI mode of a low-light microscope. The EMMI can be used for detecting photons emitted by the combination of electrons and holes in the chip, so that the EMMI can be used for detecting leakage current in the chip, and the hotspot region in the chip can be positioned by observing the brightness change of each position on the surface of the chip.

OBIRCH may also be used for chip internal resistance anomalies as well as current leakage path analysis. The laser is used to scan the internal connection position of the chip and generate a temperature gradient, so as to generate resistance value change, and the failure area in the chip is positioned by comparing the resistance value change.

The hot spot area in the chip can be determined by only adopting any one of the EMMI method and the OBIRCH method, or the two methods can be combined to determine the hot spot area, so that the positioning accuracy is improved.

Because the memory chip comprises a plurality of memory cells, the density of devices is high, the critical dimension is small, the same word line is simultaneously connected with a plurality of bit lines, and the problem of electric leakage between the bit line and the word line cannot be determined. After identifying the hot spot region, it is necessary to further locate a specific failure point on the bit line that is electrically leaked from the word line.

Step S102: the word line with leakage is identified.

The electrical parameters of the word line can be detected through the nano-probe, so that the word line with leakage can be confirmed. The word lines in the hot spot region can be detected by detecting the resistance, the current and the like of the word lines, so that the word lines with abnormal electrical parameters are found out, and the word lines with abnormal electrical parameters are the word lines with electric leakage.

In this embodiment, the specific position of the word line does not need to be exposed, and only the position of the contact hole at the top of the leaky word line needs to be located.

Step S103: and applying bias voltage to the word line with the leakage, and observing the voltage contrast of the bit line in the hot spot area until finding out a failed bit line with abnormal voltage contrast in the hot spot area.

When electrons with certain energy are emitted to the surface of a semiconductor sample, secondary electrons are scattered out of the surface of the sample, certain potential is generated, and a voltage contrast image at a low potential appears brighter. A voltage contrast image may be acquired by scanning the lens electronically.

Since the bottom of the bit line of the memory chip is an NMOS transistor, and a PN junction formed between an N-type active region and a P well is reversely biased, the surface potential on the bit line keeps a higher level, and the voltage contrast image of the bit line in the SEM is darker.

When the electric leakage problem occurs between the bit line and the word line, a short circuit is generated between the failed bit line and the word line, so that the surface potential of the failed bit line and the word line is kept consistent with the surface potential of the word line. Since the word line is insulated from the substrate and the surface potential is generally low, the surface potential of an inactive bit line short-circuited to the word line is lower than the surface potential of bit lines at other positions, so that the voltage contrast luminance is greater than that of other bit lines.

However, since the word line is actually in a floating state, it is easily affected by external charges, so that the potential of the word line is raised, and the surface potential of the failed bit line is still high, and a significant abnormal voltage contrast cannot be observed, thereby failing to perform the location of the failed point. Or, even when the leakage current is small, the abnormal voltage contrast cannot be observed.

In order to avoid the above problem, in the embodiment of the present invention, a word line having a leakage is biased so that the potential of the word line is lowered, and thus the potential of a failed bit line having a leakage with the word line is also lowered, so that a voltage contrast image of the failed bit line is brightened. The abnormal voltage contrast is the voltage contrast with the brightness larger than that of other bit lines.

Fig. 2 is a schematic diagram of applying a bias voltage to a word line with leakage in a hot spot region and observing an abnormal voltage substrate of a failed bit line according to an embodiment of the present invention.

Taking a 3D NAND chip as an example, a contact hole 202 is formed on each word line of the memory chip; the bias voltage is applied to the contact hole 202 on the word line with the leakage through the nano probe 201, and when an abnormal voltage contrast occurs in the bit line 203 in the hot spot region, the bit line is a failure bit line 203 a.

In one embodiment, the bias voltage may range from-3V to 3V.

When the applied bias voltage is not enough to cause the potential of the failed bit line to drop to the point where an obvious abnormal voltage contrast occurs, the magnitude of the bias voltage may be further adjusted, for example, the magnitude of the bias voltage is gradually reduced until the failed bit line where the abnormal voltage contrast occurs in the hot spot region is found out. To improve the detection efficiency, the bias voltage may be made smaller than 0 so that the potential on the word line is made smaller than that of the normal bit line as soon as possible, improving the positioning efficiency.

Step S104: and carrying out failure analysis on the failed bit line.

Before a failed bit line is found for failure analysis, the location of the failed bit line also needs to be saved.

In one embodiment, a photograph of the failed bit line with abnormal voltage contrast may be taken through an electronic scanning lens. Because each logic storage block is physically separated, the position of the storage block where the failed bit line is located in the whole storage chip and the specific position of the failed bit line in the storage block can be distinguished on a photo, and therefore the failed bit line can be successfully found out in the subsequent sample preparation.

In another embodiment, in order to further improve the efficiency of locating the failed bit line in the memory chip during the actual failure analysis process, after the failed bit line with abnormal voltage contrast is found, a needle is inserted at or near the position of the failed bit line through a nano probe to mark the failed bit line, so as to locate the failed bit line during the subsequent preparation of the test sample.

Performing a failure analysis on the failed bit line comprises: and cutting the memory chip by using a Focused Ion Beam (FIB) to form a test sample including the failure bit line. The memory chip can be thinned through the focused ion beam to form a test sample with a smaller size, and the failed bit line is subsequently analyzed through means such as SEM and TEM. The test sample has small size, and the difficulty of preparing the sample by FIB is reduced.

In the foregoing embodiment, the 3D NAND chip is taken as an example, and in other embodiments, other memory chips, such as SRAM and DRAM memory chips, can locate and analyze the failure point where the leakage occurs between the bit line and the word line by using the foregoing method.

In the specific implementation mode of the invention, the Active Voltage Contrast (AVC) is adopted to observe the failed bit line with abnormal voltage contrast, so that accurate positioning can be realized, the failed bit line can be accurately and conveniently observed even for small leakage, and the success rate of failure analysis is greatly improved.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A failure analysis method of a memory chip, comprising:

determining a hot spot area where a failure point is located;

confirming the word line with leakage;

applying bias voltage to the word line with the leakage, and observing the voltage contrast of the bit line in the hot spot area at the same time until finding out a failed bit line with abnormal voltage contrast in the hot spot area;

and carrying out failure analysis on the failed bit line.

2. The method of analyzing the failure of the memory chip according to claim 1, further comprising: in the process of finding the failed bit line, the bias voltage is adjusted.

3. The method of claim 1, wherein the bias voltage is in a range of-3V to 3V.

4. The method of claim 1, wherein the bias voltage is less than 0.

5. The method of claim 1, wherein the abnormal voltage contrast is a voltage contrast with a luminance greater than other bit lines.

6. The method of claim 1, wherein an electron scanning lens is used to observe the voltage contrast of the bit lines in the hot spot region.

7. The method of analyzing the failure of the memory chip according to claim 1, further comprising: and after the failed bit line is found, storing the position of the failed bit line.

8. The method of claim 7, wherein the position of the failed bit line is stored by taking a picture through an electronic scanning lens.

9. The method of claim 1, wherein the electrical parameters of the word line are detected by the nanoprobe to confirm the presence of the word line with leakage.

10. The method of claim 1, wherein the performing the failure analysis on the failed bit line comprises: and cutting the memory chip by using a focused ion beam to form a test sample including the failure bit line.

11. The method of claim 1, wherein each word line of the memory chip has a contact hole formed thereon; and applying the bias voltage to the contact hole on the word line with the leakage current through a nano probe.

12. The method of claim 1, wherein the hot spot region is determined by one or more of a light emission method or a photoresistive method.

13. The method of analyzing the failure of the memory chip according to claim 1, wherein the memory chip is a 3D NAND chip.