CN113538376B - Defect positioning method, device and equipment of storage array and readable storage medium - Google Patents

Defect positioning method, device and equipment of storage array and readable storage medium Download PDF

Info

Publication number
CN113538376B
CN113538376B CN202110801540.XA CN202110801540A CN113538376B CN 113538376 B CN113538376 B CN 113538376B CN 202110801540 A CN202110801540 A CN 202110801540A CN 113538376 B CN113538376 B CN 113538376B
Authority
CN
China
Prior art keywords
voltage contrast
defect
contour
detection
coordinates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110801540.XA
Other languages
Chinese (zh)
Other versions
CN113538376A (en
Inventor
王文琪
王班
陈金星
马霏霏
吴佳琪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN202110801540.XA priority Critical patent/CN113538376B/en
Publication of CN113538376A publication Critical patent/CN113538376A/en
Application granted granted Critical
Publication of CN113538376B publication Critical patent/CN113538376B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/12—Edge-based segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/181—Segmentation; Edge detection involving edge growing; involving edge linking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/60—Analysis of geometric attributes
    • G06T7/66—Analysis of geometric attributes of image moments or centre of gravity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/70—Determining position or orientation of objects or cameras
    • G06T7/73—Determining position or orientation of objects or cameras using feature-based methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Geometry (AREA)
  • Image Analysis (AREA)

Abstract

The application provides a defect positioning method, device and equipment of a storage array and a readable storage medium, wherein the method comprises the following steps: carrying out gray scale processing on the detection image of the storage array to obtain gray scale values of a plurality of voltage contrast in the detection image, wherein the voltage contrast indicates possible defects of the detection position corresponding to the storage array; identifying a plurality of voltage contrast contours in the gray-scale processed detection image; acquiring coordinates of a plurality of detection positions according to the identified contour so as to establish a corresponding relation with the detection positions; and locating the defects of the storage array according to the gray values and the corresponding relations. The defect positioning method can ensure that huge voltage liner data is automatically batched under the condition of unchanged detection image quality, and can obtain a defect positioning result after running for a few seconds, thereby avoiding repeated and manual operation on the data.

Description

Defect positioning method, device and equipment of storage array and readable storage medium
Technical Field
The present application relates to the field of semiconductors, and more particularly, to a defect localization method, apparatus, device, and readable storage medium for a storage array.
Background
In manufacturing a three-dimensional memory array, a step region is formed at an end of a stacked structure including insulating layers and conductive gate layers alternately stacked, contact holes (CT) connected to the gate layers are etched on each step, and then the contact holes are filled to form conductive plugs, so that an electrical signal of the gate layers is extracted by the conductive plugs.
The distribution of the three-dimensional memory array is often adjusted with the technical development and capacity of the memory. When the electric leakage is detected for the contact holes by using electron beams (E-beams), it is difficult to quickly correspond the detected at least hundreds of thousands of bright voltage contrast (Bright Voltage contrast, BVC) to the contact holes, so that the contact hole positions corresponding to the bright voltage contrast representing the defects cannot be found accurately, thereby making the positioning of the defects difficult.
It should be appreciated that this background section is intended to provide, in part, a useful background for understanding the technology, however, that such content does not necessarily fall within the knowledge or understanding of one of skill in the art prior to the filing date of this application.
Disclosure of Invention
The present application provides a method and apparatus for locating defects in a memory array that at least partially solve the above-mentioned problems in the related art.
According to one aspect of the present application, there is provided a defect localization method of a memory array, the method may include: performing gray scale processing on the detection image of the storage array to obtain gray scale values of a plurality of voltage contrast in the detection image, wherein the voltage contrast indicates possible defects of the detection position corresponding to the storage array; identifying contours of the plurality of voltage contrast in the detected image after gray processing; acquiring coordinates of the detection positions according to the identified contour so as to establish a corresponding relation with the detection positions; and locating the defects of the storage array according to the gray values and the corresponding relations.
In one embodiment of the present application, the detection image including the plurality of voltage contrast is obtained by electron beam detection of the detection position of the memory array.
In one embodiment of the present application, the detection location of the memory array comprises an array aperture location.
In one embodiment of the present application, identifying the contours of the plurality of voltage contrast in the detected image after the gradation process includes:
Acquiring a contour point set in the detected image after gray processing; and extracting the profiles of the plurality of voltage contrast from the profile point set in the detection image.
In one embodiment of the present application, extracting the profiles of the plurality of voltage contrast from the set of profile points in the detected image includes: calculating a plurality of contour circumferences based on a contour point set in the detection image; comparing a plurality of contour circumferences with circumference preset values; and responding to the comparison result of the contour perimeter and the perimeter preset value to meet a preset condition, and enabling the contour corresponding to the contour perimeter to correspond to the contour of the voltage contrast.
In one embodiment of the present application, acquiring coordinates of the plurality of the detection positions from the identified contour includes: acquiring contour point coordinates of a plurality of voltage contrast; and screening out the gravity center point coordinates of the contour based on the contour point coordinates as the coordinates of the detection position.
In one embodiment of the present application, screening the coordinates of the center of gravity point of the contour based on the coordinates of the contour point as the coordinates of the detection position includes: obtaining a coordinate set of the gravity center point based on the X coordinate and the Y coordinate set of the contour point; and screening out coordinates of the non-repeated gravity points from the coordinate set of the gravity points as coordinates of the detection position.
In one embodiment of the present application, locating the defect of the storage array according to the gray value and the correspondence includes: determining defects indicated by the voltage contrast according to the gray values; and determining the position of the defect based on the established corresponding relation.
In one embodiment of the present application, determining the defect indicated by the voltage contrast by the gray value includes: comparing the gray values of the plurality of voltage contrast values with a reference value; and responding to the comparison result of the gray value of the voltage contrast and the reference value to accord with a preset condition, and corresponding the voltage contrast to the defect.
In one embodiment of the present application, the method further comprises filling in missing values of coordinates of the detection location.
In one embodiment of the present application, the method is applied to a three-dimensional memory.
In one embodiment of the present application, the three-dimensional memory comprises a three-dimensional nonvolatile memory.
Based on the same inventive concept, another aspect of the present application provides a defect localization apparatus of a memory array, the apparatus may include:
the gray processing module is used for carrying out gray processing on the detection image of the storage array to obtain gray values of a plurality of voltage contrast in the detection image, wherein the voltage contrast indicates possible defects of the detection position corresponding to the storage array; the contour determination module is used for identifying the contours of the voltage contrast in the detection image after gray processing; the position corresponding module is used for acquiring coordinates of the detection positions according to the identified outline so as to establish a corresponding relation with the detection positions; and a defect positioning module, configured to position a defect of the storage array according to the gray value and the correspondence.
In one embodiment of the present application, the profile determination module includes: the contour point acquisition sub-module is used for acquiring a contour point set in the detection image after gray processing; and a contour determination submodule for extracting the contours of the plurality of voltage contrast from the contour point set in the detection image.
In one embodiment of the present application, the defect localization module includes: a defect determination sub-module for determining the defects indicated by the voltage contrast according to the gray values; and a defect positioning sub-module for determining the position of the defect based on the established correspondence.
In one embodiment of the present application, the defect determination submodule includes:
a comparison unit comparing the gray values of the plurality of voltage contrast with a reference value; and a correspondence unit for responding the comparison result of the gray value of the voltage contrast and the reference value to accord with a preset condition, and corresponding the voltage contrast to the defect.
In one embodiment of the present application, the defect positioning device further includes a missing value filling module, configured to fill in missing values of coordinates of the detection location.
In one embodiment of the present application, the memory array comprises a three-dimensional memory.
In one embodiment of the present application, the three-dimensional memory comprises a three-dimensional nonvolatile memory.
Yet another aspect of the present application provides an apparatus, which may include: a memory for storing program instructions; and a processor in communication with the memory to execute the program instructions to implement the method of any of the above.
In yet another aspect, the application provides a readable storage medium, where the computer instructions are configured to cause the computer to perform the method of any one of the above.
According to the defect positioning method provided by the embodiment of the application, the coordinates of the detection position corresponding to the voltage contrast are obtained through contour extraction and contour gravity point coordinate calculation, and a corresponding relation is established between the coordinates and the detection position; the voltage contrast representing the defect is further determined based on the gray value of the voltage contrast, thereby finding a defective detection position.
The defect positioning method can ensure that huge voltage contrast data is automatically batched under the condition of unchanged detection image quality, and a defect positioning result can be obtained after a few seconds of operation, so that repeated and manual operation of the data is avoided, and time and labor are saved; the method is not affected by the array layout and is suitable for popularization and use.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments, made with reference to the following drawings. Wherein:
FIG. 1 is a flow chart of a method for locating defects in a memory array according to an embodiment of the present application.
Fig. 2-6 are schematic diagrams illustrating steps of a defect localization method for a memory array according to an embodiment of the present application.
FIG. 7 is a block diagram of a defect localization apparatus of a memory array according to an embodiment of the present application.
Fig. 8 is a detection image according to an embodiment of the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed description are merely illustrative of exemplary embodiments of the application and are not intended to limit the scope of the application in any way.
In addition, in this application, the order in which the processes of the steps are described does not necessarily indicate the order in which the processes occur in actual practice, unless explicitly defined otherwise or the context may be inferred.
It will be further understood that terms such as "comprises," "comprising," "includes," "including," "having," "containing," "includes" and/or "including" are open-ended, rather than closed-ended, terms that specify the presence of the stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of the following" appears after a list of features listed, it modifies the entire list of features rather than just modifying the individual elements in the list. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and technical terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, embodiments and features of embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a flow chart illustrating a defect localization method 1000 of a memory array according to an embodiment of the present application. As shown in fig. 1, the defect localization method 1000 includes:
s1: performing gray scale processing on the detection image of the storage array to obtain gray scale values of a plurality of voltage contrast in the detection image, wherein the voltage contrast indicates possible defects of the detection position corresponding to the storage array;
s2: identifying contours of the plurality of voltage contrast in the detected image after gray processing;
S3: acquiring coordinates of the detection positions according to the identified contour so as to establish a corresponding relation with the detection positions;
s4: and positioning the defects of the storage array according to the gray values and the corresponding relations.
In the existing detection process, the defect identification and positioning of multiple identical positions of a storage array often need to be manually partitioned and then searched one by one, so that the time consumption is long; while storage array layout is changing with technology development, traditional manual identification and positioning becomes particularly difficult.
According to the defect positioning method of the storage array, as long as the detection image containing the voltage contrast is obtained, the outline of the voltage contrast is automatically identified, and the gravity center point coordinate of the voltage contrast is obtained as the coordinate of the detection position based on the identified outline, so that the corresponding relation is established with the detection position, and when the detection position is defective, the visual appearance of the voltage contrast is different from that of the normal position, therefore, the method can quickly find out the detection position of electric leakage.
The specific process of each step of the above-described preparation method 1000 will be described in detail below with reference to fig. 2 to 5.
Step S1:
in this step, the detected image of the memory array is subjected to gradation processing to obtain gradation values of a plurality of voltage contrast in the detected image. The memory array according to embodiments of the present application may be a three-dimensional NAND memory array. In manufacturing a NAND memory array, a step region is formed at an end of a stacked structure including insulating layers and conductive gate layers alternately stacked, contact holes (CT) connected to the gate layers are etched on each step, and then the contact holes are filled to form conductive plugs, so that an electrical signal of the gate layers is extracted by the conductive plugs.
As the demand for data storage density continues to increase, the number of layers in the stacked structure increases. When forming the contact hole, in order to ensure that the grid electrode layer in the lower layer step relatively close to the substrate can be smoothly led out, the grid electrode layer in the upper layer step relatively far away from the substrate is easily over etched, and etching through (punch through) occurs, so that the adjacent two layers of grid electrode layers are short-circuited through the conductive plug, and the product yield is reduced. It should be understood by those skilled in the art that the three-dimensional memory array detected in the embodiments of the present invention is not limited to devices that complete the entire fabrication process of the three-dimensional memory array, and may be device structures after the fabrication process of the contact hole is performed on the production line.
In the actual detection process, a Voltage Contrast (VC) method is generally used to detect whether a contact hole leaks electricity, where the Voltage Contrast indicates a possible defect at a detection position of a storage array, and reflects the situation of the defect. The principle is that secondary electrons are excited at the bottom of a contact hole by a focused electron beam (E-beam), the quantity of the secondary electrons generated at a defect position is different from that generated at a non-defect position, the transmission efficiency is different, and an image of secondary electron imaging is obtained based on voltage contrast, namely, the image brightness is displayed, so that whether the contact hole has a defect is determined by observing the difference of the image brightness.
Electron beam detection generally includes bright voltage contrast (Bright Voltage Contrast, BVC) and dark voltage contrast (dark voltage contrast, DVC). BVC defect detection may locate leakage-induced defects, and DVC defect detection may include identifying openings resulting from conductive plug defects. In the actual detection process of various defects, the detection range may be one memory chip (the minimum unit capable of independently executing a command or reporting a status) or one memory block (the minimum unit capable of being erased by a single erase operation) on a wafer, the detected contact Kong Liangji is at least hundreds of thousands, and when some contact holes reflected by voltage contrast are diagnosed as electric leakage, it is important to find specific positions of the contact holes in one memory chip or one memory block so as to facilitate subsequent processing.
According to one embodiment of the present application, the plurality of voltage contrast may be a voltage contrast array consistent with a memory array layout, and the detection location may be a detection location array corresponding to the voltage contrast array.
According to one embodiment of the present application, the provided detection image is not limited to the voltage contrast image obtained by detecting the contact hole of the memory array, and any detection image obtained by reflecting the detection position of the defect through the voltage contrast may use the defect positioning method provided by the embodiment of the present application, such as contact Kong Duanlu, channel hole leakage, short circuit, open circuit, word line leakage, and the like. The substrate image including the voltage contrast obtained based on the memory array is generally included in the detection image, and when the number of the voltage contrast is huge, the color of the substrate easily affects the voltage contrast reflecting the defect, so that the gray processing is adopted in step S1 to eliminate the color noise of the background substrate, and the problem that the substrate is difficult to distinguish from the voltage contrast reflecting the defect by the color image or the black-and-white image obtained by binarization is avoided. In addition, the extraction of the gray features of the image is beneficial to the subsequent extraction of the contour features of the image.
In one embodiment of the present application, in step S1, first, a three-dimensional array representing a detected image is read and stored in a Mat data format. Fig. 8 illustrates an exemplary detected image containing dot voltage contrast, wherein the three-dimensional array includes the spatial locations (e.g., length and width) of the image and BGR channels. The number of color channels according to the embodiment of the application is 3, namely, the color channels are distributed into blue (hole), green (Green) and Red (Red), and the value range of each color is 0-255.
The step converts the image in the form of read data into a gray-scale image, i.e. the number of color channels is 1, each pixel value being represented by a luminance value of 0 to 255, where 0 is black and 255 is white.
Illustratively, the gray scale process may include: (1) The computer vision library is provided with an algorithm for gray processing, and the type of the computer vision library can be different according to different applied languages or operating systems or development emphasis points, such as an OpenCV library. (2) And (5) carrying out numerical value averaging or weighted averaging on the BGR three channels to obtain single-channel image information.
Step S2:
in this step, contours of a plurality of voltage contrast are identified in the detected image after gradation processing. The contour extraction of the voltage contrast is a key step of calculating coordinates later, and in order to reduce the influence of background noise to accurately extract the contour of the voltage contrast, as shown in fig. 2, step S2 includes:
s20: acquiring a contour point set in the detected image after gray processing;
s21: and extracting the profiles of the voltage contrast from the profile point set in the detection image.
Illustratively, extracting the profiles of the voltage contrast from the set of profile points in the detected image includes acquiring the profiles of the voltage contrast in the detected image using a computer vision library in which a profile lookup algorithm is provided, by which the profiles of the voltage contrast in the detected image can be found, and drawing the profiles of the voltage contrast. Illustratively, after gray scale processing at step S1, the profile of the voltage contrast is found using, for example, the findContours () function in the OpenCV library. Contours is a vector in which each element represents a contour, each element holds a vector of a set of points consisting of consecutive points, each set of points being a contour. The findContours () function described above obtains a set of contour points containing contour information by defining a retrieval pattern of contours, a retrieval relationship between contours, and an algorithm of the contours.
According to the storage array detection image provided by the embodiment of the application, as the number of voltage contrast in the detection image is huge, the change among the voltage contrast is small and the detection image is limited by image quality, the outline of the non-voltage contrast can be easily found out in the outline searching process, such as a black point in the detection image or an image outline caused by a bulge or a recess of a substrate, and the like, after all outline points are found out, the outline and the outline points corresponding to the voltage contrast are required to be further proposed and screened out from the outline points.
Further, as shown in fig. 3, in the step S21 of extracting a plurality of voltage contrast profiles, first in step S210, a plurality of profile circumferences are calculated based on a set of profile points in a detected image, then in step S211, a plurality of the profile circumferences are compared with a circumference preset value, and finally in step S212, in response to a comparison result of the profile circumference and the circumference preset value meeting a preset condition, a profile corresponding to the profile circumference is corresponding to the voltage contrast profile.
For example, after all the contour point sets in the detected image are acquired in step S20, the length of the contour is calculated by using an arcLength () function in the OpenCV library, and the calculated contour length is compared with a perimeter preset value of the voltage contrast, where the perimeter preset value of the voltage contrast is related to the morphology of the detected position, for example, when the detected position is a contact hole, the perimeter preset value of the voltage contrast may refer to the aperture of the contact hole, and be reflected to the pixel of the image that is the image in the image of the voltage contrast. When the perimeter preset value of the voltage contrast is equal to the aperture of the contact hole, the contour corresponding to the perimeter of the contour is considered to be the contour of the voltage contrast.
In one embodiment of the present application, whether the profile points can be sequentially connected to form a closed pattern may also be used as a condition for extracting and screening the voltage contrast profile, for example: by setting the True or False of the closed image, closed=false represents non-closed, closed=true represents closed, and the perimeter of the closed image is often selected as the contour of the voltage contrast.
In one embodiment of the present application, step S2 may divide the image based on the abrupt change of the gray value, and directly take the boundary of the divided region as the contour.
In one embodiment of the present application, step S2 may extract the contour of the voltage contrast based on deep learning, for example, edge detection using HED (holisticaly-Nested Edge Detection, global nested edge detection), and extracting the contour.
The HED is an algorithm for deep learning edge extraction, and has two characteristics: (1) training and predicting the whole image; (2) multi-scale, multi-layer feature learning, HED automatically learns rich hierarchical representations using a full convolutional network. Illustratively, the contour extraction process of the key parts of the independent target object based on the deep learning is as follows: and after gray processing is carried out in the step S1, removing or hiding the image which does not belong to the voltage contrast in the image to be detected, and carrying out HED algorithm calculation on the image subjected to the removing or hiding process to obtain the contour of the voltage contrast.
Step S3:
in this step, coordinates of a plurality of detection positions are acquired based on the contour identified in the above step S2 to establish correspondence with the detection positions. Based on the detected image of the voltage contrast of the memory array, there is a one-to-one correspondence between the voltage contrast and the detection position, for example, the detection range is a memory block, the detection position is a contact hole, and the contact hole has unique numbers (such as a word line number and a bit line number) in the memory block, and the numbers need to correspond to the detection position and the voltage contrast so as to find out a defective contact hole.
As shown in fig. 4, according to an embodiment of the present application, in the above-described step S3, first, the coordinates of the contour points of the plurality of voltage contrast are acquired in step S30, and then, the coordinates of the center of gravity point of the contour are screened out as the coordinates of the detection position based on the acquired coordinates of the contour points in step S31. And obtaining a coordinate set of the gravity center point based on an X coordinate and a Y coordinate set of the contour point, and then screening out non-repeated gravity center point coordinates from the coordinate set of the gravity center point as the coordinates of the detection position.
Illustratively, the step S30 may convert the contour point vector obtained by the findContours () function in the OpenCV library into a set of X coordinates and Y coordinates by means of vector conversion coordinates, and further obtain the eigenvalue of the image moment M by means of the elements () function, and calculate the contour gravity point coordinate through the following formula:
Wherein: cx denotes the abscissa, i.e. the coordinate in the x-direction of the center of gravity of the profile; cy represents the ordinate, i.e. the coordinate in the y-direction of the centre of gravity of the profile, M 10 、M 00 、M 01 The image moment M is represented by a 10 th order moment, an origin moment, and a 1 st order moment about the center of gravity point, respectively.
As shown in fig. 8, the row direction is the Y direction, the column direction is the X direction, the voltage contrast Y coordinates of the same row are the same, and the voltage contrast X coordinates of the same column are the same, so that the profile points of the voltage contrast acquired in step S30 contain a large number of repeated X coordinates and Y coordinates, and further, a large number of repeated data may exist in the set of the X coordinates and the Y coordinates of the gravity center point obtained by calculation from the repeated X coordinates and Y coordinates, so that a large number of repeated gravity center point coordinates may be obtained, and therefore, the data needs to be cleaned, the repeated gravity center point coordinates are deleted, and a unique coordinate corresponding to each detection position is obtained.
In one embodiment of the present application, after obtaining the unique coordinates corresponding to each voltage contrast profile, the data may be further sorted, and sorted in a small-to-large manner with reference to the Y value and the X value, and due to the process limitation, the coordinates of the detection position in the X direction or the Y direction may have a small deviation, so that two adjacent barycentric coordinates may represent one detection position, and after sorting, one of the two barycentric coordinates having an adjacent distance in the preset range may be further deleted, for example, a distance preset value is set to be 1-2pixel.
The obtained barycentric coordinates are used as coordinates of voltage contrast, and the coordinates are further used as coordinates of detection positions, so that a corresponding relation is established with the detection positions, for example, the corresponding relation corresponds to numbers of the detection positions, and the numbers can be word line numbers and bit line numbers of the detection positions in a storage block or a chip.
In one embodiment of the present application, considering that when two voltage contrast images in a voltage contrast image are connected, it is often difficult to extract the outline as an independent target, so there may be few outlines of voltage contrast that cannot be extracted, and therefore the coordinates of the missing detection position may be filled, and automatic or manual filling may be performed with reference to the coordinates of the adjacent voltage substrates.
In one embodiment of the present application, due to the huge number of detection positions, a deviation of 1-5pixels between the voltage contrast coordinates and the detection position coordinates in the X direction or the Y direction may occur in the process, and thus, the obtained coordinates may be finely tuned by setting a deviation threshold. For example, by dividing the voltage contrast array into 4 partitions in the Y direction, each partition is set with 1 offset in the X direction, the offset varies so that the voltage contrast coordinates correspond to the detection position coordinates.
Step S4:
in this step, defects of the memory array are located according to the gray values and correspondence obtained in step S3. Specifically, as shown in fig. 5, step S4 includes:
s40, determining defects indicated by the voltage contrast according to the gray value; and comparing the gray values of the voltage contrast with the reference value, and responding to the comparison result of the gray values of the voltage contrast and the reference value to meet the preset condition, so as to correspond the voltage contrast with the defect.
S41, determining the position of the defect based on the established corresponding relation.
For example, for larger gray values, a batch processing manner may be adopted, the gray values of the voltage contrast may be compared with the same reference value in batches, for example, a boolean mask may be utilized, the same threshold card may be selected in batches for grouping, the value with gray less than 100 corresponds to True of the boolean mask, the value with gray greater than 100 corresponds to False of the boolean mask, and the correspondence between the coordinates of the detected positions and the detected position numbers is based on the correspondence. It will be appreciated by those skilled in the art that the reference values may be selected as appropriate based on the experience of the developer and the actual process requirements without departing from the teachings of the present invention, and are not limited to the 100 described hereinabove.
The True and False sets of data may be respectively corresponding to the numbers of the detection positions, for example, the gray value of the True set of voltage contrast indicates that the corresponding detection position is leaky, and the memory leak position may be found quickly according to the numbers of the set of detection positions for subsequent processing.
Illustratively, the batch mode of step S4 may be batched in rows or columns to perform parallel computations, saving computing resources.
The defect positioning method provided by the embodiment of the application can be used for defect positioning of the three-dimensional memory, for example, can be used for defect positioning of the three-dimensional nonvolatile memory. The method can carry out batch processing on huge voltage liner data under the condition of ensuring the unchanged quality of the detected image, and can obtain defect positioning results after running for a few seconds, thereby avoiding repeated and manual operation on the data. The defect positioning method is not affected by the array layout, can be used for further analysis in the follow-up, screens out defects with different categories and degrees, and can be used for purposefully analyzing and improving. The positioning method greatly reduces the processing time of the image and can realize the batch and efficient processing of a large array.
There is further provided, in accordance with an embodiment of the present application, a defect localization apparatus 100 of a memory array, as shown in fig. 6, the apparatus including: a gray scale processing module 10, a contour determination module 20, a position correspondence module 30, and a defect localization module 40.
The gray processing module 10 is configured to perform gray processing on a detected image of the storage array to obtain gray values of a plurality of voltage contrast in the detected image, where the storage array may include a three-dimensional memory, and the three-dimensional memory may include a three-dimensional nonvolatile memory. The voltage contrast described by the gray processing module 10 is used to indicate the possible defects at the detection location corresponding to the memory array. The three-dimensional array of the detection image can be read through the cvtColor in the OpenCV library, and the two-dimensional array is output to convert the 3-channel number into the single-channel number for gray processing.
The contour determination module 20 is configured to identify contours of the plurality of voltage contrast values in the detected image after the gray scale processing. The profile determining module 20 includes a first obtaining submodule and a profile determining submodule, where the first obtaining submodule is configured to obtain a set of profile points in the detected image after the gray processing, and find a profile of the voltage contrast by using a findContours () function in an OpenCV library and store the profile in a form of a set of profile points; the contour determination submodule is used for extracting contours of the voltage contrast from a contour point set in the detection image; calculating a plurality of contour circumferences based on the contour point set in the detection image, calculating the circumference of the contour by adopting an arcLength () function in an OpenCV library, and comparing the plurality of contour circumferences with a circumference preset value; and responding to the comparison result of the contour perimeter and the perimeter preset value to meet a preset condition, and enabling the contour corresponding to the contour perimeter to correspond to the contour of the voltage contrast.
The position correspondence module 30 is configured to obtain coordinates of the plurality of detection positions according to the identified contour, so as to establish a correspondence with the detection positions. The position corresponding module 30 includes a second acquiring sub-module and a third acquiring sub-module, where the second acquiring sub-module is configured to acquire coordinates of contour points of a plurality of voltage contrast; and the third acquisition sub-module is used for screening out the barycentric point coordinates of the contour based on the contour point coordinates as the coordinates of the detection position. Based on the X coordinate and Y coordinate set of the contour point, an image moment M can be obtained through a motion () function in an OpenCV library, the coordinate set of the gravity center point is obtained through calculation of the image moment M, the coordinate set contains repeated gravity center point coordinates, and non-repeated gravity center point coordinates are screened out of the coordinate set of the gravity center point to serve as the coordinates of the detection position through data cleaning.
The defect locating module 40 locates the defects of the storage array according to the gray values and the corresponding relations. The defect positioning module 40 comprises a defect determination sub-module and a defect positioning sub-module, wherein the defect determination sub-module is used for determining the defect indicated by the voltage contrast according to the gray value; the defect determination submodule includes: a comparison unit comparing the gray values of the plurality of voltage contrast with a reference value; and a correspondence unit for responding the comparison result of the gray value of the voltage contrast and the reference value to accord with the preset condition, and corresponding the voltage contrast to the defect. The defect positioning sub-module is used for determining the position of the defect based on the established corresponding relation.
The defect positioning device provided by the embodiment of the application can be used for defect positioning of the three-dimensional memory, for example, can be used for defect positioning of the three-dimensional nonvolatile memory.
According to an embodiment of the present application, there is further provided a defect localization apparatus, device, and readable storage medium of a storage array.
As shown in fig. 7, a block diagram of a defect localization apparatus of a memory array according to an embodiment of the present application. The device is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The apparatus may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the application described and/or claimed herein.
As shown in fig. 7, the apparatus includes: one or more processors 701, memory 702, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are interconnected using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In other embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 701 is illustrated in fig. 7.
Memory 702 is a readable storage medium provided herein. The memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method for locating defects in a memory array provided herein. The readable storage medium of the present application stores computer instructions for causing a computer to perform the defect localization method of a storage array provided by the present application.
The memory 702 is used as a non-transitory computer readable storage medium for storing non-transitory software programs, non-transitory computer executable programs, and modules. The processor 701 executes various functional applications of the server and data processing, i.e., implements the defect localization method of the storage array in the above-described method embodiments, by running non-transitory software programs, instructions, and modules stored in the memory 702.
Memory 702 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created according to the use of the apparatus for controlling quality, etc. In addition, the memory 702 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 702 may comprise memory located remotely from processor 701, which may be connected to a defect localization apparatus of the storage array through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The apparatus may further include: an input device 703 and an output device 704. The processor 701, the memory 702, the input device 703 and the output device 704 may be connected by a bus or otherwise, in fig. 7 by way of example.
The input device 703 may receive input numeric or character information and generate key signal inputs related to user settings of the apparatus for controlling quality and control of functions, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, a pointer stick, one or more mouse buttons, a track ball, a joystick, etc. The output device 704 may include a display apparatus, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors), among others. The display device may include, but is not limited to, a Liquid Crystal Display (LCD), a Light Emitting Diode (LED) display, and a plasma display. In some implementations, the display device may be a touch screen.
Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, application specific ASIC (application specific integrated circuit), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
These computing programs (also referred to as programs, software applications, or code) include machine instructions for a programmable processor, and may be implemented in a high-level procedural and/or object-oriented programming language, and/or in assembly/machine language. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and/or device (e.g., magnetic discs, optical disks, memory, programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and/or data to a programmable processor.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a server of a distributed system or a server that incorporates a blockchain. The server can also be a cloud server, or an intelligent cloud computing server or an intelligent cloud host with artificial intelligence technology. The server may be a server of a distributed system or a server that incorporates a blockchain. The server can also be a cloud server, or an intelligent cloud computing server or an intelligent cloud host with artificial intelligence technology.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present application may be performed in parallel, sequentially, or in a different order, provided that the desired results of the technical solutions disclosed in the present application can be achieved, and are not limited herein.
The purpose, technical scheme and beneficial effects of the invention are further described in detail in the detailed description. It is to be understood that the above description is only of specific embodiments of the present invention and is not intended to limit the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (21)

1. The defect positioning method of the storage array comprises the following steps:
carrying out gray scale processing on the detection image of the storage array to obtain gray scale values of a plurality of voltage contrast in the detection image, wherein the detection image is a voltage contrast image, and the voltage contrast indicates that a detection position corresponding to the storage array possibly has a defect;
identifying contours of the plurality of voltage contrast in the detected image after gray processing;
Acquiring coordinates of the corresponding detection position according to the identified contour so as to establish a corresponding relation with the number of the detection position in the storage array; and
and positioning the defects of the storage array according to the gray values and the corresponding relations.
2. The defect localization method of claim 1, wherein the detected image comprising the plurality of voltage contrast is obtained by electron beam detecting the detected location of the storage array.
3. The defect localization method of claim 1, wherein the detection location of the memory array comprises an array aperture location.
4. The defect localization method of claim 1, wherein identifying the contours of the plurality of voltage contrast in the gray-scale processed inspection image comprises:
acquiring a contour point set in the detected image after gray processing; and
and extracting the outlines of the voltage contrast from the outline point set of the detection image.
5. The defect localization method of claim 4, wherein extracting the profiles of the plurality of voltage contrast from the set of profile points of the inspection image comprises:
Calculating a plurality of contour circumferences based on a contour point set in the detection image;
comparing a plurality of contour circumferences with circumference preset values;
and responding to the comparison result of the contour perimeter and the perimeter preset value to meet a preset condition, and enabling the contour corresponding to the contour perimeter to correspond to the contour of the voltage contrast.
6. The defect localization method of claim 5, wherein obtaining coordinates of the corresponding detection location from the identified contour comprises:
acquiring contour point coordinates of a plurality of voltage contrast; and
and screening out the gravity center point coordinates of the contour based on the contour point coordinates as the coordinates of the corresponding detection position.
7. The defect localization method of claim 6, wherein screening out the coordinates of the center of gravity point of the contour as the coordinates of the corresponding detection position based on the coordinates of the contour point comprises:
obtaining a coordinate set of the gravity center point based on the X coordinate and the Y coordinate set of the contour point; and
and screening out coordinates of the non-repeated gravity points from the coordinate set of the gravity points as coordinates of the corresponding detection positions.
8. The defect localization method of claim 1, wherein localizing the defect of the storage array based on the gray value and the correspondence comprises:
Determining defects indicated by the voltage contrast according to the gray values; and
and determining the position of the defect based on the established corresponding relation.
9. The defect localization method of claim 8, wherein determining the voltage contrast indicated defect from the gray values comprises:
comparing the gray values of the plurality of voltage contrast values with a reference value; and
and responding to the comparison result of the gray value of the voltage contrast and the reference value to accord with a preset condition, and corresponding the voltage contrast to the defect.
10. The defect localization method of claim 1, further comprising populating missing values of coordinates of the inspection location.
11. The defect localization method of any one of claims 1-10, wherein the method is applied to a three-dimensional memory.
12. The defect localization method of claim 11, wherein the three-dimensional memory comprises a three-dimensional non-volatile memory.
13. A defect localization apparatus for a memory array, comprising:
the gray processing module is used for carrying out gray processing on the detection image of the storage array to obtain gray values of a plurality of voltage contrast in the detection image, wherein the detection image is a voltage contrast image, and the voltage contrast indicates that a detection position corresponding to the storage array possibly has a defect;
The contour determination module is used for identifying the contours of the voltage contrast in the detection image after gray processing;
the position corresponding module is used for acquiring the corresponding coordinate of the detection position according to the identified contour so as to establish a corresponding relation with the number of the detection position in the storage array; and
and the defect positioning module is used for positioning the defects of the storage array according to the gray values and the corresponding relations.
14. The defect localization apparatus of claim 13, wherein the contour determination module comprises:
the contour point acquisition sub-module is used for acquiring a contour point set in the detection image after gray processing; and
and the contour determination submodule is used for extracting the contours of the voltage contrast from the contour point set of the detection image.
15. The defect localization apparatus of claim 13, wherein the defect localization module comprises:
a defect determination sub-module for determining the defects indicated by the voltage contrast according to the gray values; and
and the defect positioning sub-module is used for determining the position of the defect based on the established corresponding relation.
16. The defect localization apparatus of claim 15, wherein the defect determination submodule comprises:
a comparison unit comparing the gray values of the plurality of voltage contrast with a reference value; and
and the corresponding unit is used for responding the comparison result of the gray value of the voltage contrast and the reference value to accord with a preset condition and corresponding the voltage contrast to the defect.
17. The defect localization apparatus of claim 13, further comprising a missing value filling module for filling missing values of coordinates of the detected location.
18. The defect localization apparatus of any of claims 13-17, wherein the storage array comprises a three-dimensional memory.
19. The defect localization apparatus of claim 18, wherein the three-dimensional memory comprises a three-dimensional non-volatile memory.
20. An apparatus, comprising:
a memory for storing computer instructions;
a processor in communication with the memory to execute the computer instructions to implement the method of any of claims 1-12.
21. A readable storage medium having stored therein computer instructions which, when executed by a processor, implement the method of any of claims 1-12.
CN202110801540.XA 2021-07-15 2021-07-15 Defect positioning method, device and equipment of storage array and readable storage medium Active CN113538376B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110801540.XA CN113538376B (en) 2021-07-15 2021-07-15 Defect positioning method, device and equipment of storage array and readable storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110801540.XA CN113538376B (en) 2021-07-15 2021-07-15 Defect positioning method, device and equipment of storage array and readable storage medium

Publications (2)

Publication Number Publication Date
CN113538376A CN113538376A (en) 2021-10-22
CN113538376B true CN113538376B (en) 2023-08-08

Family

ID=78128128

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110801540.XA Active CN113538376B (en) 2021-07-15 2021-07-15 Defect positioning method, device and equipment of storage array and readable storage medium

Country Status (1)

Country Link
CN (1) CN113538376B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116699456A (en) * 2022-02-28 2023-09-05 宁德时代新能源科技股份有限公司 Leakage detection method and leakage detection device
CN116452621B (en) * 2023-03-10 2023-12-15 广州市易鸿智能装备有限公司 Ideal contour generating algorithm, device and storage medium based on reinforcement learning

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010032308A (en) * 2008-07-28 2010-02-12 Hitachi High-Technologies Corp Defect review device, defect review method, and defect review execution program
CN101995223A (en) * 2009-08-25 2011-03-30 比亚迪股份有限公司 Chip appearance detection method and system
CN102053098A (en) * 2009-11-05 2011-05-11 上海华虹Nec电子有限公司 Method for positioning low impedance tiny flaws in comb metal wire structure
CN102183724A (en) * 2011-01-13 2011-09-14 博嘉圣（福州）微电子科技有限公司 A chip failure analysis method based on measuring voltage effect
CN109215094A (en) * 2017-09-22 2019-01-15 上海联影医疗科技有限公司 phase contrast image generating method and system
CN109686675A (en) * 2018-12-12 2019-04-26 上海华力集成电路制造有限公司 A kind of localization method of failure
CN109768045A (en) * 2017-11-09 2019-05-17 三星电子株式会社 Three-dimensional semiconductor memory device and the method for detecting its electric fault
CN110690133A (en) * 2019-09-05 2020-01-14 长江存储科技有限责任公司 Method and device for detecting semiconductor structure
CN110706732A (en) * 2019-10-14 2020-01-17 长江存储科技有限责任公司 Failure analysis method of memory chip
CN110876279A (en) * 2019-10-12 2020-03-10 长江存储科技有限责任公司 Method for detecting defects in depth features using laser enhanced electron tunneling effect
CN112700440A (en) * 2021-01-18 2021-04-23 上海闻泰信息技术有限公司 Object defect detection method and device, computer equipment and storage medium
CN112951737A (en) * 2021-02-18 2021-06-11 长江存储科技有限责任公司 Method for improving channel hole defect, detection method and detection system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8841933B2 (en) * 2010-09-09 2014-09-23 International Business Machines Corporation Inspection tool and methodology for three dimensional voltage contrast inspection
CN109872304B (en) * 2019-01-17 2022-12-02 京东方科技集团股份有限公司 Image defect detection method and device, electronic device and storage medium

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010032308A (en) * 2008-07-28 2010-02-12 Hitachi High-Technologies Corp Defect review device, defect review method, and defect review execution program
CN101995223A (en) * 2009-08-25 2011-03-30 比亚迪股份有限公司 Chip appearance detection method and system
CN102053098A (en) * 2009-11-05 2011-05-11 上海华虹Nec电子有限公司 Method for positioning low impedance tiny flaws in comb metal wire structure
CN102183724A (en) * 2011-01-13 2011-09-14 博嘉圣（福州）微电子科技有限公司 A chip failure analysis method based on measuring voltage effect
CN109215094A (en) * 2017-09-22 2019-01-15 上海联影医疗科技有限公司 phase contrast image generating method and system
CN109768045A (en) * 2017-11-09 2019-05-17 三星电子株式会社 Three-dimensional semiconductor memory device and the method for detecting its electric fault
CN109686675A (en) * 2018-12-12 2019-04-26 上海华力集成电路制造有限公司 A kind of localization method of failure
CN110690133A (en) * 2019-09-05 2020-01-14 长江存储科技有限责任公司 Method and device for detecting semiconductor structure
CN110876279A (en) * 2019-10-12 2020-03-10 长江存储科技有限责任公司 Method for detecting defects in depth features using laser enhanced electron tunneling effect
CN110706732A (en) * 2019-10-14 2020-01-17 长江存储科技有限责任公司 Failure analysis method of memory chip
CN112700440A (en) * 2021-01-18 2021-04-23 上海闻泰信息技术有限公司 Object defect detection method and device, computer equipment and storage medium
CN112951737A (en) * 2021-02-18 2021-06-11 长江存储科技有限责任公司 Method for improving channel hole defect, detection method and detection system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
电压衬度像技术在IC失效分析中的应用;陈琳;汪辉;;半导体技术(第07期);全文 *

Also Published As

Publication number Publication date
CN113538376A (en) 2021-10-22

Similar Documents

Publication Publication Date Title
CN110060237B (en) Fault detection method, device, equipment and system
US10600247B2 (en) Augmented reality occlusion
CN110544258B (en) Image segmentation method and device, electronic equipment and storage medium
CN113538376B (en) Defect positioning method, device and equipment of storage array and readable storage medium
CN111784663B (en) Method and device for detecting parts, electronic equipment and storage medium
CN109003260A (en) CT image pulmonary nodule detection method, device, equipment and readable storage medium storing program for executing
CN111986178A (en) Product defect detection method and device, electronic equipment and storage medium
KR20200078304A (en) Adversarial training system and method for noisy labels
US11530915B2 (en) Dimension measuring device, dimension measuring method, and semiconductor manufacturing system
KR20210020112A (en) Pattern grouping method based on machine learning
CN113538392B (en) Wafer detection method, wafer detection equipment and storage medium
CN108694265B (en) Intelligent pre-diagnosis system and method for failure risk of design layout
CN113241310B (en) Wafer defect detection method, detection device, detection equipment and readable storage medium
CN113012096B (en) Display screen sub-pixel positioning and brightness extraction method, device and storage medium
KR20210065901A (en) Method, device, electronic equipment and medium for identifying key point positions in images
CN113222967A (en) Wafer detection method and system
CN115082444A (en) Copper pipe weld defect detection method and system based on image processing
CN112070762A (en) Mura defect detection method and device for liquid crystal panel, storage medium and terminal
CN116993654B (en) Camera module defect detection method, device, equipment, storage medium and product
CN113537026B (en) Method, device, equipment and medium for detecting graphic elements in building plan
CN114897799A (en) Defect detection method and device for wafer, detection equipment and storage medium
CN113989619A (en) Storage tank prediction method and device based on deep learning recognition model
Melnyk et al. Detection of defects in printed circuit boards by flood-fill algorithm and distributed cumulative histogram
CN116188502B (en) Method for dividing infrared image of photovoltaic panel, storage medium and electronic device
CN114782710B (en) Image feature extraction method and device and display panel restoration method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant