CN111477262A - Failure analysis method of semiconductor device - Google Patents
Failure analysis method of semiconductor device Download PDFInfo
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- CN111477262A CN111477262A CN202010268633.6A CN202010268633A CN111477262A CN 111477262 A CN111477262 A CN 111477262A CN 202010268633 A CN202010268633 A CN 202010268633A CN 111477262 A CN111477262 A CN 111477262A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B15/00—Measuring arrangements characterised by the use of electromagnetic waves or particle radiation, e.g. by the use of microwaves, X-rays, gamma rays or electrons
- G01B15/04—Measuring arrangements characterised by the use of electromagnetic waves or particle radiation, e.g. by the use of microwaves, X-rays, gamma rays or electrons for measuring contours or curvatures
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/02—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material
- G01N23/04—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material and forming images of the material
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/20—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by using diffraction of the radiation by the materials, e.g. for investigating crystal structure; by using scattering of the radiation by the materials, e.g. for investigating non-crystalline materials; by using reflection of the radiation by the materials
- G01N23/20008—Constructional details of analysers, e.g. characterised by X-ray source, detector or optical system; Accessories therefor; Preparing specimens therefor
- G01N23/2005—Preparation of powder samples therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
- G01N2001/2866—Grinding or homogeneising
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/286—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising
- G01N2001/2873—Cutting or cleaving
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5006—Current
Abstract
The invention provides a failure analysis method of a semiconductor device, which comprises the following steps: performing electrical failure analysis on the semiconductor device to locate a certain failure conductive circuit; performing hotspot grabbing on the certain failed conducting circuit to position the hotspot; and if the hot spot in the certain failed conductive line is not captured, repairing the certain failed conductive line to expose the certain failed conductive line, and capturing the exposed hot spot in the certain failed conductive line to perform the next physical failure analysis. According to the technical scheme, the hot spot can be captured under the condition that the product design is changed, so that the defect position can be quickly and accurately found and the failure reason can be analyzed, and the improvement on the failed product is realized.
Description
Technical Field
The invention relates to the field of integrated circuit manufacturing, in particular to a failure analysis method of a semiconductor device.
Background
Electrical Failure Analysis (EFA) is a Failure Analysis based on Electrical measurements, and mainly works to determine a test structure with a fault in a chip. The electrical failure analysis is based on functional detection, and determines a test structure with a fault by providing an electrical test signal for the chip and analyzing whether the electrical test result conforms to theoretical analysis. The Physical Failure Analysis (PFA) is to obtain values of line width, thickness, and composition of a test structure in a test chip according to requirements, and often, a slice observation is performed on a defect occurrence position to determine the defect occurrence specific position.
In this case, the Failure Analysis (FA, Failure Analysis) is usually performed by using an EMMI (microscope) machine to capture a dynamic hot spot (dynamic hotspot) to narrow the Failure range from one word line (length about 600 μm) or one bit line (length about 300 μm) to within 3 μm, referring to fig. 1, it can be seen that a plurality of word lines 11 and a plurality of bit lines 12 are vertically distributed, the Failure word line 111 is found through the electrical Failure Analysis, and the hot spot on the EMMI machine 111 is used to capture the Failure location of the Failure area, so as to determine the physical property of the Failure area after the Failure Analysis 13.
However, in the actual production process, it often happens that due to different product designs, an electrical test program used in cooperation with the EMMI machine cannot access the inside of a failed word line or bit line, and then the EMMI machine cannot capture a hot spot, so that the cause of the failure cannot be found through further physical failure analysis, and the failed product cannot be improved.
Therefore, a new failure analysis method is needed to be provided, so that a hot spot can be captured even when the product design changes, so that the failed product can be improved after the failure reason is found through subsequent further failure analysis.
Disclosure of Invention
The invention aims to provide a failure analysis method of a semiconductor device, which can capture a hot spot under the condition that the product design is changed, so that the defect position can be quickly and accurately found and the failure reason can be analyzed, thereby improving the failure product.
In order to achieve the above object, the present invention provides a failure analysis method of a semiconductor device, comprising:
providing a semiconductor device, wherein the semiconductor device comprises a plurality of conducting wires;
performing electrical failure analysis on the semiconductor device to locate a certain failure conductive circuit; and the number of the first and second groups,
performing hotspot grabbing on the certain failed conducting circuit to locate the hotspot; if the hot point in the certain failure conducting circuit is grabbed, continuing to perform the next physical failure analysis; and if the hot spot in the certain failed conductive line is not captured, repairing the certain failed conductive line to expose the certain failed conductive line, and capturing the exposed hot spot in the certain failed conductive line to perform the next physical failure analysis.
Optionally, the semiconductor device includes a storage region having a word line and a bit line, and the step of performing an electrical failure analysis on the semiconductor device includes: and performing writing and erasing operations on the storage area to perform electrical test on each word line and bit line in the semiconductor device, and further positioning a certain failed word line or bit line to the certain failed conductive line.
Optionally, the length of the certain failed conductive line is greater than 100 μm; the hot spot is located in a range of no more than 3 μm in diameter.
Optionally, a hot spot is captured from the back of the semiconductor device on the failed conductive circuit, and the hot spot is captured by using a micro-light microscope and a light beam induced resistance change mode.
Optionally, the semiconductor device further includes an electrical structure forming a test loop with the certain failure conductive circuit, and the electrical structure and the certain failure conductive circuit are insulated and isolated from each other by a corresponding dielectric layer; the step of repairing the certain failed conducting circuit comprises the following steps:
grinding the semiconductor device to the dielectric layer;
removing part of the dielectric layer in order to expose the top end points of the certain failure conductive circuit and the electrical structure; and the number of the first and second groups,
and forming a conductive layer on the exposed top end point and the dielectric layer around the top end point.
Optionally, the one failed conductive trace includes at least one of a word line, a bit line and a conductive plug electrically connected to the word line and the bit line, and the electrical structure includes at least one of a word line, a bit line, a well region and a conductive plug electrically connected to the word line, the bit line and the well region respectively.
Optionally, an external power supply is applied to a test loop formed by the failure conductive circuit and the electrical structure through the conductive layer, so as to test a change relationship of current of the test loop along with voltage, and further obtain a leakage direction of a leakage path where the failure conductive circuit is located.
Optionally, the step of capturing the hot spot in the exposed one of the failed conductive traces includes: and providing a fixed voltage for a test loop formed by the certain failure conducting circuit and the electrical structure through the conducting layer so as to use a hot spot machine to grab the hot spot in the certain failure conducting circuit.
Optionally, the step of analyzing physical property failure comprises:
cutting the semiconductor device for multiple times according to the leakage direction and the position of the hot spot, and observing a cutting surface while cutting each time until the semiconductor device is cut to a defect position; and the number of the first and second groups,
and thinning the semiconductor device so as to detect the appearance of the cutting surface at the defect position.
Optionally, the semiconductor device is a memory, and includes a bit line, a word line, a drain region, a gate oxide, a well region, a bit line conductive plug, a word line conductive plug, and a well region conductive plug, and the certain failure conductive line is a word line, a bit line, a word line conductive plug, or a bit line conductive plug; the leakage path is a test loop from a bit line conductive plug to the well region conductive plug through a drain region and a well region below the bit line conductive plug, the leakage direction of the leakage path is that leakage current flows from the bit line conductive plug to the well region conductive plug through the drain region and the well region, and the defect position is located on the leakage path between the bit line conductive plug and the well region conductive plug; or the leakage path is a test loop from a word line to the well region conductive plug through a gate oxide and a well region below the word line, the leakage direction of the leakage path is that leakage current flows from the word line to the well region conductive plug through the gate oxide and the well region, and/or the leakage current flows from the well region conductive plug to the word line through the well region and the gate oxide, and the defect position is located on the leakage path between the word line and the well region conductive plug; or the leakage path is a test loop from a word line to the well region conductive plug through a bit line conductive plug, a drain region and a well region below the bit line conductive plug, the leakage direction of the leakage path is that leakage current flows from the word line to the well region conductive plug through the bit line conductive plug, the drain region and the well region, and the defect position is located on the leakage path between the word line and the well region conductive plug.
Compared with the prior art, the failure analysis method of the semiconductor device has the advantages that the electrical failure analysis is carried out on the semiconductor device, so that a certain failure conductive circuit in the semiconductor device is positioned; performing hotspot grabbing on the certain failed conducting circuit to position the hotspot; if the hot point in the certain failure conducting circuit is grabbed, continuing to perform the next physical failure analysis; if the hot spot in the certain failed conductive circuit is not captured, repairing the certain failed conductive circuit to expose the certain failed conductive circuit, capturing the exposed hot spot in the certain failed conductive circuit to perform next physical failure analysis, capturing the hot spot under the condition that the product design is changed, and further rapidly and accurately finding a defect position and analyzing a failure reason, thereby improving the failed product.
Drawings
FIG. 1 is a schematic diagram of the location of a captured hotspot;
fig. 2 is a flowchart of a method for failure analysis of a semiconductor device according to an embodiment of the present invention;
fig. 3a to 3c are schematic views of the direction of leakage in the semiconductor device according to an embodiment of the present invention.
Wherein the reference numerals of figures 1 to 3c are as follows:
11-word line; 111-failed word line; 12-bit line; 13-hot spot; 20-a substrate; 21-a well region; 211-well region conductive plugs; 212 — a first conductive layer; 22-a drain region; 221-bit line conductive plugs; 222-a second conductive layer; 23-word line; 231-word line conductive plugs; 232-a third conductive layer; 24-gate oxide; 25-a dielectric layer; 26-external power supply.
Detailed Description
In order to make the objects, advantages and features of the present invention clearer, the method for analyzing the failure of the semiconductor device proposed by the present invention is further described in detail with reference to fig. 2 to 3 c. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for analyzing a failure of a semiconductor device, and referring to fig. 2, fig. 2 is a flowchart of a method for analyzing a failure of a semiconductor device according to an embodiment of the present invention, where the method for analyzing a failure of a semiconductor device includes:
step S1, providing a semiconductor device, wherein the semiconductor device comprises a plurality of conducting wires;
step S2, conducting electrical failure analysis on the semiconductor device to locate a certain failure conducting circuit;
step S3, performing hotspot grabbing on the certain failure conducting circuit to locate the hotspot; if the hot point in the certain failure conducting circuit is grabbed, continuing to perform the next physical failure analysis; and if the hot spot in the certain failed conductive line is not captured, repairing the certain failed conductive line to expose the certain failed conductive line, and capturing the exposed hot spot in the certain failed conductive line to perform the next physical failure analysis.
The method for analyzing the failure of the semiconductor device provided in this embodiment will be described in more detail below.
According to step S1, a semiconductor device is provided, which includes a plurality of conductive lines including word lines, bit lines, conductive plugs, metal interconnects, and the like.
According to step S2, an electrical failure analysis is performed on the semiconductor device to locate a certain failed conductive trace. When the semiconductor device includes a memory region having a word line and a bit line, the step of performing an electrical failure analysis on the semiconductor device may include: and performing writing and erasing operations on the storage area to perform electrical test on each word line and each bit line in the semiconductor device, and further positioning to a certain failed word line or bit line to position to the certain failed conductive line. When the semiconductor device includes other conductive circuits, other corresponding electrical test procedures may be used to perform electrical tests (e.g., a current-to-voltage variation relationship) on the other conductive circuits in the semiconductor device to locate the certain failed conductive circuit.
The certain failing conductive line may include at least one of a word line, a bit line, and a conductive plug electrically connected to the word line and the bit line. When the certain failed conductive circuit comprises at least two failed conductive circuits, namely when different types of conductive circuits are electrically connected, the different types of conductive circuits are located in the same failed conductive circuit; for example, the word line and the conductive plug electrically connected to the word line are both disabled (i.e., both have defects), and both belong to the same one of the disabled conductive traces. It should be noted that the range of the certain failing conductive line is not limited to the above category, and may include any conductive structure in the semiconductor device.
The length of the certain failure conducting circuit located by performing electrical failure analysis on the semiconductor device is greater than 100 μm, and at this time, the specific position of the defect in the semiconductor device cannot be determined, and the next failure analysis needs to be performed continuously.
According to the step S3, performing hotspot grabbing on the certain failed conducting circuit to locate the hotspot; if the hot point in the certain failure conducting circuit is grabbed, continuing to perform the next physical failure analysis; and if the hot spot in the certain failed conductive line is not captured, repairing the certain failed conductive line to expose the certain failed conductive line, and capturing the exposed hot spot in the certain failed conductive line to perform the next physical failure analysis.
And performing hotspot grabbing on the certain failure conducting circuit from the back of the semiconductor device, wherein the back of the semiconductor device is the surface of a substrate, the substrate is made of materials known by persons in the art such as silicon, silicon germanium and the like, and laser emitted by a lens on a machine table for grabbing the hotspots can penetrate through the substrate to grab the hotspots in the certain failure conducting circuit. The hot spot can be captured by adopting a low-light-level microscope (EMMI) and a light beam induced resistance change (OBIRCH) mode, the low-light-level microscope can provide a high-sensitivity nondestructive fault positioning mode and can detect and position very weak luminescence, and therefore leakage current visible light generated at defects or abnormal positions in various devices is captured; the beam-induced resistance change mode is that the surface of the device is scanned by using a laser beam under a fixed voltage, partial energy of the laser beam is converted into heat energy, if a defect exists in a conductive circuit in the semiconductor device, the temperature of the defect cannot be rapidly conducted and dispersed through the conductive circuit, the temperature of the defect is increased accumulatively, the resistance of the conductive circuit and the current are further changed, and the defect can be located through the correspondence between a change area and the scanning position of the laser beam. Then, a low-light-level microscope and a beam-induced resistance change mode can be used in combination to grab the hot spot, and the specific steps may include: performing electrical test on the certain failure conducting circuit, and scanning the back surface of the semiconductor device by adopting a laser beam emitted by a light beam induced resistance change mode to locate the defect position in the semiconductor device; and capturing leakage current visible light generated at the position of the defect by using a micro-light microscope, thereby capturing the hot spot in the certain failure conducting circuit.
By capturing the hot spot of the certain failed conducting circuit, the position of the hot spot can be positioned in the range of the diameter not more than 3 mu m, so that the specific failed position can be quickly and accurately positioned and the failure reason can be found, the time required by failure analysis is reduced, the success rate of the failure analysis is improved, and the semiconductor device can be improved according to the failure reason.
However, when the product design is changed, the electric test program used in cooperation with the machine for capturing the hot spot cannot access the inside of the certain failure conductive circuit, and then the machine for capturing the hot spot cannot capture the hot spot, so that the failure reason cannot be found through further physical failure analysis, and the failed product cannot be improved. Therefore, it is necessary to repair the failed conductive trace that cannot be accessed by the electrical test program, so as to perform subsequent electrical test and hot spot capture after the failed conductive trace is exposed.
The semiconductor device further comprises an electrical structure which forms a test loop with the certain failure conductive circuit, the electrical structure is different from the certain failure conductive circuit in the semiconductor device and can form the test loop with the certain failure conductive circuit, and the electrical structure and the certain failure conductive circuit are insulated and isolated from each other through corresponding dielectric layers. The step of repairing the certain failed conducting circuit comprises the following steps: firstly, grinding the semiconductor device to the dielectric layer, and removing the multiple metal layers and other dielectric layers to prepare for the subsequent steps as the multiple metal layers and other dielectric layers are formed on the dielectric layer; then, removing part of the dielectric layer in order to expose the top end points of the certain failure conductive circuit and the electrical structure; and then, forming a conductive layer on the exposed top end point and the dielectric layer around the top end point, so that voltage can be introduced into a test loop formed by the certain failure conductive circuit and the electrical structure through the conductive layer, and further an electrical test program used in cooperation with a machine for capturing hot spots can access the inside of the certain failure conductive circuit, so that the hot spots in the certain failure conductive circuit can be captured. A repair tool may be used to remove a portion of the dielectric layer and form the conductive layer on the exposed top end point and on the dielectric layer around the top end point.
The electrical structure comprises a word line, a bit line, a well region and at least one of conductive plugs electrically connected with the word line, the bit line and the well region respectively. Of course, the scope of the electrical structure is not limited to the above, and may include any conductive structure in the semiconductor device. The repairing machine comprises a focused ion beam machine, wherein the focused ion beam machine can etch the dielectric layer so as to remove the dielectric layer in a partial region; and the focused ion beam machine can grow conductive materials on the exposed top end point and the dielectric layer around the top end point so as to form a conductive layer on the dielectric layer around the top end point.
In addition, after the repairing process is performed on the certain failure conductive circuit, the leakage direction of the leakage path where the certain failure conductive circuit is located may be tested and analyzed, and specifically, an external power supply (i.e., grounding and connecting to a working voltage respectively) may be performed on a test loop formed by the certain failure conductive circuit and the electrical structure through the conductive layer to test a change relationship of a current of the test loop with the voltage, so as to obtain the leakage direction of the leakage path where the certain failure conductive circuit is located by analyzing the change relationship of the current of the test loop with the voltage.
Taking the semiconductor device as an example of a memory, the memory includes a bit line, a word line, a drain region, a gate oxide, a well region, a bit line conductive plug, a word line conductive plug, and a well region conductive plug, the certain failure conductive line is a word line, a bit line, a word line conductive plug, or a bit line conductive plug, and a leakage direction of a leakage path where the certain failure conductive line is located is illustrated as follows: referring to fig. 3a to 3c, a well region 21 is formed on the top of a substrate 20, a well region conductive plug 211, a bit line conductive plug 221 and a word line 23 are formed on the substrate 20, and the well region conductive plug 211, the word line 23 and the bit line conductive plug 221 are isolated by a dielectric layer 25 in an insulating manner, wherein the bottom of the well region conductive plug 211 is electrically connected to the well region 21, the bottom of the bit line conductive plug 221 is electrically connected to a drain region 22 in the well region 21, a gate oxide 24 is formed between the word line 23 and the substrate 20, a word line conductive plug 231 is formed on the top of the word line 23, and a first conductive layer 212, a third conductive layer 232 and a second conductive layer 222 are formed on the tops of the well region conductive plug 211, the word line conductive plug 231 and the bit line conductive plug 221 by using a FIB repair machine. As shown in fig. 3a, the first conductive layer 212 and the second conductive layer 222 are applied with an external power source 26 (i.e. grounded and connected with an operating voltage, respectively), after the electrical test, the leakage path is obtained as a test loop from the bit line conductive plug 221 to the well region conductive plug 211 through the drain region 22 and the well region 21 therebelow, and the leakage direction of the leakage path is that the leakage current flows from the bit line conductive plug 221 to the well region conductive plug 211 through the drain region 22 and the well region 21, and the leakage current breaks the PN junction between the drain region 22 and the well region 21, so that the defect position is located on the leakage path between the bit line conductive plug 221 and the well region conductive plug 211; alternatively, as shown in fig. 3b, the first conductive layer 212 and the third conductive layer 232 are subjected to an external power supply 26 (i.e. grounded and connected to an operating voltage, respectively), after the electrical test, the leakage path is obtained as a test loop from the word line 23 to the well region conductive plug 211 through the gate oxide 24 and the well region 21 therebelow, and the leakage direction of the leakage path is that the leakage current flows from the word line 23 to the well region conductive plug 211 through the gate oxide 24 and the well region 21, and the leakage current flows from the well region conductive plug 211 to the word line 23 through the well region 21 and the gate oxide 24, i.e. the leakage has a bidirectional property, and the defect position is located on the leakage path between the word line 23 and the well region conductive plug 211, of course, the leakage may also have a unidirectional property, i.e. the leakage current flows from the word line 23 to the well region conductive plug 211 through the gate oxide 24 and the well region, leakage current flows from the well region conductive plug 211 through the well region 21, the gate oxide 24, and to the word line 23; alternatively, as shown in fig. 3c, the first conductive layer 212 and the third conductive layer 232 are subjected to an external power supply 26 (i.e. grounded and connected to an operating voltage, respectively), after an electrical test, a leakage path is obtained in a test loop from the word line 23 to the well region conductive plug 211 through the bit line conductive plug 221, the drain region 22 under the bit line conductive plug 221, and the well region 21, and a leakage direction of the leakage path is a leakage current flowing from the word line 23 to the well region conductive plug 211 through the bit line conductive plug 221, the drain region 22, and the well region 21, an actually detected current is an on current of a PN junction, the word line 23 leaks electricity under a negative voltage and does not leak electricity under a positive voltage, and then a defect position is located on the leakage path between the word line 23 and the well region conductive plug 211. The leakage direction of the leakage path where the certain failure conductive circuit is located is not limited to the above example, and the corresponding leakage direction may be obtained by analyzing according to the result of the actual electrical test, so as to perform subsequent physical failure analysis.
Additionally, the step of catching the exposed hot spot in the one of the failed conductive traces may comprise: providing a fixed voltage or a variable voltage to a test loop formed by the certain failure conductive circuit and the electrical structure through the conductive layer to perform electrical test, and scanning the back surface of the semiconductor device by adopting a laser beam emitted in a beam-induced resistance variation mode to locate a defect position in the semiconductor device; and capturing leakage current visible light generated at the position of the defect by using a micro-light microscope, thereby capturing the hot spot in the certain failure conducting circuit.
After the leakage direction of a leakage path where the certain failure conductive circuit is located and the position range of the hot spot are determined, the defect position in the semiconductor device can be obtained through analysis, and further physical property failure analysis can be carried out on the semiconductor device so as to find the defect position and carry out observation analysis. The physical property failure analysis step comprises: firstly, cutting the semiconductor device for multiple times according to the leakage direction and the position of the hot spot, starting from the position range close to the hot spot, gradually cutting the semiconductor device in the direction parallel to the leakage direction of the leakage path from the position range close to the hot spot to gradually cut into the position range of the hot spot and further gradually close to the defect position, cutting by adopting a focused ion beam machine, observing a cutting surface while cutting each time, and stopping cutting until the cutting reaches the defect position, wherein the diameter of the hot spot is within 3 microns; then, it is right to carry out the attenuate semiconductor device, can with semiconductor device attenuate to 100 nm's thickness to make can be with after the attenuate semiconductor device puts into transmission electron microscope etc. board, and then can be right the cutting face of defect position department carries out the appearance and detects the reason of finding out the inefficacy after.
As can be seen from the above steps S1 to S3, when the product design changes and the electrical test program used in cooperation with the machine for capturing the hot spot cannot access the inside of the certain failed conductive circuit, the method of the present invention is adopted to repair the certain failed conductive circuit, so that the electrical test program can access the inside of the certain failed conductive circuit to deeply analyze the inside of the certain failed conductive circuit, and further, the electric leakage direction can be determined, and the hot spot in the certain failed conductive circuit can be captured, thereby providing a determined direction for subsequent physical failure analysis, facilitating quick finding of the failure reason, and improving the failed product.
In addition, each step in the failure analysis method of the semiconductor device is not limited to the above formation sequence, and the sequence of each step can be adaptively adjusted.
In summary, the failure analysis method of the semiconductor device provided by the invention includes: providing a semiconductor device, wherein the semiconductor device comprises a plurality of conducting wires; performing electrical failure analysis on the semiconductor device to locate a certain failure conductive circuit; performing hotspot grabbing on the certain failed conducting circuit to position the hotspot; if the hot point in the certain failure conducting circuit is grabbed, continuing to perform the next physical failure analysis; and if the hot spot in the certain failed conductive line is not captured, repairing the certain failed conductive line to expose the certain failed conductive line, and capturing the exposed hot spot in the certain failed conductive line to perform the next physical failure analysis. The failure analysis method of the semiconductor device can capture the hot spot under the condition that the product design is changed, so that the defect position can be quickly and accurately found and the failure reason can be analyzed, and further the improvement of the failed product is realized.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A failure analysis method of a semiconductor device, comprising:
providing a semiconductor device, wherein the semiconductor device comprises a plurality of conducting wires;
performing electrical failure analysis on the semiconductor device to locate a certain failure conductive circuit; and the number of the first and second groups,
performing hotspot grabbing on the certain failed conducting circuit to locate the hotspot; if the hot point in the certain failure conducting circuit is grabbed, continuing to perform the next physical failure analysis; and if the hot spot in the certain failed conductive line is not captured, repairing the certain failed conductive line to expose the certain failed conductive line, and capturing the exposed hot spot in the certain failed conductive line to perform the next physical failure analysis.
2. The method of failure analysis of a semiconductor device according to claim 1, wherein the semiconductor device includes a memory region having a word line and a bit line, and the step of performing electrical failure analysis on the semiconductor device includes: and performing writing and erasing operations on the storage area to perform electrical test on each word line and bit line in the semiconductor device, and further positioning a certain failed word line or bit line to the certain failed conductive line.
3. The method of failure analysis of a semiconductor device according to claim 1, wherein the length of the certain failure conductive line is greater than 100 μm; the hot spot is located in a range of no more than 3 μm in diameter.
4. The method of claim 1, wherein the certain failed conductive trace is hot-spot captured from a back side of the semiconductor device, and the hot spot is captured using a micro-light microscope and a beam-induced resistance variation pattern.
5. The method for analyzing the failure of the semiconductor device according to claim 1, wherein the semiconductor device further comprises an electrical structure forming a test loop with the certain failure conductive line, and the electrical structure and the certain failure conductive line are insulated and isolated from each other by a corresponding dielectric layer; the step of repairing the certain failed conducting circuit comprises the following steps:
grinding the semiconductor device to the dielectric layer;
removing part of the dielectric layer in order to expose the top end points of the certain failure conductive circuit and the electrical structure; and the number of the first and second groups,
and forming a conductive layer on the exposed top end point and the dielectric layer around the top end point.
6. The method according to claim 5, wherein the certain failed conductive trace comprises at least one of a word line, a bit line and a conductive plug electrically connected to the word line and the bit line, and the electrical structure comprises at least one of a word line, a bit line, a well region and a conductive plug electrically connected to the word line, the bit line and the well region respectively.
7. The method for analyzing the failure of the semiconductor device according to claim 5, wherein an external power supply is applied to a test loop formed by the certain failure conductive trace and the electrical structure through the conductive layer to test a variation relationship of a current of the test loop with a voltage, so as to obtain a leakage direction of a leakage path where the certain failure conductive trace is located.
8. The method of failure analysis of a semiconductor device according to claim 5, wherein the step of capturing the hot spot in the exposed one of the failed conductive lines comprises: and providing a fixed voltage for a test loop formed by the certain failure conducting circuit and the electrical structure through the conducting layer so as to use a hot spot machine to grab the hot spot in the certain failure conducting circuit.
9. The method for failure analysis of a semiconductor device according to claim 7, wherein the step of physical property failure analysis includes:
cutting the semiconductor device for multiple times according to the leakage direction and the position of the hot spot, and observing a cutting surface while cutting each time until the semiconductor device is cut to a defect position; and the number of the first and second groups,
and thinning the semiconductor device so as to detect the appearance of the cutting surface at the defect position.
10. The method according to claim 7, wherein the semiconductor device is a memory and includes bit lines, word lines, drain regions, gate oxides, well regions, bit line conductive plugs, word line conductive plugs, and well region conductive plugs, and the one of the plurality of failure conductive lines is a word line, a bit line, a word line conductive plug, or a bit line conductive plug; the leakage path is a test loop from a bit line conductive plug to the well region conductive plug through a drain region and a well region below the bit line conductive plug, the leakage direction of the leakage path is that leakage current flows from the bit line conductive plug to the well region conductive plug through the drain region and the well region, and the defect position is located on the leakage path between the bit line conductive plug and the well region conductive plug; or the leakage path is a test loop from a word line to the well region conductive plug through a gate oxide and a well region below the word line, the leakage direction of the leakage path is that leakage current flows from the word line to the well region conductive plug through the gate oxide and the well region, and/or the leakage current flows from the well region conductive plug to the word line through the well region and the gate oxide, and the defect position is located on the leakage path between the word line and the well region conductive plug; or the leakage path is a test loop from a word line to the well region conductive plug through a bit line conductive plug, a drain region and a well region below the bit line conductive plug, the leakage direction of the leakage path is that leakage current flows from the word line to the well region conductive plug through the bit line conductive plug, the drain region and the well region, and the defect position is located on the leakage path between the word line and the well region conductive plug.
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