WO2023130578A1 - 存储器的测试方法及测试装置 - Google Patents

存储器的测试方法及测试装置 Download PDF

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WO2023130578A1
WO2023130578A1 PCT/CN2022/081496 CN2022081496W WO2023130578A1 WO 2023130578 A1 WO2023130578 A1 WO 2023130578A1 CN 2022081496 W CN2022081496 W CN 2022081496W WO 2023130578 A1 WO2023130578 A1 WO 2023130578A1
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Prior art keywords
signal
read
tested
read operation
word line
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PCT/CN2022/081496
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English (en)
French (fr)
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刘�东
楚西坤
第五天昊
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长鑫存储技术有限公司
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Priority to US17/857,235 priority Critical patent/US20230223098A1/en
Publication of WO2023130578A1 publication Critical patent/WO2023130578A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Definitions

  • Embodiments of the present disclosure relate to semiconductor manufacturing technology, and relate to but not limited to a memory testing method and testing device.
  • the embodiments of the present disclosure provide a memory testing method and testing device.
  • an embodiment of the present disclosure provides a method for testing a memory, including:
  • At least one word line is activated, at least two read operations are performed on the memory cells to be tested connected to the activated word line;
  • performing at least two read operations on the activated memory cells connected to the word line includes:
  • the performing the first read operation includes:
  • the second read operation includes:
  • a second gate signal is generated to perform a second read operation on the storage unit to be tested.
  • the first read operation generates a first read signal; the second read operation generates a second read signal; the obtaining the output signal corresponding to the second read operation includes :
  • Sensing processing is performed on the second read signal to obtain the output signal.
  • performing sensing processing on the second read signal includes pull-up processing or pull-down processing.
  • the output signal includes a high level signal or a low level signal.
  • the second read signal includes a voltage signal; performing sensing processing on the second read signal to obtain the output signal includes:
  • the output signal is a high level signal
  • the output signal is a low level signal.
  • the method before activating the word line, the method further includes:
  • Preset data is stored in the storage unit to be tested through a first signal, where the first signal includes a high level signal or a low level signal.
  • the determining whether there is a read exception in the storage unit to be tested includes:
  • a plurality of memory cells to be tested are arranged sequentially on the same word line, and among the plurality of memory cells to be tested, at least two adjacent memory cells to be tested have different first signals.
  • the first signals of any two adjacent storage units to be tested are different.
  • the method before activating the word line, the method further includes:
  • the plurality of memory cells under test connected to the same word line through the first signal synchronously store preset data.
  • the output signal is transmitted to a global output bus through a local output bus.
  • an embodiment of the present disclosure provides a device for testing a memory, including:
  • the read module is configured to: after activating at least one word line, perform at least two read operations on the memory cells to be tested connected to the activated word line;
  • the test module is configured to: determine whether there is a read abnormality in the storage unit to be tested according to the output signal obtained after the at least two read operations.
  • the reading module is configured to:
  • the reading module includes:
  • the instruction execution module is configured to:
  • a second gate signal is generated to perform a second read operation on the storage unit to be tested.
  • At least two reading operations are performed in the storage unit to be tested, and the detection result is determined based on the output signal obtained at last.
  • the reading time can be extended.
  • the output signal obtained after multiple readings can more easily reflect the abnormality, which is convenient for detection and improves the accuracy of detection. , to reduce missed detection.
  • FIG. 1 is a flow chart 1 of a memory testing method according to an embodiment of the present disclosure
  • FIG. 2 is a second flowchart of a memory testing method according to an embodiment of the present disclosure
  • FIG. 3 is a third flowchart of a memory testing method according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of data writing and reading in a memory testing method according to an embodiment of the present disclosure
  • FIG. 5 is a structural block diagram of a memory testing device according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of the principle of abnormality detected in a memory testing method according to an embodiment of the present disclosure
  • FIG. 7 is a second schematic diagram of the principle of abnormality detected in a memory testing method according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a method for testing a memory, including:
  • Step S101 after activating at least one word line, perform at least two read operations on the memory cells to be tested connected to the activated word line;
  • Step S102 according to the output signal obtained after the at least two read operations, determine whether there is a read abnormality in the storage unit to be tested.
  • connection points may not be in direct contact, and some connections may be insufficiently isolated, resulting in leakage.
  • These failure locations may be able to read and write correctly during the process of reading and writing, or there may be abnormal reading and writing, but they may not be able to read and write correctly every time.
  • due to the existence of electric leakage, in previous tests, data may be read immediately after writing, and electric leakage has not affected the entire process, so it is difficult to detect. Such missed inspection products may fail in subsequent use, thereby affecting product reliability.
  • multiple readings are used to prolong the data collection time of the reading operation during the testing process, artificially deteriorating the conditions for reading data, and making abnormalities more likely to be highlighted.
  • the memory cell to be tested connected to the word line is turned on, so that the charge of the capacitor or other charge storage node connected to it can be transferred to the connected bit line, and is transferred to the sense amplifier in the sense amplifier. Measuring action changes the potential on the bit line accordingly.
  • at least two read operations are performed, and each read operation will cause charge sharing between the memory cell to be tested and its corresponding connected bit line, thereby affecting the potential on the bit line.
  • the potential on the bit line can be processed by a structure such as a sense amplifier to obtain an output signal. Finally, it can be judged whether there is a reading abnormality in the storage unit to be tested according to whether the output signal satisfies the judgment standard.
  • the reading abnormality here includes not only the abnormality of the memory cell itself, but also the structural abnormality of circuit elements and wires connected to the memory cell. For example, there is leakage between a bit line and an adjacent bit line, between a bit line and a reference bit line, between a bit line and a word line, there is an abnormal contact structure of a memory cell, and there is leakage in a storage capacitor; It is also possible that there is an abnormality in a sense amplifier connected to the memory cell, or an abnormality in various peripheral circuits such as a write signal line.
  • the output data obtained only based on the reading may not be identified because the leakage is not obvious and still meets the normal judgment standard.
  • the leakage is amplified by performing the read operation multiple times, so that the final output signal is more easily affected by the leakage and thus can be identified.
  • performing at least two read operations on the activated memory cells to be tested connected to the word line includes:
  • Step S201 performing a first read operation on the memory cell under test connected to the activated word line
  • Step S202 performing a second read operation on the storage unit to be tested after a predetermined period of time after the first read operation
  • Step S203 acquiring the output signal corresponding to the second read operation.
  • the above at least two read operations can be two, the first read operation can be performed after the addressing and other operations are completed after the word line is activated, and the first read operation can be performed after the word line is activated in normal use.
  • the time is the same, and it can also be extended for a certain period of time.
  • an output signal corresponding to the second read operation can be obtained, and the output signal can more easily reflect whether there is a read abnormality in the storage unit to be tested.
  • the performing the first read operation includes:
  • the second read operation includes:
  • a second gate signal is generated to perform a second read operation on the storage unit to be tested.
  • the read operation is performed based on the read instruction.
  • the memory When the read instruction is detected, the memory will generate a strobe signal strobe and a data channel connected to the bit line, such as strobe the local input and output bus (LIO, Local Input/Output) , so that the voltage on the bit line can be transmitted to the data processing module of the memory through the data channel.
  • a strobe signal strobe and a data channel connected to the bit line, such as strobe the local input and output bus (LIO, Local Input/Output) , so that the voltage on the bit line can be transmitted to the data processing module of the memory through the data channel.
  • the read operation can be performed on the memory cell to be tested through multiple read instructions.
  • the first read operation generates a first read signal; the second read operation generates a second read signal; the obtaining the output signal corresponding to the second read operation includes :
  • Sensing processing is performed on the second read signal to obtain the output signal.
  • the bit line connected to the memory cell and its reference bit line are at the same reference voltage V bleq .
  • the memory cell is turned on, so that the charge in the storage capacitor of the memory cell flows to the bit line, so that the bit line BL and the reference bit line /BL There is a voltage difference between them.
  • this voltage difference is too weak to be used as an output signal for data reading.
  • the bit line is connected to the data channel. It is also necessary to sense and process the signal on the bit line through a circuit structure such as a sense amplifier, so that the voltage of the bit line reaches a level that can be used as an output signal, and then the data channel that is turned on by the above-mentioned strobe signal is output.
  • the sensing process may be to amplify the signal, or to perform other processing such as signal conversion.
  • the tiny voltage signal on the bit line is amplified by the charge stored in the memory cell to obtain an easily identifiable output signal, which is transmitted to an external data processing module through a gated data channel.
  • the output charge of the memory cell is transferred to the bit line to generate a read signal, but it is not necessary to perform sensing processing for each read to output the read signal. Therefore, the sensing process may be performed on the read signal only after the last read operation, for example, two read operations are performed, and the sensing process is performed on the second read signal. And the output signal obtained after the last reading operation sensing process is output through the above output channel.
  • the read operation will cause the charge of the memory cell to flow to the bit line, resulting in a voltage difference between the bit line and the reference bit line. If the read operation is performed again, there will still be a voltage difference between the bit line and the reference bit line. At this time, the voltage signal on the bit line and the reference bit line, such as the above-mentioned second read signal, can be amplified, so that the signal on the bit line is amplified into an output signal, thereby obtaining an output result.
  • a read signal greater than the reference voltage V bleq (for example, the reference voltage is 0.5V) is generated on the bit line, so that the bit line A voltage difference ⁇ V appears between the reference bit line and the bit line voltage V bl at this time is slightly greater than the reference voltage V bleq .
  • the read signal is sensed by the sense amplifier SA, so that the voltage on the bit line is amplified, for example, a voltage of 1V is obtained, and transmitted as an output signal.
  • the output signal is read by the external data processing module, it can be confirmed that the data stored in the memory unit is logic “1” through the fact that the bit line voltage is greater than the reference voltage.
  • the bit line is short-circuited with other bit lines or the reference bit line, the sense amplifier is abnormal, or the data path of the output signal is abnormal, etc.
  • multiple read operations The output signal output at the end may not get the correct data.
  • the bit line read line there is a leakage condition on the bit line read line.
  • the data "1" is stored in the memory cell in advance.
  • the charge of the memory cell is released to the bit line, and the voltage of the bit line should be pulled up slightly, so that there is a voltage difference between it and the reference bit line ⁇ V.
  • the voltage V bl on the bit line is not slightly pulled up normally due to leakage on the read line.
  • the sense amplifier SA cannot sense and amplify the signal, that is, the sense amplifier SA cannot continue to convert the voltage on the bit line V bl is pulled high. Therefore, the data finally read by the external data processing module may be logic "0". At this time, the abnormality can be detected by the difference between the read data and the pre-stored data.
  • the charge of the memory cell is released to the bit line during multiple read operations, so that a voltage difference - ⁇ V appears between the bit line and the reference bit line.
  • the voltage V bl on the bit line is not slightly lowered normally due to leakage on the read line, so that the voltage difference - ⁇ V between the reference bit line and the bit line becomes smaller or there is no voltage difference.
  • the sense amplifier SA also cannot sense and amplify the signal, that is, the sense amplifier SA cannot continue to pull down the voltage V bl on the bit line and simultaneously pull up the signal V /bl on the reference bit line, and the output result may be Logical "1", resulting in an exception that the read data is different from the pre-stored data.
  • the output signal is transmitted to a global output bus through a local output bus.
  • the local output bus can be located in the peripheral circuit of the memory, connected with each word line, and connected with the external data processing module through the global output bus.
  • the output signal can be transmitted to the global data bus (GIO, Global Input/Output) through the local output bus (LIO), and then processed in the data processing module.
  • GIO Global Input/Output
  • LIO local output bus
  • performing sensing processing on the second read signal includes pull-up processing or pull-down processing.
  • the second read signal can be detected by the sense amplifier. Take the signal and pull it up to make it much larger than the reference voltage.
  • the output signal obtained at this time corresponds to logic "1" (this is only an example, and the voltage corresponding to the logic data can also be set according to actual needs).
  • the second read signal can be detected by the sense amplifier.
  • the signal is pulled low so that it is well below the reference voltage.
  • the output signal obtained at this time corresponds to logic "0".
  • the output signal includes a high level signal or a low level signal.
  • the sense amplifier can pull up or pull down the read weak signal to obtain a clearly distinguishable high-level signal or low-level signal.
  • Different output signals can represent different data, for example, a high level signal represents a logic "1", and a low level signal represents a logic "0".
  • the second read signal includes a voltage signal; performing sensing processing on the second read signal to obtain the output signal includes:
  • the output signal of a low level signal is obtained.
  • the voltages of the bit line and the reference bit line are generally equal to the reference voltage, that is, the voltage value of the reference signal in the non-read/write state.
  • the reference voltage that is, the voltage value of the reference signal in the non-read/write state.
  • one of the voltage of the bit line and the voltage of the reference bit line after the reading and sensing process is higher than the reference voltage, and the other is lower than the reference voltage.
  • the external signal processing module can recognize that the read data is "1" (or "0") after receiving a high-level signal through the data bus. If the sensed and processed voltage signal is lower than the reference signal, the output signal is a low level signal. Exemplarily, at this time, the external signal processing module can recognize that the read data is "0" (or “1") when it receives a low-level signal through the data bus.
  • the method before activating the word line, the method further includes:
  • Step S301 storing preset data in the storage unit to be tested through a first signal, where the first signal includes a high level signal or a low level signal.
  • data "1” or data "0” may be pre-stored in the memory cell to be tested. Then, during subsequent reading, it can be judged whether the memory unit and its related circuits are abnormal according to whether the read data is the same as the pre-stored data.
  • the first signal may be input to the storage unit to be tested, so that corresponding charges are stored in components such as storage capacitors of the storage unit to be tested.
  • data "1” when data "1" is written, it can be written through a high-level signal, and when data "0" is written, it can be written through a low-level signal.
  • the determining whether there is a read exception in the storage unit to be tested includes:
  • voltage signals of the same polarity or magnitude may be used to represent the same input data or output data.
  • the first signal used for pre-storing data in the memory unit to be tested is consistent with the output signal obtained by reading. Therefore, by judging whether the output signal is consistent with the first signal corresponding to the stored data, it is judged whether there is an abnormality in the memory unit and its peripheral circuits. If not, it can be determined that there are various possible problems in the storage unit or the peripheral circuit connected to the storage unit, such as leakage, short circuit, disconnection or abnormality of the sense amplifier.
  • a plurality of memory cells to be tested are arranged sequentially on the same word line, and among the plurality of memory cells to be tested, at least two adjacent memory cells to be tested have different first signals.
  • a plurality of memory cells on the same word line can be tested, since the plurality of memory cells to be tested on the same word line may have the possibility of short circuit or leakage between each other, therefore, different methods are used here.
  • the first signal causes at least two differences in the data stored in the storage units to be tested.
  • the first signals of any two adjacent storage units to be tested are different.
  • first signals are used. For example, there are a plurality of memory cells to be tested adjacent to one word line, and the first signal of each memory cell is represented by a A high-level signal and a low-level signal are regularly provided alternately. In this way, the pre-stored data are arranged in a pattern similar to "101010". In this way, if there is leakage between adjacent memory cells, it will be detected more easily, thereby improving the accuracy of detection.
  • the steps of storing data, reading multiple times, and detecting output signals may also be performed on each memory cell to be tested on the same word line.
  • Different data are pre-stored in each detection process, for example, the pre-stored data for the first detection is "101010", the pre-stored data for the second detection is “010101", and the pre-stored data for the third detection is "111111... ", the fourth detection pre-stored data is "000000" and so on.
  • the possible abnormalities can be judged more accurately.
  • prestored data taking 8 bits as an example in various combinations as shown in Table 1 below can be used for detection.
  • the method before activating the word line, the method further includes:
  • the plurality of memory cells under test connected to the same word line through the first signal synchronously store preset data.
  • preset data can be stored synchronously for a plurality of memory cells to be tested. That is to say, the first signal required to store data can be transmitted synchronously through the multiple bit lines connected to the multiple memory cells to be tested, so that the multiple memory cells to be tested connected to the word lines can store data at the same time. In this way, the speed of storing data is relatively fast, and the detection speed can be improved.
  • the state of applying the turn-on voltage can be maintained for the same word line, and then the preset data is stored in batches for a plurality of memory cells to be tested connected to the entire word line, for example, according to one write 8bit (bit ) data at the speed of storage. That is, after the word line is turned on, write data to the 8 memory cells to be tested synchronously, and then write data to the next 8 memory cells to be tested synchronously, until the memory cells connected to the entire word line are written with preset data, Then close the word line.
  • This writing method may be referred to as a "Y-Page" writing method.
  • the data reading operation may also be performed synchronously on memory cells coupled to multiple bit lines (ie, multiple memory cells to be tested on the same word line).
  • multiple bit lines ie, multiple memory cells to be tested on the same word line.
  • complete multiple data read operations of all memory cells to be tested on the word line and the above-mentioned operation of detecting output signals that is, adopt the above-mentioned "Y-Page” read operation.
  • Y-Fast reading method ,As shown in Figure 4.
  • the method of data reading and writing can be decided according to the actual performance of the product.
  • the data read operation may be directly performed on each memory cell on the word line. In this way, the addressing time can be reduced, the detection efficiency can be improved, and the signal change on the word line can be further reduced to save power consumption and the detection speed is fast.
  • an embodiment of the present disclosure provides a memory testing device 100 connected to a memory storage array 200, including:
  • the reading module 501 is configured to: after activating at least one word line, perform at least two read operations on the memory cells to be tested connected to the activated word line;
  • the testing module 502 is configured to: determine whether there is a reading abnormality in the storage unit to be tested according to the output signal obtained after the at least two reading operations.
  • the reading module and the testing module can be realized by various circuit structures in the peripheral circuits of the memory, and can also be the control module of the external controller.
  • the reading module is configured to:
  • the reading module includes:
  • the instruction execution module is configured to:
  • a second gate signal is generated to perform a second read operation on the storage unit to be tested.
  • the embodiment of the present disclosure prolongs the reading time TRCD by adopting multiple reading methods, so that the reading conditions of the bit line leakage or abnormality of the sense amplifier are deteriorated, and thus can be detected more easily.
  • the leakage between the bit lines has not been affected during normal reading, and the sense amplifier SA can still amplify the signal correctly at this time, so that the output signal is a correct signal.
  • the leakage between the bit lines has had a serious impact, and it is difficult for the sense amplifier to amplify correct data, resulting in wrong read data, and then abnormality can be detected.
  • the bit line and the data channel are opened by strobing YS.
  • the leakage between the bit lines is obvious. If the sensing process is performed at this time, it is difficult for the sense amplifier SA to amplify the signal, resulting in The output data is wrong, and even the signal on the bit line is reversely amplified as shown in FIG. 7 because the sense amplifier SA is difficult to correctly sense the signal, resulting in wrong output data.
  • the embodiments of the present disclosure can detect abnormalities by reading twice, that is, by extending the read operation after TRCD, thereby reducing the situation of missed detection, and facilitating timely discovery of abnormalities and timely detection of abnormalities. improve.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be used as a single unit, or two or more units can be integrated into one unit; the above-mentioned integration
  • the unit can be realized in the form of hardware or in the form of hardware plus software functional unit.
  • the detection result is determined by performing at least two read operations in the storage unit to be tested and based on the finally obtained output signal. By reading at least twice, the reading time can be extended. In the case of an abnormality in the storage unit, the output signal obtained after multiple readings can more easily reflect the abnormality, which is convenient for detection and improves the accuracy of detection. , to reduce missed detection.

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Abstract

一种存储器的测试方法及测试装置，所述方法包括：激活至少一条字线后，对激活的所述字线连接的待测存储单元进行至少两次读取操作（S101）；根据所述至少两次读取操作后得到的输出信号，确定所述待测存储单元是否存在读取异常（S102）。

Description

存储器的测试方法及测试装置
相关申请的交叉引用
本公开基于申请号为202210021520.5、申请日为2022年01月10日、发明名称为“存储器的测试方法及测试装置”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及半导体制造技术，涉及但不限于一种存储器的测试方法及测试装置。
背景技术
在存储器的研发与制造过程中，往往需要对存储器进行大量的测试以确定是否存在制造过程中产生的异常。例如，由于产品制造过程中产生的线路短路、接触不良等等情况造成的漏电或者读写异常等现象。由于存储器产品的结构精密且复杂，需要通过一系列电性测试来识别出异常。然而，由于有些异常情况在一般的读写条件下不容易显现出来，但会影响使用寿命以及产品的可靠性。因此，需要一些更为可靠的测试方法，以准确识别出不易显现的异常情况。
发明内容
有鉴于此，本公开实施例提供一种存储器的测试方法及测试装置。
第一方面，本公开实施例提供一种存储器的测试方法，包括：
激活至少一条字线后，对激活的所述字线连接的待测存储单元进行至少两次读取操作；
根据所述至少两次读取操作后得到的输出信号，确定所述待测存储单元是否存在读取异常。
在一些实施例中，所述对激活的所述字线连接的待测存储单元进行至少两次读取操作，包括：
对激活的所述字线连接的所述待测存储单元进行第一读取操作；
在所述第一读取操作后的预定时长后，对所述待测存储单元进行第二读取操作；
获取第二读取操作对应的所述输出信号。
在一些实施例中，所述进行第一读取操作，包括：
根据检测到的第一读取指令，产生第一选通信号以对所述待测存储单元进行第一次读取操作；
所述第二读取操作，包括：
根据检测到的第二读取指令，产生第二选通信号以对所述待测存储单元进行第二次读取操作。
在一些实施例中，所述第一读取操作产生第一读取信号；所述第二读取操作产生第二读取信号；所述获取第二读取操作对应的所述输出信号，包括：
对所述第二读取信号进行感测处理，获得所述输出信号。
在一些实施例中，对所述第二读取信号进行感测处理包括拉高处理或拉低处理。
在一些实施例中，所述输出信号包括高电平信号或低电平信号。
在一些实施例中，所述第二读取信号包括电压信号；所述对所述第二读取信号进行感测处理，获得所述输出信号，包括：
对所述第二读取信号进行感测处理，并将感测处理后的所述电压信号与参考信号比较；
若所述电压信号高于所述参考信号，所述输出信号为高电平信号；
若所述电压信号低于所述参考信号，所述输出信号为低电平信号。
在一些实施例中，激活所述字线前，所述方法还包括：
通过第一信号在所述待测存储单元存入预设数据，所述第一信号包括高电平信号或低电平信号。
在一些实施例中，所述确定所述待测存储单元是否存在读取异常，包括：
判断所述输出信号与所述待测存储单元内存储数据对应的第一信号是否一致，若不一致则存在读取异常。
在一些实施例中，同一条字线上依次排列多个所述待测存储单元，在所述多个待测存储单元中至少存在两个相邻待测存储单元的第一信号不同。
在一些实施例中，任意两个相邻的所述待测存储单元的第一信号均不同。
在一些实施例中，激活所述字线之前，所述方法还包括：
通过所述第一信号在所述同一条字线上连接的多个待测存储单元同步存入预设数据。
在一些实施例中，所述输出信号通过局部输出总线传送至全局输出总线。
第二方面，本公开实施例提供一种存储器的测试装置，包括：
读取模块，被配置为：在激活至少一条字线后，对激活的所述字线连接的待测存储单元进行至少两次读取操作；
测试模块，被配置为：根据所述至少两次读取操作后得到的输出信号，确定所述待测存储单元是否存在读取异常。
在一些实施例中，所述读取模块，被配置为：
对激活的所述字线连接的所述待测存储单元进行第一读取操作；
在所述第一读取操作后的预定时长后，对所述待测存储单元进行第二读取操作；
获取第二读取操作对应的所述输出信号。
在一些实施例中，所述读取模块，包括：
指令执行模块，被配置为：
根据检测到的第一读取指令，产生第一选通信号以对所述待测存储单元进行第一次读取操作；以及
根据检测到的第二读取指令，产生第二选通信号以对所述待测存储单元进行第二次读取操作。
本公开实施例的技术方案，通过对待测存储单元中执行至少两次读取操作，并基于最后得到的输出信号，确定检测结果。通过至少两次读取，可以延长读取的时长，在存储单元存在异常的情况下，则在多次读取后得到的输出信号能够更容易体现出异常，进而便于检测，提升检测的准确率，降低漏检的情况。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
图1为本公开实施例的一种存储器的测试方法的流程图一；
图2为本公开实施例的一种存储器的测试方法的流程图二；
图3为本公开实施例的一种存储器的测试方法的流程图三；
图4为本公开实施例的一种存储器的测试方法中进行数据写入和读取的示意图；
图5本公开实施例的一种存储器的测试装置的结构框图；
图6本公开实施例的一种存储器的测试方法中检测出异常的原理示意图一；
图7本公开实施例的一种存储器的测试方法中检测出异常的原理示意图二。
通过上述附图，已示出本申请明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本申请构思的范围，而是通过参考特定实施例为本领域技术人员说明本申请的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由权利要求书的内容指出。下面结合附图和实施例对本申请的技术方案进一步详细阐述。
如图1所述，本公开实施例提供一种存储器的测试方法，包括：
步骤S101、激活至少一条字线后，对激活的所述字线连接的待测存储单元进行至少两次读取操作；
步骤S102、根据所述至少两次读取操作后得到的输出信号，确定所述待测存储单元是否存在读取异常。
对于存储器的测试，一般是利用与存储器使用过程中类似的读写操作来实现的。激活字线后会进行一次读取操作，根据读取到的电压电平或者读取到的数据与预先写入的数据进行对比，从而确定存储器是否能够正常读取，进而检测出异常的存储单元。
然而，有些存储器在制造的过程中会由于工艺的误差产生性能不足的 情况，例如，有些连接点直接接触不良，有些接线之间隔离不足进而存在漏电。这些失效位置在进行读写的过程中可能能够读写正确，也可能会出现读写异常，但不一定每次都能够读写正确。并且，由于漏电的存在，在以往的测试中可能写入数据后立即读取，整个过程漏电还未产生影响，因而难以检测出来。这种漏检的产品在后续的使用中则可能会失效，进而影响产品可靠性。
因此，在本公开实施例中，在测试过程中采用多次读取的方式延长读取操作采集数据的时长，人为恶化读取数据的条件，使异常情况更容易凸显出来。
在本公开实施例中，激活字线后，字线连接的待测存储单元被打开，使其连接的电容或其他电荷存储节点的电荷能够传递至连接的位线，并在感测放大器的感测作用下相应地改变位线上的电位。这里，进行至少两次读取操作，每次读取操作都会使待测存储单元与其对应连接的位线之间产生电荷的分享，进而影响位线上的电位。
在上述至少两次读取操作后，可以通过感测放大器等结构对位线上的电位进行处理，得到输出的信号。最后，可以根据输出信号是否满足判定的标准来判断待测存储单元是否存在读取异常。
需要说明的是，这里的读取异常，不仅包括存储单元本身的异常，还可以包括存储单元连接的电路元件以及导线等结构的异常。例如，位线与相邻位线之间存在漏电、位线与参考位线之间存在漏电、位线与字线之间存在漏电、存储单元的接触结构存在异常以及存储电容存在漏电等情况；还有可能是与存储单元连接的感测放大器的异常或写入信号线路等各种外围电路的异常。
对于存在上述读取异常的存储单元，仅基于读取得到的输出数据可能由于漏电不明显仍满足正常的判定标准从而无法被识别出来。而在本公开实施例中，通过多次执行读取操作，使得漏电的情况被放大，进而使得最 终的输出信号更容易受到漏电的影响从而能够被识别出来。
在一些实施例中，如图2所示，所述对激活的所述字线连接的待测存储单元进行至少两次读取操作，包括：
步骤S201、对激活的所述字线连接的所述待测存储单元进行第一读取操作；
步骤S202、在所述第一读取操作后的预定时长后，对所述待测存储单元进行第二读取操作；
步骤S203、获取第二读取操作对应的所述输出信号。
上述至少两次读取操作可以为两次，第一读取操作可以在激活字线后完成寻址等操作后进行，第一读取操作在激活字线后可以与正常使用时进行读取操作的时间相同，也可以延长一定的时长后再进行。
第一读取操作后可以等待预定时长再进行第二读取操作，可见，第二读取操作的执行相比于第一读取操作更晚，该第二读取操作执行时的时间相较于正常使用存储器时进行读取操作的时间是更晚的，因此，可以达到恶化检测条件的作用。也就是说，第二读取操作执行时，若存在漏电，则漏电产生的影响会更明显。
因此，在执行第二读取操作后，可以获取第二读取操作对应的输出信号，该输出信号则可以更容易地体现出待测存储单元是否存在读取异常。
在一些实施例中，所述进行第一读取操作，包括：
根据检测到的第一读取指令，产生第一选通信号以对所述待测存储单元进行第一次读取操作；
所述第二读取操作，包括：
根据检测到的第二读取指令，产生第二选通信号以对所述待测存储单元进行第二次读取操作。
读取操作是基于读取指令执行的，在检测到读取指令时，存储器会产生选通信号选通以及连接位线的数据通道，例如选通局部输入输出总线 (LIO，Local Input/Output)，使得位线上的电压能够通过该数据通道传递至存储器的数据处理模块。
因此，在本公开实施例中，可以在激活字线后，多次通过读取指令对待测存储单元执行读取操作。
在一些实施例中，所述第一读取操作产生第一读取信号；所述第二读取操作产生第二读取信号；所述获取第二读取操作对应的所述输出信号，包括：
对所述第二读取信号进行感测处理，获得所述输出信号。
在未进行数据读取时，存储单元所连接的位线及其参考位线都处于相同的参考电压V bleq。在需要进行数据读取时，在存储单元连接的字线上施加开启电压后，存储单元被打开，进而使得存储单元的存储电容内的电荷流向位线，使位线BL与参考位线/BL之间产生电压差。然而，这种电压差非常微弱，不足以作为输出信号来实现数据读取。
因此，要获得读取操作的输出和数据，除了在检测到读取指令时产生选通信号，使得位线与数据通道连接。还需要通过感测放大器等电路结构对位线上的信号进行感测处理，使得位线电压达到能够作为输出信号的量级再通过上述选通信号实现导通的数据通道输出出来。这里，感测处理可以是将信号进行放大处理，也可以是进行信号的转换等其他处理。例如，将存储单元中存储电荷对位线上微小的电压信号进行信号放大处理，得到便于识别的输出信号，并通过选通后的数据通道传递至外部的数据处理模块。
在本公开实施例中，通过进行多次选通操作，使得存储单元的输出的电荷传递至位线，产生读取信号，但不需要每次读取都进行感测处理输出读取信号。因此，这里可以仅在最后一次读取操作后对读取信号进行感测处理，示例性地，进行两次读取操作，并对第二读取信号进行感测处理。并将最后一次读取操作感测处理后得到的输出信号通过上述输出通道输出。
对于整个电路正常的情况，读取操作会使得存储单元的电荷流向位线，导致位线与参考位线之间出现电压差。若再次进行执行读取操作，则位线与参考位线之间仍然会存在电压差。此时可以对位线与参考位线上的电压信号，如上述第二读取信号进行放大处理，使得位线上的信号被放大为输出信号，从而得到输出结果。示例性地，若存储单元存储的数据为“1”，执行读取多次操作后，在位线上产生大于参考电压V bleq(例如，参考电压为0.5V)的读取信号，使得位线与参考位线之间出现电压差△V，此时位线电压V bl略大于参考电压V bleq。此时通过感测放大器SA对该读取信号进行感测处理，使得位线上的电压放大，例如，得到1V的电压，并作为输出信号传递出来。此时，通过外部的数据处理模块读取该输出信号后，可以通过该位线电压大于参考电压确认存储单元存储的数据为逻辑“1”。
然而，如果存储单元所连接的电路存在异常的情况下(例如，位线与其他位线或参考位线短路、感测放大器异常或者输出信号的数据通道存在异常等情况)，多次读取操作最后输出的输出信号可能无法得到正确的数据。
例如，位线读取线路上存在漏电情况。预先在存储单元中存储数据“1”，在多次读取操作的过程中，存储单元的电荷释放到位线，应当将位线电压略微拉高，使其与参考位线之间出现电压差△V。但位线由于读取线路上漏电，导致位线上的电压V bl没有被正常地略微拉高。此时，由于位线与参考位线之间的电压差△V较小或不存在电压差，感测放大器SA则无法感测及放大信号，即感测放大器SA无法继续将位线上的电压V bl拉高。因此，最终外部的数据处理模块读取到的数据可能为逻辑“0”。此时，就可以通过读取到的数据与预存的数据不同检测出异常。
相应地，如果预先在存储单元中存储数据“0”，在多次读取操作的过程中，存储单元的电荷释放到位线，使得位线与参考位线之间出现电压差-△V。但位线由于读取线路上漏电，导致位线上的电压V bl未被正常地略微拉低，使得参考位线与位线上的电压差-△V变小或不存在电压差。此时， 感测放大器SA同样无法感测及放大信号，即感测放大器SA无法继续将位线上的电压V bl拉低同时将参考位线上的信号V /bl拉高，进而输出结果可能为逻辑“1”，导致读取数据不同于预存数据的异常。
可以理解的是，如果存在上述异常的情况下，仅进行一次读取操作，位线上的电压受到短路的影响还未体现，那么仍可能被感测放大器正常放大并输出，使得读出的结果为正确的逻辑“1”，从而导致漏检。但是通过本公开实施例中的方法，通过多次读取操作使得读取数据的条件被恶化，存在的异常则会被放大，进而更容易被读取出来，从而可以减少漏检的概率，提升检测的准确性。
在一些实施例中，所述输出信号通过局部输出总线传送至全局输出总线。
局部输出总线可以位于存储器的外围电路中，与各条字线连接，并与外部数据处理模块通过全局输出总线连接。输出信号可以通过局部输出总线(LIO)传送至全局数据总线(GIO，Global Input/Output)，在进入数据处理模块进行处理。
在一些实施例中，对所述第二读取信号进行感测处理包括拉高处理或拉低处理。
示例性地，若位线电压在存储单元进行电荷分享后与参考电压之间的电压差为正值，即位线上的第二读取信号大于参考电压，则可以通过感测放大器对第二读取信号进行拉高处理，使其远大于参考电压。此时得到的输出信号则对应为逻辑“1”(这里仅为示例，也可以根据实际需求设定逻辑数据所对应的电压大小)。
相应地，若位线电压在存储单元进行电荷分享后与参考电压之间的电压差为负值，即位线上的第二读取信号小于参考电压，则可以通过感测放大器对第二读取信号进行拉低处理，使其远低于参考电压。此时得到的输出信号则对应为逻辑“0”。
在一些实施例中，所述输出信号包括高电平信号或低电平信号。
感测放大器可以将读取到的微弱信号拉高或拉低处理，得到能够明显区分的高电平信号或者低电平信号。不同的输出信号则可以代表不同的数据，例如，高电平信号代表逻辑“1”，低电平信号代表逻辑“0”。
因此，通过输出信号代表的逻辑数据，与预存的数据进行比较，就可以确定待测存储单元是否存在上述读取异常，从而便于进一步排查原因或者进行异常产品的处理。
在一些实施例中，所述第二读取信号包括电压信号；所述对所述第二读取信号进行感测处理，获得所述输出信号，包括：
对所述第二读取信号进行感测处理，并将感测处理后的所述电压信号与参考信号比较；
若所述电压信号高于所述参考信号，则获得高电平信号的所述输出信号；
若所述电压信号低于所述参考信号，则获得低电平信号的所述输出信号。
在本公开实施例中，位线及参考位线的电压在非读写状态下一般为相等的参考电压，即参考信号的电压值。而在读取以及感测处理后的位线电压与参考位线的电压则会有一个大于参考电压，另一个小于参考电压。
因此，通过感测处理后位线上的电压信号，可以检测到位线电压是否高于参考信号的电压，如果感测处理后的电压信号高于参考信号，则输出信号为高电平信号。此时，示例性地，外部的信号处理模块通过数据总线接收到高电平信号则可以识别出读取数据为“1”(或“0”)。如果感测处理后的电压信号低于参考信号，则输出信号为低电平信号。示例性地，此时外部的信号处理模块通过数据总线接收到低电平信号则可以识别出读取的数据为“0”(或“1”)。
在一些实施例中，如图3所示，在激活所述字线前，所述方法还包括：
步骤S301、通过第一信号在所述待测存储单元存入预设数据，所述第一信号包括高电平信号或低电平信号。
在激活字线进行数据读取的过程之前，可以先在待测存储单元中预存数据“1”或者数据“0”。那么后续读取的时候则可以根据读取到的数据是否与预存的数据相同来判断存储单元及其相关电路是否异常。
写入预存数据的过程可以通过第一信号向待测存储单元中输入，使得相应的电荷存储在待测存储单元的存储电容等部件中。示例性地，在写入数据“1”时，可以通过高电平信号写入，在写入数据“0”时，可以通过低电平信号写入。
在一些实施例中，所述确定所述待测存储单元是否存在读取异常，包括：
判断所述输出信号与所述待测存储单元内存储数据对应的第一信号是否一致，若不一致则存在读取异常。
在本公开实施例中，可以采用相同极性或者量级的电压信号表示相同的输入数据或者输出数据。示例性地，如果存储单元及其外围电路是正常的，则在待测存储单元内预存数据所采用的第一信号与读取得到的输出信号是一致的。因此，通过判断输出信号与存储数据对应的第一信号是否一致，来判断存储单元及其外围电路是否存在异常。若不一致，则可以确定存储单元或者存储单元所连接的外围电路存在诸如漏电、短路、断线或者感测放大器异常等等各种可能存在的问题。
这样，通过写入数据再进行多次读取操作，然后通过输出信号就可以进行快速且准确的异常检测，从而便于后续对产品进行进一步测试或处理。
在一些实施例中，同一条字线上依次排列多个所述待测存储单元，在所述多个待测存储单元中至少存在两个相邻待测存储单元的第一信号不同。
在本公开实施例中，同一字线上的多个存储单元均可以进行测试，由于同一字线上的多个待测存储单元可能相互之间存在短路或者漏电的可能 性，因此，这里采用不同的第一信号使多个待测存储单元存储的数据存在至少两个不同。
这样，就可以减少由于预存数据都相同导致的漏电不明显从而无法检测出异常的漏检情况。
在一些实施例中，任意两个相邻的所述待测存储单元的第一信号均不同。
同一字线上的各待测存储单元如果相邻，则采用不同的第一信号，示例性地，一条字线上存在相邻的多个待测存储单元，各存储单元的第一信号以一个高电平信号、一个低电平信号的规律交替提供。这样，预存的数据则以类似于“101010……”的规律排布。这样，如果相邻的存储单元之间存在漏电，则会更容易被检测出来，从而提升检测的准确性。
此外，为了更加准确地检测，还可以对同一字线上的各待测存储单元进行多次存储数据、多次读取以及检测输出信号的步骤。在每次检测过程中预存不同的数据，例如，第一次检测预存数据为“101010……”，第二次检测预存数据为“010101……”，第三次检测预存数据为“111111……”，第四次检测预存数据为“000000……”等等。通过每次检测的预存数据的规律以及输出信号的不同情况，可以更准确的判断可能存在的异常。针对多条字线(如下表1中的WL0-WL3)可以采用如下表1中所示的多种组合的预存数据(以8bit为例)进行检测。
Figure PCTCN2022081496-appb-000001
在一些实施例中，激活所述字线之前，所述方法还包括：
通过所述第一信号在所述同一条字线上连接的多个待测存储单元同步存入预设数据。
在对待测存储单元存入预设数据时，需要在对应字线上施加开启电压，使得字线连接的各存储单元被打开，从而能够将数据写入存储单元。在本公开实施例中，可以在对字线施加开启电压的过程中，同步对多个待测存储单元存储预设数据。也就是说，可以同步通过多个待测存储单元所连接的多条位线传输存储数据所需的第一信号，使得字线连接的多个待测存储单元同时存储数据。这样，存储数据的速度较快，可以提升检测速度。
在一实施例中，可以针对同一条字线维持施加开启电压的状态，然后对整条字线上连接的多个待测存储单元分批存储预设数据，例如，按照一次写入8bit(位)数据的速度进行存储。即开启字线后，同步向8个待测存储单元写入数据，再同步向下面8个待测存储单元写入数据，直至整条字线连接的存储单元都被写入预设数据后，再关闭该条字线。这种写入方式可以被称为“Y-Page”写入方式。
可以理解的是，在进行数据读取时，也可以同步对多条位线耦接的存储单元(即同一字线上的多个待测存储单元)执行数据读取操作。在开启一条字线的状态下完成该字线上全部待测存储单元的多次数据读取操作以及上述检测输出信号的操作，即采用上述“Y-Page”的读取操作。当然，也可以一次读取一笔8bit数据(8个存储单元同步执行检测)，然后再重新开启字线后继续读取下一笔数据，这种方式被称为“Y-Fast”读取方式，如图4所示。在实际应用中可以根据产品的实际性能来决定采用何种方式进行数据读写。
这样，可以减少预存数据过程中字线的反复开关，提升检测效率。
在一实施例中，可以在完成一条字线的各存储单元预存数据后，直接对该条字线上的各存储单元执行数据的读取操作。这样，可以减少寻址时 间，提升检测效率，同时进一步减少字线上的信号变化，节省功耗且检测速度快。
如图5所示，本公开实施例提供一种存储器的测试装置100，与存储器的存储阵列200连接，包括：
读取模块501，被配置为：在激活至少一条字线后，对激活的所述字线连接的待测存储单元进行至少两次读取操作；
测试模块502，被配置为：根据所述至少两次读取操作后得到的输出信号，确定所述待测存储单元是否存在读取异常。
这里的读取模块及测试模块可以由存储器的外围电路中的各种电路结构实现，也可以为外部控制器的控制模块。
在一些实施例中，所述读取模块，被配置为：
对激活的所述字线连接的所述待测存储单元进行第一读取操作；
在所述第一读取操作后的预定时长后，对所述待测存储单元进行第二读取操作；
获取第二读取操作对应的所述输出信号。
在一些实施例中，所述读取模块，包括：
指令执行模块，被配置为：
根据检测到的第一读取指令，产生第一选通信号以对所述待测存储单元进行第一次读取操作；以及
根据检测到的第二读取指令，产生第二选通信号以对所述待测存储单元进行第二次读取操作。
对于上述各模块的功能和执行各步骤的相关说明已经在本申请的各方法实施例中详细说明，这里不再赘述。
本公开实施例还提供如下示例：
本公开实施例采用多次读取的方式延长了读取时间TRCD，使得位线漏电或者灵敏放大器异常等情况的读取条件被恶化，进而更容易被检测出 来。
如果位线之间存在漏电，正常读取时位线间的漏电还未产生影响，此时灵敏放大器SA仍能正确放大信号，使得输出信号为正确信号。而通过本公开实施例中的方法，第二次读取命令后，位线之间的漏电已经产生严重影响，灵敏放大器难以放大正确的数据，从而导致读出数据错误，进而可以检测到异常。
如图6所示，在第一次读取命令1st Rd后，通过选通信号YS打开位线与数据通道，可以看出此时受到的漏电影响并不明显，如果在此时进行感测处理，则感测放大器SA仍能将信号正确放大。
在第二次读取命令2nd Rd后，通过选通YS打开位线与数据通道，此时位线间的漏电明显，如果此时进行感测处理，则感测放大器SA难以将信号放大，导致输出数据错误，甚至会由于感测放大器SA难以正确感测信号导致位线上的信号如图7所示的被反向放大，导致输出数据错误。
这样，针对一次以正常TRCD读取操作无法检测出的异常，本公开实施例可以通过两次读取即延长TRCD后的读取操作检测出异常，从而减少漏检的情况，便于及时发现异常并改善。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物 品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本申请各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本申请的实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例的技术方案，通过对待测存储单元中执行至少两次读取 操作，并基于最后得到的输出信号，确定检测结果。通过至少两次读取，可以延长读取的时长，在存储单元存在异常的情况下，则在多次读取后得到的输出信号能够更容易体现出异常，进而便于检测，提升检测的准确率，降低漏检的情况。

Claims (16)

  1. 一种存储器的测试方法，所述方法包括：
    激活至少一条字线后，对激活的所述字线连接的待测存储单元进行至少两次读取操作；
    根据所述至少两次读取操作后得到的输出信号，确定所述待测存储单元是否存在读取异常。
  2. 根据权利要求1所述的方法，其中，所述对激活的所述字线连接的待测存储单元进行至少两次读取操作，包括：
    对激活的所述字线连接的所述待测存储单元进行第一读取操作；
    在所述第一读取操作后的预定时长后，对所述待测存储单元进行第二读取操作；
    获取第二读取操作对应的所述输出信号。
  3. 根据权利要求2所述的方法，其中，所述进行第一读取操作，包括：
    根据检测到的第一读取指令，产生第一选通信号以对所述待测存储单元进行第一次读取操作；
    所述第二读取操作，包括：
    根据检测到的第二读取指令，产生第二选通信号以对所述待测存储单元进行第二次读取操作。
  4. 根据权利要求2所述的方法，其中，所述第一读取操作产生第一读取信号；所述第二读取操作产生第二读取信号；所述获取第二读取操作对应的所述输出信号，包括：
    对所述第二读取信号进行感测处理，获得所述输出信号。
  5. 根据权利要求4所述的方法，其中，对所述第二读取信号进行感测处理包括拉高处理或拉低处理。
  6. 根据权利要求4所述的方法，其中，所述输出信号包括高电平信号 或低电平信号。
  7. 根据权利要求6所述的方法，其中，所述第二读取信号包括电压信号；所述对所述第二读取信号进行感测处理，获得所述输出信号，包括：
    对所述第二读取信号进行感测处理，并将感测处理后的所述电压信号与参考信号比较；
    若所述电压信号高于所述参考信号，所述输出信号为高电平信号；若所述电压信号低于所述参考信号，所述输出信号为低电平信号。
  8. 根据权利要求1所述的方法，其中，激活所述字线前，所述方法还包括：
    通过第一信号在所述待测存储单元存入预设数据，所述第一信号包括高电平信号或低电平信号。
  9. 根据权利要求8所述的方法，其中，所述确定所述待测存储单元是否存在读取异常，包括：
    判断所述输出信号与所述待测存储单元内存储数据对应的第一信号是否一致，若不一致则存在读取异常。
  10. 根据权利要求8所述的方法，其中，同一条字线上依次排列多个所述待测存储单元，在所述多个待测存储单元中至少存在两个相邻待测存储单元的第一信号不同。
  11. 根据权利要求10所述的方法，其中，任意两个相邻的所述待测存储单元的第一信号均不同。
  12. 根据权利要求10所述的方法，其中，激活所述字线之前，所述方法还包括：
    通过所述第一信号在所述同一条字线上连接的多个待测存储单元同步存入预设数据。
  13. 根据权利要求1所述的方法，其中，所述输出信号通过局部输出总线传送至全局输出总线。
  14. 一种存储器的测试装置，所述装置包括：
    读取模块，被配置为：在激活至少一条字线后，对激活的所述字线连接的待测存储单元进行至少两次读取操作；
    测试模块，被配置为：根据所述至少两次读取操作后得到的输出信号，确定所述待测存储单元是否存在读取异常。
  15. 根据权利要求14所述的测试装置，其中，所述读取模块，被配置为：
    对激活的所述字线连接的所述待测存储单元进行第一读取操作；
    在所述第一读取操作后的预定时长后，对所述待测存储单元进行第二读取操作；
    获取第二读取操作对应的所述输出信号。
  16. 根据权利要求15所述的测试装置，其中，所述读取模块，包括：
    指令执行模块，被配置为：
    根据检测到的第一读取指令，产生第一选通信号以对所述待测存储单元进行第一次读取操作；以及
    根据检测到的第二读取指令，产生第二选通信号以对所述待测存储单元进行第二次读取操作。
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CN107068187A (zh) * 2016-02-11 2017-08-18 希捷科技有限公司 似然值指派针对每一读取重试在不同读取电压处改变正负号的读取重试操作
CN113012745A (zh) * 2021-03-23 2021-06-22 长鑫存储技术有限公司 存储器的检测方法及检测装置

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