WO2022190908A1 - 積層基板の製造方法、及び基板処理装置 - Google Patents

積層基板の製造方法、及び基板処理装置 Download PDF

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Publication number
WO2022190908A1
WO2022190908A1 PCT/JP2022/007959 JP2022007959W WO2022190908A1 WO 2022190908 A1 WO2022190908 A1 WO 2022190908A1 JP 2022007959 W JP2022007959 W JP 2022007959W WO 2022190908 A1 WO2022190908 A1 WO 2022190908A1
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Prior art keywords
semiconductor substrate
layer
substrate
bonding layer
bonding
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PCT/JP2022/007959
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English (en)
French (fr)
Japanese (ja)
Inventor
陽平 山下
康隆 溝本
隼斗 田之上
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to KR1020237033854A priority Critical patent/KR20230154934A/ko
Priority to CN202280018447.4A priority patent/CN116941013A/zh
Priority to US18/549,616 priority patent/US20240162081A1/en
Priority to JP2023505288A priority patent/JP7643816B2/ja
Publication of WO2022190908A1 publication Critical patent/WO2022190908A1/ja
Anticipated expiration legal-status Critical
Priority to JP2025025713A priority patent/JP7834217B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/0006—Working by laser beam, e.g. welding, cutting or boring taking account of the properties of the material involved
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/08—Devices involving relative movement between laser beam and workpiece
    • B23K26/082—Scanning systems, i.e. devices involving movement of the laser beam relative to the laser head
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/08—Devices involving relative movement between laser beam and workpiece
    • B23K26/0823—Devices involving rotation of the workpiece
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/362—Laser etching
    • B23K26/364—Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/40—Removing material taking account of the properties of the material involved
    • B23K26/402—Removing material taking account of the properties of the material involved involving non-metallic material, e.g. isolators
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/50—Working by transmitting the laser beam through or within the workpiece
    • B23K26/53—Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0428—Apparatus for mechanical treatment or grinding or cutting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/11—Separation of active layers from substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic materials other than metals or composite materials
    • B23K2103/56—Inorganic materials other than metals or composite materials being semiconducting

Definitions

  • the present disclosure relates to a laminated substrate manufacturing method and a substrate processing apparatus.
  • Patent Documents 1 and 2 describe a method for manufacturing an SOI substrate.
  • the manufacturing method described in Patent Document 1 includes the following steps (a) to (f). (a) After forming a buried oxide film layer at a predetermined depth on a first wafer, an oxide film is formed on the first wafer.
  • Patent Document 2 prepares a silicon substrate for forming an active layer made of silicon single crystal, and forms a buried insulating layer on the surface of the silicon substrate.
  • An ion-implanted layer for peeling is formed by implanting hydrogen ions through the embedded insulating layer, and an amorphous layer is formed by implanting Ar ions or the like between the ion-implanted layer and the embedded insulating layer. .
  • the silicon substrate and the supporting substrate are bonded together with the buried insulating layer interposed therebetween.
  • heat treatment is applied to form an active layer by exfoliating part of the silicon substrate at the location of the ion-implanted layer using the smart cut method, and further heat treatment is applied to polycrystallize the amorphous layer for gettering.
  • a polysilicon layer is formed to function as a site.
  • One aspect of the present disclosure provides a technique for improving the productivity of a laminated substrate including a semiconductor substrate, an oxide layer, and a semiconductor layer in this order, and improving the peelability between the oxide layer and the semiconductor substrate.
  • a method for manufacturing a laminated substrate includes the following (A) to (D).
  • (B) The oxide layer of the bonding layer and the second semiconductor substrate are brought into contact with each other, and the first semiconductor substrate and the second semiconductor substrate are bonded via the bonding layer.
  • D splitting the first semiconductor substrate starting from the modified layer formed on the first splitting surface, thereby dividing the first semiconductor substrate bonded to the second semiconductor substrate via the bonding layer; thin.
  • a laminated substrate including a semiconductor substrate, an oxide layer, and a semiconductor layer in this order, and improve the peelability between the oxide layer and the semiconductor substrate.
  • FIG. 1 is a flow chart showing a method for manufacturing a laminated substrate according to one embodiment.
  • 2A is a cross-sectional view showing an example of S102
  • FIG. 2B is a cross-sectional view showing an example of S103
  • FIG. 2C shows an example of S103 following FIG. 2B.
  • FIG. 3 is a flowchart showing a first example of processing following
  • FIG. 4A is a cross-sectional view showing an example of S201
  • FIG. 4B is a cross-sectional view showing an example of S202
  • FIG. 4C is a cross-sectional view showing an example of S203.
  • D is a cross-sectional view showing an example of S203 subsequent to FIG. 4(C), and FIG.
  • FIG. 4(E) is a cross-sectional view showing an example of S204.
  • FIG. 5 is a flowchart showing a second example of processing following FIG. 6A is a cross-sectional view showing an example of S301, FIG. 6B is a cross-sectional view showing an example of S302, and FIG. 6C is a cross-sectional view showing an example of S303.
  • (D) is a cross-sectional view showing an example of S303 subsequent to FIG. 6C, and FIG. 6E is a cross-sectional view showing an example of S304.
  • FIG. 7 is a flowchart showing a third example of processing following FIG. 8A is a cross-sectional view showing an example of S401, FIG.
  • FIG. 8B is a cross-sectional view showing an example of S402
  • FIG. 8C is a cross-sectional view showing an example of S403.
  • D is a cross-sectional view showing an example of S403 following FIG. 8C
  • FIG. 8E is a cross-sectional view showing an example of S404.
  • FIG. 9 is a flowchart illustrating an example of processing subsequent to FIG. 10A is a cross-sectional view showing an example of a laminated substrate prepared before S501
  • FIG. 10B is a cross-sectional view showing an example of S501
  • FIG. 10C is an example of S502.
  • It is a sectional view showing.
  • 11A is a cross-sectional view showing an example of S503
  • FIG. 11B is a cross-sectional view showing an example of S504, and
  • FIG. 11C shows an example of S504 following FIG.
  • FIG. 12 is a plan view showing a substrate processing apparatus according to one embodiment.
  • the X-axis direction, the Y-axis direction, and the Z-axis direction are directions perpendicular to each other.
  • the X-axis direction and Y-axis direction are horizontal directions, and the Z-axis direction is vertical direction.
  • a method for manufacturing a laminated substrate according to one embodiment will be described with reference to FIGS.
  • the method for manufacturing a laminated substrate includes steps S101 to S107, for example, as shown in FIG. It should be noted that the method for manufacturing the laminated substrate should include at least S101 to S103. Also, the order of S104 to S107 is not limited to the order in FIG. 1, and for example, S106 may be performed after S107.
  • Step S ⁇ b>101 includes forming the bonding layer 11 on the surface of the first semiconductor substrate 10 .
  • the bonding layer 11 includes an oxide layer 11a.
  • the oxide layer 11a is a thermal oxide layer formed by, for example, a thermal oxidation method.
  • the thermal oxidation method the heated surface of the first semiconductor substrate 10 is exposed to oxygen or water vapor to grow the oxide layer 11a from the surface of the first semiconductor substrate 10 inward.
  • a dense oxide layer 11a can be obtained and an oxide layer 11a having excellent insulating properties can be obtained as compared with the CVD method or the like, which will be described later.
  • the thickness of the oxide layer 11a is set so that laser lift-off, which will be described later, can be easily performed.
  • the first semiconductor substrate 10 is, for example, a silicon wafer
  • the oxide layer 11a is, for example, a silicon oxide layer.
  • the first semiconductor substrate 10 is not limited to a silicon wafer, and may be a compound semiconductor wafer or the like.
  • the oxide layer 11a may be formed by a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or the like.
  • Step S102 includes bonding the first semiconductor substrate 10 and the second semiconductor substrate 20 via the bonding layer 11, as shown in FIG. No oxide layer or the like is formed on the surface of the second semiconductor substrate 20, and the second semiconductor substrate 20 and the oxide layer 11a of the bonding layer 11 are in direct contact.
  • the second semiconductor substrate 20 is, for example, a silicon wafer.
  • a laminated substrate T including the first semiconductor substrate 10, the bonding layer 11, and the second semiconductor substrate 20 is obtained.
  • the surface of the second semiconductor substrate 20 and the surface of the oxide layer 11a of the bonding layer 11 may be activated with plasma or the like, and further water or water. It may be hydrophilized by supplying water vapor. Hydrogen bonding occurs between OH groups at the time of bonding. Also, a covalent bond may be generated by a dehydration condensation reaction of a hydrogen bond. Since the solids are directly bonded together without using a liquid adhesive, misalignment due to deformation of the adhesive can be prevented. In addition, it is possible to prevent the occurrence of inclination due to uneven thickness of the adhesive.
  • Step S103 includes thinning the first semiconductor substrate 10 .
  • the modified layer 15 is formed by the laser beam LB on the first dividing surface 12 which is to be divided in the thickness direction of the first semiconductor substrate 10 .
  • the modified layer 15 may also be formed on the ring-shaped second splitting surface 13 set on the periphery of the first splitting surface 12 by the laser beam LB.
  • the laser beam LB is irradiated into the inside of the first semiconductor substrate 10 from, for example, the surface of the first semiconductor substrate 10 opposite to the second semiconductor substrate 20 .
  • the modified layer 15 is formed in a dot shape, and a plurality of modified layers 15 are formed on the first planned division surface 12 and the second planned division surface 13 .
  • the formation position of the modified layer 15 is moved using a galvanometer scanner or an XY ⁇ stage. When the modified layers 15 are formed, cracks connecting the modified layers 15 are also formed.
  • the first semiconductor substrate 10 is divided starting from the modified layer 15 formed on the first dividing surface 12, thereby dividing the second semiconductor substrate with the bonding layer 11 interposed therebetween.
  • the first semiconductor substrate 10 bonded with 20 is thinned.
  • a laminated substrate T including the thinned first semiconductor substrate 10, the bonding layer 11, and the second semiconductor substrate 20 is obtained.
  • the bevel of the first semiconductor substrate 10 may be removed by dividing the first semiconductor substrate 10 starting from the modified layer 15 formed on the second dividing plane 13 .
  • the upper chuck 131 holds the first semiconductor substrate 10 and the lower chuck 132 holds the second semiconductor substrate 20 .
  • the first semiconductor substrate 10 and the second semiconductor substrate 20 may be arranged upside down, and the upper chuck 131 may hold the second semiconductor substrate 20 and the lower chuck 132 may hold the first semiconductor substrate 10 .
  • the crack spreads planarly starting from the modified layer 15 and the first semiconductor substrate 10 is split between the first splitting surface 12 and the second splitting surface 13 . split.
  • the lower chuck 132 may be lowered. Also, rotation of the lower chuck 132 about the vertical axis may be performed.
  • steps S104 to S107 the strain remaining in the thinned first semiconductor substrate 10 is removed, and the quality of the first semiconductor substrate 10 is improved. As will be described later, defects in the first device layer formed on the surface of the first semiconductor substrate 10 can be reduced.
  • step S104 the thinned surface of the first semiconductor substrate 10 is ground.
  • step S105 the thinned surface of the first semiconductor substrate 10 is etched.
  • step S106 the thinned first semiconductor substrate 10 is annealed.
  • step S107 the thinned first semiconductor substrate 10 is polished.
  • the depth to which hydrogen ions can be implanted into the first semiconductor substrate is about 1 ⁇ m at maximum, and the thickness of the thinned first semiconductor substrate is about 1 ⁇ m at maximum. Therefore, a process such as epitaxial growth is required to add a semiconductor layer to the thinned first semiconductor substrate. Moreover, since radioactivity is generated when hydrogen ions are implanted into the first semiconductor substrate, a special chamber for shielding radioactivity is required.
  • the first semiconductor substrate 10 is thinned by forming the modified layer 15 with the laser beam LB and dividing the first semiconductor substrate 10 with the modified layer 15 as a starting point. Irradiation with the laser beam LB can reduce power consumption compared to implantation of hydrogen ions. In addition, the depth of forming the modified layer 15 can be controlled by the condensing position of the laser beam LB, etc., the thinned first semiconductor substrate 10 can be prevented from becoming too thin, and processing such as epitaxial growth can be omitted. Furthermore, unlike the implantation of hydrogen ions, the irradiation with the laser beam LB does not generate radioactivity, so a special chamber for shielding radioactivity is not required. Therefore, the productivity of the laminated substrate T including the thinned first semiconductor substrate 10, the bonding layer 11, and the second semiconductor substrate 20 can be improved, and the production cost of the laminated substrate T can be reduced.
  • the laminated substrate T including the thinned first semiconductor substrate 10, the bonding layer 11, and the second semiconductor substrate 20 is obtained.
  • the thickness of the thinned first semiconductor substrate 10 is thinner than the thickness of the second semiconductor substrate 20 .
  • the laminated substrate T obtained by the manufacturing method shown in FIG. (Silicon on Insulator) substrate.
  • the first device layer 16 is formed on the thinned surface of the first semiconductor substrate 10 .
  • the first device layer 16 includes, for example, semiconductor elements.
  • the modified layer 15 is formed with a laser beam LB passing through the second semiconductor substrate 20 .
  • the oxide layer 11 a of the bonding layer 11 has a high absorption rate of the laser beam LB, and the modified layer 15 is formed at the interface between the second semiconductor substrate 20 and the bonding layer 11 .
  • the modified layer 15 may be formed inside the bonding layer 11 .
  • the second semiconductor substrate 20 and the bonding layer 11 are separated from the modified layer 15 as a starting point.
  • the bonding layer 11 is formed on the first semiconductor substrate 10 instead of on the second semiconductor substrate 20 . Therefore, the bonding layer 11 is strongly bonded to the first semiconductor substrate 10 . Since the bonding layer 11 and the second semiconductor substrate 20 are separated without being separated at the interface between the bonding layer 11 and the first semiconductor substrate 10, the peel strength is low and the separation is easy. The separated second semiconductor substrate 20 is bonded to a new first semiconductor substrate 10 and reused.
  • Step S201 includes forming a first device layer 16 on the surface of the thinned first semiconductor substrate 10, as shown in FIG. 4A.
  • the first device layer 16 includes, for example, an image sensor.
  • the image sensor is, for example, of the BSI (Back Side Illumination) type.
  • Step S202 includes facing and bonding the first device layer 16 and the second device layer 31 formed on the third semiconductor substrate 30, as shown in FIG. 4(B).
  • a second device layer 31 is formed on the third semiconductor substrate 30 before bonding with the first device layer 16 .
  • a separation layer 35 may be formed between the third semiconductor substrate 30 and the second device layer 31 as shown in FIG. 10(A).
  • the third semiconductor substrate 30 is, for example, a silicon wafer, and the second device layer 31 includes, for example, logic circuits of image sensors.
  • a device layer 32 is composed of the first device layer 16 and the second device layer 31 .
  • the surface of the first device layer 16 and the surface of the second device layer 31 may be activated by plasma or the like, and water or water vapor may be supplied.
  • water or water vapor may be supplied.
  • a covalent bond may be generated by a dehydration condensation reaction of a hydrogen bond.
  • step S203 the second semiconductor substrate 20 and the bonding layer 11 are separated.
  • a modified layer 15 is formed at the interface between the second semiconductor substrate 20 and the bonding layer 11 with a laser beam LB passing through the second semiconductor substrate 20 .
  • the oxide layer 11a of the bonding layer 11 has a high absorption rate of the laser beam LB, and the modified layer 15 is formed at the interface between the second semiconductor substrate 20 and the oxide layer 11a. Note that the modified layer 15 may be formed inside the bonding layer 11 .
  • the second semiconductor substrate 20 and the bonding layer 11 are separated from the second semiconductor substrate 20 starting from the modified layer 15 formed at the interface between the second semiconductor substrate 20 and the bonding layer 11 (or inside the bonding layer 11). 11 are peeled off.
  • an upper chuck (not shown) holds the second semiconductor substrate 20 and a lower chuck (not shown) holds the third semiconductor substrate 30 .
  • the arrangement of the second semiconductor substrate 20 and the third semiconductor substrate 30 may be reversed.
  • the upper chuck rises with respect to the lower chuck, the crack spreads planarly starting from the modified layer 15, and the second semiconductor substrate 20 and the bonding layer 11 are separated.
  • the lower chuck may be lowered instead of or in addition to the upper chuck ascent. Also, rotation of the lower chuck about a vertical axis may be implemented.
  • Step S204 includes removing the bonding layer 11 after separating the second semiconductor substrate 20 and the bonding layer 11, as shown in FIG. 4(E).
  • the bonding layer 11 is removed by CMP (Chemical Mechanical Polishing) or the like. As a result, the thinned first semiconductor substrate 10 is exposed on the surface of the laminated substrate T. Next, as shown in FIG. 4(E).
  • the bonding layer 11 does not have to be removed if it does not affect subsequent processes. Also, the bonding layer 11 is not removed when it is used as a gettering layer, which will be described later.
  • the gettering layer is a layer that captures impurities such as heavy metals.
  • the method for manufacturing a laminated substrate includes steps S301 to S304, for example, as shown in FIG.
  • Step S301 includes forming a first device layer 16 on the surface of the thinned first semiconductor substrate 10, as shown in FIG. 6A.
  • the first device layer 16 includes, for example, a backside PDN (Power Delivery Network).
  • Step S302 includes facing and bonding the first device layer 16 and the second device layer 31 formed on the third semiconductor substrate 30, as shown in FIG. 6(B).
  • a second device layer 31 is formed on the third semiconductor substrate 30 before bonding with the first device layer 16 .
  • the third semiconductor substrate 30 is, for example, a silicon wafer, and the second device layer 31 includes, for example, a backside PDN logic circuit.
  • a device layer 32 is composed of the first device layer 16 and the second device layer 31 .
  • the surface of the first device layer 16 and the surface of the second device layer 31 may be activated by plasma or the like, and water or water vapor may be supplied.
  • water or water vapor may be supplied.
  • a covalent bond may be generated by a dehydration condensation reaction of a hydrogen bond.
  • step S303 the second semiconductor substrate 20 and the bonding layer 11 are separated, similar to step S203 in FIG.
  • a modified layer 15 is formed at the interface between the second semiconductor substrate 20 and the bonding layer 11 with a laser beam LB passing through the second semiconductor substrate 20 .
  • the modified layer 15 may be formed inside the bonding layer 11 .
  • FIG. 6D the second semiconductor substrate 20 and the bonding layer 11 are separated starting from the modified layer 15 formed at the interface between the second semiconductor substrate 20 and the bonding layer 11 .
  • step S304 the vias 17 are formed in the bonding layer 11 and the first semiconductor substrate 10 after the second semiconductor substrate 20 and the bonding layer 11 are separated, as shown in FIG. 6(E).
  • the via 17 is a through electrode formed through the bonding layer 11 and the first semiconductor substrate 10 . Note that the formation of the vias 17 (step S304) may be performed before the formation of the first device layer 16 (step S301).
  • the method for manufacturing a laminated substrate includes steps S401 to S404, for example, as shown in FIG.
  • Step S401 includes forming vias 18 in the thinned first semiconductor substrate 10 and forming a first device layer 16 on the surface of the first semiconductor substrate 10, as shown in FIG. 8A.
  • the via 18 is a through electrode formed through the first semiconductor substrate 10 .
  • the first device layer 16 includes, for example, a DRAM (Dynamic Random Access Memory). More specifically, the DRAM may be HBM (High Bandwidth Memory).
  • Step S402 includes facing and bonding the first device layer 16 and the carrier substrate 40, as shown in FIG. 8(B).
  • the carrier substrate 40 is temporarily bonded to the first device layer 16 using, for example, an adhesive (not shown).
  • a glass substrate, for example, is used as the carrier substrate 40 .
  • step S403 the second semiconductor substrate 20 and the bonding layer 11 are separated, similar to step S203 in FIG.
  • a modified layer 15 is formed at the interface between the second semiconductor substrate 20 and the bonding layer 11 with a laser beam LB passing through the second semiconductor substrate 20 .
  • the modified layer 15 may be formed inside the bonding layer 11 .
  • FIG. 8D the second semiconductor substrate 20 and the bonding layer 11 are separated starting from the modified layer 15 formed at the interface between the second semiconductor substrate 20 and the bonding layer 11 .
  • Step S404 includes forming a mask pattern on the surface of the bonding layer 11 after separating the second semiconductor substrate 20 and the bonding layer 11, and etching the bonding layer 11 using the mask pattern. Etching is, for example, dry etching. After etching the bonding layer 11, the mask pattern is removed. As a result, the via 18 is exposed as shown in FIG. 8(E).
  • FIG. 10A The method for manufacturing a laminated substrate includes steps S501 to S504, as shown in FIG. 9, for example.
  • a laminated substrate T shown in FIG. 10A is obtained by the process shown in FIG.
  • the laminated substrate T has the first semiconductor substrate 10, the device layer 32, the release layer 35, and the third semiconductor substrate 30 in this order.
  • the release layer 35 may include an oxide layer, similar to the bonding layer 11 .
  • the exfoliation layer 35 may include a nitride layer. It is also possible to form the modified layer 15 on the nitride layer.
  • the release layer 35 may have a multi-layer structure.
  • the laminated substrate T may further have a bonding layer 11 functioning as a gettering layer on the surface of the first semiconductor substrate 10 opposite to the device layer 32 .
  • the device layer 32 may include the first device layer 16 and the second device layer 31 as described above.
  • the first device layer 16 includes, for example, semiconductor memory.
  • the second device layer 31 includes, for example, semiconductor memory peripheral circuits (also called “peripherals”) or semiconductor memory input/output circuits (also called “IO”).
  • a die attach film (DAF: Die Attach Film) 33 is formed on the surface of the bonding layer 11 (the first semiconductor substrate 10 if there is no bonding layer 11). including.
  • the die attach film 33 is an adhesive sheet for die bonding.
  • the die attach film 33 is used for stacking semiconductor chips.
  • the die attach film 33 may be either conductive or insulating.
  • the die attach film 33 is obtained by applying a liquid material and drying it.
  • Step S502 includes dicing the bonding layer 11, the first semiconductor substrate 10, the device layer 32, and the separation layer 35, as shown in FIG. 10(C).
  • a groove 19 is formed through the bonding layer 11 , the first semiconductor substrate 10 , the device layer 32 and the separation layer 35 .
  • the die attach film 33 is formed in advance on the bonding layer 11 , the die attach film 33 is also diced, and the grooves 19 are also formed through the die attach film 33 .
  • the dicing method is, for example, laser dicing or blade dicing.
  • Laser dicing includes ablation using the laser beam LB2.
  • the die attach film 33, the bonding layer 11, the first semiconductor substrate 10, the device layer 32, and the release layer 35 absorb the laser beam LB2 to generate heat and sublimate or evaporate. As a result, grooves 19 are formed.
  • the controller may change the energy of the laser beam LB2 when dicing the first semiconductor substrate 10 and when dicing the device layer 32 and the peeling layer 35 .
  • an energy that can process silicon is set.
  • the energy is set so that the conductive film and the oxide film can be processed but silicon cannot be processed. Damage to the third semiconductor substrate 30 can be prevented when the device layer 32 and the separation layer 35 are processed.
  • step S503 the laminated substrate T is attached to the tape 51 arranged on the side opposite to the third semiconductor substrate 30, and mounted on the frame 52 via the tape 51.
  • the frame 52 is formed in an annular shape, and the tape 51 is attached to the frame 52 so as to cover the opening of the frame 52 .
  • a die attach film 33 is arranged between the bonding layer 11 (the first semiconductor substrate 10 if there is no bonding layer 11 ) and the tape 51 .
  • the die attach film 33 is formed in advance on the bonding layer 11 and the like in this embodiment, it may be adhered in advance to the surface of the tape 51 . In the latter case, steps S503 and S501 are performed simultaneously. In this case, the dicing of the die attach film 33 may be performed after step S504, which will be described later.
  • step S504 the third semiconductor substrate 30 and the separation layer 35 are separated, similar to step S203 in FIG.
  • the modified layer 15 is formed at the interface between the third semiconductor substrate 30 and the peeling layer 35 with a laser beam LB passing through the third semiconductor substrate 30 .
  • the modified layer 15 may be formed inside the release layer 35 .
  • FIG. 11C the third semiconductor substrate 30 and the separation layer 35 are separated starting from the modified layer 15 formed at the interface between the third semiconductor substrate 30 and the separation layer 35 . Even after peeling, the tape 51 can prevent scattering of the semiconductor chips. Semiconductor chips are picked up one by one.
  • the bonding layer 11 remains on the surface of the first semiconductor substrate 10 after the third semiconductor substrate 30 and the separation layer 35 are separated.
  • the remaining bonding layer 11 is used as a gettering layer that captures impurities such as heavy metals. Therefore, processing for forming a gettering layer is not required.
  • a device layer 32 is formed on the surface of a thick first semiconductor substrate 10, the device layer 32 is diced with a blade, a protective tape is attached to the device layer 32, and then the first semiconductor substrate 10 is ground. and thinned. The blade fully cuts the device layer 32 and half cuts the first semiconductor substrate 10 . Thereafter, by grinding the first semiconductor substrate 10 from the side opposite to the device layer 32, the first semiconductor substrate 10 is divided to obtain a plurality of semiconductor chips. After that, a gettering layer is formed on the ground surface of the first semiconductor substrate 10, a tape 51 is placed on the side opposite to the protective tape with the first semiconductor substrate 10 interposed therebetween, and the first semiconductor substrate 10 is obtained through the tape 51. 10 was attached to the frame 52, the protective tape was removed, and so on.
  • the first semiconductor substrate 10 is already thinned before forming the device layer 32 (see FIG. 4). (1) Since the first semiconductor substrate 10 is not ground after forming the device layer 32 unlike the conventional method, damage to the device layer 32 and the first semiconductor substrate 10 can be suppressed. Further, according to this embodiment, the device layer 32 and the first semiconductor substrate 10 are diced to obtain a plurality of semiconductor chips. Next, the first semiconductor substrate 10 is attached to the frame 52 via the tape 51 arranged on the side opposite to the third semiconductor substrate 30 . Furthermore, after that, the third semiconductor substrate 30 is removed by laser lift-off. The third semiconductor substrate 30 is harder than the conventional masking tape.
  • the semiconductor chip can be reinforced with the third semiconductor substrate 30, and damage to the semiconductor chip can be suppressed.
  • the bonding layer 11 remaining after the removal of the third semiconductor substrate 30 can be used as a gettering layer, eliminating the need for processing for forming a gettering layer. As described above, according to this embodiment, the productivity of semiconductor chips can be improved.
  • the laminated substrate T in which the bonding layer 11 is formed on the first semiconductor substrate 10 is prepared. good. Even in this case, the above effects (1) to (4) can be obtained, and the productivity of semiconductor chips can be improved.
  • the second semiconductor substrate 20 and the bonding layer 11 can be easily separated.
  • the substrate processing apparatus 100 has a loading/unloading section 101 , a transport section 110 , a laser processing section 120 , a dividing section 130 and a control section 140 .
  • the loading/unloading section 101 has a mounting section 102 on which the cassette C is mounted.
  • the cassette C accommodates a plurality of laminated substrates T shown in FIG. 2(A), for example.
  • the laminated substrate T includes a first semiconductor substrate 10 , a second semiconductor substrate 20 , and a bonding layer 11 that bonds the first semiconductor substrate 10 and the second semiconductor substrate 20 .
  • the number of mounting units 102 and the number of cassettes C are not limited to those shown in FIG.
  • the transport unit 110 is arranged next to the loading/unloading unit 101, the laser processing unit 120, and the dividing unit 130, and transports the laminated substrate T to these.
  • the transport unit 110 has a transport arm 111 that holds the laminated substrate T. As shown in FIG.
  • the transport arm 111 can move horizontally (both in the X-axis direction and the Y-axis direction) and vertically, and rotate about the vertical axis.
  • the laser processing unit 120 forms the modified layer 15 with the laser beam LB on the planned division surface for dividing the laminated substrate T in the thickness direction.
  • the laser processing unit 120 includes, for example, a stage 121 that holds the laminated substrate T, and an optical system 122 that irradiates the laminated substrate T held by the stage 121 with the laser beam LB.
  • the stage 121 is, for example, an XY ⁇ stage or an XYZ ⁇ stage.
  • Optical system 122 includes, for example, a condenser lens. The condensing lens converges the laser beam LB toward the laminated substrate T. As shown in FIG. Optical system 122 may further include a galvanometer scanner.
  • the dividing unit 130 divides the multilayer substrate T starting from the modified layer 15 formed on the surface to be divided.
  • the dividing section 130 includes, for example, an upper chuck 131 and a lower chuck 132 .
  • the upper chuck 131 holds the first semiconductor substrate 10 and the lower chuck 132 holds the second semiconductor substrate 20 .
  • the arrangement of the first semiconductor substrate 10 and the second semiconductor substrate 20 may be upside down.
  • the upper chuck 131 rises with respect to the lower chuck 132
  • the crack spreads planarly starting from the modified layer 15 and the multilayer substrate T is divided along the first dividing plane 12 and the like.
  • the downward movement of the lower chuck 132 may be performed.
  • rotation of the lower chuck 132 about the vertical axis may be performed.
  • the control unit 140 is, for example, a computer, and as shown in FIG. 12, includes a CPU (Central Processing Unit) 141 and a storage medium 142 such as a memory.
  • the storage medium 142 stores programs for controlling various processes executed in the substrate processing apparatus 100 .
  • the control unit 140 controls the operation of the substrate processing apparatus 100 by causing the CPU 141 to execute programs stored in the storage medium 142 .
  • the control unit 140 sets the intended division plane inside the first semiconductor substrate 10 .
  • the control unit 140 forms the modified layer 15 on the first dividing surface 12 and divides the first semiconductor substrate 10 starting from the formed modified layer 15 , thereby dividing the second semiconductor substrate through the bonding layer 11 .
  • the first semiconductor substrate 10 bonded with 20 is thinned.
  • the substrate processing apparatus 100 shown in FIG. 12 can be used in steps other than step S103 in FIG. 1.
  • step S203 in FIG. 3 can also be used for S504.
  • the division part 130 has the upper chuck 131 holding the second semiconductor substrate 20 and the lower chuck 132 holding the third semiconductor substrate 30 .
  • the modified layer 15 may be formed inside the bonding layer 11 .
  • the control unit 140 sets the planned split plane to the interface between the second semiconductor substrate 20 and the bonding layer 11, and divides the second semiconductor substrate starting from the modified layer 15 formed at the interface. 20 and the bonding layer 11 are peeled off.
  • the division part 130 has the upper chuck 131 holding the second semiconductor substrate 20 and the lower chuck 132 holding the carrier substrate 40 .
  • the control unit 140 sets the intended split plane to the interface between the third semiconductor substrate 30 and the separation layer 35, and divides the third semiconductor substrate starting from the modified layer 15 formed at the interface. 30 and the release layer 35 are peeled off.
  • the division part 130 has the upper chuck 131 holding the third semiconductor substrate 30 and the lower chuck 132 holding the tape 51 .
  • the modified layer 15 may be formed inside the release layer 35 .
  • the transport arm 111 of the transport unit 110 holds the laminated substrate T by holding the frame 52 shown in FIG.

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  • Chemical & Material Sciences (AREA)
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  • Electromagnetism (AREA)
PCT/JP2022/007959 2021-03-09 2022-02-25 積層基板の製造方法、及び基板処理装置 Ceased WO2022190908A1 (ja)

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CN202280018447.4A CN116941013A (zh) 2021-03-09 2022-02-25 层叠基板的制造方法和基板处理装置
US18/549,616 US20240162081A1 (en) 2021-03-09 2022-02-25 Stacked substrate manufacturing method and substrate processing apparatus
JP2023505288A JP7643816B2 (ja) 2021-03-09 2022-02-25 積層基板の製造方法
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Citations (4)

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JP2012038932A (ja) * 2010-08-06 2012-02-23 Sumco Corp 半導体ウェーハの薄厚化方法および貼り合せウェーハの製造方法
JP2013089720A (ja) * 2011-10-17 2013-05-13 Shin Etsu Handotai Co Ltd 剥離ウェーハの再生加工方法
US20180118562A1 (en) * 2015-04-09 2018-05-03 Siltectra Gmbh Method for the low-loss production of multi-component wafers
WO2020213479A1 (ja) * 2019-04-19 2020-10-22 東京エレクトロン株式会社 処理装置及び処理方法

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JP3849683B2 (ja) * 1998-02-25 2006-11-22 セイコーエプソン株式会社 薄膜トランジスタの剥離方法
JP2005086089A (ja) * 2003-09-10 2005-03-31 Seiko Epson Corp ３次元デバイスの製造方法
JP2006173568A (ja) 2004-12-14 2006-06-29 Korea Electronics Telecommun Ｓｏｉ基板の製造方法
JP2009218381A (ja) 2008-03-11 2009-09-24 Denso Corp ＳＯＩ（Ｓｉｌｉｃｏｎｏｎｉｎｓｕｌａｔｏｒ）基板の製造方法

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JP2012038932A (ja) * 2010-08-06 2012-02-23 Sumco Corp 半導体ウェーハの薄厚化方法および貼り合せウェーハの製造方法
JP2013089720A (ja) * 2011-10-17 2013-05-13 Shin Etsu Handotai Co Ltd 剥離ウェーハの再生加工方法
US20180118562A1 (en) * 2015-04-09 2018-05-03 Siltectra Gmbh Method for the low-loss production of multi-component wafers
WO2020213479A1 (ja) * 2019-04-19 2020-10-22 東京エレクトロン株式会社 処理装置及び処理方法

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