WO2022185784A1 - 遅延信号生成回路、送信回路、電子制御ユニット、及び車両 - Google Patents

遅延信号生成回路、送信回路、電子制御ユニット、及び車両 Download PDF

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Publication number
WO2022185784A1
WO2022185784A1 PCT/JP2022/002574 JP2022002574W WO2022185784A1 WO 2022185784 A1 WO2022185784 A1 WO 2022185784A1 JP 2022002574 W JP2022002574 W JP 2022002574W WO 2022185784 A1 WO2022185784 A1 WO 2022185784A1
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WIPO (PCT)
Prior art keywords
delay
terminal
circuit
signal
variable resistance
Prior art date
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Ceased
Application number
PCT/JP2022/002574
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English (en)
French (fr)
Japanese (ja)
Inventor
雄二 矢野
徹 向井
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Rohm Co Ltd
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Rohm Co Ltd
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Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to DE112022000540.8T priority Critical patent/DE112022000540T5/de
Priority to JP2023503630A priority patent/JPWO2022185784A1/ja
Priority to CN202280018108.6A priority patent/CN116918308A/zh
Publication of WO2022185784A1 publication Critical patent/WO2022185784A1/ja
Priority to US18/451,313 priority patent/US12334993B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40032—Details regarding a bus interface enhancer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215—Controller Area Network CAN
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40267—Bus for use in transportation systems
    • H04L2012/40273—Bus for use in transportation systems the transportation system being a vehicle

Definitions

  • the invention disclosed in this specification relates to a delay signal generation circuit that generates a plurality of delay signals, a transmission circuit that includes the delay signal generation circuit, an electronic control unit, and a vehicle.
  • ECU Electronic Control Unit
  • CAN Controller Area Network
  • Each of the CAN communication transmission signal and reception signal is a differential signal.
  • a differential signal formed by the first signal and the second signal can be decomposed into a common mode component and a differential mode component.
  • the common mode component is the average of the first signal and the second signal
  • the differential mode component is the difference between the first signal and the second signal
  • Common mode noise occurs when a time difference (skew) occurs between the first signal and the second signal.
  • skew time difference
  • the delay signal generation circuit disclosed in this specification includes 1st to nth (n is a natural number of 2 or more) delay circuits and 1st to nth output terminals, and in a first mode, , the input signal reaches the k-th output terminal through the first to the k-th (k is a natural number of 1 to n) delay circuits in order, and in the second mode,
  • the configuration is such that an input signal reaches the k-th output terminal via the k-th to n-th delay circuits in reverse order.
  • a transmitter circuit disclosed herein includes a first terminal configured to receive a first voltage, a second terminal, a third terminal, and a second voltage lower than the first voltage. a fourth terminal configured to be applied, a first variable resistance section provided between the first terminal and the second terminal and configured to vary a resistance value, and the third terminal and the fourth terminal and configured to vary a resistance value; and each resistance value of the first variable resistance unit and the second variable resistance unit based on transmission data and a control unit configured to control the first variable resistance unit and the second variable resistance unit, each including a parallel circuit in which a plurality of series circuits of resistors and switches are connected in parallel, the control unit is a configuration including the delay signal generation circuit configured as described above.
  • the electronic control unit disclosed in this specification has a configuration including a transmission circuit configured as described above and a computer that transmits the transmission data to the transmission circuit.
  • the vehicle disclosed in this specification is configured to include a communication bus and a plurality of electronic control units configured as described above connected to the communication bus.
  • FIG. 1 is an external view of a vehicle according to one embodiment.
  • FIG. 2 is a schematic diagram of a CAN communication system.
  • FIG. 3 is a diagram showing a configuration example of an ECU.
  • FIG. 4 is a diagram showing a configuration example of a transceiver circuit.
  • FIG. 5 is a time chart showing differential signals.
  • FIG. 6 is a diagram showing a configuration example of the first variable resistance section.
  • FIG. 7 is a diagram showing a configuration example of the second variable resistance section.
  • FIG. 8 is a diagram illustrating a configuration example of a control unit.
  • FIG. 9 is a diagram showing another configuration example of the control unit.
  • a MOS transistor is defined as a gate structure that includes a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-type, N-type, or intrinsic semiconductor.
  • layer refers to a transistor consisting of at least three layers. In other words, the structure of the gate of a MOS transistor is not limited to a three-layer structure of metal, oxide, and semiconductor.
  • a constant current means a current that is constant in an ideal state, and is actually a current that can slightly fluctuate due to temperature changes and the like.
  • a constant voltage means a voltage that is constant in an ideal state, and is actually a voltage that can slightly fluctuate due to temperature changes and the like.
  • FIG. 1 is an external view of a vehicle X according to one embodiment.
  • Vehicle X includes a plurality of ECUs 1 (not shown in FIG. 1).
  • Vehicle X also includes a battery (not shown).
  • FIG. 2 is a schematic diagram of a CAN communication system provided in vehicle X.
  • the CAN communication system shown in FIG. 2 includes multiple ECUs 1, a first bus line BL1, a second bus line BL2, and resistors R101 and R102.
  • One end of the resistor R101 is connected to one end of the first bus line BL1, and one end of the resistor R102 is connected to the other end of the first bus line BL1.
  • the other end of the resistor R101 is connected to one end of the second bus line BL2, and the other end of the resistor R102 is connected to the other end of the second bus line BL2.
  • a plurality of ECUs 1 are respectively connected to a first bus line BL1 and a second bus line BL2.
  • a voltage VBAT output from the battery is supplied to each of the plurality of ECUs 1 . Further, each of the multiple ECUs 1 is connected to a ground potential.
  • a plurality of ECUs 1 use the voltage VBAT as a power supply voltage.
  • FIG. 3 is a diagram showing a configuration example of the ECU 1. As shown in FIG. The ECU 1 of the configuration example shown in FIG.
  • a voltage VBAT is supplied to the terminal T1.
  • the anode of diode 5 is connected to terminal T1.
  • the cathode of diode 5 is connected to the input terminal of power supply circuit 2 and capacitor 6 .
  • the output terminal of the power supply circuit 2 is connected to the power supply voltage input terminal of the microcomputer 3, the terminal VCC of the transceiver circuit 4, and one end of the capacitor 7. A constant voltage is output from the output terminal of the power supply circuit 2 .
  • the microcomputer 3 sends transmission data to the terminal TXD of the transceiver circuit 4 and receives reception data from the terminal RXD of the transceiver circuit 4.
  • the transmitted data and received data are each single signals.
  • the terminal CANH of the transceiver circuit 4 is connected to the terminal T2, and the terminal CANL of the transceiver circuit 4 is connected to the terminal T3.
  • the terminal T2 is connected to the first bus line BL1 shown in FIG. 2, and the terminal T3 is connected to the second bus line BL2 shown in FIG.
  • the transceiver circuit 4 converts transmission data into a differential signal (CAN signal) composed of a first signal SCANH (see FIG. 5 described later) and a second signal SCANL (see FIG. 5 described later) and outputs the differential signal. Further, the transceiver circuit 4 converts a differential signal (CAN signal) composed of the first signal and the second signal into received data and outputs the received data. That is, the transceiver circuit 4 includes a transmission circuit that transmits differential signals and a reception circuit that receives the differential signals. A first signal is transmitted by a first bus line BL1 and a second signal is transmitted by a second bus line BL2.
  • the ground terminal of the power supply circuit 2 is connected to the other end of the capacitor 6, the terminal T4, the terminal GND of the transceiver circuit 4, the ground terminal of the microcomputer 3, and the other end of the capacitor 7. Terminal T4 is connected to the ground potential.
  • FIG. 4 is a diagram showing a configuration example of the transceiver circuit 4. As shown in FIG.
  • the transceiver circuit 4 of the configuration example shown in FIG. 4 includes a terminal VCC, a terminal GND, a terminal TXD, a terminal RXD, a terminal CANH, and a terminal CANL.
  • the transceiver circuit 4 of the configuration example shown in FIG. It further includes an N-channel MOS transistor (NMOS transistor) Q7, which is a limiting section, and a control section CNT1.
  • NMOS transistor N-channel MOS transistor
  • the transceiver circuit 4 of the configuration example shown in FIG. 4 further includes a pull-up resistor R1, a pull-down resistor R2, backflow prevention diodes D1 and D3, and a PMOS transistor Q2 and an NMOS transistor Q6 as clamp elements.
  • the pull-up resistor R1 stabilizes the potential of the node N1 (connection point between the first variable resistance section VR1 and the diode D1) when the first variable resistance section VR1 is in a high impedance state.
  • the pull-down resistor R2 stabilizes the potential of the node N2 (the connection point between the second variable resistance section VR2 and the NMOS transistor Q6) when the second variable resistance section VR2 is in a high impedance state.
  • the PMOS transistor Q2 and the NMOS transistor Q6 are double diffusion MOS transistors with high breakdown voltage.
  • the PMOS transistor Q2 clamps the source potential of the PMOS transistor Q2
  • the NMOS transistor Q6 clamps the source potential of the NMOS transistor Q6.
  • the transceiver circuit 4 of the configuration example shown in FIG. 4 includes a receiver circuit RCV1, a diode D2, a PMOS transistor Q3, an NMOS transistor Q4, an NMOS transistor Q5, and a Zener diode ZD1.
  • the terminal VCC is connected to the source of the PMOS transistor Q1 and one end of the pull-up resistor R1.
  • a bias voltage Vbp which is a constant voltage, is supplied to the gate of the PMOS transistor Q1. Therefore, the PMOS transistor Q1 becomes a constant current source.
  • PMOS transistor Q1 limits the current flowing from terminal VCC to terminal CANH. As a result, overcurrent flowing from the terminal VCC to the terminal CANH can be suppressed.
  • the drain of the PMOS transistor Q1 is connected to one end of the first variable resistance section VR1.
  • the other end of the first variable resistor VR1 is connected to the other end of the pull-up resistor R1 and the anode of the diode D1.
  • the cathode of diode D1 is connected to the source of PMOS transistor Q2.
  • the drain of PMOS transistor Q2 is connected to terminal CANH and the first input terminal of receiver circuit RCV1.
  • a gate drive signal generation circuit composed of a PMOS transistor Q3, an NMOS transistor Q4, an NMOS transistor Q5, a diode D2, and a Zener diode ZD1 generates a gate drive signal for the PMOS transistor Q2.
  • An internal voltage VREG1 generated inside the transceiver circuit 4 is applied to the source of the PMOS transistor Q3.
  • the drain of PMOS transistor Q3 is connected to the anode of diode D2.
  • the cathode of diode D2 is connected to the anode of Zener diode ZD1 and the drain of NMOS transistor Q4.
  • the cathode of Zener diode ZD1 is connected to the source of PMOS transistor Q1.
  • An enable signal EN is supplied to each gate of the PMOS transistor Q3 and the NMOS transistor Q4.
  • the enable signal EN is at high level, the transceiver circuit 4 is enabled.
  • the enable signal EN is at low level, the transceiver circuit 4 is disabled.
  • the source of NMOS transistor Q4 is connected to the drain of NMOS transistor Q5.
  • the source of NMOS transistor Q5 is connected to the ground potential.
  • a bias voltage Vbn1 which is a constant voltage, is supplied to the gate of the NMOS transistor Q5.
  • the anode of the diode D3 is connected to the terminal CANL and the second input terminal of the receiver circuit RCV1.
  • the cathode of diode D3 is connected to the drain of NMOS transistor Q6.
  • the source of the NMOS transistor Q6 is connected to one end of the second variable resistor VR2 and one end of the pull-down resistor R2.
  • An enable signal EN is supplied to the gate of the NMOS transistor Q6.
  • the other end of the second variable resistance section VR2 is connected to the drain of the NMOS transistor Q7.
  • the source of the NMOS transistor Q7 is connected to the other end of the pull-down resistor R2 and the terminal GND.
  • a bias voltage Vbp2 which is a constant voltage, is supplied to the gate of the NMOS transistor Q7. Therefore, the NMOS transistor Q7 becomes a constant current source.
  • the control unit CNT1 receives transmission data supplied to the terminal TXD, and controls each resistance value of the first variable resistance unit VR1 and the second variable resistance unit VR2 based on the transmission data.
  • the above-mentioned first signal SCANH is a binary signal of V1 and (V1+V2) as shown in FIG. 5
  • the above-mentioned second signal SCANL is a binary signal of V1 and (V1-V2) as shown in FIG. is a signal.
  • a differential signal (CAN signal) composed of the first signal SCANH and the second signal SCANL is composed of a common mode component COM which is the average of the first signal SCANH and the second signal SCANL, the first signal SCANH and the second signal SCANL. and a differential mode component DIFF, which is the difference between .
  • the resistance value of the first variable resistance unit VR1 is gradually decreased, and the voltage value of the first signal SCANH transitions from (V1+V2) to V1 in the third transition period and the second signal SCANL During the fourth transition period in which the voltage value transitions from (V1-V2) to V1, the resistance value of the first variable resistance unit VR1 is gradually increased, and the first signal SCANH and the second signal SCANL have waveforms with small high-frequency components. no signal.
  • the control unit CNT1 sets the resistance value of the first variable resistance unit VR1 to the maximum value during periods other than the transition period described above.
  • the resistance value of the second variable resistor VR2 is gradually decreased, and the voltage value of the first signal SCANH transitions from (V1+V2) to V1 in a third transition period and the second signal SCANL During the fourth transition period in which the voltage value of (V1-V2) transitions to V1, the resistance value of the second variable resistance unit VR2 is gradually increased, and the first signal SCANH and the second signal SCANL have small high-frequency components. Waveform signal. Note that the control unit CNT1 sets the resistance value of the second variable resistance unit VR2 to the maximum value during periods other than the transition period described above.
  • FIG. 6 is a diagram showing a configuration example of the first variable resistance section VR1
  • FIG. 7 is a diagram showing a configuration example of the second variable resistance section VR2.
  • the first variable resistance unit VR1 in the configuration example shown in FIG. 6 includes PMOS transistors M1 to M60 as switches and resistors Z1 to Z60, and is a circuit in which 60 series circuits of resistors and switches are connected in parallel.
  • the PMOS transistors M1 to M60 are on/off controlled by control signals S1 to S60 output from the control unit CNT1. Note that the number of series circuits may be more than 60.
  • the resistance value of the first variable resistance section VR1 is determined by the combined resistance of the resistors Z1 to Z60, so the resistance value of the first variable resistance section VR1 can be controlled with high accuracy.
  • the second variable resistance unit VR2 in the configuration example shown in FIG. 7 includes NMOS transistors M101 to M160 as switches and resistors Z101 to Z160, and is a circuit in which 60 series circuits of resistors and switches are connected in parallel.
  • the NMOS transistors M101 to M160 are on/off controlled by control signals S101 to S160 output from the control unit CNT1. Note that the number of series circuits may be more than 60.
  • the resistance value of the second variable resistance section VR2 is determined by the combined resistance of the resistors Z101 to Z160, so the resistance value of the second variable resistance section VR2 can be controlled with high accuracy.
  • FIG. 8 is a diagram showing a configuration example of the control unit CNT1.
  • the first variable resistance unit VR1 includes the PMOS transistors M1 to M60 and the PMOS transistors M1 to M4, and the second variable resistance unit VR2 includes the NMOS transistors M101 to M160. M104 is provided.
  • the control unit CNT1 of the configuration example shown in FIG. 8 includes a delay signal generation circuit 41 and conversion circuits CNV1 to CNV4.
  • the delay signal generation circuit 41 includes delay circuits DL1 to DL4, selectors SEL1 to SEL4, and output terminals TM1 to TM4.
  • the transmission data STXD is supplied to the input terminal of the first delay circuit DL1.
  • the output terminal of the first delay circuit DL1 is connected to the input terminal of the second delay circuit DL2, the first input terminal of the selector SEL1, and the second input terminal of the selector SEL4.
  • the output terminal of the second delay circuit DL2 is connected to the input terminal of the third delay circuit DL3, the first input terminal of the selector SEL2, and the second input terminal of the selector SEL3.
  • the output terminal of the third delay circuit DL3 is connected to the input terminal of the fourth delay circuit DL4, the first input terminal of the selector SEL4, and the first input terminal of the selector SEL1.
  • Output terminals of selectors SEL1 to SEL4 are connected to output terminals TM1 to TM4, respectively.
  • the output terminals TM1-TM4 output the delayed signals SD1-SD4 to the conversion circuits CNV1-CNV4, respectively.
  • the conversion circuit CNV1 converts the delayed signal SD1 into control signals S1 and S101.
  • the conversion circuit CNV2 converts the delayed signal SD2 into control signals S2 and S102.
  • the conversion circuit CNV3 converts the delayed signal SD3 into control signals S3 and S103.
  • the conversion circuit CNV4 converts the delayed signal SD4 into control signals S4 and S104.
  • each of the selectors SEL1 to SEL4 selects and outputs the signal input to the first input terminal. Therefore, in the first mode, the transmission data STXD which is an input signal reaches the k-th output terminal TMk through the 1st to k-th (k is a natural number of 1 to 4) delay circuits in order. .
  • each of the selectors SEL1 to SEL4 selects and outputs the signal input to the second input terminal. Therefore, in the second mode, the transmission data STXD, which is the input signal, passes through the 1st to kth (k is a natural number between 1 and 4) delay circuits in order, and passes through the (5-k)th output terminal. TM(5-k) is reached.
  • the delay time between the delay signal SD1 and the delay signal SD2 the delay time between the delay signal SD2 and the delay signal SD3, and the delay signal SD3 and the delay
  • the delay time with the signal SD4 can be shortened.
  • the delay time between the delay signal SD1 and the delay signal SD2, the delay time between the delay signal SD2 and the delay signal SD3, and the delay time between the delay signal SD3 and the delay signal SD4 are shifted.
  • FIG. 9 is a diagram showing another configuration example of the control unit CNT1.
  • the first variable resistance unit VR1 includes the PMOS transistors M1 to M60 and the PMOS transistors M1 to M4, and the second variable resistance unit VR2 includes the NMOS transistors M101 to M160. M104 is provided.
  • the control unit CNT1 of the configuration example shown in FIG. 9 includes a delay signal generation circuit 42 and conversion circuits CNV1 to CNV4.
  • the delay signal generation circuit 42 includes delay circuits DL1 to DL4, selectors SEL1 to SEL4, and output terminals TM1 to TM4.
  • the transmission data STXD is supplied to the first input terminal of the selector SEL1 and the second input terminal of the selector SEL4.
  • a second input terminal of the selector SEL1 is connected to the output terminal of the second delay circuit DL2, the first input terminal of the selector SEL3, and the second output terminal TM2.
  • the output terminal of the selector SEL1 is connected to the input terminal of the first delay circuit DL1.
  • the output terminal of the first delay circuit DL1 is connected to the first output terminal TM1 and the first input terminal of the selector SEL2.
  • the output terminal of the selector SEL2 is connected to the input terminal of the second delay circuit DL2.
  • a second input terminal of the selector SEL2 is connected to the output terminal of the third delay circuit DL3, the first input terminal of the selector SEL4, and the third output terminal TM3.
  • the output terminal of the selector SEL3 is connected to the input terminal of the third delay circuit DL3.
  • a second input terminal of the selector SEL3 is connected to the output terminal of the fourth delay circuit DL4 and the fourth output terminal TM4.
  • the output terminal of the selector SEL4 is connected to the input terminal of the fourth delay circuit DL4.
  • the output terminals TM1-TM4 output the delayed signals SD1-SD4 to the conversion circuits CNV1-CNV4, respectively.
  • the conversion circuit CNV1 converts the delayed signal SD1 into control signals S1 and S101.
  • the conversion circuit CNV2 converts the delayed signal SD2 into control signals S2 and S102.
  • the conversion circuit CNV3 converts the delayed signal SD3 into control signals S3 and S103.
  • the conversion circuit CNV4 converts the delayed signal SD4 into control signals S4 and S104.
  • each of the selectors SEL1 to SEL4 selects and outputs the signal input to the first input terminal. Therefore, in the first mode, the transmission data STXD which is an input signal reaches the k-th output terminal TMk through the 1st to k-th (k is a natural number of 1 to 4) delay circuits in order. .
  • each of the selectors SEL1 to SEL4 selects and outputs the signal input to the second input terminal. Therefore, in the second mode, the transmission data STXD, which is the input signal, passes through the 1st to kth (k is a natural number between 1 and 4) delay circuits in reverse order and reaches the kth output terminal TMk. .
  • the delay time between the delay signal SD1 and the delay signal SD2 the delay time between the delay signal SD2 and the delay signal SD3, and the delay signal SD3 and the delay
  • the delay time with the signal SD4 can be shortened.
  • the delay is propagated from the first delay circuit DL1 to the fourth delay circuit DL4, and in the second mode, the delay is propagated from the fourth delay circuit DL4 to the first delay circuit. Since it is in the direction toward the circuit DL1, no long and complicated wiring is required. Therefore, the delay time between the delay signal SD1 and the delay signal SD2, the delay time between the delay signal SD2 and the delay signal SD3, and the delay time between the delay signal SD3 and the delay signal SD4 are prevented from occurring. can be suppressed.
  • the (m-1)-th delay circuit (m is a natural number of 2 or more and n or less) and the m-th delay circuit are arranged adjacent to each other. That is, in the circuit arrangement of the control unit CNT1 of the configuration example shown in FIG. 9, there is no other delay circuit between the first delay circuit DL1 and the second delay circuit DL2, and the third delay circuit DL3, and no other delay circuit exists between the third delay circuit DL3 and the fourth delay circuit DL4. .
  • the wiring can be shortened, the delay time between the delay signal SD1 and the delay signal SD2, the delay time between the delay signal SD2 and the delay signal SD3, and the delay time between the delay signal SD3 and the delay signal SD4 are reduced. It is possible to further suppress the occurrence of a deviation in the delay time between.
  • the communication performed by the transceiver circuit is CAN communication, but the communication performed by the transceiver circuit may be communication other than CAN communication.
  • the delay signal generation circuits (41, 42) described above include first to n-th (n is a natural number of 2 or more) delay circuits (DL1 to DL4) and first to n-th output terminals (TM1 to TM4). and so that in the first mode, the input signal reaches the k-th output terminal through the first to k-th delay circuits (k is a natural number from 1 to n) in order. and in the second mode, the input signal reaches the k-th output terminal via the k-th to n-th delay circuits in reverse order (first configuration). .
  • the delay signal generation circuit having the first configuration can generate a plurality of delay signals with little deviation in delay time.
  • the (m ⁇ 1)-th delay circuit (m is a natural number of 2 or more and n or less) and the m-th delay circuit are arranged adjacent to each other. 2 configuration).
  • the delay signal generation circuit having the second configuration can shorten the wiring, it is possible to further suppress the deviation of the delay time.
  • the transmission circuit described above includes a first terminal (VCC) configured to receive a first voltage, a second terminal (CANH), a third terminal (CANL), and a third voltage lower than the first voltage.
  • VCC first terminal
  • CANH second terminal
  • CANL third terminal
  • GND fourth terminal
  • a first variable resistance section provided between the first terminal and the second terminal and configured to vary a resistance value.
  • VR1 a second variable resistor unit (VR2) provided between the third terminal and the fourth terminal and configured to vary a resistance value
  • the first variable resistor based on transmission data and a control unit (CNT1) configured to control each resistance value of the second variable resistance unit
  • the first variable resistance unit and the second variable resistance unit are respectively resistors (Z1 to Z60, Z101 to Z160) and switches (M1 to M60, M101 to M160) are connected in parallel to form a plurality of parallel circuits
  • the control unit includes a delay signal generation circuit having the first or second configuration. This is the configuration (third configuration).
  • the transmission circuit having the third configuration can reduce delay time deviations in the plurality of delay signals generated by the delay signal generation circuit.
  • the electronic control unit (1) described above has a configuration (fourth configuration) including the transmission circuit of the third configuration and a computer (3) that transmits the transmission data to the transmission circuit.
  • the electronic control unit having the fourth configuration can reduce delay time deviations in the plurality of delay signals generated by the delay signal generation circuit.
  • the vehicle (X) described above has a configuration (fifth configuration) including communication buses (BL1, BL2) and a plurality of electronic control units of the fourth configuration connected to the communication buses.
  • the vehicle having the fifth configuration can reduce delay time deviations in the plurality of delay signals generated by the delay signal generation circuit.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
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PCT/JP2022/002574 2021-03-01 2022-01-25 遅延信号生成回路、送信回路、電子制御ユニット、及び車両 Ceased WO2022185784A1 (ja)

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JPH01177221A (ja) * 1988-01-07 1989-07-13 Seiko Epson Corp 直並列変換器
JP2021013143A (ja) * 2019-07-09 2021-02-04 ローム株式会社 差動信号送信回路

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DE112022000540T5 (de) 2024-03-14

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