WO2022183313A1 - 移位寄存器、栅极驱动电路和显示面板 - Google Patents

移位寄存器、栅极驱动电路和显示面板 Download PDF

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Publication number
WO2022183313A1
WO2022183313A1 PCT/CN2021/078442 CN2021078442W WO2022183313A1 WO 2022183313 A1 WO2022183313 A1 WO 2022183313A1 CN 2021078442 W CN2021078442 W CN 2021078442W WO 2022183313 A1 WO2022183313 A1 WO 2022183313A1
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Prior art keywords
comb
tooth
tooth portion
shift register
electrode
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PCT/CN2021/078442
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English (en)
French (fr)
Inventor
王婷婷
王祺
闫岩
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/078442 priority Critical patent/WO2022183313A1/zh
Priority to CN202180000383.0A priority patent/CN115335890B/zh
Priority to US17/764,259 priority patent/US11862061B2/en
Publication of WO2022183313A1 publication Critical patent/WO2022183313A1/zh
Priority to US18/496,888 priority patent/US20240054938A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the embodiments of the present disclosure belong to the field of display technology, and specifically relate to a shift register, a gate driving circuit and a display panel.
  • GOA Gate Driver on Array, integrated gate driver circuit
  • Gate IC Gate Integrated Circuit, gate driver chip
  • Embodiments of the present disclosure provide a shift register, a gate driving circuit and a display panel.
  • an embodiment of the present disclosure provides a shift register, including: a transistor;
  • the transistor includes a gate electrode, a gate insulating layer, an active layer, a first electrode and a second electrode; the first electrode and the second electrode have a comb-like structure;
  • the first pole includes a first comb tooth part and a second comb tooth part arranged at intervals, and a first comb handle part connecting the first comb tooth part and the second comb tooth part, the first comb tooth part
  • the comb-tooth electrodes of the second comb-tooth part and the second comb-tooth part have different lengths
  • the second pole includes a third comb tooth portion and a fourth comb tooth portion arranged at intervals, and a second comb handle portion connecting the third comb tooth portion and the fourth comb tooth portion;
  • the first comb-tooth portion and the third comb-tooth portion form an interdigitated structure
  • the second comb-tooth portion and the fourth comb-tooth portion form an interdigitated structure
  • the orthographic projections of the first comb tooth portion, the second comb tooth portion, the first comb handle portion, and the second comb handle portion on the active layer enclose a short-circuit prevention area, which is used to prevent A short circuit occurs between the first pole and the second pole.
  • the length of the comb-tooth electrodes of the first comb-tooth portion is greater than the length of the comb-tooth electrodes of the second comb-tooth portion; the length of the comb-tooth electrodes of the third comb-tooth portion is greater than that of the fourth comb Comb electrode length of the teeth.
  • the first comb-tooth portion includes a plurality of comb-tooth electrodes arranged in parallel and at equal intervals;
  • the second comb-tooth portion includes a plurality of comb-tooth electrodes arranged in parallel and at equal intervals;
  • the third comb-tooth portion includes a plurality of parallel and equidistant comb-tooth electrodes
  • the fourth comb-tooth portion includes a plurality of comb-tooth electrodes arranged in parallel and at equal intervals.
  • the first comb-tooth portion and the third comb-tooth portion are alternately arranged to form the first portion of the interdigitated structure, and the second comb-tooth portion and the fourth comb-tooth portion are alternately arranged
  • the cloth forms the second part of the interdigitated structure.
  • adjacent first comb-tooth portions and the comb-tooth electrodes of the third comb-tooth portion are separated by a first interval; in the second portion, adjacent ones There is a second interval between the second comb-tooth portion and the comb-tooth electrode of the fourth comb-tooth portion.
  • the first comb-tooth portion and the second comb-tooth portion are arranged in parallel, and between the first comb-tooth portion and the second comb-tooth portion interval third interval;
  • the third pitch is greater than the first pitch, and the third pitch is greater than the second pitch.
  • the third pitch is greater than or equal to 6 microns.
  • the orthographic projection of the first comb handle portion on the active layer is an oblique line.
  • the first comb-tooth portion is adjacent to the second comb-tooth portion, and the first comb-tooth portion and the second comb-tooth portion are spaced apart the first distance or the second distance.
  • the orthographic projection of the first comb handle portion on the active layer is an arc.
  • the second pole further includes a fifth comb tooth part, the fifth comb tooth part is connected with the second comb handle part; the fifth comb tooth part is located in the short-circuit proof area , and is located on the midline of the interval area between the first comb-tooth portion and the second comb-tooth portion that is parallel to the two;
  • the fourth pitch is greater than the first pitch, and the fourth pitch is greater than the second pitch.
  • the first pitch is equal to the second pitch.
  • the first comb handle part is connected with any two adjacent comb-tooth electrodes in the first comb-tooth part to form a U-shaped unit, and the first comb-handle part and the second comb Any two adjacent comb-tooth electrodes in the tooth portion are connected to form a U-shaped unit, and the first pole includes a plurality of the U-shaped units connected in series.
  • the second comb handle portion is connected with any two adjacent comb-tooth electrodes in the third comb-tooth portion to form a U-shaped unit, and the second comb handle portion and the fourth comb Any two adjacent comb-tooth electrodes in the tooth portion are connected to form a U-shaped unit, and the second pole includes a plurality of the U-shaped units connected in series.
  • the gate is located below the active layer, or the gate is located above the active layer.
  • the first electrode is a source electrode
  • the second electrode is a drain electrode
  • the first electrode is a drain electrode
  • the second electrode is a source electrode
  • the number of transistors is one or more;
  • At least one is a first combination composed of two transistors, and in the first combination, the gates of the transistors are connected to each other, the first electrodes are connected to each other, and the first The two poles are connected to each other;
  • the two transistors in the first combination are arranged in an axisymmetric pattern.
  • an embodiment of the present disclosure provides a gate driving circuit, including a plurality of the above shift registers; the plurality of shift registers are cascaded.
  • an embodiment of the present disclosure provides a display panel including the above gate driving circuit.
  • an array substrate is also included, the array substrate includes a display area and a frame area, and the frame area is arranged around the periphery of the display area;
  • the gate driving circuits are disposed on the array substrate and are respectively located in the frame regions on opposite sides of the display region.
  • FIG. 1 is a schematic top view of the distribution of gate drive circuits in a display panel
  • Fig. 2 is the circuit diagram of the shift register of 21T1C circuit structure
  • Figure 3 is a partial layout of a shift register in which each transistor is one size type
  • FIG. 4 is a partial layout of a shift register in which one of the transistors is a different size type
  • Fig. 5 is a structural cross-sectional view along the AA section line in Fig. 4;
  • FIG. 6 is a schematic diagram of a channel short circuit occurring in a transistor in the transition zone in FIG. 4;
  • FIG. 8 is a schematic top view of the structure of a transistor in the shift register of FIG. 7;
  • Fig. 9 is a structural cross-sectional view along the BB section line in Fig. 8;
  • FIG. 10 is a schematic top view of the structure of a transistor in another shift register according to an embodiment of the disclosure.
  • Figure 11 is a structural cross-sectional view along the CC section line in Figure 10;
  • FIG. 12 is a schematic top view of the structure of a transistor in yet another shift register according to an embodiment of the disclosure.
  • FIG. 13 is a cross-sectional view of the structure along the line DD in FIG. 12 .
  • Embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes. Accordingly, the regions illustrated in the figures are of schematic nature and the shapes of the regions shown in the figures are illustrative of the specific shapes of the regions and are not intended to be limiting.
  • a display panel generally has a display area 5 and a frame area 6 surrounding the display area 5; a plurality of pixel units 7 arranged in an array are arranged in the display area 5, and each pixel unit 7 is arranged There is a pixel circuit; wherein, the pixel units 7 located in the same row are connected to the same gate line 8 , and the pixel units 7 located in the same column are connected to the same data line 9 .
  • a gate driving circuit is provided in the frame area 6, and the gate driving circuit includes a plurality of cascaded shift registers (GOA, Gate on Array) 14.
  • the shift registers 14 are arranged in a one-to-one correspondence with the gate lines 8, that is, each One shift register 14 is connected to one gate line 8 .
  • the gate scanning signal is output to the corresponding gate line 8 through the step-by-step shift register 14 to complete the line-by-line scanning of the pixel circuit.
  • the data lines 9 write data voltage signals into the pixel circuits of the row to light up the pixel cells 7 in the row.
  • the shift register is a gate drive circuit composed of a plurality of thin film transistors 15 (Thin Film Transistor) and capacitors and other devices.
  • the shift register most of the thin film transistors 15 are respectively composed of a plurality of gates (the gates are connected together), the same source (the source electrodes 108 are connected together), and the same drain (the drain electrodes 109 are connected together).
  • the small transistors 16 are electrically connected to form, and the active layers of these small transistors 16 are formed by a whole film layer, so as to achieve the requirements for the channel lengths of the thin film transistors 15 designed.
  • the width of the border region is sufficient, most of the smaller transistors 16 in the thin film transistor 15 are transistors of one size type. Referring to FIG.
  • the size of each small transistor 16 in the thin film transistor 15 is uniform.
  • display products such as MNT display products, that is, display products of 18.5 to 34 inches
  • ultra-narrow borders that is, to make the display area of the display product as large as possible. Satisfy the visual enjoyment of customers during the viewing process.
  • the thin film transistors 15 in the shift register must be laid out in the limited frame width, so the small-sized transistors 16 constituting some thin film transistors 15 are usually For size matching design, refer to Figure 4.
  • the photoresist (such as PR glue) is easy to gather in the channel of the transistors 16 of different sizes in the transition region G, so that the source and drain film layers in part of the channel should not be protected by the photoresist but are covered and protected by the photoresist, so that the part of the channel is protected by the photoresist.
  • the source and drain film layers in the channel remain during the etching process, resulting in a short circuit between the source 108 and the drain 109 of the large and small transistors 16 (also called channel short circuit), which makes the shift register signal output abnormal, This leads to defects such as horizontal stripes when the display product is displayed.
  • the embodiments of the present disclosure provide the following technical solutions.
  • an embodiment of the present disclosure provides a shift register, referring to FIGS. 7-9 , including: a transistor 1 ; the transistor 1 includes a gate 101 , a gate insulating layer 102 , an active layer 103 , a first electrode 104 and a second The second pole 105; the first pole 104 and the second pole 105 are comb-like structures; the first pole 104 includes the first comb tooth part 142 and the second comb tooth part 143 arranged at intervals, and the first comb tooth part 142 and the second comb tooth part 143 are arranged at intervals.
  • the first comb-tooth part 141 of the second comb-tooth part 143 , the comb-tooth electrodes of the first comb-tooth part 142 and the second comb-tooth part 143 have different lengths;
  • the second pole 105 includes the third comb-tooth parts 152 and The fourth comb-tooth part 153 and the second comb-tooth part 151 connecting the third comb-tooth part 152 and the fourth comb-tooth part 153;
  • the first comb-tooth part 142 and the third comb-tooth part 152 form an interdigitated structure,
  • the second The comb-tooth portion 143 and the fourth comb-tooth portion 153 form an interdigitated structure, and none of the orthographic projections on the active layer 103 overlap;
  • the active layer 103 in the facing gap between the first comb-tooth portion 142 and the third comb-tooth portion 152 , and the active layer 103 in the facing gap between the second comb-tooth portion 143 and the fourth comb-tooth portion 153 forms part of the channel 100 of the transistor 1 .
  • the turn-on voltage is input to the gate 101 of the transistor 1
  • the first electrode 104 and the second electrode 105 of the transistor 1 are turned on, and the current flows from the first electrode 104 to the second electrode 105 through the channel 100 of the transistor 1, or the current flows through the channel 100 of the transistor 1.
  • the channel 100 of the transistor 1 flows from the second pole 105 to the first pole 104 , so that the transistor 1 is turned on.
  • the gate 101 is located below the active layer 103 , that is, the transistor 1 is a bottom-gate transistor. In some embodiments, the gate 101 is located above the active layer 103 , that is, the transistor 1 is a top-gate transistor. In this embodiment, a bottom-gate transistor is taken as an example for description.
  • the transistor 1 further includes a passivation layer 110 disposed on the side of the first electrode 104 and the second electrode 105 away from the active layer 103 .
  • the preparation of the transistor 1 includes forming the pattern of the gate electrode 101, the gate insulating layer 102 and the active layer 103 in sequence, then forming the pattern of the first electrode 104 and the second electrode 105 on the pattern of the active layer 103, and finally forming the pattern of the first electrode 104 and the second electrode 105 on the pattern of the active layer 103.
  • a passivation layer 110 is formed over 104 and the second pole 105 .
  • the patterns of the gate electrode 101 , the active layer 103 , the first electrode 104 and the second electrode 105 are respectively formed by conventional patterning processes (including steps of film formation, photoresist coating, exposure, development and etching).
  • the short-circuit prevention area is formed.
  • the patterning process forms the first comb-tooth portion 142 and the second comb-tooth portion 143 of the first pole 104 with different lengths and the third comb-tooth portion 152 and the fourth comb-tooth portion of the second pole 105 with different lengths on the active layer 103
  • the photoresist can be prevented from accumulating in the channel 100 formed between the comb-tooth portions of different lengths of the transistor 1, thereby avoiding the formation of the first electrode 104 and the second electrode 105 in this part of the channel 100.
  • the film layer of the pattern is retained during the etching process, thereby preventing the first pole 104 and the second pole 105 from short-circuiting in this part of the channel 100, that is, avoiding channel short-circuiting, and finally ensuring that the signal output of the shift register is normal. , to avoid defects such as horizontal stripes in display products using this shift register.
  • the length of the comb-tooth electrodes of the first comb-tooth portion 142 is greater than the length of the comb-tooth electrodes of the second comb-tooth portion 143 ; the length of the comb-tooth electrodes of the third comb-tooth portion 152 is greater than that of the fourth comb-tooth portion 153 Tooth electrode length.
  • the first comb tooth portion 142 includes a plurality of comb tooth electrodes arranged in parallel and at equal intervals; the second comb tooth portion 143 includes a plurality of comb tooth electrodes arranged in parallel and at equal intervals; the third comb tooth portion The portion 152 includes a plurality of comb-teeth electrodes arranged in parallel and at equal intervals; the fourth comb-teeth portion 153 includes a plurality of comb-teeth electrodes arranged in parallel and at equal intervals.
  • first comb-tooth portion 142 and the third comb-tooth portion 152 are alternately arranged to form the first portion 11 of the interdigitated structure, and the second comb-tooth portion 143 and the fourth comb-tooth portion 153 are alternately arranged to form a fork Refers to the second part 12 of the structure.
  • the comb-tooth electrodes of the adjacent first comb-tooth parts 142 and the third comb-tooth part 152 are separated by a first distance h1 ; in the second part 12 , adjacent There is a second interval h2 between the comb-tooth electrodes of the second comb-tooth portion 143 and the fourth comb-tooth portion 153 .
  • the first distance h1 is the width of the channel 100 formed between the first comb-tooth portion 142 and the third comb-tooth portion 152 having a longer length.
  • the second distance h2 is the width of the channel 100 formed between the second comb-tooth portion 143 and the fourth comb-tooth portion 153 with a shorter length.
  • the first distance h1 is equal to the second distance h2, that is, the widths of the channels 100 formed between the comb tooth portions with different lengths are the same.
  • the first pitch h1 and the second pitch h2 are both 3.5 ⁇ m.
  • the first distance h1 may not be equal to the second distance h2. That is, the widths of the channels 100 formed between the comb tooth portions with different lengths are different.
  • the first comb-tooth portion 142 and the second comb-tooth portion 143 are arranged in parallel, and there is a third distance a between the first comb-tooth portion 142 and the second comb-tooth portion 143 ;
  • the third distance a is greater than the first distance h1, and the third distance a is greater than the second distance h2.
  • the first comb-tooth portion 142 and the second comb-tooth portion of different comb-tooth lengths can be formed on the active layer 103 by using a conventional patterning process.
  • the patterns of the third comb-tooth portion 152 and the fourth comb-tooth portion 153 avoid photoresist from gathering and remaining in the third spacing a, so as to avoid the formation of the first pole 104 and the second pole in the third spacing a
  • the film layer of the 105 pattern is retained during the etching process, thereby preventing the first pole 104 and the second pole 105 from short-circuiting within the third spacing a, that is, avoiding channel short-circuiting within the third spacing a, and finally ensuring displacement.
  • the signal output of the register is normal, and the display products using this shift register are prevented from displaying defects such as horizontal stripes.
  • the width of the third pitch a is greater than or equal to 6 microns. In some embodiments, the width of the third pitch a pattern on the mask on which the third pitch a pattern is formed is 6 microns. In this way, on the one hand, the minimum manufacturing process precision requirement of the third spacing a can be met; on the other hand, the setting of the third spacing a will not greatly increase the occupied space of the transistor 1, thereby ensuring the display panel using the shift register. On the other hand, it can ensure that the first pole 104 and the second pole 105 will not be short-circuited in the short-circuit prevention area H, so as to ensure that the signal output of the shift register is normal, and avoid using the display of the shift register.
  • the product has defects such as horizontal stripes when displayed.
  • the width of the third pitch a pattern is more than 6 microns. In some embodiments, the width of the third pitch a is 10 microns.
  • the orthographic projection of the first comb handle portion 141 on the active layer 103 is an oblique line, which can be obtained by using a conventional patterning process.
  • the active layer 103 is disconnected at the third pitch a. Since the width of the third spacing a can be realized under the current preparation process conditions, when preparing the pattern of the active layer 103, a traditional patterning process (including film formation, photoresist coating, exposure, development, etching, etc.) is used. step) can also realize that the active layer 103 is disconnected at the third distance a, so as to realize the patterning of the active layer 103; further, the disconnection of the active layer 103 at the third distance a can further avoid the third distance a A short circuit occurs between the nearby first pole 104 and the second pole 105 .
  • a traditional patterning process including film formation, photoresist coating, exposure, development, etching, etc.
  • the active layers 103 of the first part 11 of the interdigitated structure are connected as a whole, and the active layers 103 of the second part 12 are connected as a whole.
  • the gates 101 of the first part 11 and the second part 12 of the interdigitated structure are connected as a whole, that is, the gate 101 of the transistor 1 is designed as a whole conductive film layer. This arrangement can not only better realize the transistor 1 with parameter setting performance, but also better realize the narrow frame or ultra-narrow frame of the display product using the shift register.
  • the first comb handle portion 141 is connected to any two adjacent comb-tooth electrodes in the first comb-tooth portion 142 to form a U-shaped unit 10
  • the first comb handle portion 141 and the second comb-tooth portion 143 are connected to form a U-shaped unit 10
  • Any two adjacent comb-teeth electrodes are connected to form a U-shaped unit 10
  • the first pole 104 includes a plurality of U-shaped units 10 connected in series.
  • the second comb handle portion 151 and any adjacent two comb-tooth electrodes in the third comb-tooth portion 152 are connected to form a U-shaped unit 10
  • the second comb handle portion 151 and the fourth comb-tooth portion 153 are connected to form a U-shaped unit 10
  • Any two adjacent comb-teeth electrodes are connected to form a U-shaped unit 10
  • the second pole 105 includes a plurality of U-shaped units 10 connected in series. This arrangement is beneficial to reduce the occupied area of the transistor 1, thereby helping to reduce the occupied area of the shift register, thereby reducing the frame width of the display product using the shift register, and realizing a narrow frame or an ultra-narrow frame.
  • the first electrode 104 is a source electrode
  • the second electrode 105 is a drain electrode.
  • the first electrode may be the drain electrode
  • the second electrode may be the source electrode.
  • the number of transistors 1 is one or more; among the plurality of transistors 1, at least one is a first combination 2 composed of two transistors 1, and the gates 101 of the transistors 1 in the first combination 2 are connected to each other , the first poles 104 are connected to each other, and the second poles 105 are connected to each other; the arrangement of the two transistors 1 in the first combination 2 is an axisymmetric pattern.
  • the number of transistors 1 is one. With this arrangement, the occupied area of the transistor 1 can be reduced, thereby reducing the occupied area of the shift register, thereby reducing the frame width of the display product using the shift register, and realizing a narrow frame or an ultra-narrow frame.
  • the shift register further includes one or more second transistors 3, the second transistor 3 includes a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, and the source electrode and the drain electrode have the same size and shape Comb-like structure, the source and drain form an interdigitated structure.
  • This arrangement can not only better realize the second transistor 3 for setting parameter performance, but also better realize the narrow frame or ultra-narrow frame of the display product using the shift register.
  • the plurality of second transistors 3 there is at least one second combination 4 composed of two second transistors 3, and the gates of the two second transistors 3 in the second combination 4 are connected to each other and the source
  • the two second transistors 3 in the second combination 4 are arranged in an axisymmetric pattern.
  • the number of the second transistors 3 is multiple. This arrangement can reduce the occupied area of the second transistor 3, thereby reducing the occupied area of the shift register, thereby reducing the frame width of the display product using the shift register, and realizing a narrow frame or an ultra-narrow frame.
  • the shift register is designed as a 21T1C circuit structure.
  • M6 and M6' transistors have the structure of transistor 1 in this embodiment, and M6 and M6' constitute a first combination 2, and M6 and M6' are arranged in an axisymmetric pattern.
  • the function of M6 in the shift register is to control the potential of point PD1 and pull down the potential of point PD1; the function of M6' in the shift register is to control the potential of point PD2 and pull down the potential of point PD2.
  • M5, M6, M6' and M5' are arranged in sequence along the width direction of the display screen frame (that is, the direction away from the display area of the display screen frame), and the M5 and M5' transistors are this embodiment.
  • the display screen will be arranged in M5, M6, M6' and M5'
  • the width of the frame at the position is wider, and by designing the M6 and M6' transistors to the structure of the transistor 1 in this embodiment, the frame of the display screen at the arrangement positions of M5, M6, M6' and M5' will be greatly reduced width, which is conducive to realizing a narrow border of the display screen.
  • the channel lengths of M6 and M6' are the same, 800 microns, respectively, and the channel lengths of M5 and M5' are the same, 100 microns, respectively.
  • all transistors with a channel length of more than 600 ⁇ m can be designed as the structure of transistor 1 .
  • the channel length of the transistor refers to the length of the orthographic projection of the active layer located in the facing gap between the source and the drain extending along the extending direction of the facing gap.
  • the preparation of the shift register adopts a traditional preparation process, such as a patterning process, which will not be repeated here.
  • An embodiment of the present disclosure further provides a shift register.
  • the difference from the above embodiments is that, referring to FIGS. 10 and 11 , in the short-circuit prevention area H, the first comb-tooth portion 142 is adjacent to the second comb-tooth portion 143 , And the first interval h1 or the second interval h2 between the first comb-tooth portion 142 and the second comb-tooth portion 143 , that is, the value of the third interval a is the channel length of the first portion 11 or the groove of the second portion 12 . track length.
  • the comb-tooth electrode of the second pole 105 is not provided between the first comb-tooth portion 142 and the second comb-tooth portion 143, it is equivalent to setting a short-circuit-proof area H in the short-circuit proof area H.
  • the dummy U-shaped cell 13 of the pole is not formed with a channel, so the dummy U-shaped cell 13 will not function as a conventional transistor.
  • the orthographic projection of the first comb handle portion 141 on the active layer 103 is an arc
  • the interval between the first comb tooth portion 142 and the second comb tooth portion 143 is a first
  • the spacing h1 or the second spacing h2 can be prepared by using a conventional patterning process.
  • the second pole 105 further includes a fifth comb-tooth portion 154 , and the fifth comb-tooth portion 154 is connected to the second The comb handle part 151 is connected; the fifth comb tooth part 154 is located in the short-circuit prevention area H, and is located on the center line parallel to the interval area between the first comb tooth part 142 and the second comb tooth part 143; the fifth comb tooth part 154 A fourth interval b is spaced between the teeth portion 154 and the first comb handle portion 141 ; the fourth interval b is greater than the first interval h1 , and the fourth interval b is greater than the second interval h2 .
  • the photoresist in the short-circuit prevention region H is easily gathered on the side close to the first comb handle portion 141 . Since the length of the comb-tooth electrode of the fifth comb-tooth portion 154 is smaller than that of the third comb-tooth portion 152 , the active layer 103 in the orthographic overlapping area with the fourth pitch b will form the opening 106 , and the opening 106 will form an opening 106 in the area of the active layer 103 . The inner active layer 103 has lost the function of the channel, so the channel short circuit will not be formed; A short circuit occurs between the one pole 104 and the second pole 105 .
  • the shift register provided in the above embodiment is surrounded by the orthographic projection of the first comb tooth portion and the second comb tooth portion, the first comb handle portion and the second comb handle portion on the active layer with different comb tooth lengths.
  • a short-circuit prevention area H is formed, and the first and second comb-tooth parts of the first pole with different lengths and the third comb-tooth part and
  • the photoresist can be prevented from accumulating in the channel formed between the comb-tooth portions of different lengths of the transistor, so as to avoid the film layer forming the first pole and the second pole pattern in this part of the channel.
  • the display product has defects such as horizontal stripes during display.
  • an embodiment of the present disclosure provides a gate driving circuit, including a plurality of shift registers in any of the above embodiments; the plurality of shift registers are cascaded.
  • the shift register in any of the above embodiments, not only the occupied area of the gate driving circuit can be reduced, thereby facilitating the realization of a narrow frame or an ultra-narrow frame of a display product using the gate driving circuit, but also avoiding the need for The gate driving circuit has a channel short circuit defect, thereby ensuring that the display product using the gate driving circuit can display normally.
  • embodiments of the present disclosure provide a display panel including the gate driving circuit in the above embodiments.
  • the display panel further includes an array substrate, the array substrate includes a display area and a frame area, the frame area is arranged around the periphery of the display area; the gate driving circuits are arranged on the array substrate and are respectively located on opposite sides of the display area border area.
  • the gate driving circuits respectively located in the frame areas on opposite sides of the display area can realize bilateral driving of pixels in each row of the display area, so that the display brightness of the display panel is more uniform and the display effect is better.
  • the gate driving circuits respectively located in the border areas on opposite sides of the display area can also realize unilateral driving of each row of pixels in the display area.
  • the gate driving circuit is disposed on the array substrate and is located in a frame area on one side of the display area. Wherein, the gate driving circuit located in the frame area of a certain side of the display area can realize unilateral driving of each row of pixels in the display area.
  • the gate driving circuit in the above-mentioned embodiment, not only the width of the frame of the display panel can be reduced, thereby facilitating the realization of a narrow frame or an ultra-narrow frame of the display panel, but also the occurrence of the display panel due to the gate driving circuit can be avoided.
  • the display failure caused by the short-circuit in the middle channel ensures that the display panel can display normally.
  • the display panel provided by the embodiments of the present disclosure may be any product or component with a display function, such as an LCD panel, an LCD TV, a display, a mobile phone, and a navigator.

Abstract

提供一种移位寄存器、栅极驱动电路和显示面板。移位寄存器包括：晶体管（1）；晶体管（1）包括栅极（101）、栅绝缘层（102）、有源层（103）、第一极（104）和第二极（105）；第一极（104）和第二极（105）为梳状结构；第一极（104）包括间隔排布的第一梳齿部（142）和第二梳齿部（145），以及连接第一梳齿部（142）和第二梳齿部（145）的第一梳柄部（141），第一梳齿部（142）和第二梳齿部（145）的梳齿电极长度不同；第二极（105）包括间隔排布的第三梳齿部（152）和第四梳齿部（153），以及连接第三梳齿部（152）和第四梳齿部（153）的第二梳柄部（151）；第一梳齿部（142）与第三梳齿部（152）构成叉指结构，第二梳齿部（145）与第四梳齿部（153）构成叉指结构，且在有源层（103）上的正投影均无交叠；第一梳齿部（142）、第二梳齿部（145）、第一梳柄部（141）和第二梳柄部（151）在有源层（103）上的正投影围成防短路区（H），用于防止第一极（104）与第二极（105）之间发生短路。

Description

移位寄存器、栅极驱动电路和显示面板 技术领域
本公开实施例属于显示技术领域，具体涉及一种移位寄存器、栅极驱动电路和显示面板。
背景技术
GOA(Gate Driver on Array，集成栅极驱动电路)技术可以将栅极驱动电路集成在显示面板的阵列基板上，替代由外接硅片制作的驱动芯片，可以省掉Gate IC(Gate Integrated Circuit，栅极驱动集成电路)部分以及扇出型(Fan-out)布线空间，以简化显示产品的结构，减小显示产品边框。
发明内容
本公开实施例提供一种移位寄存器、栅极驱动电路和显示面板。
第一方面，本公开实施例提供一种移位寄存器，包括：晶体管；
所述晶体管包括栅极、栅绝缘层、有源层、第一极和第二极；所述第一极和所述第二极为梳状结构；
所述第一极包括间隔排布的第一梳齿部和第二梳齿部，以及连接所述第一梳齿部和第二梳齿部的第一梳柄部，所述第一梳齿部和所述第二梳齿部的梳齿电极长度不同；
所述第二极包括间隔排布的第三梳齿部和第四梳齿部，以及连接所述第三梳齿部和所述第四梳齿部的第二梳柄部；
所述第一梳齿部与所述第三梳齿部构成叉指结构，所述第二梳齿部与所述第四梳齿部构成叉指结构，且在所述有源层上的正投影均无交叠；
所述第一梳齿部、所述第二梳齿部、所述第一梳柄部和所述第二梳柄部在所述有源层上的正投影围成防短路区，用于防止所述第一极与所述第二极之间发生短路。
在一些实施例中，所述第一梳齿部的梳齿电极长度大于所述第二梳齿部的梳齿电极长度；所述第三梳齿部的梳齿电极长度大于所述第四梳齿部的梳齿电极长度。
在一些实施例中，所述第一梳齿部包括多个平行且等间距排布的梳齿电极；
所述第二梳齿部包括多个平行且等间距排布的梳齿电极；
所述第三梳齿部包括多个平行且等间距排布的梳齿电极；
所述第四梳齿部包括多个平行且等间距排布的梳齿电极。
在一些实施例中，所述第一梳齿部与所述第三梳齿部交错排布构成叉指结构的第一部，所述第二梳齿部与所述第四梳齿部交错排布构成叉指结构的第二部。
在一些实施例中，所述第一部内，相邻的所述第一梳齿部与所述第三梳齿部梳齿电极之间间隔第一间距；所述第二部内，相邻的所述第二梳齿部与所述第四梳齿部梳齿电极之间间隔第二间距。
在一些实施例中，所述防短路区内，所述第一梳齿部与所述第二梳齿部平行排布，且所述第一梳齿部与所述第二梳齿部之间间隔第三间距；
所述第三间距大于所述第一间距，且所述第三间距大于所述第二间距。
在一些实施例中，所述第三间距大于或等于6微米。
在一些实施例中，所述防短路区内，所述第一梳柄部在所述有源层上的正投影为斜线。
在一些实施例中，所述防短路区内，所述第一梳齿部与所述第二梳齿部相邻，且所述第一梳齿部与所述第二梳齿部之间间隔所述第一间距或者所述第二间距。
在一些实施例中，所述防短路区内，所述第一梳柄部在所述有源层上的正投影为弧形。
在一些实施例中，所述第二极还包括第五梳齿部，所述第五梳齿部与 所述第二梳柄部连接；所述第五梳齿部位于所述防短路区内，且位于所述第一梳齿部与所述第二梳齿部之间间隔区域的与二者平行的中线上；
所述第五梳齿部与所述第一梳柄部之间间隔第四间距；
所述第四间距大于所述第一间距，且所述第四间距大于所述第二间距。
在一些实施例中，所述第一间距等于所述第二间距。
在一些实施例中，所述第一梳柄部与所述第一梳齿部中任意相邻的两个梳齿电极连接形成U形单元，所述第一梳柄部与所述第二梳齿部中任意相邻的两个梳齿电极连接形成U形单元，所述第一极包括多个串联连接的所述U形单元。
在一些实施例中，所述第二梳柄部与所述第三梳齿部中任意相邻的两个梳齿电极连接形成U形单元，所述第二梳柄部与所述第四梳齿部中任意相邻的两个梳齿电极连接形成U形单元，所述第二极包括多个串联连接的所述U型单元。
在一些实施例中，所述栅极位于所述有源层的下方，或者，所述栅极位于所述有源层的上方。
在一些实施例中，所述第一极为源极，所述第二极为漏极；
或者，所述第一极为漏极，所述第二极为源极。
在一些实施例中，所述晶体管的数量为一个或多个；
多个所述晶体管中，至少有一个由两个所述晶体管构成的第一组合，所述第一组合中所述晶体管的所述栅极相互连接、所述第一极相互连接、所述第二极相互连接；
所述第一组合中两个所述晶体管的排布呈轴对称图形。
第二方面，本公开实施例提供一种栅极驱动电路，包括多个上述移位寄存器；多个所述移位寄存器级联。
第三方面，本公开实施例提供一种显示面板，包括上述栅极驱动电路。
在一些实施例中，还包括阵列基板，所述阵列基板包括显示区和边框 区，所述边框区围设于所述显示区外围；
所述栅极驱动电路设置于所述阵列基板上，且分别位于所述显示区相对两侧的所述边框区。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1为显示面板中栅极驱动电路的分布俯视示意图；
图2为21T1C电路结构的移位寄存器的电路图；
图3为每个晶体管是一种尺寸类型的移位寄存器的局部版图；
图4为其中一个晶体管是不同尺寸类型的移位寄存器的局部版图；
图5为沿图4中AA剖切线的结构剖视图；
图6为图4中过渡区内晶体管发生沟道短路的示意图；
图7为本公开实施例中移位寄存器的局部版图；
图8为图7的移位寄存器中晶体管的结构俯视示意图；
图9为沿图8中BB剖切线的结构剖视图；
图10为本公开实施例中另一种移位寄存器中晶体管的结构俯视示意图；
图11为沿图10中CC剖切线的结构剖视图；
图12为本公开实施例中又一种移位寄存器中晶体管的结构俯视示意图；
图13为沿图12中DD剖切线的结构剖视图。
其中附图标记为：
1、晶体管；10、U形单元；100、沟道；101、栅极；102、栅绝缘层；103、有源层；104、第一极；105、第二极；11、第一部；12、第二部；141、 第一梳柄部；142、第一梳齿部；143、第二梳齿部；151、第二梳柄部；152、第三梳齿部；153、第四梳齿部；154、第五梳齿部；13、虚设U形单元；2、第一组合；3、第二晶体管；4、第二组合；106、开口；108、源极；109、漏极；110、钝化层；5、显示区；6、边框区；7、像素单元；8、栅线；9、数据线；14、移位寄存器；15、薄膜晶体管；16、晶体管。
具体实施方式
为使本领域技术人员更好地理解本公开实施例的技术方案，下面结合附图和具体实施方式对本公开实施例提供的一种移位寄存器、栅极驱动电路和显示面板作进一步详细描述。
在下文中将参考附图更充分地描述本公开实施例，但是所示的实施例可以以不同形式来体现，且不应当被解释为限于本公开阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了区的具体形状，但并不是旨在限制性的。
公开技术中，参照图1，显示面板通常具有显示区5和环绕显示区5的边框区6；在显示区5中设置有呈阵列排布的多个像素单元7，每个像素单元7中设置有像素电路；其中，位于同一行的像素单元7连接同一条栅线8，位于同一列的像素单元7连接同一条数据线9。在边框区6设置有栅极驱动电路，而栅极驱动电路则包括多个级联的移位寄存器(GOA，Gate on Array)14，移位寄存器14与栅线8一一对应设置，即每一个移位寄存器14连接一条栅线8。在显示每一帧画面时，通过逐级移位寄存器14输出栅极扫描信号至与各自对应的栅线8，以完成像素电路的逐行扫描，在每一行栅线8被扫描的同时，各条数据线9将数据电压信号写入该行的像素电路，以点亮该行像素单元7。
参照图2和图3，移位寄存器(GOA)是由多个薄膜晶体管15(Thin Film Transistor)以及电容等器件构成的栅极驱动电路。在移位寄存器中，大多数薄膜晶体管15都分别由多个同栅(栅极连接在一起)、同源(源极108连接在一起)、同漏(漏极109连接在一起)的尺寸较小的晶体管16电连接构成，且这些尺寸较小的晶体管16的有源层由一整片膜层构成，以实现对各个薄膜晶体管15设计的沟道长度的要求。在边框区宽度足够的情况下，薄膜晶体管15中尺寸较小的晶体管16大多都是一种尺寸类型的晶体管，参照图3，薄膜晶体管15中各小晶体管16的尺寸均一。但近来，为了提升显示产品的外观形象，客户大多要求显示产品(如MNT显示产品，即18.5～34英寸的显示产品)为超窄边框，也即尽可能的使显示产品的显示区足够大，满足客户在观看过程中的视觉享受。
当显示产品为超窄边框设计时，为了满足显示产品正常驱动，移位寄存器中的薄膜晶体管15必须在有限的边框宽度中完成布局，所以通常会将构成某些薄膜晶体管15的小尺寸晶体管16大小搭配设计，参照图4。
参照图5和图6，某些薄膜晶体管15中，在大小尺寸晶体管16搭配设计的过渡区G中，一方面，由于分布有大小尺寸晶体管16的过渡区G的尺寸相对于大尺寸晶体管分布区和小尺寸晶体管分布区尺寸有所变化，即过渡区G是一个尺寸不规则区；另一方面，由于构成该薄膜晶体管15的所有大小尺寸的晶体管16的沟道宽度h(即晶体管源极108和漏极109之间的正对间隙宽度)都是相同的，约为3.5μm；所以当采用传统构图工艺在有源层103图形上形成大小尺寸晶体管16的源漏极图形时，光刻胶(如PR胶)容易聚集在过渡区G内大小尺寸晶体管16的沟道内，导致部分沟道内的源漏极膜层本不应该被光刻胶保护却被光刻胶覆盖保护，以致该部分沟道内的源漏极膜层在刻蚀过程中保留下来，导致了大小尺寸晶体管16的源极108和漏极109之间发生短路(也称沟道短路)，这使得移位寄存器信号输出异常，导致显示产品显示时出现横纹等不良。
针对移位寄存器存在的上述沟道短路不良问题，本公开实施例提供如下技术方案。
第一方面，本公开实施例提供一种移位寄存器，参照图7-图9，包括：晶体管1；晶体管1包括栅极101、栅绝缘层102、有源层103、第一极104和第二极105；第一极104和第二极105为梳状结构；第一极104包括间隔排布的第一梳齿部142和第二梳齿部143，以及连接第一梳齿部142和第二梳齿部143的第一梳柄部141，第一梳齿部142和第二梳齿部143的梳齿电极长度不同；第二极105包括间隔排布的第三梳齿部152和第四梳齿部153，以及连接第三梳齿部152和第四梳齿部153的第二梳柄部151；第一梳齿部142与第三梳齿部152构成叉指结构，第二梳齿部143与第四梳齿部153构成叉指结构，且在有源层103上的正投影均无交叠；第一梳齿部142、第二梳齿部143、第一梳柄部141和第二梳柄部151在有源层103上的正投影围成防短路区H，用于防止第一极104与第二极105之间发生短路。
其中，第一梳齿部142和第三梳齿部152之间的正对间隙中的有源层103，以及第二梳齿部143和第四梳齿部153之间的正对间隙中的有源层103构成了晶体管1沟道100的一部分。当晶体管1的栅极101输入开启电压时，晶体管1的第一极104和第二极105导通，电流经过晶体管1的沟道100由第一极104流向第二极105，或者，电流经过晶体管1的沟道100由第二极105流向第一极104，从而实现晶体管1的开启。
在一些实施例中，栅极101位于有源层103的下方，即晶体管1为底栅型晶体管。在一些实施例中，栅极101位于有源层103的上方，即晶体管1为顶栅型晶体管。本实施例中，以底栅型晶体管为例进行说明，晶体管1还包括设置于第一极104和第二极105背离有源层103一侧的钝化层110。晶体管1的制备包括依次形成栅极101、栅绝缘层102、有源层103的图形，然后在有源层103的图形上形成第一极104和第二极105的图形， 最后在第一极104和第二极105上方形成钝化层110。栅极101、有源层103、第一极104和第二极105的图形分别采用传统构图工艺(包括成膜、光刻胶涂覆、曝光、显影和刻蚀等步骤)形成。
通过由不同长度的第一梳齿部142和第二梳齿部143、第一梳柄部141以及第二梳柄部151在有源层103上的正投影围成防短路区，在采用传统构图工艺在有源层103上形成不同长度的第一极104的第一梳齿部142和第二梳齿部143以及不同长度的第二极105的第三梳齿部152和第四梳齿部153的图形时，能够避免光刻胶聚集在晶体管1的不同长度的梳齿部之间形成的沟道100内，从而避免该部分沟道100内的形成第一极104和第二极105图形的膜层在刻蚀过程中保留下来，进而避免第一极104和第二极105在该部分沟道100内发生短路，也即避免发生沟道短路，最终确保移位寄存器的信号输出正常，避免采用该移位寄存器的显示产品在显示时出现横纹等不良。
在一些实施例中，第一梳齿部142的梳齿电极长度大于第二梳齿部143的梳齿电极长度；第三梳齿部152的梳齿电极长度大于第四梳齿部153的梳齿电极长度。
在一些实施例中，第一梳齿部142包括多个平行且等间距排布的梳齿电极；第二梳齿部143包括多个平行且等间距排布的梳齿电极；第三梳齿部152包括多个平行且等间距排布的梳齿电极；第四梳齿部153包括多个平行且等间距排布的梳齿电极。
在一些实施例中，第一梳齿部142与第三梳齿部152交错排布构成叉指结构的第一部11，第二梳齿部143与第四梳齿部153交错排布构成叉指结构的第二部12。
在一些实施例中，第一部11内，相邻的第一梳齿部142与第三梳齿部152的梳齿电极之间间隔第一间距h1；第二部12内，相邻的第二梳齿部143与第四梳齿部153的梳齿电极之间间隔第二间距h2。其中，第一间距h1为 长度较长的第一梳齿部142与第三梳齿部152之间形成的沟道100的宽度。第二间距h2为长度较短的第二梳齿部143与第四梳齿部153之间形成的沟道100的宽度。
在一些实施例中，第一间距h1等于第二间距h2，即长度不同的梳齿部之间形成的沟道100的宽度相同。在一些实施例中，第一间距h1和第二间距h2均为3.5μm。
在一些实施例中，第一间距h1也可以不等于第二间距h2。即长度不同的梳齿部之间形成的沟道100的宽度不同。
在一些实施例中，防短路区H内，第一梳齿部142与第二梳齿部143平行排布，且第一梳齿部142与第二梳齿部143之间间隔第三间距a；第三间距a大于第一间距h1，且第三间距a大于第二间距h2。
通过在防短路区H内设置宽度大于沟道宽度的第三间距a，可在采用传统构图工艺在有源层103上形成不同梳齿长度的的第一梳齿部142、第二梳齿部143、第三梳齿部152和第四梳齿部153的图形时，避免光刻胶聚集并残留在第三间距a内，从而避免第三间距a内的形成第一极104和第二极105图形的膜层在刻蚀过程中保留下来，进而避免第一极104和第二极105在第三间距a内发生短路，也即避免第三间距a内发生沟道短路，最终确保移位寄存器的信号输出正常，避免采用该移位寄存器的显示产品在显示时出现横纹等不良。
在一些实施例中，第三间距a的宽度大于或等于6微米。在一些实施例中，形成第三间距a图形的掩膜板上的第三间距a图形的宽度为6微米。如此设置，一方面，能满足第三间距a的最低制备工艺精度要求；另一方面，第三间距a的设置不会大幅增加晶体管1的占用空间，从而可保证采用该移位寄存器的显示面板实现窄边框；再一方面，能确保第一极104和第二极105在防短路区H内不会发生沟道短路，从而确保移位寄存器的信号输出正常，避免采用该移位寄存器的显示产品在显示时出现横纹等不良。
在一些实施例中，在目前的制备工艺条件下，第三间距a图形的宽度为6微米以上。在一些实施例中，第三间距a的宽度为10微米。
在一些实施例中，防短路区H内，第一梳柄部141在有源层103上的正投影为斜线，可采用传统构图工艺制备得到。
在一些实施例中，有源层103在第三间距a处断开。由于第三间距a的宽度能在目前的制备工艺条件下实现，所以，在制备有源层103图形时，采用传统构图工艺(包括成膜、光刻胶涂覆、曝光、显影、刻蚀等步骤)也能够实现有源层103在第三间距a处断开，从而实现有源层103的图案化；进一步地，有源层103在第三间距a处断开能进一步避免第三间距a附近的第一极104和第二极105之间发生短路。
在一些实施例中，叉指结构的第一部11的有源层103连接为一体，第二部12的有源层103连接为一体。在一些实施例中，叉指结构的第一部11和第二部12的栅极101连接为一体，即晶体管1的栅极101为一整片导电膜层设计。如此设置，不仅能够更好地实现设定参数性能的晶体管1，而且还能更好地实现采用该移位寄存器的显示产品的窄边框或超窄边框。
在一些实施例中，第一梳柄部141与第一梳齿部142中任意相邻的两个梳齿电极连接形成U形单元10，第一梳柄部141与第二梳齿部143中任意相邻的两个梳齿电极连接形成U形单元10，第一极104包括多个串联连接的U形单元10。
在一些实施例中，第二梳柄部151与第三梳齿部152中任意相邻的两个梳齿电极连接形成U形单元10，第二梳柄部151与第四梳齿部153中任意相邻的两个梳齿电极连接形成U形单元10，第二极105包括多个串联连接的U型单元10。如此设置，有利于减小晶体管1的占用面积，从而有利于减小移位寄存器的占用面积，进而有利于减小采用该移位寄存器的显示产品的边框宽度，实现窄边框或超窄边框。
在一些实施例中，第一极104为源极，第二极105为漏极。在一些实 施例中，也可以为第一极为漏极，第二极为源极。
在一些实施例中，晶体管1的数量为一个或多个；多个晶体管1中，至少有一个由两个晶体管1构成的第一组合2，第一组合2中晶体管1的栅极101相互连接、第一极104相互连接、第二极105相互连接；第一组合2中两个晶体管1的排布呈轴对称图形。本实施例中，晶体管1的数量为一个。如此设置，能够减小晶体管1的占用面积，从而减小移位寄存器的占用面积，进而减小采用该移位寄存器的显示产品的边框宽度，实现窄边框或超窄边框。
在一些实施例中，移位寄存器还包括一个或多个第二晶体管3，第二晶体管3包括栅极、栅绝缘层、有源层、源极和漏极，源极和漏极为大小形状相同的梳状结构，源极和漏极构成叉指结构。如此设置，不仅能够更好地实现设定参数性能的第二晶体管3，而且还能更好地实现采用该移位寄存器的显示产品的窄边框或超窄边框。
在一些实施例中，多个第二晶体管3中，至少有一个由两个第二晶体管3构成的第二组合4，第二组合4中两个第二晶体管3的栅极相互连接、源极相互连接、漏极相互连接；第二组合4中两个第二晶体管3的排布呈轴对称图形。本实施例中，第二晶体管3的数量为多个。如此设置，能够减小第二晶体管3的占用面积，从而减小移位寄存器的占用面积，进而减小采用该移位寄存器的显示产品的边框宽度，实现窄边框或超窄边框。
参照图2，移位寄存器设计为21T1C电路结构。其中，M6和M6＇晶体管为本实施例中晶体管1的结构，且M6和M6＇构成第一组合2，M6和M6＇的排布呈轴对称图形。M6在移位寄存器中的作用是控制PD1点的电位，拉低PD1点的电位；M6＇在移位寄存器中的作用是控制PD2点的电位，拉低PD2点的电位。在移位寄存器的21T1C电路中，M5、M6、M6＇和M5＇沿显示屏边框的宽度方向(即显示屏边框的远离显示区的方向)依次排布，M5和M5＇晶体管为本实施例中第二晶体管3的结构，如果M6和M6＇中第一 极的梳齿部长度相同，第二极的梳齿部长度相同，会使显示屏在M5、M6、M6＇和M5＇排布位置处的边框宽度较宽，而通过将M6和M6＇晶体管设计为本实施例中晶体管1的结构，则会大大减小显示屏在M5、M6、M6＇和M5＇排布位置处的边框宽度，从而有利于实现显示屏的窄边框。
参照图2，M6和M6＇的沟道长度相同，分别为800微米，M5和M5＇的沟道长度相同，分别为100微米。本实施例中，为了实现采用上述移位寄存器的显示屏的窄边框或者超窄边框，沟道长度在600微米以上的晶体管都可以设计为晶体管1的结构。晶体管的沟道长度指正投影位于源极和漏极之间的正对间隙中的有源层沿该正对间隙的延伸方向延伸的长度。
移位寄存器的制备采用传统制备工艺，如构图工艺，这里不再赘述。
本公开实施例还提供一种移位寄存器，与上述实施例中不同的是，参照图10和图11，防短路区H内，第一梳齿部142与第二梳齿部143相邻，且第一梳齿部142与第二梳齿部143之间间隔第一间距h1或者第二间距h2，即第三间距a的数值为第一部11的沟道长度或第二部12的沟道长度。
其中，防短路区H内，由于在第一梳齿部142与第二梳齿部143之间未设置第二极105梳齿电极，所以相当于在防短路区H内设置了一个缺少第二极的虚设U形单元13，该虚设U形单元13由于未形成沟道，所以不会起到常规晶体管的功能性作用。如此设置，即使在第一极104和第二极105的图形刻蚀过程中光刻胶聚集在防短路区H的虚设U形单元13处，也不会导致第一极104和第二极105之间发生短路，即不会使晶体管1发生沟道短路。
在一些实施例中，防短路区H内，第一梳柄部141在有源层103上的正投影为弧形，第一梳齿部142与第二梳齿部143之间间隔为第一间距h1或者第二间距h2，可采用传统构图工艺制备得到。
本实施例中移位寄存器的其他结构设置与上述实施例中相同，此处不 再赘述。
本公开实施例还提供一种移位寄存器，与上述实施例中不同的是，参照图12和图13，第二极105还包括第五梳齿部154，第五梳齿部154与第二梳柄部151连接；第五梳齿部154位于防短路区H内，且位于第一梳齿部142与第二梳齿部143之间间隔区域的与二者平行的中线上；第五梳齿部154与第一梳柄部141之间间隔第四间距b；第四间距b大于第一间距h1，且第四间距b大于第二间距h2。
在采用传统刻蚀工艺对第一极104和第二极105图案化时，防短路区H的光刻胶容易聚集在靠近第一梳柄部141的一侧。由于第五梳齿部154的梳齿电极长度小于第三梳齿部152的梳齿电极长度，所以与第四间距b正投影交叠区域的有源层103会形成开口106，在开口106区域内的有源层103已经失去沟道的作用，因此不会形成沟道短路；另一方面，由于第四间距b的宽度较大，光刻胶不会残留在该处，进一步地避免了第一极104和第二极105之间发生短路。
本实施例中移位寄存器的其他结构设置与上述实施例中相同，此处不再赘述。
上述实施例中所提供的移位寄存器，通过由不同梳齿长度的第一梳齿部和第二梳齿部、第一梳柄部以及第二梳柄部在有源层上的正投影围成防短路区H，在采用传统构图工艺在有源层图形上形成不同长度的第一极的第一梳齿部和第二梳齿部以及不同长度的第二极的第三梳齿部和第四梳齿部的图形时，能够避免光刻胶聚集在晶体管的不同长度的梳齿部之间形成的沟道内，从而避免该部分沟道内的形成第一极和第二极图形的膜层在刻蚀过程中保留下来，进而避免第一极和第二极在该部分沟道内发生短路，也即避免发生沟道短路，最终确保移位寄存器的信号输出正常，避免采用该移位寄存器的显示产品在显示时出现横纹等不良。
第二方面，本公开实施例提供一种栅极驱动电路，包括多个上述任一实施例中的移位寄存器；多个移位寄存器级联。
通过采用上述任一实施例中的移位寄存器，不仅能够减小该栅极驱动电路的占用面积，从而有利于实现采用该栅极驱动电路的显示产品的窄边框或超窄边框，而且能够避免该栅极驱动电路发生沟道短路不良，进而确保采用该栅极驱动电路的显示产品能够正常显示。
第三方面，本公开实施例提供一种显示面板，包括上述实施例中的栅极驱动电路。
在一些实施例中，显示面板还包括阵列基板，阵列基板包括显示区和边框区，边框区围设于显示区外围；栅极驱动电路设置于阵列基板上，且分别位于显示区相对两侧的边框区。其中，分别位于显示区相对两侧边框区的栅极驱动电路能够实现对显示区内每行像素的双边驱动，从而使该显示面板的显示亮度更加均匀，显示效果更佳。当然，分别位于显示区相对两侧边框区的栅极驱动电路也可以实现对显示区内每行像素的单边驱动。
在一些实施例中，栅极驱动电路设置于阵列基板上，且位于显示区某一侧的边框区。其中，位于显示区某一侧边框区的栅极驱动电路能够实现对显示区内每行像素的单边驱动。
通过采用上述实施例中的栅极驱动电路，不仅能够减小该显示面板的边框宽度，从而有利于实现该显示面板的窄边框或超窄边框，而且能够避免该显示面板发生由于栅极驱动电路中沟道短路所导致的显示不良，进而确保该显示面板能够正常显示。
本公开实施例所提供的显示面板可以为LCD面板、LCD电视、显示器、手机、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (20)

  1. 一种移位寄存器，其特征在于，包括：
    晶体管；
    所述晶体管包括栅极、栅绝缘层、有源层、第一极和第二极；所述第一极和所述第二极为梳状结构；
    所述第一极包括间隔排布的第一梳齿部和第二梳齿部，以及连接所述第一梳齿部和第二梳齿部的第一梳柄部，所述第一梳齿部和所述第二梳齿部的梳齿电极长度不同；
    所述第二极包括间隔排布的第三梳齿部和第四梳齿部，以及连接所述第三梳齿部和所述第四梳齿部的第二梳柄部；
    所述第一梳齿部与所述第三梳齿部构成叉指结构，所述第二梳齿部与所述第四梳齿部构成叉指结构，且在所述有源层上的正投影均无交叠；
    所述第一梳齿部、所述第二梳齿部、所述第一梳柄部和所述第二梳柄部在所述有源层上的正投影围成防短路区，用于防止所述第一极与所述第二极之间发生短路。
  2. 根据权利要求1所述的移位寄存器，其特征在于，所述第一梳齿部的梳齿电极长度大于所述第二梳齿部的梳齿电极长度；所述第三梳齿部的梳齿电极长度大于所述第四梳齿部的梳齿电极长度。
  3. 根据权利要求2所述的移位寄存器，其特征在于，所述第一梳齿部包括多个平行且等间距排布的梳齿电极；
    所述第二梳齿部包括多个平行且等间距排布的梳齿电极；
    所述第三梳齿部包括多个平行且等间距排布的梳齿电极；
    所述第四梳齿部包括多个平行且等间距排布的梳齿电极。
  4. 根据权利要求3所述的移位寄存器，其特征在于，所述第一梳齿部与所述第三梳齿部交错排布构成叉指结构的第一部，所述第二梳齿部与所述第四梳齿部交错排布构成叉指结构的第二部。
  5. 根据权利要求4所述的移位寄存器，其特征在于，所述第一部内，相邻的所述第一梳齿部与所述第三梳齿部梳齿电极之间间隔第一间距；所述第二部内，相邻的所述第二梳齿部与所述第四梳齿部的梳齿电极之间间隔第二间距。
  6. 根据权利要求5所述的移位寄存器，其特征在于，所述防短路区内，所述第一梳齿部与所述第二梳齿部平行排布，且所述第一梳齿部与所述第二梳齿部之间间隔第三间距；
    所述第三间距大于所述第一间距，且所述第三间距大于所述第二间距。
  7. 根据权利要求6所述的移位寄存器，其特征在于，所述第三间距大于或等于6微米。
  8. 根据权利要求6所述的移位寄存器，其特征在于，所述防短路区内，所述第一梳柄部在所述有源层上的正投影为斜线。
  9. 根据权利要求5所述的移位寄存器，其特征在于，所述防短路区内，所述第一梳齿部与所述第二梳齿部相邻，且所述第一梳齿部与所述第二梳齿部之间间隔所述第一间距或者所述第二间距。
  10. 根据权利要求9所述的移位寄存器，其特征在于，所述防短路区 内，所述第一梳柄部在所述有源层上的正投影为弧形。
  11. 根据权利要求5所述的移位寄存器，其特征在于，所述第二极还包括第五梳齿部，所述第五梳齿部与所述第二梳柄部连接；所述第五梳齿部位于所述防短路区内，且位于所述第一梳齿部与所述第二梳齿部之间间隔区域的与二者平行的中线上；
    所述第五梳齿部与所述第一梳柄部之间间隔第四间距；
    所述第四间距大于所述第一间距，且所述第四间距大于所述第二间距。
  12. 根据权利要求5所述的移位寄存器，其特征在于，所述第一间距等于所述第二间距。
  13. 根据权利要求5所述的移位寄存器，其特征在于，所述第一梳柄部与所述第一梳齿部中任意相邻的两个梳齿电极连接形成U形单元，所述第一梳柄部与所述第二梳齿部中任意相邻的两个梳齿电极连接形成U形单元，所述第一极包括多个串联连接的所述U形单元。
  14. 根据权利要求5所述的移位寄存器，其特征在于，所述第二梳柄部与所述第三梳齿部中任意相邻的两个梳齿电极连接形成U形单元，所述第二梳柄部与所述第四梳齿部中任意相邻的两个梳齿电极连接形成U形单元，所述第二极包括多个串联连接的所述U型单元。
  15. 根据权利要求1所述的移位寄存器，其特征在于，所述栅极位于所述有源层的下方，或者，所述栅极位于所述有源层的上方。
  16. 根据权利要求1所述的移位寄存器，其特征在于，所述第一极为 源极，所述第二极为漏极；
    或者，所述第一极为漏极，所述第二极为源极。
  17. 根据权利要求1所述的移位寄存器，其特征在于，所述晶体管的数量为一个或多个；
    多个所述晶体管中，至少有一个由两个所述晶体管构成的第一组合，所述第一组合中所述晶体管的所述栅极相互连接、所述第一极相互连接、所述第二极相互连接；
    所述第一组合中两个所述晶体管的排布呈轴对称图形。
  18. 一种栅极驱动电路，其特征在于，包括多个如权利要求1-17任意一项所述的移位寄存器；多个所述移位寄存器级联。
  19. 一种显示面板，其特征在于，包括权利要求18所述的栅极驱动电路。
  20. 根据权利要求19所述的显示面板，其特征在于，还包括阵列基板，所述阵列基板包括显示区和边框区，所述边框区围设于所述显示区外围；
    所述栅极驱动电路设置于所述阵列基板上，且分别位于所述显示区相对两侧的所述边框区。
PCT/CN2021/078442 2021-03-01 2021-03-01 移位寄存器、栅极驱动电路和显示面板 WO2022183313A1 (zh)

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