WO2022174430A1 - 一种存储器及电子设备 - Google Patents

一种存储器及电子设备 Download PDF

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Publication number
WO2022174430A1
WO2022174430A1 PCT/CN2021/077120 CN2021077120W WO2022174430A1 WO 2022174430 A1 WO2022174430 A1 WO 2022174430A1 CN 2021077120 W CN2021077120 W CN 2021077120W WO 2022174430 A1 WO2022174430 A1 WO 2022174430A1
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Prior art keywords
memory
storage array
storage
array
layer
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PCT/CN2021/077120
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English (en)
French (fr)
Inventor
卜思童
方亦陈
张恒
许俊豪
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华为技术有限公司
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Priority to CN202180087479.5A priority Critical patent/CN116670764A/zh
Priority to PCT/CN2021/077120 priority patent/WO2022174430A1/zh
Publication of WO2022174430A1 publication Critical patent/WO2022174430A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of data storage, and in particular, to a memory and an electronic device.
  • DRAM Dynamic Random Access Memory
  • Traditional semiconductor memory chips achieve capacity growth by increasing the storage capacity per unit area.
  • bottlenecks such as increased crosstalk between cells and increased cost per word.
  • the three-dimensional stacked semiconductor storage technology achieves storage density growth by increasing the storage stack instead of reducing the two-dimensional size of the device, bringing the development space of semiconductor memory into the third dimension, and becoming the key to sustainable growth of memory chip capacity in the future.
  • a memory and an electronic device provided by the present application can increase the storage capacity of the memory.
  • a memory in a first aspect, includes a stacked multi-layer storage array, each layer of the storage array in the multi-layer storage array includes: a plurality of storage cells arranged in a matrix, and the storage cells include Ferroelectric transistors; source lines connected to the first electrodes of the ferroelectric transistors in the memory cells in each row; bit lines connected to the second electrodes of the ferroelectric transistors in the memory cells in each row; The word line to which the gate electrode of the ferroelectric transistor in the memory cell is connected.
  • bit lines connected to the memory cells in the same position are not interconnected, and the specific implementation is as follows:
  • the first case at least two layers in the multi-layer storage array are interconnected at the same position of the source lines in the storage array.
  • the second case the bit lines in the same position in at least two memory arrays in the multi-layer memory array are interconnected.
  • source lines at the same position and bit lines at the same position are interconnected in at least two layers of the storage array in the multi-layer storage array.
  • word lines in at least two layers in the multi-layer memory array at the same position in the memory array are interconnected.
  • the multi-layer storage array at least two layers of source lines in the same position in the storage array are interconnected; in the multi-layer storage array, at least two layers in the multi-layer storage array are interconnected with word lines in the same position in the storage array.
  • bit lines in the same position in at least two layers of the multi-layer storage array are interconnected; word lines in the same position in the storage array in at least two layers in the multi-layer storage array are interconnected, and the word lines are interconnected with each other.
  • the bit lines connected to the memory cells in the same position are not interconnected.
  • At least two layers in the multi-layer storage array are interconnected with source lines at the same position in the storage array, and bit lines at the same position are interconnected; at least two layers in the multi-layer storage array are at the same position in the storage array.
  • the word lines are interconnected, and in the at least two layers of memory arrays where the word lines are interconnected, the bit lines connected to the memory cells in the same position are not interconnected.
  • the storage unit is a ferroelectric transistor, so that the memory has the advantages of high storage density, low power consumption, and high speed. And, due to the three-dimensional structure of the multi-layer storage array stacking, the storage capacity can be effectively increased. In addition, due to the source line interconnection in the same position in at least two layers of the multi-layer memory array, and/or the bit line interconnection in the same position in at least two layers of the memory array; or, the multi-layer memory array Word lines at the same location in the memory array are interconnected in at least two layers in the array.
  • the number of lines used to connect the multi-layer memory array and the control circuit can be reduced, thereby reducing the occupied area of the lines in the memory and increasing the occupied area of the memory array
  • the storage capacity of the memory can be further increased, and the manufacturing cost of the memory can also be reduced.
  • a storage unit is the smallest unit in the memory with data storage and read/write functions, and can be used to store a smallest information unit, that is, 1-bit data (eg, 0 or 1), that is, a binary bit.
  • 1-bit data eg, 0 or 1
  • the storage of multiple binary bit data can be realized.
  • one storage unit is used to store one binary bit.
  • the ferroelectric transistor may include: a semiconductor column, an oxide layer, a floating metal layer, a ferroelectric material layer and a gate electrode are sequentially arranged around the semiconductor column from the inside to the outside; one end of the semiconductor column is the ferroelectric The first electrode of the transistor, and the other end of the semiconductor column is the second electrode of the ferroelectric transistor.
  • the first electrode may be the source electrode and the second electrode may be the drain electrode, or the first electrode may be the drain electrode and the second electrode may be the source electrode.
  • the source electrode and the drain electrode of the ferroelectric transistor may be interchanged without specific distinction.
  • the ferroelectric transistor utilizes the change of the polarization direction or polarization strength of the ferroelectric material layer to modulate the carrier concentration of the channel in the semiconductor column, thereby changing the read current and realizing the storage of "0" state and "1" state.
  • the state to be written when the state to be written is "0", the first electrode and the second electrode of the ferroelectric transistor are connected to electricity, the gate electrode is connected to the forward bias voltage V W , and the ferroelectric material layer is in a positive state, so that the The carrier concentration of the channel in the semiconductor pillar becomes higher, and thus the read current is higher.
  • the state to be written is "1”
  • the first electrode and the second electrode of the ferroelectric transistor are connected to the forward bias voltage V W , the gate electrode is grounded, and the ferroelectric material layer is in a negative state, so that the channel in the semiconductor column is in a negative state.
  • the carrier concentration becomes lower and the read current is lower.
  • the first electrode of the ferroelectric transistor is grounded, the second electrode is connected to the bias electrode VR, and the gate electrode of the ferroelectric transistor that needs to read data is connected to the bias voltage V WLR , so that the ferroelectric transistor is turned on, and the The gate electrode of the ferroelectric transistor that does not need to read data is grounded, so that the ferroelectric transistor is turned off.
  • the position of the memory unit can be determined by the bit line and the word line connected with the memory cell. Therefore, in the present application, in the at least two-layer memory array where the word line is interconnected, , the bit lines connected to the memory cells in the same position are not interconnected, thereby ensuring that in all memory cells of the present application, at least one of the bit lines and word lines connected to any two memory cells is different.
  • the present application does not limit the areas of the oxide layer, the floating metal layer, the ferroelectric material layer and the gate electrode that are sequentially arranged around the semiconductor pillar.
  • the extending direction of the semiconductor pillars in the ferroelectric transistor is the same as the stacking direction of the multi-layer memory array.
  • each source line is parallel to each other
  • each bit line is parallel to each other
  • each word line is parallel to each other
  • the bit line and the source line are arranged in parallel.
  • the bit lines are arranged perpendicular to the word lines.
  • the 90° cross-array structure can reduce the memory cell area to 4F 2 , where F is the feature size.
  • the bit line and the source line may be located at both ends of the memory cell, for example, the bit line is located at the top end of the memory cell, and the source line is located at the bottom end of the memory cell.
  • the bottom end of the storage unit, and the source line is located at the top end of the storage unit, which is not limited here.
  • the word line is located between the bit line and the source line and is connected to the gate electrode of the memory cell.
  • a dielectric layer is arranged between the two adjacent layers of storage arrays, so that the storage arrays of adjacent layers are independent of each other.
  • a circuit layer may also be included in the memory.
  • the circuit layer may include: a word line control circuit connected to each of the word lines, a bit line control circuit connected to each of the bit lines, a sense amplifier circuit connected to each of the bit lines, and each of the source Line-connected source line control circuits; the stacked multi-layer memory array is located above the circuit layers. Therefore, compared with forming the circuit layer around the memory array layer, the occupied area of the memory can be reduced, thereby further increasing the capacity of the memory. Moreover, the circuit layer is located under the memory array, so that the control circuit can be located in the area covered by the memory array as much as possible.
  • the sense amplifier circuit in the present application is used to read the feedback current received by the correspondingly connected bit line, so as to read the data in the memory cell.
  • the sense amplifier circuit has an amplifier corresponding to each bit line, and each amplifier can judge the current level of the storage unit by comparing the feedback current of the storage unit with a reference value, and then determine the storage unit in the storage unit. The data.
  • each bit line can be controlled by the corresponding control circuit configured in the circuit layer, wherein the bit line
  • the line control circuit is used for providing the corresponding bit line with the required voltage
  • the source line control circuit is used for providing the corresponding source line with the required voltage
  • the word line control circuit is used for providing the required voltage for the word line.
  • the memory may also include a row address decoding circuit and a column address decoding circuit, which are used to select the corresponding storage unit through the word line and the bit line when writing or reading data.
  • the voltage applied to the corresponding bit line, source line or word line by the selection of the decoding circuit realizes read and write operations on one or several memory cells selected by the row address decoding circuit and the column address decoding circuit.
  • source lines in the same position in at least two layers of memory arrays in the multi-layer memory array are interconnected, and/or bit lines in the same position in at least two layers of memory arrays are interconnected; Word lines at the same location in at least two of the layer memory arrays are interconnected.
  • the number of lines used to connect the word line and the word line control circuit can be reduced, thereby reducing the occupied area of the lines in the memory, increasing the occupied area ratio of the storage array, and further increasing the storage of the memory. capacity.
  • two adjacent layers of storage arrays are used as a first storage array group or a second storage array group, and the three-dimensional storage includes at least one of the first storage array groups and/or at least one of the first storage array groups.
  • Two storage array groups, and one layer of storage arrays only belongs to one of the storage array groups.
  • the first electrodes of the ferroelectric transistors in the storage cells in one layer of the storage array and the electrodes of the ferroelectric transistors in the storage cells in the other storage array are opposite to each other, and the memory cells belonging to the same position in the two-layer storage arrays in the same first storage array group share the same source line; since the two-layer storage arrays belong to the same first storage array group in the same position of memory cells share the source line. In this way, the source line interconnection is realized by sharing the source line.
  • the number of traces connected to the source line can be reduced, and on the other hand, the number of masks used to make the source line can be reduced, and the storage of adjacent layers can be avoided.
  • the second electrodes of the ferroelectric transistors in the storage cells in one layer of the storage array and the ferroelectric transistors in the storage cells in the other storage array are opposite to each other, and the memory cells in the same position in the two-layer memory arrays in the same second memory array group share the same bit line. Because the memory cells in the same position in the two-layer memory arrays belonging to the same first memory array group share bit lines. In this way, the bit line interconnection is realized by sharing the bit line. On the one hand, the number of wirings connected to the bit line can be reduced. On the other hand, the number of masks used for making the bit line can be reduced, and the storage of adjacent layers can be avoided. The placement of the dielectric layer between the arrays, thereby reducing the manufacturing cost.
  • bit lines at the same position in the two-layer memory arrays belonging to the same first memory array group are interconnected.
  • source lines at the same position in the two-layer memory arrays belonging to the same second memory array group are interconnected.
  • the memory when the number of layers of the storage array in the memory is an even number, the memory includes a T-layer storage array, where T is an even number greater than or equal to 4, and the T-layer storage array includes T/2 of the storage array groups. , that is, all layers of storage arrays in the memory are grouped, so that the number of storage array groups in the memory increases.
  • all storage array groups are the first storage array group.
  • all storage array groups are second storage array groups.
  • a part of all the storage array groups is the first storage array group, and the other part is the second storage array group.
  • the memory when the number of layers of the storage array in the memory is an odd number, the memory includes a T-layer storage array, where T is an odd number greater than or equal to 3, and the T-layer storage array includes (T-1)/2 all storage arrays.
  • the storage array group and a layer of first storage arrays are included, wherein the first storage array does not belong to any of the storage array groups, even if there are more storage array groups in the memory.
  • the storage array groups are provided on both sides of the first storage array, or the storage array groups are all located on the same side of the first storage array.
  • the first storage array and other adjacent storage arrays can be combined.
  • Set to share the source line and/or the bit line there are the following five cases:
  • Case 1 The storage array groups are all located on the same side of the first storage array, and the storage array group adjacent to the first storage array is the first storage array group; the first storage array The array shares a bit line with the memory cells in the same position in the adjacent memory array.
  • the second case the storage array groups are all located on the same side of the first storage array, and the storage array group adjacent to the first storage array is the second storage array group; the first storage array The array shares the source line with the memory cells in the same position in the adjacent memory array.
  • the third situation the storage array groups are provided on both sides of the first storage array, and the storage array groups adjacent to the first storage array are the first storage array groups; A memory array shares bit lines with memory cells at the same position in one of the adjacent layers of the memory array.
  • the fourth situation the storage array groups are provided on both sides of the first storage array, and the storage array groups adjacent to the first storage array are the second storage array groups; A memory array shares source lines with memory cells in the same position in one of the adjacent layers of the memory array.
  • the storage array groups are provided on both sides of the first storage array, and the storage array groups adjacent to the first storage array are the first storage array group and the third storage array group respectively.
  • Two storage array groups; in the first storage array group of the first storage array, a layer of storage array adjacent to the first storage array, and a storage unit in the same position in the first storage array Shared bit lines; shared with the second storage array group of the first storage array, a layer of storage array adjacent to the first storage array, and the storage cells in the same position in the first storage array source line.
  • all The storage array groups are all first storage array groups.
  • all of the storage array groups are second storage array groups.
  • all the storage array groups include the first storage array group and the second storage array group; all the first storage array groups are located on the first side of the first storage array, and all the second storage array groups A storage array group is located on the second side of the first storage array.
  • any two adjacent first storage array groups belonging to different first storage array groups are The memory cells in the same position in the adjacent two-layer storage arrays share the bit line; the memory cells in the same position in the adjacent two-layer storage arrays belonging to different storage array groups in any two adjacent second storage array groups share the source Wire.
  • two adjacent storage array groups mean that there are no other storage arrays between the two storage array groups, and two adjacent storage arrays refer to the storage arrays that are directly adjacent to the same layer, such as the t-tier storage array. and t+1 layer storage array.
  • T is an even number greater than or equal to 4, and all the storage array groups are the first storage array group; any two adjacent first storage array groups belong to phases in different first storage array groups. Memory cells in the same position in two adjacent memory arrays share bit lines.
  • T is an even number greater than or equal to 4, and all the storage array groups are second storage array groups; any two adjacent second storage array groups belong to phases in different second storage array groups.
  • the memory cells in the same position in the adjacent two-layer memory array share the source line.
  • T is an odd number greater than or equal to 5, all the storage array groups are the first storage array group; any two adjacent first storage array groups located on the same side of the first storage array Among them, memory cells in the same position in two adjacent layers of memory arrays belonging to different first memory array groups share bit lines.
  • T is an odd number greater than or equal to 5
  • all the storage array groups are second storage array groups; any two adjacent second storage array groups located on the same side of the first storage array Among them, memory cells in the same position in adjacent two-layer memory arrays belonging to different second memory array groups share source lines.
  • T is an odd number greater than or equal to 5, all the storage array groups include the first storage array group and the second storage array group; the first storage array group is located in the first storage array group On the first side of the array, the second storage array group is located on the second side of the first storage array; any two adjacent first storage array groups located on the first side of the first storage array belong to different Memory cells in the same position in the adjacent two-layer storage arrays in the first storage array group share bit lines; any two adjacent second storage array groups located on the first side of the first storage array group , the memory cells in the same position in the adjacent two-layer memory arrays belonging to different second memory array groups share the source line.
  • the ferroelectric transistors in the memory cells in one layer of the memory array when the memory cells in the same position in the adjacent two-layer memory array share the source line, in the adjacent two-layer memory array, the ferroelectric transistors in the memory cells in one layer of the memory array
  • the first electrode is opposite to the first electrode of the ferroelectric transistor in the memory cell in the other layer of the memory array.
  • the second electrodes of the ferroelectric transistors in the memory cells in one layer of the memory array and the second electrode of the ferroelectric transistor in the other layer of the memory array are opposite.
  • N ⁇ (T ⁇ 1) lines when source lines at the same position in all layers of memory arrays are interconnected, N ⁇ (T ⁇ 1) lines can be reduced. When the bit lines at the same position in the memory array of all layers are interconnected, N ⁇ (T-1) lines can also be reduced. When the source lines at the same position in all layers of memory arrays are interconnected, and the bit lines at the same position in all layers of memory arrays are interconnected, 2N ⁇ (T-1) wires can be reduced, so that the number of wires can be reduced. as little as possible.
  • word lines at the same position in all layer storage arrays in the memory need to be independent of each other.
  • parallel writing and reading of the memory cells of all layers are realized by using the word line gating.
  • word lines at the same location in the memory array of all layers in this application are interconnected. This situation requires that the bit lines at the same location in the memory array of all levels in the memory are independent of each other. Thus, parallel writing and reading of memory cells of all layers are realized by using bit line gating.
  • bit lines at the same position in the memory arrays of all layers are not completely interconnected in the memory, there may be at least two interconnection of the word lines at the same position in the storage arrays of two layers, as long as the word lines are ensured In the interconnected at least two layers of memory arrays, the bit lines connected to the memory cells in the same position may not be interconnected.
  • bit line and the word line are combined together to illustrate the memory of the present application through specific embodiments.
  • the memory includes a T-layer storage array, where T is an even number greater than or equal to 4, and the T-layer storage array includes T/2 of the storage array groups; all the storage array groups All are the first storage array group or both are the second storage array group; the word lines in the same position in the T/2 layer storage array are interconnected through the first wiring, and the remaining words in the same position in the T/2 layer storage array are interconnected. Lines are interconnected through second lines; and for two-layer memory arrays belonging to the same memory array group, among word lines in the same position, one word line is connected to the first line, and the other word line is connected to the first line. Second trace connection.
  • the memory includes a T-layer storage array, where T is an odd number greater than or equal to 3, and the T-layer storage array includes (T-1)/2 the storage array groups and one layer A first storage array, wherein the first storage array does not belong to any of the storage array groups; the storage array groups are all located on the same side of the first storage array, or both sides of the first storage array are The storage array group is provided; the word lines in the same position in the (T+1)/2-layer storage array are interconnected through the first wiring, and the words in the same position in the remaining (T-1)/2-layer storage array Lines are interconnected through second lines; and for two-layer memory arrays belonging to the same memory array group, among word lines in the same position, one word line is connected to the first line, and the other word line is connected to the first line. Second trace connection.
  • an electronic device provided by an embodiment of the present application includes a processor and the memory described in the foregoing embodiments coupled to the processor.
  • the processor can call the software program stored in the memory to execute the corresponding method and realize the corresponding function of the electronic device.
  • FIG. 1 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a one-layer storage array of a memory provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a ferroelectric transistor provided by an embodiment of the present application.
  • Fig. 8 is a schematic cross-sectional structure diagram of the ferroelectric transistor shown in Fig. 7 along the AA' direction;
  • FIG. 9 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • FIG. 10 is a schematic partial structure of a memory provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a circuit layer provided by an embodiment of the present application.
  • FIG. 12 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 13 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 14 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 15 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 16 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 17 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 18 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 19 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 20 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 21 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 22 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 23 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 24 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 25 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 26 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 27 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 28 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • FIG. 29 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • FIG. 30 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 31 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 32 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • FIG. 33 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 34 is a schematic structural diagram of another memory provided by an embodiment of the present application.
  • FIG. 35 is a schematic partial structure of another memory provided by an embodiment of the present application.
  • FIG. 36 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • Ferroelectric memory is based on the ferroelectric effect of ferroelectric materials to store data. Due to its ultra-high storage density, low power consumption and high speed, ferroelectric memory is expected to become a major competitor to replace DRAM.
  • the present application provides a three-dimensional memory based on a ferroelectric memory, which can effectively increase the storage capacity and reduce the manufacturing cost on the basis of ensuring the advantages of low power consumption and high speed of the memory.
  • the three-dimensional memory can be applied to various data information storage fields, for example, can be applied to the memory in electronic equipment such as processors, computers or servers, the processor can be a central processing unit, an artificial intelligence processor, a digital signal processing of course, the three-dimensional memory in this embodiment of the present application can also be applied to other electronic devices, which is not limited here.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • FIG. 1 is a schematic structural diagram of a memory according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a layer of storage array in the memory according to an embodiment of the present application.
  • the memory cells 11 tnm include ferroelectric transistors; the first electrodes of the ferroelectric transistors of the memory cells 11 tnm in each row are connected to one of the source lines SLtn, and the second electrodes of the ferroelectric transistors of the memory cells 11 tnm in each row are connected to one of the source lines SLtn.
  • the electrodes are connected to one of the bit lines BLtn, and the gate electrodes of the ferroelectric transistors of 11 tnm in each column of the memory cells are connected to one of the word lines WLtm.
  • bit lines connected to the memory cells in the same position are not interconnected, and the specific implementation is as follows:
  • the source line SLn1 in the memory array 10n is interconnected with the source line SLm1 in the memory array 10m
  • the source line SLn2 in the memory array 10n is interconnected with the source line SLm2 in the memory array 10m
  • the source line SLn3 in the memory array 10n is interconnected with the source line SLm3 in the memory array 10m
  • the source line SLn4 in the memory array 10n is interconnected with the source line SLm4 in the memory array 10m.
  • FIG. 3 only shows the two-layer memory arrays 10n and 10m interconnected by source lines.
  • the present application is not limited to only two-layer memory arrays, and the memory array layers interconnected by source lines are not limited to two layers.
  • the second case the bit lines in the same position in at least two memory arrays in the multi-layer memory array are interconnected.
  • the bit line BLn1 in the memory array 10n is interconnected with the bit line BLm1 in the memory array 10m
  • the bit line BLn2 in the memory array 10n is interconnected with the bit line BLm2 in the memory array 10m
  • the bit line BLn3 in the memory array 10n is interconnected with the bit line BLm3 in the memory array 10m
  • the bit line BLn4 in the memory array 10n is interconnected with the bit line BLm4 in the memory array 10m.
  • FIG. 4 only shows the two-layer memory arrays 10n and 10m interconnected by source lines.
  • the present application is not limited to only two-layer memory arrays, and the memory array layers interconnected by bit lines are not limited to two layers.
  • the third situation source lines at the same position and bit lines at the same position are interconnected in at least two layers of the storage array in the multi-layer storage array.
  • the source line SLn1 in the storage array 10n is interconnected with the source line SLm1 in the storage array 10m
  • the source line SLn2 in the storage array 10n is interconnected with the source line SLm2 in the storage array 10m
  • the source line SLn3 in the memory array 10n is interconnected with the source line SLm3 in the memory array 10m
  • the source line SLn4 in the memory array 10n is interconnected with the source line SLm4 in the memory array 10m.
  • the bit line BLn1 in the memory array 10n is interconnected with the bit line BLm1 in the memory array 10m
  • the bit line BLn2 in the memory array 10n is interconnected with the bit line BLm2 in the memory array 10m
  • the bit line BLn3 in the memory array 10n is interconnected with the memory array 10n.
  • the bit line BLm3 in the array 10m is interconnected
  • the bit line BLn4 in the memory array 10n is interconnected with the bit line BLm4 in the memory array 10m.
  • FIG. 5 only shows two layers of memory arrays 10n and 10m interconnected by source lines. The present application is not limited to only two layers of memory arrays, and the memory array layers interconnected by source lines and bit lines are not limited to two layers.
  • the fourth situation word lines in at least two layers in the multi-layer memory array at the same position in the memory array are interconnected.
  • the word line WLn1 in the memory array 10n is interconnected with the word line WLm1 in the memory array 10m
  • the word line WLn2 in the memory array 10n is interconnected with the word line WLm2 in the memory array 10m
  • the word line WLn3 in the memory array 10n is interconnected with the word line WLm3 in the memory array 10m
  • the word line WLn4 in the memory array 10n is interconnected with the word line WLm4 in the memory array 10m
  • the word line WLn5 in the memory array 10n is interconnected with the memory array 10n.
  • FIG. 6 only shows the two-layer memory arrays 10n and 10m interconnected by source lines.
  • the present application is not limited to only two-layer memory arrays, and the memory array layers interconnected by word lines are not limited to two layers.
  • the multi-layer storage array at least two layers of source lines in the same position in the storage array are interconnected; in the multi-layer storage array, at least two layers in the multi-layer storage array are interconnected with word lines in the same position in the storage array.
  • bit lines in the same position in at least two layers of the multi-layer storage array are interconnected; word lines in the same position in the storage array in at least two layers in the multi-layer storage array are interconnected, and the word lines are interconnected with each other.
  • the bit lines connected to the memory cells in the same position are not interconnected.
  • At least two layers in the multi-layer storage array are interconnected with source lines at the same position in the storage array, and bit lines at the same position are interconnected; at least two layers in the multi-layer storage array are at the same position in the storage array.
  • the word lines are interconnected, and in the at least two layers of memory arrays where the word lines are interconnected, the bit lines connected to the memory cells in the same position are not interconnected.
  • the storage unit is a ferroelectric transistor, so that the memory has the advantages of high storage density, low power consumption and high speed. And, due to the three-dimensional structure of the multi-layer storage array stacking, the storage capacity can be effectively increased. In addition, due to the source line interconnection in the same position in at least two layers of the multi-layer memory array, and/or the bit line interconnection in the same position in at least two layers of the memory array; or, the multi-layer memory array Word lines at the same location in the memory array are interconnected in at least two layers in the array.
  • the number of lines used to connect the multi-layer memory array and the control circuit can be reduced, thereby reducing the occupied area of the lines in the memory and increasing the occupied area of the memory array
  • the storage capacity of the memory can be further increased, and the manufacturing cost of the memory can also be reduced.
  • the number of layers of the memory array in this application is T, and each layer of the memory array has N rows ⁇ M columns of memory cells, N source lines, N bit lines, and M word lines.
  • the capacity is N ⁇ M ⁇ T.
  • BLtn and SLtn are the n-th bit line BL and the n-th source line SL of the t-th layer storage array respectively
  • WLtm is the m-th word line WL of the t-th layer storage array
  • the memory cell 11 tnm is the t-th layer storage array.
  • the storage unit 11 is located in the nth row and the mth column.
  • the memory cells 11 tnm located at the same position in different layers of storage arrays refer to: the layer positions t are different, the row position n and the column position m are the same memory cells;
  • the source line SLtn refers to the source line with the same layer position t and the same row position n;
  • the bit line BLtn located at the same position in the storage array of different layers refers to the bit line with different layer position t and the same row position n;
  • the word lines WLtm located at the same position in the memory array of different layers refer to word lines with different layer positions t and the same column position m.
  • a storage unit is the smallest unit in the memory with data storage and read/write functions, and can be used to store a smallest information unit, that is, 1-bit data (eg, 0 or 1), that is, a binary bit.
  • 1-bit data eg, 0 or 1
  • the storage of multiple binary bit data can be realized.
  • one storage unit is used to store one binary bit.
  • FIG. 7 is a schematic structural diagram of a ferroelectric transistor provided by an embodiment of the application
  • FIG. 8 is a cross-sectional structural schematic diagram of the ferroelectric transistor shown in FIG. 7 along the AA' direction.
  • the ferroelectric transistor may include: a semiconductor column 11e, an oxide layer 11d, a floating metal layer 11c, a ferroelectric material layer 11b, and a gate electrode 11a arranged in sequence around the semiconductor column 11e from the inside to the outside; One end is the first electrode of the ferroelectric transistor, and the other end of the semiconductor pillar 11e is the second electrode of the ferroelectric transistor.
  • the first electrode may be the source electrode and the second electrode may be the drain electrode, or the first electrode may be the drain electrode and the second electrode may be the source electrode.
  • the source electrode and the drain electrode of the ferroelectric transistor may be interchanged without specific distinction.
  • the ferroelectric transistor utilizes the change of the polarization direction or polarization strength of the ferroelectric material layer 11b to modulate the carrier concentration of the channel in the semiconductor column 11e, thereby changing the read current, and realizing the “0” state and the “1” state. storage.
  • the state to be written when the state to be written is "0", the first electrode and the second electrode of the ferroelectric transistor are connected to electricity, the gate electrode is connected to the forward bias voltage V W , and the ferroelectric material layer is in a positive state, so that the The carrier concentration of the channel in the semiconductor pillar becomes higher, and thus the read current is higher.
  • the state to be written is "1”
  • the first electrode and the second electrode of the ferroelectric transistor are connected to the forward bias voltage V W , the gate electrode is grounded, and the ferroelectric material layer is in a negative state, so that the channel in the semiconductor column is in a negative state.
  • the carrier concentration becomes lower and the read current is lower.
  • the first electrode of the ferroelectric transistor is grounded, the second electrode is connected to the bias electrode VR, and the gate electrode of the ferroelectric transistor that needs to read data is connected to the bias voltage V WLR , so that the ferroelectric transistor is turned on, and the The gate electrode of the ferroelectric transistor that does not need to read data is grounded, so that the ferroelectric transistor is turned off.
  • the position of the memory unit can be determined by the bit line and the word line connected with the memory cell. Therefore, in the present application, in the at least two-layer memory array where the word line is interconnected, , the bit lines connected to the memory cells in the same position are not interconnected, thereby ensuring that in all memory cells of the present application, at least one of the bit lines and word lines connected to any two memory cells is different.
  • the present application does not limit the areas of the oxide layer, the floating metal layer, the ferroelectric material layer and the gate electrode that are sequentially arranged around the semiconductor pillar.
  • the extending direction of the semiconductor pillars 11e in the ferroelectric transistor is the same as the stacking direction z of the multi-layer memory array.
  • the source lines SLtn are parallel to each other
  • the bit lines BLtn are parallel to each other
  • the word lines WLtm are parallel to each other
  • the bit lines BLtn and the source lines SLtn are arranged in parallel.
  • the bit line BLtn is arranged perpendicular to the word line WLtm.
  • the 90° cross-array structure can reduce the memory cell area to 4F 2 , where F is the feature size.
  • the xyz coordinate system is shown in the memories shown in FIGS. 1 to 6 .
  • a plurality of source lines SLtn are arranged in parallel along the y-axis
  • a plurality of bit lines BLtn are arranged in parallel along the y-axis
  • a plurality of word lines WLtm are arranged in parallel along the x-axis
  • the multi-layer memory array 10t is arranged in parallel along the y-axis. Stacked in order along the z-axis direction.
  • the bit line BLtn and the source line SLtn may be located at both ends of the memory cell 11 tnm , for example, the bit line BLtn is located at the top of the memory cell 11 tnm .
  • the source line SLtn is located at the bottom end of the memory cell 11 tnm , of course, the bit line BLtn can also be located at the bottom end of the memory cell 11 tnm , and the source line SLtn is located at the top end of the memory cell 11 tnm , which is not limited here.
  • the word line WLtm is located between the bit line BLtn and the source line SLtn and is connected to the gate electrode of the memory cell 11 tnm .
  • a dielectric layer 30 is provided between the two adjacent layers of memory arrays 10t, so that the adjacent layers of memory arrays 10t are independent of each other.
  • the memory also includes a circuit layer 20 .
  • the circuit layer 20 may include: a word line control circuit 201 connected to each of the word lines WLtm, a bit line control circuit 202 connected to each of the bit lines BLtn, and a word line control circuit 202 connected to each of the bit lines BLtn.
  • the sense amplifier circuit 203 connected to the bit line BLtn, the source line control circuit 204 connected to each of the source lines SLtn; the stacked multi-layer memory array 10t is located above the circuit layer 20 . Therefore, compared with forming the circuit layer around the memory array layer, the occupied area of the memory can be reduced, thereby further increasing the capacity of the memory.
  • the circuit layer 20 is located below the memory array 10t so that the control circuit can be located in the area covered by the memory array as much as possible.
  • the sense amplifier circuit in the present application is used to read the feedback current received by the correspondingly connected bit line, so as to read the data in the memory cell.
  • the sense amplifier circuit has an amplifier corresponding to each bit line, and each amplifier can judge the current level of the storage unit by comparing the feedback current of the storage unit with a reference value, and then determine the storage unit in the storage unit. The data.
  • each bit line can be controlled by the corresponding control circuit configured in the circuit layer, wherein the bit line
  • the line control circuit is used for providing the corresponding bit line with the required voltage
  • the source line control circuit is used for providing the corresponding source line with the required voltage
  • the word line control circuit is used for providing the required voltage for the word line.
  • the memory may also include a row address decoding circuit and a column address decoding circuit, which are used to select the corresponding storage unit through the word line and the bit line when writing or reading data.
  • the voltage applied to the corresponding bit line, source line or word line by the selection of the decoding circuit realizes read and write operations on one or several memory cells selected by the row address decoding circuit and the column address decoding circuit.
  • the T layer The T ⁇ N bit lines of the memory array can be connected to the same bit line control circuit and the same sense amplifier circuit through T ⁇ N lines and through holes located around the memory array; the lines connected to the bit lines can be separate bit lines. both ends.
  • the T ⁇ N source lines of the T-layer memory array can be connected to the same source line control circuit through the T ⁇ N lines and through holes located around the memory array; the lines connected to each source line can be respectively connected to both ends of the source line. .
  • T ⁇ M word lines of the T-layer memory array can be connected to the same word line control circuit through T ⁇ M lines and through holes located around the memory array; the lines connected to each word line can be respectively connected to both ends of the word line .
  • a total of T ⁇ (2N+M) wirings need to be set in the memory, and a large number of wirings will increase the peripheral area of the storage array.
  • source lines in the same position in at least two layers of memory arrays in the multi-layer memory array are interconnected, and/or bit lines in the same position in at least two layers of memory arrays are interconnected; Word lines at the same location in at least two of the layer memory arrays are interconnected.
  • the number of lines used to connect the word line and the word line control circuit can be reduced, thereby reducing the occupied area of the lines in the memory, increasing the occupied area ratio of the storage array, and further increasing the storage of the memory. capacity.
  • FIGS. 12 to 14 in the memory provided by the embodiment of the present application, two adjacent layers of memory arrays 10t and 10t+1 are used as a first memory array group Cn or a second memory array group Dn; the memory It includes at least one first storage array group Cn and/or at least one second storage array group Dn; and one layer of storage array 10t only belongs to one of said storage array groups Cn or Dn.
  • FIG. 12 to FIG. 14 take the memory including two storage array groups as an example for illustration.
  • FIG. 12 includes two first storage array groups C1 and C2
  • FIG. 13 includes two second storage array groups.
  • Groups D1 and D2, in FIG. 14, include a first storage array group C1 and a second storage array group D1.
  • the first electrodes of the ferroelectric transistors in the memory cells in one layer of the memory array 10t are connected to the other layer of the memory array
  • the first electrodes of the ferroelectric transistors in the memory cells in 10t+1 are opposite, and the memory cells in the same position in the two-layer memory arrays 10t and 10t+1 in the same first memory array group Cn share the source line SLtn.
  • the first storage array group C1 includes a storage array 101 and a storage array 102.
  • the first electrodes of the ferroelectric transistors in the storage cells 11 and 1 nm in the storage array 101 are all at the bottom of the ferroelectric transistors, and the The second electrodes are all at the top of the ferroelectric transistors, while the first electrodes of the ferroelectric transistors in the memory cells 11 to 1 nm in the memory array 102 are all at the top of the ferroelectric transistors, and the second electrodes of the ferroelectric transistors are all at the bottom of the ferroelectric transistors end, that is, the first electrode of the ferroelectric transistor in the memory cell 11.1nm is opposite to the first electrode of the ferroelectric transistor in the memory cell 11.2nm , so that the memory cells in the same position in the memory arrays 101 and 102 in the first memory array group C1 can be Shared source line SLtn.
  • the memory cells in the same position in the two-layer memory arrays belonging to the same first memory array group share the source line.
  • the source line interconnection is realized by sharing the source line.
  • the number of traces connected to the source line can be reduced, and on the other hand, the number of masks used to make the source line can be reduced, and the storage of adjacent layers can be avoided.
  • the second electrodes of the ferroelectric transistors in the memory cells in one layer of the memory array 10t are connected to the other layer of the memory array
  • the second electrodes of the ferroelectric transistors in the memory cells in 10t+1 are opposite, and the memory cells in the same position in the two-layer memory arrays 10t and 10t+1 in the same second memory array group Dn share the bit line BLtn.
  • the second memory array group D1 includes a memory array 101 and a memory array 102 .
  • the first electrodes of the ferroelectric transistors in the memory cells 11 and 1 nm in the memory array 101 are all at the top of the ferroelectric transistors, and the first electrodes of the ferroelectric transistors are at the top of the ferroelectric transistors. Both electrodes are located at the bottom of the ferroelectric transistor, while the first electrodes of the ferroelectric transistors in the memory cells 11 to 1 nm in the memory array 102 are located at the bottom of the ferroelectric transistors, and the second electrodes of the ferroelectric transistors are located at the bottom of the ferroelectric transistors.
  • the top that is, the second electrode of the ferroelectric transistor in the memory cell 11 1 nm is opposite to the second electrode of the ferroelectric transistor in the memory cell 11 2 nm , so that the memory cells in the same position in the memory arrays 101 and 102 in the second memory array group D1 can be Shared bit line BLtn.
  • bit lines Because the memory cells in the same position in the two-layer memory arrays belonging to the same first memory array group share bit lines. In this way, the bit line interconnection is realized by sharing the bit line. On the one hand, the number of wirings connected to the bit line can be reduced. On the other hand, the number of masks used for making the bit line can be reduced, and the storage of adjacent layers can be avoided. The placement of the dielectric layer between the arrays, thereby reducing the manufacturing cost.
  • two adjacent layers of storage arrays may be arranged in mirror symmetry with respect to the shared source line, and in the same second storage array group, two adjacent layers of storage arrays The arrays may be arranged in mirror symmetry with respect to the common bit lines.
  • bit lines BLtn and BLt+1n at the same position in 10t and 10t+1 are interconnected.
  • the bit lines BL11 in the memory array 101 and the bit line BL21 in the memory array 102 are interconnected, and in the first memory array group C2, the bit lines BL31 and BL31 in the memory array 103 are interconnected.
  • the bit lines BL41 in the memory array 104 are interconnected.
  • two layers of storage arrays 10t and 10t belong to the same second storage array group Dn
  • the source lines SLtn and SLt+1n at the same position in +1 are interconnected.
  • the source lines SL11 in the storage array 101 and the source lines SL21 in the storage array 102 are interconnected
  • the source lines SL31 and SL31 in the storage array 103 are interconnected.
  • Source lines SL41 in the memory array 104 are interconnected.
  • the memory when the number of layers of the storage array in the memory is an even number, as shown in FIGS. 12 , 13 , and 15 to 17 , the memory includes a T-layer storage array 10t, where T is an even number greater than or equal to 4,
  • the T-layer storage array 10t includes T/2 storage array groups Cn and/or Dn, that is, all layers of storage arrays in the memory are grouped, so that the memory has more storage array groups.
  • all storage array groups are the first storage array group Cn.
  • all storage array groups are the second storage array group Dn.
  • a part of all the storage array groups is the first storage array group Cn, and the other part is the second storage array group Dn.
  • the memory includes a T-layer storage array, where T is an odd number greater than or equal to 3, and the T-layer
  • the storage array includes (T-1)/2 of the storage array groups and a layer of first storage arrays, wherein the first storage array does not belong to any of the storage array groups, even if there are memory, the number of storage array groups more.
  • FIGS. 14 and 18 the storage array 103 is the first storage array, and in FIG. 19 , the storage array 105 is the first storage array.
  • the storage array groups are provided on both sides of the first storage array.
  • the first storage array group C1 and the second storage array group D1 are located in the first storage array group C1 and the second storage array group D1 respectively. Both sides of array 103 .
  • the storage array groups are all located on the same side of the first storage array.
  • the first storage array groups C1 and C2 are both located on the same side of the first storage array 105 .
  • the first storage array and other adjacent storage arrays can be combined.
  • Set to share the source line and/or the bit line there are the following five cases:
  • Case 1 The storage array groups are all located on the same side of the first storage array, and the storage array group adjacent to the first storage array is the first storage array group; the first storage array The array shares a bit line with the memory cells in the same position in the adjacent memory array.
  • the first memory array groups C1 and C2 are both located above the first memory array 105 , and the memory cells in the same position in the first memory array 105 and the memory array 104 share the bit line BLtn.
  • the second case the storage array groups are all located on the same side of the first storage array, and the storage array group adjacent to the first storage array is the second storage array group; the first storage array The array shares the source line with the memory cells in the same position in the adjacent memory array.
  • the third situation the storage array groups are provided on both sides of the first storage array, and the storage array groups adjacent to the first storage array are the first storage array groups; A memory array shares bit lines with memory cells at the same position in one of the adjacent layers of the memory array.
  • the first memory array groups C1 and C2 are located on two sides of the first memory array 103 respectively, and the memory cells in the same position in the first memory array 103 and the memory array 104 share the bit line BLtn.
  • the fourth situation the storage array groups are provided on both sides of the first storage array, and the storage array groups adjacent to the first storage array are the second storage array groups; A memory array shares source lines with memory cells in the same position in one of the adjacent layers of the memory array.
  • the storage array groups are provided on both sides of the first storage array, and the storage array groups adjacent to the first storage array are the first storage array group and the third storage array group respectively.
  • Two storage array groups; in the first storage array group of the first storage array, a layer of storage array adjacent to the first storage array, and a storage unit in the same position in the first storage array Shared bit lines; shared with the second storage array group of the first storage array, a layer of storage array adjacent to the first storage array, and the storage cells in the same position in the first storage array source line. Exemplarily, as shown in FIG.
  • the first storage array groups C1 and C2 are located on two sides of the first storage array 103 respectively, and the storage cells in the same position in the first storage array 103 and the storage array 102 share the bit line BLtn, Memory cells in the same position in a memory array 103 and memory array 104 share a source line SLtn.
  • all the storage array groups are the first storage array group Cn.
  • all of the storage array groups are second storage array groups.
  • all the storage array groups include the first storage array group Cn and the second storage array group Dn; all the first storage array groups Cn are located in the On the first side of the first storage array, all the second storage array groups Dn are located on the second side of the first storage array.
  • any two adjacent first storage array groups belonging to different first storage array groups are The memory cells in the same position in the adjacent two-layer storage arrays share the bit line; the memory cells in the same position in the adjacent two-layer storage arrays belonging to different storage array groups in any two adjacent second storage array groups share the source Wire.
  • two adjacent storage array groups mean that there are no other storage arrays between the two storage array groups, and two adjacent storage arrays refer to the storage arrays that are directly adjacent to the same layer, such as the t-tier storage array. and t+1 layer storage array.
  • T is an even number greater than or equal to 4, and all the storage array groups are the first storage array group; any two adjacent first storage array groups belong to phases in different first storage array groups.
  • Memory cells in the same position in two adjacent memory arrays share bit lines. Exemplarily, as shown in FIG. 23 , the memory cells in the same position in the memory array 102 of the first memory array group C1 and the memory array 103 of the first memory array group C2 share the bit line BLtn.
  • T is an even number greater than or equal to 4, and all the storage array groups are second storage array groups; any two adjacent second storage array groups belong to phases in different second storage array groups.
  • the memory cells in the same position in the adjacent two-layer memory array share the source line. Exemplarily, as shown in FIG. 24 , the memory cells in the same position in the memory array 102 of the second memory array group D1 and the memory array 103 of the second memory array group D2 share the source line SLtn.
  • the first storage array group C1 and the second storage array group C2 are both above the first storage array 105 , and the storage array 102 and the second storage array group C2 in the first storage array group C1 Memory cells in the same position in the memory array 103 in the memory array 103 share the bit line BLtn.
  • T is an odd number greater than or equal to 5
  • all the storage array groups are second storage array groups; any two adjacent second storage array groups located on the same side of the first storage array Among them, memory cells in the same position in adjacent two-layer memory arrays belonging to different second memory array groups share source lines.
  • T is an odd number greater than or equal to 5, all the storage array groups include the first storage array group and the second storage array group; the first storage array group is located in the first storage array group On the first side of the array, the second storage array group is located on the second side of the first storage array.
  • a first storage array group C1 is arranged above the first storage array 103
  • a second storage array group D1 is arranged below the first storage array 103 .
  • the shared bit lines between adjacent first memory array groups Cn can refer to FIG. 23 .
  • the source lines shared between adjacent second memory array groups Dn may refer to FIG. 24 .
  • the ferroelectric transistors in the memory cells in one layer of the memory array when the memory cells in the same position in the adjacent two-layer memory array share the source line, in the adjacent two-layer memory array, the ferroelectric transistors in the memory cells in one layer of the memory array
  • the first electrode is opposite to the first electrode of the ferroelectric transistor in the memory cell in the other layer of the memory array.
  • the second electrodes of the ferroelectric transistors in the memory cells in one layer of the memory array and the second electrode of the ferroelectric transistor in the other layer of the memory array are opposite.
  • N ⁇ (T ⁇ 1) lines when source lines at the same position in all layers of memory arrays are interconnected, N ⁇ (T ⁇ 1) lines can be reduced. When the bit lines at the same position in the memory array of all layers are interconnected, N ⁇ (T-1) lines can also be reduced. When the source lines at the same position in all layers of memory arrays are interconnected, and the bit lines at the same position in all layers of memory arrays are interconnected, 2N ⁇ (T-1) wires can be reduced, so that the number of wires can be reduced. as little as possible. For example, as shown in FIGS. 23 to 26 , the source lines SLtn at the same position in the memory arrays 10t of all layers are interconnected, and the bit lines BLtn of the memory arrays 10t of all layers at the same position are interconnected.
  • the word lines WLtm at the same position in the memory arrays of all layers in the memory need to be independent of each other.
  • parallel writing and reading of memory cells of all layers are realized by gating the word line WLtm. For example, as shown in FIG.
  • the word lines WLtm at the same position in the memory array 10t of all layers are independent of each other, the word line WL11 is connected to the word line control circuit 201 via the wiring W1, and the word line WL21 is controlled to the word line via the wiring W2
  • the circuit 201 is connected, the word line WL31 is connected to the word line control circuit 201 through the wire W3, and the word line WL41 is connected to the word line control circuit 201 through the wire W4.
  • each bit line BLtn is connected to the bit line control circuit 202 and the sense amplifier circuit 203 through its corresponding line B0; the interconnected bit line BLtn can pass through the same line.
  • the line B0 is connected to the bit line control circuit 202 and the sense amplifier circuit 203, that is, the interconnected bit line BLtn can be interconnected through its corresponding line B0.
  • Each source line SLtn is connected to the source line control circuit 204 through its corresponding wiring S0.
  • the interconnected source lines SLtn can be connected to the source line control circuit 204 through the same wire S0, that is, the interconnected source lines SLtn can be interconnected through the corresponding wire B0.
  • word lines WLtm at the same position in the memory array 10t of all layers in this application are interconnected.
  • This situation requires that the bit lines BLtn at the same position in all layers of the memory array in the memory are independent of each other.
  • parallel writing and reading of memory cells of all layers are realized by gating the bit line BLtn.
  • bit lines at the same position in the memory arrays of all layers are not completely interconnected in the memory, there may be at least two interconnection of the word lines at the same position in the storage arrays of two layers, as long as the word lines are ensured In the interconnected at least two layers of memory arrays, the bit lines connected to the memory cells in the same position may not be interconnected.
  • bit line and the word line are combined together to illustrate the memory of the present application through specific embodiments.
  • bit lines at the same position in the storage array of all layers are interconnected, and the word lines at the same position are independent of each other.
  • FIG. 29 in the memory, memory cells in the same position of the memory arrays 10t of adjacent layers share the source line SLtn or the bit line BLtn, that is, the memory arrays of the adjacent layer have the common source line SLtn or the bit line BLtn.
  • the memory arrays of adjacent layers are mirror-symmetrical along a common bit line or source line.
  • FIG. 23 is a schematic diagram of the connection between the source line and the bit line and the corresponding control circuit in the memory.
  • FIG. 27 is a schematic diagram of the connection between word lines and corresponding control circuits in the memory. Referring to FIG.
  • the bit lines BLtn at the same position in the memory arrays 10 t of each layer are connected to each other through the wiring B0 outside the array and the via holes, and are connected to the same bit line control circuit 202 and sense amplifier circuit 203 .
  • the source lines SLtn at the same position of each layer of the memory array 10t are connected to each other through the wiring S0 outside the array and the through hole, and are connected to the same source line control circuit 204 .
  • the word lines WLtm of the memory arrays 10 t of each layer are independent of each other, and are connected to the word line control circuit 201 with a gating function through a one-to-one corresponding wiring line Wm.
  • each layer of memory arrays in the memory shares a source line or a bit line, and the word line gating is used to realize parallel writing and reading of a single-layer memory cell.
  • the read bandwidth and write bandwidth of this embodiment are determined by the single-layer storage array, and the read and write bandwidth is not expanded through multi-layer stacking. Since the bit lines of each layer of memory arrays are connected together, stacking the multi-layer memory arrays may increase the load on the bit lines and increase the read delay of a single-bit memory cell.
  • each layer of storage array includes N bit lines, N bit lines, and M word lines
  • T ⁇ N bit lines require N wirings to be connected to the bit line control
  • T ⁇ N source lines need N lines to be connected to the source line control circuit
  • T ⁇ M word lines need T ⁇ M lines to be connected to the word line control circuit.
  • the wiring connected to the bit line and the wiring connected to the source line can be drawn out from both ends of the bit line or the source line, respectively, and N wirings are provided at each end.
  • the wirings connected to the word lines can be drawn out from both ends of the word lines, and T ⁇ M/2 wirings are arranged at each of the two ends.
  • the number of lines connecting the memory and the circuit layer is the smallest, and the layout area is the smallest.
  • the adjacent memory arrays share source lines or bit lines, the number of masks is minimized, which can reduce the manufacturing cost. Therefore, this embodiment may be suitable for storage application scenarios that require low speed and low cost.
  • word lines at the same position in the storage array of all layers are interconnected, and bit lines at the same position are independent of each other.
  • FIG. 30 is a schematic diagram of the connection between the source line and the bit line and the corresponding control circuit in the memory.
  • Figure 31 is a schematic diagram of the connection between word lines and corresponding control circuits in the memory. Referring to FIG. 31 , the bit lines BLtn in the same position of each layer of memory array 10t are independent of each other, and are connected to the sense amplifier circuit 203 and the bit line control circuit 202 with gating function through the one-to-one corresponding wiring B0.
  • the source lines SLtn at the same position of 10t are independent of each other, and are connected to the source line control circuit 204 through the one-to-one corresponding wiring S0.
  • the word lines WLtm of the memory arrays 10 t of each layer are connected to each other through the wires W1 outside the array and the via holes, and are connected to the same word line control circuit 201 .
  • the bit lines and source lines in the same position of each layer of the storage array in the memory are independent of each other, and the word line gating is used to realize parallel writing and reading of the memory cells of all layers.
  • this embodiment can effectively expand the read bandwidth and write bandwidth through three-dimensional stacking, and the read and write bandwidth is proportional to the number of stacked layers. Assuming that the bandwidth of a single-layer storage unit is N, the read and write bandwidth that can be achieved by stacking T layers is T ⁇ N. Since the bit lines of the memory arrays of each layer are independent of each other, the stacking of the multi-layer memory arrays will not deteriorate the load of the bit lines, and the read delay of the single-bit memory cell is smaller than that of the first example. Therefore, the memory can achieve higher bandwidth rates.
  • each layer of storage array includes N bit lines, N bit lines, and M word lines.
  • T ⁇ N source lines need T ⁇ N lines to be connected to the source line control circuit
  • T ⁇ M word lines need M lines to be connected to the word line control circuit.
  • the wiring connected to the bit line and the wiring connected to the source line can be drawn out from both ends of the bit line or the source line, respectively, and T ⁇ N wirings are provided at each end.
  • the wirings connected to the word lines can be drawn out from both ends of the word lines, and M/2 wirings are arranged at each of the two ends.
  • Example 1 Compared with Example 1, the number of traces is large, the number of traces in the bit line direction and the word line direction is unevenly distributed, and the layout area is larger. Since adjacent layers of memory arrays are separated by dielectric layers, the number of masks required increases and the manufacturing cost is higher. Therefore, this embodiment may be applicable to a storage application scenario with high performance requirements.
  • two adjacent layers of storage arrays are regarded as a group of storage array groups, the storage array groups are isolated from each other, and the storage array groups share word lines.
  • the two layers of storage arrays 10t in the same first storage array group Cn share the source line SLtn, and the same location
  • the bit lines BLtn are interconnected
  • the two-layer memory arrays 10t in the same second memory array group Dn share the bit lines BLtn
  • the source lines SLtn at the same position are interconnected.
  • the word lines WLtm at the same position in the T/2 layer memory array 10t are interconnected through the first wire W1
  • the word lines WLtm at the same position in the remaining T/2 layer memory array 10t are interconnected through the second wire W2 and for the two-layer storage arrays 10t belonging to the same storage array group, among the word lines WLtm in the same position, one of the word lines WLtm is connected to the first wiring W1, and the other word line WLtm is connected to the first wiring W1.
  • Two traces W2 are connected; the first trace is insulated from the second trace.
  • FIG. 15 is a schematic diagram of the connection between the source line and the bit line and the corresponding control circuit in the memory.
  • FIG. 33 is a schematic diagram of the connection between word lines and corresponding control circuits in the memory.
  • two adjacent layers of storage arrays 10t are regarded as a set of first storage array groups Cn, and the two adjacent storage array groups Cn are separated by a medium layer 30 .
  • the two-layer storage arrays 10t in the same first storage array group Cn share the source line SLtn, and the bit lines BLtn at the same position are connected to each other through external wirings and vias.
  • the word of the two-layer storage array 10t in the first storage array group Cn Lines WLtm are independent of each other.
  • the bit lines BLtn and source lines SLtn of different memory array groups Cn are independent of each other.
  • the word lines WLtm of the upper memory arrays 10t in each first memory array group Cn are connected to each other through the first wirings W1 and through holes outside the array, and the word lines WLtm of the lower memory arrays 10t in each first memory array group Cn pass through the outside of the array.
  • the second trace W2 and the via are connected to each other.
  • parallel writing and reading of multi-layer memory cells can be implemented by gating the word line WLtm.
  • this architecture can expand the read and write bandwidth through three-dimensional stacking, and the read and write bandwidth is proportional to the number of stacked layers. Assuming that the bandwidth of a single-layer storage unit is N, the read and write bandwidth that can be achieved by stacking T layers is TN/2. Since the bit lines at the same position of only two layers of memory arrays are connected to each other at most, the stacking of the multi-layer memory arrays does not deteriorate the bit line load, and the read delay of a single-bit memory cell is smaller than that of the first example. Therefore, the memory can achieve high bandwidth rates.
  • each layer of storage array includes N bit lines, N bit lines, and M word lines, and T ⁇ N bit lines need T ⁇ N/2 wiring connections
  • T ⁇ N source lines need T ⁇ N/2 lines to connect to the source line control circuit
  • T ⁇ M word lines need 2M lines to connect to the word line control circuit.
  • the wiring connected to the bit line and the wiring connected to the source line can be drawn out from both ends of the bit line or the source line, respectively, and T ⁇ N/2 wirings are provided at each end.
  • the wirings connected to the word lines can be drawn out from both ends of the word lines, and M wirings are arranged at each of the two ends.
  • the number of storage array layers T is an odd number, see FIGS. 18 to 22 , including T/2 storage array groups and one layer of first storage arrays, and the two layers of storage arrays 10t in the same first storage array group Cn share the same source Line SLtn, and the bit lines BLtn at the same position are interconnected, the two-layer memory arrays 10t in the same second memory array group Dn share the bit line BLtn, and the source lines SLtn at the same position are interconnected.
  • the word lines at the same position in the (T+1)/2-layer memory array are interconnected by the first wiring, and the word lines at the same position in the remaining (T-1)/2-layer memory array are interconnected by the second wiring ; And for two-layer storage arrays belonging to the same storage array group, in the word lines at the same position, one of the word lines is connected with the first line, and the other word line is connected with the second line; the first The trace is insulated from the second trace.
  • FIG. 18 is a schematic diagram of the connection between the source line and the bit line and the corresponding control circuit in the memory.
  • FIG. 35 is a schematic diagram of the connection between word lines and corresponding control circuits in the memory.
  • the adjacent two-layer storage arrays 10t are regarded as a group of storage array groups Cn or Dn, and the medium layer 30 is used between the two adjacent storage array groups, as well as between the storage array group and the first storage array 103 . for isolation.
  • the two-layer storage arrays 10t in the same first storage array group Cn share the source line SLtn, and the bit lines BLtn at the same position are connected to each other through external wirings and vias.
  • the word of the two-layer storage array 10t in the first storage array group Cn Lines WLtm are independent of each other.
  • the two-layer storage arrays 10t in the same second storage array group Dn share the bit line BLtn, and the source lines SLtn at the same position are connected to each other through external wirings and vias.
  • the word of the two-layer storage array 10t in the second storage array group Dn Lines WLtm are independent of each other.
  • the bit lines BLtn and source lines SLtn of different memory array groups are independent of each other.
  • the word lines WLtm of the upper memory array 10t in each memory array group are connected to each other through the first wiring W1 outside the array and the through holes, and the word lines WLtm of the lower memory array 10t in each memory array group are connected to each other through the second wiring W2 outside the array. and through holes are connected to each other.
  • the word line WLtm of the first memory array 103 can be connected to the first wire W1, and certainly can also be connected to the second wire W2.
  • parallel writing and reading of multi-layer memory cells can be implemented by gating the word line WLtm.
  • this architecture can expand the read and write bandwidth through three-dimensional stacking, and the read and write bandwidth is proportional to the number of stacked layers. Assuming that the bandwidth of a single-layer storage unit is N, the read and write bandwidth that can be achieved by stacking T layers is (T+1)N/2. Since the bit lines at the same position of only two layers of memory arrays are connected to each other at most, the stacking of the multi-layer memory arrays does not deteriorate the bit line load, and the read delay of a single-bit memory cell is smaller than that of the first example. Therefore, the memory can achieve high bandwidth rates.
  • each layer of storage array includes N bit lines, N bit lines, M word lines, and T ⁇ N bit lines require (T+1)N/2 routing lines Connect to the bit line control circuit and the sense amplifier circuit, T ⁇ N source lines need (T+1)N/2 lines to connect to the source line control circuit, T ⁇ M word lines need 2M lines to connect to the word line Line control circuit.
  • the wiring connected to the bit line and the wiring connected to the source line can be drawn from both ends of the bit line or the source line, respectively, and (T+1)N/2 wirings are provided at each end.
  • the wirings connected to the word lines can be drawn out from both ends of the word lines, and M wirings are arranged at each of the two ends.
  • Example 1 Compared with Example 1, the number of wirings can be compared with Example 1, the number of wirings in the bit line direction and the word line direction is evenly distributed, and the layout is simple to implement.
  • the storage array groups are separated by a dielectric layer. Compared with the second example, the number of photomasks is reduced, and the manufacturing cost is controllable.
  • this embodiment can reduce the number of lines in the memory and reduce the layout area overhead.
  • the number of photomasks required for manufacturing is small, and the manufacturing cost is low.
  • an increase in the read bandwidth and write bandwidth of the memory array can be achieved through three-dimensional stacking without causing severe degradation of single-bit read latency, and a high overall bandwidth rate can be achieved. Therefore, this embodiment is suitable for low-cost, high-performance application scenarios.
  • the source lines or bit lines of adjacent layers of memory arrays in the memory are shared, and the word lines at the same position are independent of each other. If the increase of the read bandwidth and write bandwidth of the storage array is to be achieved without deteriorating the read delay of a single-bit memory cell and to achieve a high total bandwidth rate, the source lines and bit lines of the storage arrays of different layers in the memory are independent, and all layers of storage Word lines at the same location in the array are interconnected. If it is necessary to achieve low cost and increase the read bandwidth and write bandwidth of the memory array, in the memory, only some adjacent layer memory arrays share source lines or bit lines, and some word lines in the same position in the memory array are interconnected. . The number of layers of shared source lines or bit lines and the number of layers of the memory array interconnected by word lines can be specifically designed according to the requirements of cost and bandwidth rate.
  • the embodiments of the present application also provide an electronic device.
  • the electronic device includes a processor 1001 and a memory 1002 coupled with the processor 1001 , and the memory 1002 may be the memory shown in FIG. 1 .
  • the processor 1001 can call the software program stored in the memory 1002 to execute the corresponding method and realize the corresponding function of the electronic device.

Abstract

本申请公开了一种存储器及电子设备。其中，存储器包括堆叠的多层存储阵列，多层存储阵列中的每一层存储阵列包括：矩阵排列的多个存储单元，多条源线，多条位线以及多条字线。由于存储单元为铁电晶体管，从而使该存储器具有较高的存储密度、低功耗和高速度等优势。并且，由于是多层存储阵列堆叠的三维结构，因此可以有效地增加存储容量。另外，由于多层存储阵列中至少两层存储阵列中相同位置的源线互连，和/或位线互连，和/或字线互连。从而通过源线互连、位线互连或字线互连可以减少用于连接存储阵列与控制电路的走线的数量，从而减少走线的占用面积，增大存储阵列的占用面积比例，进而进一步增大存储器的存储容量。

Description

一种存储器及电子设备 技术领域
本申请涉及数据存储技术领域，特别涉及一种存储器及电子设备。
背景技术
动态随机存取存储器(DRAM)已成为高性能运算不可或缺的主要存储器，市场每年对DRAM的容量需求呈指数增长。传统半导体存储器芯片是通过提高单位面积的存储能力实现容量增长，但随着市场对存储容量需求愈发强烈，目前已不可避免地面临单元间串扰加剧和单字位成本增加等瓶颈。而三维堆叠半导体存储技术，通过增加存储叠层而非缩小器件二维尺寸实现存储密度增长，将半导体存储器的发展空间带入第三维度，成为未来实现存储器芯片容量可持续增长的关键。
然后，通过将DRAM芯片叠加实现存储容量的增加，会导致芯片成本和功耗快速增加。
发明内容
本申请提供的一种存储器及电子设备，可以增大存储器的存储容量。
第一方面，本申请实施例提供的一种存储器，包括堆叠的多层存储阵列，所述多层存储阵列中的每一层存储阵列包括：矩阵排列的多个存储单元，所述存储单元包括铁电晶体管；与每一行所述存储单元中的铁电晶体管的第一电极连接的源线；与每一行所述存储单元中的铁电晶体管的第二电极连接的位线；与每一列所述存储单元中的铁电晶体管的栅电极连接的字线。并且，在本申请中，存在至少两层所述存储阵列中相同位置的源线互连，和/或位线互连，和/或，字线互连，且字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连，具体实施方式如下：
第一种情况：所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连。
第二种情况：所述多层存储阵列中至少两层存储阵列中相同位置的位线互连。
第三种情况：所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连，相同位置的位线互连。
第四种情况：所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连。
第五种情况：将上述第四种情况与上述第一种情况、第二种情况或第三种情况进行结合，且需要满足字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连。第五种情况具体为：
所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连；所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连。
或者，所述多层存储阵列中至少两层存储阵列中相同位置的位线互连；所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连，且字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连。
或者，所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连，相同位置的位线互连；所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连，且字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连。
本申请提供的存储器，存储单元为铁电晶体管，从而使该存储器具有较高的存储密度、 低功耗和高速度等优势。并且，由于是多层存储阵列堆叠的三维结构，因此可以有效地增加存储容量。另外，由于所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连，和/或至少两层存储阵列中相同位置的位线互连；或者，所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连。通过源线互连、位线互连或字线互连可以减少用于连接多层存储阵列与控制电路的走线的数量，从而减少存储器中走线的占用面积，增大存储阵列的占用面积比例，进而进一步增大存储器的存储容量，并且还可以降低存储器的制作成本。
应理解，存储单元是存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即1比特数据(例如0或1)，也就是一个二进制位。通过多个存储单元，可以实现多个二进制位数据的存储。具体地，本申请实施例中，一个存储单元用于存储一个二进制位。
其中，铁电晶体管可以包括：半导体柱，由内向外依次围绕所述半导体柱设置的氧化物层、浮置金属层、铁电材料层和栅电极；所述半导体柱的一端为所述铁电晶体管的第一电极，所述半导体柱的另一端为所述铁电晶体管的第二电极。其中，第一电极可以为源极，第二电极为漏电，或者，第一电极为漏极，第二电极为源极，铁电晶体管的源极和漏极可以互换，不做具体区分。铁电晶体管利用铁电材料层的极化方向或极化强度的改变，调制半导体柱中沟道的载流子浓度，进而改变读取电流，实现“0”状态和“1”状态的存储。
写操作时，当需写入的状态为“0”时，铁电晶体管的第一电极和第二电极接电，栅电极接正向偏执电压V W，铁电材料层呈正极化状态，使半导体柱中沟道的载流子浓度变高，进而读取电流较高。当需写入的状态为“1”时，铁电晶体管的第一电极和第二电极接正向偏执电压V W，栅电极接地，铁电材料层呈负极化状态，使半导体柱中沟道的载流子浓度变低，进而读取电流较低。
读操作时，铁电晶体管的第一电极接地，第二电极接偏执电极V R，将需要读取数据的铁电晶体管的栅电极接偏执电压V WLR，使铁电晶体管呈导通状态，将不需要读取数据的铁电晶体管的栅电极接地，使铁电晶体管呈截止状态。
可以理解的是，在读操作和写操作的过程中，与存储单元连接的位线和字线可以确定存储单位的位置，因此在本申请中，字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连，从而保证本申请的所有存储单元中，任意两个存储单元所连接的位线和字线中至少有一个不相同。
需要说明的是，本申请对依次围绕所述半导体柱设置的氧化物层、浮置金属层、铁电材料层和栅电极的面积不作限定。在具体实施时，在每一层存储阵列中，铁电晶体管中半导体柱的延伸方向与所述多层存储阵列的堆叠方向相同。
示例性的，为了便于布线，在本申请中，各源线相互平行，各位线相互平行，各字线相互平行，且位线与源线平行设置。进一步地，位线与字线垂直设置。该90°交叉阵列结构可将存储单元面积微缩至4F 2，F为特征尺寸。
需要说明的是，本申请实施例中，平行的概念并不是严格意义上的平行，在存储器的制备过程中，由于制备工艺和制备设备的影响，可能存在并非严格平行的情况，这种情况是由于具体制备流程导致的，并不能说明不严格平行的情况超脱本申请的保护范围。此外，对于垂直这种位置关系也有类似理解，此处不再赘述。
示例性的，在本申请的存储器中，位线和源线可以分别位于存储单元的两端，例如位 线位于存储单元的顶端，源线位于存储单元的底端，当然，也可以位线位于存储单元的底端，源线位于存储单元的顶端，在此不作限定。字线位于位线和源线之间与存储单元的栅电极连接。
为了避免相邻两层存储阵列发生短路，在相邻两层存储阵列之间设置有介质层，以使相邻层的存储阵列相互独立。
存储器中还可以包括电路层。所述电路层可以包括：与各所述字线连接的字线控制电路，与各所述位线连接的位线控制电路，与各所述位线连接的灵敏放大器电路，与各所述源线连接的源线控制电路；所述堆叠的多层存储阵列位于电路层的上方。从而与将电路层形成在存储阵列层的周围相比，可以减少存储器的占用面积，从而进一步提高存储器的容量。并且，电路层位于存储阵列的下方可以尽可能的使控制电路位于存储阵列覆盖的区域内。
本申请中的灵敏放大器电路用于读取对应连接的位线所接收的反馈电流，从而读取存储单元中的数据。具体地，灵敏放大器电路中具有与每一位线对应的放大器，每个放大器可以通过将存储单元的反馈电流与参考值做比较，来判断该存储单元的电流高低，进而确定该存储单元中存储的数据。
实际应用中，在向存储器写入或读取数据时，上述在各位线、各源线和各字线上施加电压的过程可以由电路层中配置的与其对应的控制电路进行控制，其中，位线控制电路用于为对应的位线提供所需的电压，源线控制电路用于为对应的源线提供所需的电压，字线控制电路用于为字线提供所需的电压。
存储器中还可以包括行地址解码电路和列地址解码电路，用于在写入或读取数据时通过字线和位线选择对应的存储单元，上述各控制电路可以根据行地址解码电路和列地址解码电路的选择向对应的位线、源线或字线施加的电压，实现对行地址解码电路和列地址解码电路选择的某一个或某几个存储单元进行读写操作。
为了减少走线的数量，本申请中，多层存储阵列中至少两层存储阵列中相同位置的源线互连，和/或至少两层存储阵列中相同位置的位线互连；或者，多层存储阵列中至少两层存储阵列中相同位置的字线互连。从而通过源线互连可以减少用于连接源线与源线控制电路的走线的数量，通过位线互连可以减少用于连接位线与位线控制电路和灵敏放大器电路的走线的数量，通过字线互连可以减少用于连接字线与字线控制电路的走线的数量，从而减少存储器中走线的占用面积，增大存储阵列的占用面积比例，进而进一步增大存储器的存储容量。
在具体实施时，以相邻的两层存储阵列为一第一存储阵列组或一第二存储阵列组，所述三维存储器包括至少一个所述第一存储阵列组和/或至少一个所述第二存储阵列组，且一层存储阵列仅属于一个所述存储阵列组。
在一种实现方式中，所述第一存储阵列组中的两层存储阵列中，其中一层存储阵列中存储单元中铁电晶体管的第一电极与另一层存储阵列中存储单元中铁电晶体管的第一电极相对，且属于同一所述第一存储阵列组中的两层存储阵列中相同位置的存储单元共用源线；由于属于同一所述第一存储阵列组中的两层存储阵列中相同位置的存储单元共用源线。这样通过共用源线的方式实现源线互连，一方面可以减少与源线连接的走线数量，另一方面，可以减少用于制作源线的光罩数量，并且还避免了相邻层存储阵列之间的介质层的设置，从而降低制造成本。
或者，在另一种实现方式中，所述第二存储阵列组中的两层存储阵列中，其中一层存储阵列中存储单元中铁电晶体管的第二电极与另一层存储阵列中存储单元中铁电晶体管的第二电极相对，且属于同一所述第二存储阵列组中的两层存储阵列中相同位置的存储单元共用位线。由于属于同一所述第一存储阵列组中的两层存储阵列中相同位置的存储单元共用位线。这样通过共用位线的方式实现位线互连，一方面可以减少与位线连接的走线数量，另一方面，可以减少用于制作位线的光罩数量，并且还避免了相邻层存储阵列之间的介质层的设置，从而降低制造成本。
为了进一步减少走线的数量，针对各第一存储阵列组，属于同一所述第一存储阵列组中的两层存储阵列中相同位置的位线互连。
为了进一步减少走线的数量，针对各第二存储阵列组，属于同一所述第二存储阵列组中的两层存储阵列中相同位置的源线互连。
综上，本申请提供的存储器中，存储阵列组的数量越多，走线的数量越少，生产过程中能够减少的光罩数量也越多，制造成本也会越低。
示例性的，当存储器中存储阵列的层数为偶数时，所述存储器包括T层存储阵列，T为大于或等于4的偶数，所述T层存储阵列包括T/2个所述存储阵列组，即将存储器中所有层存储阵列均进行了分组，从而使存储器中，存储阵列组的数量越多。在具体实施时，所有存储阵列组均为第一存储阵列组。或者，所有存储阵列组均为第二存储阵列组。或者，所有存储阵列组中一部分为第一存储阵列组，另一部分为第二存储阵列组。
示例性的，当存储器中存储阵列的层数为奇数时，所述存储器包括T层存储阵列，T为大于或等于3的奇数，所述T层存储阵列包括(T-1)/2个所述存储阵列组和一层第一存储阵列，其中所述第一存储阵列不属于任一所述存储阵列组，即使存储器中，存储阵列组的数量越多。在具体实施时，所述第一存储阵列的两侧均设置有所述存储阵列组，或者，所述存储阵列组均位于所述第一存储阵列的同一侧。
进一步，当存储器中存储阵列的层数为奇数时，为了进一步减少走线的数量，减少生产过程中光罩数量，以进一步降低制造成本，可以将第一存储阵列和与其相邻的其它存储阵列设置为共用源线和/或位线，具体存在如下五种情况：
第一种情况：所述存储阵列组均位于所述第一存储阵列的同一侧，且与所述第一存储阵列相邻的存储阵列组为所述第一存储阵列组；所述第一存储阵列和与其相邻的所述存储阵列中相同位置的存储单元共用位线。
第二种情况：所述存储阵列组均位于所述第一存储阵列的同一侧，且与所述第一存储阵列相邻的存储阵列组为所述第二存储阵列组；所述第一存储阵列和与其相邻的所述存储阵列中相同位置的存储单元共用源线。
第三种情况：所述第一存储阵列的两侧均设置有所述存储阵列组，且与所述第一存储阵列相邻的存储阵列组均为所述第一存储阵列组；所述第一存储阵列和与其相邻的其中一层所述存储阵列中相同位置的存储单元共用位线。
第四种情况：所述第一存储阵列的两侧均设置有所述存储阵列组，且与所述第一存储阵列相邻的存储阵列组均为所述第二存储阵列组；所述第一存储阵列和与其相邻的其中一层所述存储阵列中相同位置的存储单元共用源线。
第五种情况：所述第一存储阵列的两侧均设置有所述存储阵列组，且与所述第一存储阵列相邻的存储阵列组分别为所述第一存储阵列组和所述第二存储阵列组；与所述第一存 储阵列的所述第一存储阵列组中，与所述第一存储阵列相邻的一层存储阵列，以及所述第一存储阵列中相同位置的存储单元共用位线；与所述第一存储阵列的所述第二存储阵列组中，与所述第一存储阵列相邻的一层存储阵列，以及所述第一存储阵列中相同位置的存储单元共用源线。
在具体实施时，当存储器中存储阵列的层数T为大于或等于5的奇数，且所述存储器包括(T-1)/2个所述存储阵列组和一层第一存储阵列时，所有所述存储阵列组均为第一存储阵列组。或者，所有所述存储阵列组均为第二存储阵列组。或者，所有所述存储阵列组中包括所述第一存储阵列组和第二存储阵列组；所有所述第一存储阵列组均位于所述第一存储阵列的第一侧，所有所述第二存储阵列组位于所述第一存储阵列的第二侧。
在申请中，为了进一步减少走线的数量，减少生产过程中光罩数量，减少介质层，以进一步降低制造成本，任意相邻两个第一存储阵列组中属于不同第一存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用位线；任意相邻两个第二存储阵列组中属于不同存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用源线。
需要说明的是，相邻两个存储阵列组是指该两个存储阵列组之间没有其它存储阵列，相邻两层存储阵列是指所在层直接相邻的存储阵列，例如第t层存储阵列和第t+1层存储阵列。
在具体实施时，对于相邻存储阵列组之间共用源线或位线存在如下五种情况：
第一种情况：T为大于或等于4的偶数，所有所述存储阵列组均为第一存储阵列组；任意相邻两个第一存储阵列组中，属于不同第一存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用位线。
第二种情况：T为大于或等于4的偶数，所有所述存储阵列组均为第二存储阵列组；任意相邻两个第二存储阵列组中，属于不同第二存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用源线。
第三种情况：T为大于或等于5的奇数，所有所述存储阵列组均为第一存储阵列组；位于所述第一存储阵列同一侧的任意相邻两个所述第一存储阵列组中，属于不同所述第一存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用位线。
第四种情况：T为大于或等于5的奇数，所有所述存储阵列组均为第二存储阵列组；位于所述第一存储阵列同一侧的任意相邻两个所述第二存储阵列组中，属于不同所述第二存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用源线。
第五种情况：T为大于或等于5的奇数，所有所述存储阵列组中包括所述第一存储阵列组和第二存储阵列组；所述第一存储阵列组均位于所述第一存储阵列第一侧，所述第二存储阵列组位于所述第一存储阵列第二侧；位于所述第一存储阵列第一侧的任意相邻两个所述第一存储阵列组中，属于不同所述第一存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用位线；位于所述第一存储阵列第一侧的任意相邻两个所述第二存储阵列组中，属于不同所述第二存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用源线。
可以理解的是，在本申请中，当相邻两层存储阵列中相同位置的存储单元共用源线时，该相邻的两层存储阵列中，其中一层存储阵列中存储单元中铁电晶体管的第一电极与另一层存储阵列中存储单元中铁电晶体管的第一电极相对。当相邻两层存储阵列中相同位置的存储单元共用位线时，该相邻的两层存储阵列中，其中一层存储阵列中存储单元中铁电晶 体管的第二电极与另一层存储阵列中存储单元中铁电晶体管的第二电极相对。
在本申请，当所有层存储阵列中相同位置的源线均互连时，这样可以减少N×(T-1)条走线。当所有层存储阵列中相同位置的位线均互连时，同样可以减少N×(T-1)条走线。当所有层存储阵列中相同位置的源线均互连，且所有层存储阵列中相同位置的位线均互连时，可以减少2N×(T-1)条走线，从而可以将走线数量尽可能的少。
在具体实施时，当所有层存储阵列中相同位置的位线均互连时，不管相同位置的源线是否互连，存储器中所有层存储阵列中相同位置的字线均需要相互独立。从而利用字线选通实现对所有层的存储单元并行写入和读出。
当然，在本申请中，为了减少走线的数量，也可以是不同层存储阵列中相同位置的字线互连。
示例性，本申请中所有层所述存储阵列中相同位置的字线均互连。这种情况需要存储器中所有层存储阵列中相同位置的位线均相互独立。从而利用位线选通实现对所有层的存储单元并行写入和读出。
当然，在本申请实施例中，对于存储器中，所有层存储阵列中相同位置的位线不完全互连的情况，可以存在至少两层存储阵列中相同位置的字线互连，只要保证字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连即可。
下面将位线和字线结合在一起，通过具体实施例说明本申请的存储器。
在一种可行的实施方式中，所述存储器包括T层存储阵列，T为大于或等于4的偶数，所述T层存储阵列包括T/2个所述存储阵列组；所有所述存储阵列组均为第一存储阵列组或均为第二存储阵列组；T/2层存储阵列中的相同位置的字线通过第一走线互连，剩余T/2层存储阵列中的相同位置的字线通过第二走线互连；且对于属于同一存储阵列组中的两层存储阵列，相同位置的字线中，其中一条字线与所述第一走线连接，另一条字线与所述第二走线连接。
在一种可行的实施方式中，所述存储器包括T层存储阵列，T为大于或等于3的奇数，所述T层存储阵列包括(T-1)/2个所述存储阵列组和一层第一存储阵列，其中所述第一存储阵列不属于任一所述存储阵列组；所述存储阵列组均位于所述第一存储阵列的同一侧，或所述第一存储阵列的两侧均设置有所述存储阵列组；(T+1)/2层存储阵列中的相同位置的字线通过第一走线互连，剩余(T-1)/2层存储阵列中的相同位置的字线通过第二走线互连；且对于属于同一存储阵列组中的两层存储阵列，相同位置的字线中，其中一条字线与所述第一走线连接，另一条字线与所述第二走线连接。
第二方面，本申请实施例提供的一种电子设备，该电子设备包括处理器以及与处理器耦合的、上述实施例所述的存储器。具体地，处理器可以调用存储器中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
附图说明
图1为本申请实施例提供的一种存储器的结构示意；
图2为本申请实施例提供的存储器的一层存储阵列的结构示意；
图3为本申请实施例提供的又一种存储器的结构示意；
图4为本申请实施例提供的又一种存储器的结构示意；
图5为本申请实施例提供的又一种存储器的结构示意；
图6为本申请实施例提供的又一种存储器的结构示意；
图7为本申请实施例提供的一种铁电晶体管的结构示意；
图8为图7所示铁电晶体管沿AA’方向的剖面结构示意图；
图9为本申请实施例提供的又一种存储器的结构示意；
图10为本申请实施例提供的一种存储器的局部结构示意；
图11为本申请实施例提供的电路层的结构示意；
图12为本申请实施例提供的又一种存储器的局部结构示意；
图13为本申请实施例提供的又一种存储器的局部结构示意；
图14为本申请实施例提供的又一种存储器的局部结构示意；
图15为本申请实施例提供的又一种存储器的局部结构示意；
图16为本申请实施例提供的又一种存储器的局部结构示意；
图17为本申请实施例提供的又一种存储器的局部结构示意；
图18为本申请实施例提供的又一种存储器的局部结构示意；
图19为本申请实施例提供的又一种存储器的局部结构示意；
图20为本申请实施例提供的又一种存储器的局部结构示意；
图21为本申请实施例提供的又一种存储器的局部结构示意；
图22为本申请实施例提供的又一种存储器的局部结构示意；
图23为本申请实施例提供的又一种存储器的局部结构示意；
图24为本申请实施例提供的又一种存储器的局部结构示意；
图25为本申请实施例提供的又一种存储器的局部结构示意；
图26为本申请实施例提供的又一种存储器的局部结构示意；
图27为本申请实施例提供的又一种存储器的局部结构示意；
图28为本申请实施例提供的又一种存储器的结构示意；
图29为本申请实施例提供的又一种存储器的结构示意；
图30为本申请实施例提供的又一种存储器的局部结构示意；
图31为本申请实施例提供的又一种存储器的局部结构示意；
图32为本申请实施例提供的又一种存储器的结构示意；
图33为本申请实施例提供的又一种存储器的局部结构示意；
图34为本申请实施例提供的又一种存储器的结构示意；
图35为本申请实施例提供的又一种存储器的局部结构示意；
图36为本申请实施例提供的电子设备的结构示意图。
具体实施方式
铁电存储器是基于铁电材料的铁电效应来存储数据，铁电存储器因其超高的存储密度、低功耗和高速度等优势，有望成为替代DRAM的主要竞争者。
有鉴于此，本申请提供一种基于铁电存储器的三维存储器，在保证存储器低功耗和高速度等优势的基础上，可以有效地增加存储容量，降低制造成本。
该三维存储器可以应用于各种数据信息存储领域中，例如，可以应用于处理器、计算机或服务器等电子设备中的存储器中，该处理器可以为中央处理器、人工智能处理器、数字信号处理器或神经网络处理器等，当然，本申请实施例中的三维存储器也可以应用于其 他电子设备中，此处不做限定。
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
应注意的是，在本说明书中，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
参见图1和图2，图1为本申请一种实施例提供的存储器的结构示意图，图2为本申请一种实施例提供的存储器中一层存储阵列的结构示意图。在本申请实施例提供的存储器中，包括：堆叠的多层存储阵列101～10T(T为大于1的整数，图1以T＝3为例进行示意)，所述多层存储阵列101～10T中的每一层存储阵列10t(t为1至T的任意整数)可以包括：矩阵排列的多个存储单元11 tnm(n为1至N的任意整数，m为1至M的任意整数，N为一层存储阵列中存储单元的总行数，M为一层存储阵列中存储单元的总列数，图1和图2中以N＝2，M＝2为例进行示意)，多条源线SLtn，多条位线BLtn和多条字线WLtm。所述存储单元11 tnm包括铁电晶体管；每一行所述存储单元11 tnm的铁电晶体管的第一电极连接一条所述源线SLtn，每一行所述存储单元11 tnm的铁电晶体管的第二电极连接一条所述位线BLtn，每一列所述存储单元11 tnm的铁电晶体管的栅电极连接一条所述字线WLtm。
并且，在本申请中，存在至少两层所述存储阵列中相同位置的源线互连，和/或位线互连，和/或，字线互连，且字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连，具体实施方式如下：
第一种情况：所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连。示例性的，如图3所示，存储阵列10n中的源线SLn1与存储阵列10m中的源线SLm1互连，存储阵列10n中的源线SLn2与存储阵列10m中的源线SLm2互连，存储阵列10n中的源线SLn3与存储阵列10m中的源线SLm3互连，存储阵列10n中的源线SLn4与存储阵列10m中的源线SLm4互连。图3仅视出了源线互连的两层存储阵列10n和10m，本申请中不限于仅有两层存储阵列，且源线互连的存储阵列层也不限于是两层。
第二种情况：所述多层存储阵列中至少两层存储阵列中相同位置的位线互连。示例性的，如图4所示，存储阵列10n中的位线BLn1与存储阵列10m中的位线BLm1互连，存储阵列10n中的位线BLn2与存储阵列10m中的位线BLm2互连，存储阵列10n中的位线BLn3与存储阵列10m中的位线BLm3互连，存储阵列10n中的位线BLn4与存储阵列10m中的位线BLm4互连。图4仅视出了源线互连的两层存储阵列10n和10m，本申请中不限于仅有两层存储阵列，且位线互连的存储阵列层也不限于是两层。
第三种情况：所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连，相同位置的位线互连。示例性的，如图5所示，存储阵列10n中的源线SLn1与存储阵列10m中的源线SLm1互连，存储阵列10n中的源线SLn2与存储阵列10m中的源线SLm2互连，存储阵列10n中的源线SLn3与存储阵列10m中的源线SLm3互连，存储阵列10n中的源线SLn4与存储阵列10m中的源线SLm4互连。存储阵列10n中的位线BLn1与存储阵列10m中的位线BLm1互连，存储阵列10n中的位线BLn2与存储阵列10m中的位线BLm2互连，存储阵列10n中的位线BLn3与存储阵列10m中的位线BLm3互连，存储阵列10n中的位线BLn4与存储阵列10m中的位线BLm4互连。图5仅视出了源线互连的两层存储阵列10n和10m，本申请中不限于仅有两层存储阵列，且源线以及位线互连的存储阵列层也不限于是两层。
第四种情况：所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连。示例性的，如图6所示，存储阵列10n中的字线WLn1与存储阵列10m中的字线WLm1互连，存储阵列10n中的字线WLn2与存储阵列10m中的字线WLm2互连，存储阵列10n中的字线WLn3与存储阵列10m中的字线WLm3互连，存储阵列10n中的字线WLn4与存储阵列10m中的字线WLm4互连，存储阵列10n中的字线WLn5与存储阵列10m中的字线WLm5互连。图6仅视出了源线互连的两层存储阵列10n和10m，本申请中不限于仅有两层存储阵列，且字线互连的存储阵列层也不限于是两层。
第五种情况：将上述第四种情况与上述第一种情况、第二种情况或第三种情况进行结合，且需要满足字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连。第五种情况具体为：
所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连；所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连。
或者，所述多层存储阵列中至少两层存储阵列中相同位置的位线互连；所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连，且字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连。
或者，所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连，相同位置的位线互连；所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连，且字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连。
本申请提供的存储器，存储单元为铁电晶体管，从而使该存储器具有较高的存储密度、低功耗和高速度等优势。并且，由于是多层存储阵列堆叠的三维结构，因此可以有效地增加存储容量。另外，由于所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连，和/或至少两层存储阵列中相同位置的位线互连；或者，所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连。通过源线互连、位线互连或字线互连可以减少用于连接多层存储阵列与控制电路的走线的数量，从而减少存储器中走线的占用面积，增大存储阵列的占用面积比例，进而进一步增大存储器的存储容量，并且还可以降低存储器的制作成本。
为了便于描述，本申请中存储阵列的层数为T，每一层存储阵列中均具有N行×M列个存储单元，N条源线、N条位线和M条字线，该存储器的容量为N×M×T。BLtn、SLtn分别为第t层存储阵列的第n条位线BL和第n条源线SL，WLtm为第t层存储阵列的第m条字线WL，存储单元11 tnm为第t层存储阵列中位于第n行、第m列的存储单元11。
可以理解的是，位于不同层存储阵列中的相同位置的存储单元11 tnm是指：层位置t不相同，行位置n和列位置m相同的存储单元；位于不同层存储阵列中的相同位置的源线SLtn是指：层位置t不相同，行位置n相同的源线；位于不同层存储阵列中的相同位置的位线BLtn是指：层位置t不相同，行位置n相同的位线；位于不同层存储阵列中的相同位置的字线WLtm是指：层位置t不相同，列位置m相同的字线。
应理解，存储单元是存储器中具有数据存储和读写功能的最小单元，可以用于存储一个最小信息单位，即1比特数据(例如0或1)，也就是一个二进制位。通过多个存储单元，可以实现多个二进制位数据的存储。具体地，本申请实施例中，一个存储单元用于存储一个二进制位。
参见图7和图8，图7为本申请一种实施例提供的铁电晶体管的结构示意图；图8为图7所示的铁电晶体管沿AA’方向的剖面结构示意图。该铁电晶体管可以包括：半导体柱11e，由内向外依次围绕所述半导体柱11e设置的氧化物层11d、浮置金属层11c、铁电材料层11b和栅电极11a；所述半导体柱11e的一端为所述铁电晶体管的第一电极，所述半导体柱11e的另一端为所述铁电晶体管的第二电极。其中，第一电极可以为源极，第二电极为漏电，或者，第一电极为漏极，第二电极为源极，铁电晶体管的源极和漏极可以互换，不做具体区分。铁电晶体管利用铁电材料层11b的极化方向或极化强度的改变，调制半导体柱11e中沟道的载流子浓度，进而改变读取电流，实现“0”状态和“1”状态的存储。
写操作时，当需写入的状态为“0”时，铁电晶体管的第一电极和第二电极接电，栅电极接正向偏执电压V W，铁电材料层呈正极化状态，使半导体柱中沟道的载流子浓度变高，进而读取电流较高。当需写入的状态为“1”时，铁电晶体管的第一电极和第二电极接正向偏执电压V W，栅电极接地，铁电材料层呈负极化状态，使半导体柱中沟道的载流子浓度变低，进而读取电流较低。
读操作时，铁电晶体管的第一电极接地，第二电极接偏执电极V R，将需要读取数据的铁电晶体管的栅电极接偏执电压V WLR，使铁电晶体管呈导通状态，将不需要读取数据的铁电晶体管的栅电极接地，使铁电晶体管呈截止状态。
可以理解的是，在读操作和写操作的过程中，与存储单元连接的位线和字线可以确定存储单位的位置，因此在本申请中，字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连，从而保证本申请的所有存储单元中，任意两个存储单元所连接的位线和字线中至少有一个不相同。
需要说明的是，本申请对依次围绕所述半导体柱设置的氧化物层、浮置金属层、铁电材料层和栅电极的面积不作限定。
在具体实施时，在每一层存储阵列中，如图7所示，铁电晶体管中半导体柱11e的延伸方向与所述多层存储阵列的堆叠方向z相同。
示例性的，为了便于布线，在本申请中，参见图1至图6，各源线SLtn相互平行，各位线BLtn相互平行，各字线WLtm相互平行，且位线BLtn与源线SLtn平行设置。进一步地，位线BLtn与字线WLtm垂直设置。该90°交叉阵列结构可将存储单元面积微缩至4F 2，F为特征尺寸。
需要说明的是，本申请实施例中，平行的概念并不是严格意义上的平行，在存储器的制备过程中，由于制备工艺和制备设备的影响，可能存在并非严格平行的情况，这种情况是由于具体制备流程导致的，并不能说明不严格平行的情况超脱本申请的保护范围。此外， 对于垂直这种位置关系也有类似理解，此处不再赘述。
为了方便描述，在附图1至6所示的存储器中均示出了xyz坐标系。其中，在每个层存储阵列10t中，多条源线SLtn沿y轴平行排列，多条位线BLtn沿y轴平行排列，多条字线WLtm沿x轴平行排列，多层存储阵列10t沿着z轴方向依次堆叠。
示例性的，如图9和图10所示，在本申请的存储器中，位线BLtn和源线SLtn可以分别位于存储单元11 tnm的两端，例如位线BLtn位于存储单元11 tnm的顶端，源线SLtn位于存储单元11 tnm的底端，当然，也可以位线BLtn位于存储单元11 tnm的底端，源线SLtn位于存储单元11 tnm的顶端，在此不作限定。字线WLtm位于位线BLtn和源线SLtn之间与存储单元11 tnm的栅电极连接。
继续参见图9和图10，为了避免相邻两层存储阵列10t发生短路，在相邻两层存储阵列10t之间设置有介质层30，以使相邻层的存储阵列10t相互独立。
继续参见图9，存储器中还包括电路层20。示例性的，如图11所示，所述电路层20可以包括：与各所述字线WLtm连接的字线控制电路201，与各所述位线BLtn连接的位线控制电路202，与各所述位线BLtn连接的灵敏放大器电路203，与各所述源线SLtn连接的源线控制电路204；所述堆叠的多层存储阵列10t位于电路层20的上方。从而与将电路层形成在存储阵列层的周围相比，可以减少存储器的占用面积，从而进一步提高存储器的容量。并且，电路层20位于存储阵列10t的下方可以尽可能的使控制电路位于存储阵列覆盖的区域内。
本申请中的灵敏放大器电路用于读取对应连接的位线所接收的反馈电流，从而读取存储单元中的数据。
具体地，灵敏放大器电路中具有与每一位线对应的放大器，每个放大器可以通过将存储单元的反馈电流与参考值做比较，来判断该存储单元的电流高低，进而确定该存储单元中存储的数据。
实际应用中，在向存储器写入或读取数据时，上述在各位线、各源线和各字线上施加电压的过程可以由电路层中配置的与其对应的控制电路进行控制，其中，位线控制电路用于为对应的位线提供所需的电压，源线控制电路用于为对应的源线提供所需的电压，字线控制电路用于为字线提供所需的电压。
存储器中还可以包括行地址解码电路和列地址解码电路，用于在写入或读取数据时通过字线和位线选择对应的存储单元，上述各控制电路可以根据行地址解码电路和列地址解码电路的选择向对应的位线、源线或字线施加的电压，实现对行地址解码电路和列地址解码电路选择的某一个或某几个存储单元进行读写操作。
在具体实施时，以存储阵列的层数为T，每一层存储阵列中均具有N行×M列个存储单元，N条源线、N条位线和M条字线为例，T层存储阵列的T×N条位线可以通过T×N条位于存储阵列周围的走线和通孔连接至同一位线控制电路和同一灵敏放大器电路；其中与各位线连接的走线可以分别位线两端。T层存储阵列的T×N条源线可以通过T×N条位于存储阵列周围的走线和通孔连接至同一源线控制电路；其中与各源线连接的走线可以分别源线两端。T层存储阵列的T×M条字线可以通过T×M条位于存储阵列周围的走线和通孔连接至同一字线控制电路；其中与各字线连接的走线可以分别字线两端。在该存储器中总共需要设置T×(2N+M)条走线，走线数量多会增加存储阵列外围的面积。
为了减少走线的数量，本申请中，多层存储阵列中至少两层存储阵列中相同位置的源 线互连，和/或至少两层存储阵列中相同位置的位线互连；或者，多层存储阵列中至少两层存储阵列中相同位置的字线互连。从而通过源线互连可以减少用于连接源线与源线控制电路的走线的数量，通过位线互连可以减少用于连接位线与位线控制电路和灵敏放大器电路的走线的数量，通过字线互连可以减少用于连接字线与字线控制电路的走线的数量，从而减少存储器中走线的占用面积，增大存储阵列的占用面积比例，进而进一步增大存储器的存储容量。
下面结合具体实施例，对本申请互连的具体实施方式进行详细说明。需要说明的是，本实施例中是为了更好的解释本申请，但不限制本申请。
下面先介绍不同层存储阵列中相同位置的位线和/或源线互连的具体情况。
参见图12至图14，在本申请实施例提供的存储器中，以相邻的两层存储阵10t和10t+1为一个第一存储阵列组Cn或一个第二存储阵列组Dn；所述存储器包括至少一个第一存储阵列组Cn和/或至少一个第二存储阵列组Dn；且一层存储阵列10t仅属于一个所述存储阵列组Cn或Dn。例如图12至图14均是以存储器包括两个存储阵列组为例进行示意，示例性的，图12中包括两个第一存储阵列组C1和C2，图13中包括两个第二存储阵列组D1和D2，图14中包括一个第一存储阵列组C1和一个第二存储阵列组D1。
参见图12和图14，所述第一存储阵列组Cn中的两层存储阵列10t和10t+1中，其中一层存储阵列10t中存储单元中铁电晶体管的第一电极与另一层存储阵列10t+1中存储单元中铁电晶体管的第一电极相对，且属于同一所述第一存储阵列组Cn中的两层存储阵列10t和10t+1中相同位置的存储单元共用源线SLtn。例如图12中，第一存储阵列组C1中包括存储阵列101和存储阵列102，存储阵列101中的存储单元11 1nm中铁电晶体管的第一电极均在铁电晶体管的底端，铁电晶体管的第二电极均在铁电晶体管的顶端，而存储阵列102中的存储单元11 1nm中铁电晶体管的第一电极均在铁电晶体管的顶端，铁电晶体管的第二电极均在铁电晶体管的底端，即存储单元11 1nm中铁电晶体管的第一电极与存储单元11 2nm中铁电晶体管的第一电极相对，从而可以使第一存储阵列组C1中的存储阵列101和102中相同位置的存储单元共用源线SLtn。
由于属于同一所述第一存储阵列组中的两层存储阵列中相同位置的存储单元共用源线。这样通过共用源线的方式实现源线互连，一方面可以减少与源线连接的走线数量，另一方面，可以减少用于制作源线的光罩数量，并且还避免了相邻层存储阵列之间的介质层的设置，从而降低制造成本。
参见图13和图14，所述第二存储阵列组Dn中的两层存储阵列10t和10t+1中，其中一层存储阵列10t中存储单元中铁电晶体管的第二电极与另一层存储阵列10t+1中存储单元中铁电晶体管的第二电极相对，且属于同一所述第二存储阵列组Dn中的两层存储阵列10t和10t+1中相同位置的存储单元共用位线BLtn。例如图13中，第二存储阵列组D1中包括存储阵列101和存储阵列102，存储阵列101中的存储单元11 1nm中铁电晶体管的第一电极均在铁电晶体管的顶端，铁电晶体管的第二电极均在铁电晶体管的底端，而存储阵列102中的存储单元11 1nm中铁电晶体管的第一电极均在铁电晶体管的底端，铁电晶体管的第二电极均在铁电晶体管的顶端，即存储单元11 1nm中铁电晶体管的第二电极与存储单元11 2nm中铁电晶体管的第二电极相对，从而可以使第二存储阵列组D1中的存储阵列101和102中相同位置的存储单元共用位线BLtn。
由于属于同一所述第一存储阵列组中的两层存储阵列中相同位置的存储单元共用位 线。这样通过共用位线的方式实现位线互连，一方面可以减少与位线连接的走线数量，另一方面，可以减少用于制作位线的光罩数量，并且还避免了相邻层存储阵列之间的介质层的设置，从而降低制造成本。
在具体实施时，在本申请中，在同一第一存储阵列组中，相邻两层存储阵列可以相对共用的源线呈镜像对称设置，在同一第二存储阵列组中，相邻两层存储阵列可以相对共用的位线呈镜像对称设置。
为了进一步减少走线的数量，针对各第一存储阵列组Cn，参见图15、图17、图18和图19，在存储器中，属于同一所述第一存储阵列组Cn中的两层存储阵列10t和10t+1中相同位置的位线BLtn和BLt+1n互连。例如图15中，第一存储阵列组C1中，存储阵列101中的位线BL11和存储阵列102中的位线BL21互连，第一存储阵列组C2中，存储阵列103中的位线BL31和存储阵列104中的位线BL41互连。
为了进一步减少走线的数量，针对各第二存储阵列组Dn，参见图16、图17和图18，在存储器中，属于同一所述第二存储阵列组Dn中的两层存储阵列10t和10t+1中相同位置的源线SLtn和SLt+1n互连。例如图16中，第二存储阵列组D1中，存储阵列101中的源线SL11和存储阵列102中的源线SL21互连，第二存储阵列组D2中，存储阵列103中的源线SL31和存储阵列104中的源线SL41互连。
综上，本申请提供的存储器中，存储阵列组的数量越多，走线的数量越少，生产过程中能够减少的光罩数量也越多，制造成本也会越低。
示例性的，当存储器中存储阵列的层数为偶数时，如图12、图13、图15至图17所示，所述存储器包括T层存储阵列10t，T为大于或等于4的偶数，所述T层存储阵列10t包括T/2个所述存储阵列组Cn和/或Dn，即将存储器中所有层存储阵列均进行了分组，从而使存储器中，存储阵列组的数量越多。其中，图12、图13、图15至图17中是以T＝4为例进行示意，本申请对T的数量不作限定。
在具体实施时，参见如图12和图15，所有存储阵列组均为第一存储阵列组Cn。或者，参见图13和图16，所有存储阵列组均为第二存储阵列组Dn。或者，参见图14和图17，所有存储阵列组中一部分为第一存储阵列组Cn，另一部分为第二存储阵列组Dn。
示例性的，当存储器中存储阵列的层数为奇数时，如图14、图18和图19所示，所述存储器包括T层存储阵列，T为大于或等于3的奇数，所述T层存储阵列包括(T-1)/2个所述存储阵列组和一层第一存储阵列，其中所述第一存储阵列不属于任一所述存储阵列组，即使存储器中，存储阵列组的数量越多。其中，图14、图18和图19中是以T＝5为例进行示意，本申请对T的数量不作限定。在图14和图18中，存储阵列103为第一存储阵列，在图19中，存储阵列105为第一存储阵列。
在具体实施时，所述第一存储阵列的两侧均设置有所述存储阵列组，例如图14和图18所示，第一存储阵列组C1和第二存储阵列组D1分别位于第一存储阵列103的两侧。或者，所述存储阵列组均位于所述第一存储阵列的同一侧，例如图19所示，第一存储阵列组C1和C2均位于第一存储阵列105的同一侧。
进一步，当存储器中存储阵列的层数为奇数时，为了进一步减少走线的数量，减少生产过程中光罩数量，以进一步降低制造成本，可以将第一存储阵列和与其相邻的其它存储阵列设置为共用源线和/或位线，具体存在如下五种情况：
第一种情况：所述存储阵列组均位于所述第一存储阵列的同一侧，且与所述第一存储 阵列相邻的存储阵列组为所述第一存储阵列组；所述第一存储阵列和与其相邻的所述存储阵列中相同位置的存储单元共用位线。示例性的，如图20所示，第一存储阵列组C1和C2均位于第一存储阵列105上方，第一存储阵列105和存储阵列104中相同位置的存储单元共用位线BLtn。
第二种情况：所述存储阵列组均位于所述第一存储阵列的同一侧，且与所述第一存储阵列相邻的存储阵列组为所述第二存储阵列组；所述第一存储阵列和与其相邻的所述存储阵列中相同位置的存储单元共用源线。
第三种情况：所述第一存储阵列的两侧均设置有所述存储阵列组，且与所述第一存储阵列相邻的存储阵列组均为所述第一存储阵列组；所述第一存储阵列和与其相邻的其中一层所述存储阵列中相同位置的存储单元共用位线。示例性的，如图21所示，第一存储阵列组C1和C2分别位于第一存储阵列103的两侧，第一存储阵列103和存储阵列104中相同位置的存储单元共用位线BLtn。
第四种情况：所述第一存储阵列的两侧均设置有所述存储阵列组，且与所述第一存储阵列相邻的存储阵列组均为所述第二存储阵列组；所述第一存储阵列和与其相邻的其中一层所述存储阵列中相同位置的存储单元共用源线。
第五种情况：所述第一存储阵列的两侧均设置有所述存储阵列组，且与所述第一存储阵列相邻的存储阵列组分别为所述第一存储阵列组和所述第二存储阵列组；与所述第一存储阵列的所述第一存储阵列组中，与所述第一存储阵列相邻的一层存储阵列，以及所述第一存储阵列中相同位置的存储单元共用位线；与所述第一存储阵列的所述第二存储阵列组中，与所述第一存储阵列相邻的一层存储阵列，以及所述第一存储阵列中相同位置的存储单元共用源线。示例性的，如图22所示，第一存储阵列组C1和C2分别位于第一存储阵列103的两侧，第一存储阵列103和存储阵列102中相同位置的存储单元共用位线BLtn，第一存储阵列103和存储阵列104中相同位置的存储单元共用源线SLtn。
在具体实施时，当存储器中存储阵列的层数T为大于或等于5的奇数，且所述存储器包括(T-1)/2个所述存储阵列组和一层第一存储阵列时，如图19至图21所示，所有所述存储阵列组均为第一存储阵列组Cn。或者，所有所述存储阵列组均为第二存储阵列组。或者，如图14、图18和图22所示，所有所述存储阵列组中包括所述第一存储阵列组Cn和第二存储阵列组Dn；所有所述第一存储阵列组Cn均位于所述第一存储阵列的第一侧，所有所述第二存储阵列组Dn位于所述第一存储阵列的第二侧。
在申请中，为了进一步减少走线的数量，减少生产过程中光罩数量，减少介质层，以进一步降低制造成本，任意相邻两个第一存储阵列组中属于不同第一存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用位线；任意相邻两个第二存储阵列组中属于不同存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用源线。
需要说明的是，相邻两个存储阵列组是指该两个存储阵列组之间没有其它存储阵列，相邻两层存储阵列是指所在层直接相邻的存储阵列，例如第t层存储阵列和第t+1层存储阵列。
在具体实施时，对于相邻存储阵列组之间共用源线或位线存在如下五种情况：
第一种情况：T为大于或等于4的偶数，所有所述存储阵列组均为第一存储阵列组；任意相邻两个第一存储阵列组中，属于不同第一存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用位线。示例性的，如图23所示，第一存储阵列组C1的存储阵列102 和第一存储阵列组C2的存储阵列103中相同位置的存储单元共用位线BLtn。
第二种情况：T为大于或等于4的偶数，所有所述存储阵列组均为第二存储阵列组；任意相邻两个第二存储阵列组中，属于不同第二存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用源线。示例性的，如图24所示，第二存储阵列组D1的存储阵列102和第二存储阵列组D2的存储阵列103中相同位置的存储单元共用源线SLtn。
第三种情况：T为大于或等于5的奇数，所有所述存储阵列组均为第一存储阵列组；位于所述第一存储阵列同一侧的任意相邻两个所述第一存储阵列组中，属于不同所述第一存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用位线。示例性的，如图25所示，第一存储阵列组C1和第二存储阵列组C2均第一存储阵列105的上方，第一存储阵列组C1中的存储阵列102和第二存储阵列组C2中的存储阵列103中相同位置的存储单元共用位线BLtn。
第四种情况：T为大于或等于5的奇数，所有所述存储阵列组均为第二存储阵列组；位于所述第一存储阵列同一侧的任意相邻两个所述第二存储阵列组中，属于不同所述第二存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用源线。
第五种情况：T为大于或等于5的奇数，所有所述存储阵列组中包括所述第一存储阵列组和第二存储阵列组；所述第一存储阵列组均位于所述第一存储阵列第一侧，所述第二存储阵列组位于所述第一存储阵列第二侧。示例性的，图22所示，第一存储阵列103的上方设置有一个第一存储阵列组C1，第一存储阵列103的下方设置有一个第二存储阵列组D1，当第一存储阵列103的上方设置有多个第一存储阵列组Cn时，相邻第一存储阵列组Cn之间共用位线可以参考图23，当第一存储阵列103的下方设置有多个第二存储阵列组Dn时，相邻第二存储阵列组Dn之间共用源线可以参考图24。
可以理解的是，在本申请中，当相邻两层存储阵列中相同位置的存储单元共用源线时，该相邻的两层存储阵列中，其中一层存储阵列中存储单元中铁电晶体管的第一电极与另一层存储阵列中存储单元中铁电晶体管的第一电极相对。当相邻两层存储阵列中相同位置的存储单元共用位线时，该相邻的两层存储阵列中，其中一层存储阵列中存储单元中铁电晶体管的第二电极与另一层存储阵列中存储单元中铁电晶体管的第二电极相对。
在本申请，当所有层存储阵列中相同位置的源线均互连时，这样可以减少N×(T-1)条走线。当所有层存储阵列中相同位置的位线均互连时，同样可以减少N×(T-1)条走线。当所有层存储阵列中相同位置的源线均互连，且所有层存储阵列中相同位置的位线均互连时，可以减少2N×(T-1)条走线，从而可以将走线数量尽可能的少。例如图23至图26所示，所有层存储阵列10t中相同位置的源线SLtn均互连，且所有层存储阵列10t中相同位置的位线BLtn均互连。
在具体实施时，当所有层存储阵列中相同位置的位线均互连时，不管相同位置的源线是否互连，存储器中所有层存储阵列中相同位置的字线WLtm均需要相互独立。从而利用字线WLtm选通实现对所有层的存储单元并行写入和读出。例如图27所示，所有层所述存储阵列10t中相同位置的字线WLtm均相互独立，字线WL11通过走线W1与字线控制电路201连接，字线WL21通过走线W2与字线控制电路201连接，字线WL31通过走线W3与字线控制电路201连接，字线WL41通过走线W4与字线控制电路201连接。
在具体实施时，如图10、图12至26所示，各位线BLtn通过与其对应的走线B0与位线控制电路202以及灵敏放大器电路203连接；互连的位线BLtn可以通过同一条走线B0 连接至位线控制电路202以及灵敏放大器电路203，即互连的位线BLtn可以通过与其对应的走线B0实现互连。各源线SLtn通过与其对应的走线S0与源线控制电路204连接。互连的源线SLtn可以通过同一条走线S0连接至源线控制电路204，即互连的源线SLtn可以通过与其对应的走线B0实现互连。
当然，在本申请中，为了减少走线的数量，也可以是不同层存储阵列中相同位置的字线互连。
示例性，如图28所示，本申请中所有层所述存储阵列10t中相同位置的字线WLtm均互连。这种情况需要存储器中所有层存储阵列中相同位置的位线BLtn均相互独立。从而利用位线BLtn选通实现对所有层的存储单元并行写入和读出。
当然，在本申请实施例中，对于存储器中，所有层存储阵列中相同位置的位线不完全互连的情况，可以存在至少两层存储阵列中相同位置的字线互连，只要保证字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连即可。
下面将位线和字线结合在一起，通过具体实施例说明本申请的存储器。
示例一
存储器中，所有层存储阵列中相同位置的位线互连，相同位置的字线均相互独立。
参见图29，在存储器中，相邻层的存储阵列10t相同位置的存储单元共用源线SLtn或位线BLtn，即相邻层的存储阵列具有公共的源线SLtn或位线BLtn。相邻层的存储阵列沿共用位线或源线镜像对称。图23为该存储器中源线和位线与对应的控制电路的连接示意图。图27为该存储器中字线与对应的控制电路的连接示意图。参见图23，各层存储阵列10t相同位置的位线BLtn通过阵列外部的走线B0与通孔相互连接，并连接至同一位线控制电路202和灵敏放大器电路203。各层存储阵列10t相同位置的源线SLtn通过阵列外部的走线S0与通孔相互连接，并连接至同一源线控制电路204。参见图27，各层存储阵列10t的字线WLtm相互独立，并通过与其一一对应的走线Wm连接至具有选通功能的字线控制电路201。
该实施例中，存储器中各层存储阵列共用源线或位线，利用字线选通实现对某单层存储单元并行写入和读出。该实施例的读带宽和写带宽由单层存储阵列决定，不通过多层堆叠拓展读写带宽。由于各层存储阵列的位线连接在一起，多层存储阵列堆叠有可能会加重位线负载，增加单比特存储单元的读延迟。
在该三维存器中，存在T层存储阵列，每一层存储阵列包括N条位线、N条位线、M条字线，T×N条位线需要N条走线连接至位线控制电路和灵敏放大器电路，T×N条源线需要N条走线连接至源线控制电路，T×M条字线需要T×M条走线连接至字线控制电路。与位线连接的走线和与源线连接的走线可分别从位线或源线两端引出，且两端各设置N条走线。与字线连接的走线可分别从字线的两端引出，且两端各设置T×M/2条走线。
在该实施例中，存储器与电路层连接的走线数量最少，版图面积最小。此外，由于相邻层存储阵列共用源线或位线，光罩数量最少，能够降低制造成本。因此，该实施例可以适用于对速度要求低、成本低的存储应用场景。
示例二
存储器中，所有层存储阵列中相同位置的字线互连，相同位置的位线均相互独立。
参见图30，在存储器中，相邻层存储阵列10t以介质层30为隔离，各层存储阵列10t相互独立。图30为该存储器中源线和位线与对应的控制电路的连接示意图。图31为该存 储器中字线与对应的控制电路的连接示意图。参见图31，各层存储阵列10t相同位置的位线BLtn相互独立，并通过与其一一对应的走线B0连接至灵敏放大器电路203和具有选通功能的位线控制电路202，各层存储阵列10t相同位置的源线SLtn相互独立，并通过与其一一对应的走线S0连接至源线控制电路204。参见图28，各层存储阵列10t的字线WLtm通过阵列外部的走线W1与通孔相互连接，并连接至同一字线控制电路201。
该实施例中，存储器中各层存储阵列相同位置的位线以及相同位置的源线均相互独立，利用字线选通实现对所有层的存储单元并行写入和读出。与示例一相比，该实施例可通过三维堆叠有效拓展读带宽和写带宽，读写带宽与堆叠层数成正比。假设单层存储单元的带宽为N，通过T层堆叠可实现读写带宽为T×N。由于各层存储阵列的位线相互独立，多层存储阵列堆叠不会恶化位线的负载，单比特存储单元的读延迟较示例一更小。因此，该存储器可以实现更高的带宽速率。
在该三维存器中，存在T层存储阵列，每一层存储阵列包括N条位线、N条位线、M条字线，T×N条位线需要T×N条走线连接至位线控制电路和灵敏放大器电路，T×N条源线需要T×N条走线连接至源线控制电路，T×M条字线需要M条走线连接至字线控制电路。与位线连接的走线和与源线连接的走线可分别从位线或源线两端引出，且两端各设置T×N条走线。与字线连接的走线可分别从字线的两端引出，且两端各设置M/2条走线。
与示例一相比，走线的数量较多，位线方向和字线方向走线数量分配不均，版图面积较大。由于相邻层存储阵列以介质层隔离，所需光罩数量增加，制造成本更高。因此，该实施例可以适用于对性能要求高的存储应用场景。
示例三
存储器中，将相邻两层存储阵列视为一组存储阵列组，存储阵列组之间相互隔离，存储阵列组共用字线。
对于存储阵列层数T为偶数的情况，参见图15至图17，包括T/2个存储阵列组，同一第一存储阵列组Cn中的两层存储阵列10t共用源线SLtn，且相同位置的位线BLtn互连，同一第二存储阵列组Dn中的两层存储阵列10t共用位线BLtn，且相同位置的源线SLtn互连。参见图33，T/2层存储阵列10t中的相同位置的字线WLtm通过第一走线W1互连，剩余T/2层存储阵列10t中的相同位置的字线WLtm通过第二走线W2互连；且对于属于同一存储阵列组中的两层存储阵列10t，相同位置的字线WLtm中，其中一条字线WLtm与所述第一走线W1连接，另一条字线WLtm与所述第二走线W2连接；第一走线与第二走线绝缘。
示例性的，以图32为例，图15为该存储器中源线和位线与对应的控制电路的连接示意图。图33为该存储器中字线与对应的控制电路的连接示意图。在该存储器中，将相邻两层存储阵列10t视为一组第一存储阵列组Cn，相邻两个存储阵列组Cn之间以介质层30为隔离。同一第一存储阵列组Cn中的两层存储阵列10t共用源线SLtn，且相同位置的位线BLtn通过外部走线和通孔相互连接，第一存储阵列组Cn内两层存储阵列10t的字线WLtm相互独立。不同存储阵列组Cn的位线BLtn和源线SLtn相互独立。各第一存储阵列组Cn内上层存储阵列10t的字线WLtm通过阵列外部的第一走线W1和通孔相互连接，各第一存储阵列组Cn内下层存储阵列10t的字线WLtm通过阵列外部的第二走线W2和通孔相互连接。
该实施例可利用字线WLtm选通实现对多层存储单元进行并行写入和读出。与方案一 相比，该架构可通过三维堆叠拓展读带宽和写带宽，读写带宽与堆叠层数成正比。假设单层存储单元的带宽为N，通过T层堆叠可实现读写带宽为TN/2。由于最多仅两层存储阵列相同位置的位线相互连接，多层存储阵列堆叠不会恶化位线负载，单比特存储单元的读延迟较示例一更小。因此，该存储器可以实现高的带宽速率。
在该三维存器中，存在T层存储阵列，每一层存储阵列包括N条位线、N条位线、M条字线，T×N条位线需要T×N/2条走线连接至位线控制电路和灵敏放大器电路，T×N条源线需要T×N/2条走线连接至源线控制电路，T×M条字线需要2M条走线连接至字线控制电路。与位线连接的走线和与源线连接的走线可分别从位线或源线两端引出，且两端各设置T×N/2条走线。与字线连接的走线可分别从字线的两端引出，且两端各设置M条走线。
对于存储阵列层数T为奇数的情况，参见图18至图22，包括T/2个存储阵列组和一层第一存储阵列，同一第一存储阵列组Cn中的两层存储阵列10t共用源线SLtn，且相同位置的位线BLtn互连，同一第二存储阵列组Dn中的两层存储阵列10t共用位线BLtn，且相同位置的源线SLtn互连。(T+1)/2层存储阵列中的相同位置的字线通过第一走线互连，剩余(T-1)/2层存储阵列中的相同位置的字线通过第二走线互连；且对于属于同一存储阵列组中的两层存储阵列，相同位置的字线中，其中一条字线与所述第一走线连接，另一条字线与所述第二走线连接；第一走线与第二走线绝缘。
示例性的，以图34为例，图18为该存储器中源线和位线与对应的控制电路的连接示意图。图35为该存储器中字线与对应的控制电路的连接示意图。在该存储器中，将相邻两层存储阵列10t视为一组存储阵列组Cn或Dn，相邻两个存储阵列组之间、以及存储阵列组与第一存储阵列103之间以介质层30为隔离。同一第一存储阵列组Cn中的两层存储阵列10t共用源线SLtn，且相同位置的位线BLtn通过外部走线和通孔相互连接，第一存储阵列组Cn内两层存储阵列10t的字线WLtm相互独立。同一第二存储阵列组Dn中的两层存储阵列10t共用位线BLtn，且相同位置的源线SLtn通过外部走线和通孔相互连接，第二存储阵列组Dn内两层存储阵列10t的字线WLtm相互独立。不同存储阵列组的位线BLtn和源线SLtn相互独立。各存储阵列组内上层存储阵列10t的字线WLtm通过阵列外部的第一走线W1和通孔相互连接，各存储阵列组内下层存储阵列10t的字线WLtm通过阵列外部的第二走线W2和通孔相互连接。第一存储阵列103的字线WLtm可以与第一走线W1连接，当然也可以与第二走线W2连接。
该实施例可利用字线WLtm选通实现对多层存储单元进行并行写入和读出。与方案一相比，该架构可通过三维堆叠拓展读带宽和写带宽，读写带宽与堆叠层数成正比。假设单层存储单元的带宽为N，通过T层堆叠可实现读写带宽为(T+1)N/2。由于最多仅两层存储阵列相同位置的位线相互连接，多层存储阵列堆叠不会恶化位线负载，单比特存储单元的读延迟较示例一更小。因此，该存储器可以实现高的带宽速率。
在该存储器中，存在T层存储阵列，每一层存储阵列包括N条位线、N条位线、M条字线，T×N条位线需要(T+1)N/2条走线连接至位线控制电路和灵敏放大器电路，T×N条源线需要(T+1)N/2条走线连接至源线控制电路，T×M条字线需要2M条走线连接至字线控制电路。与位线连接的走线和与源线连接的走线可分别从位线或源线两端引出，且两端各设置(T+1)N/2条走线。与字线连接的走线可分别从字线的两端引出，且两端各设置M条走线。
与示例一相比，走线的数量可与示例一比拟，位线方向和字线方向走线数量分配均匀，版图实现简单。存储阵列组之间以介质层隔离，与示例二相比，光罩数量有所降低，制造成本可控。
因此，该实施例可降低存储器的走线数量，降低版图面积开销。且制造所需光罩数量较少，制造成本较低。另外，可通过三维堆叠实现存储阵列读带宽和写带宽的增加，同时不造成单比特读延迟的严重恶化，可实现高的总带宽速率。因此，该实施例适用于低成本、高性能的应用场景。
综上，如果想要降低存储器的成本，将存储器中相邻层存储阵列共用源线或位线，且相同位置的字线相互独立。如果要实现存储阵列读带宽和写带宽的增加，同时不造成单比特存储单元读延迟的恶化，实现高的总带宽速率，存储器中不同层存储阵列的源线和位线均独立，所有层存储阵列中相同位置的字线互连。如果既要实现低成本，又要实现存储阵列读带宽和写带宽的增加，则在存储器中，仅部分邻层存储阵列共用源线或位线，部分层存储阵列中相同位置的字线互连。共用源线或位线的层数，字线互连的存储阵列的层数具体可以根据成本和带宽速率的要求进行设计。
基于同一技术构思，本申请实施例还提供一种电子设备。参见图36该电子设备包括处理器1001以及与处理器1001耦合的存储器1002，存储器1002可以是图1所示的存储器。具体地，处理器1001可以调用存储器1002中存储的软件程序，以执行相应的方法，实现电子设备的相应功能。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (15)

  1. 一种存储器，其特征在于，包括堆叠的多层存储阵列，
    所述多层存储阵列中的每一层存储阵列包括：
    矩阵排列的多个存储单元，所述存储单元包括铁电晶体管；
    与每一行所述存储单元中的铁电晶体管的第一电极连接的源线；
    与每一行所述存储单元中的铁电晶体管的第二电极连接的位线；
    与每一列所述存储单元中的铁电晶体管的栅电极连接的字线；
    所述多层存储阵列中至少两层所述存储阵列中相同位置的源线互连；和/或
    所述多层存储阵列中至少两层所述存储阵列中相同位置的位线互连，且位线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的字线不互连；和/或
    所述多层存储阵列中至少两层所述存储阵列中相同位置的字线互连，且字线互连的所述至少两层存储阵列中，位置相同的存储单元所连接的位线不互连。
  2. 如权利要求1所述的存储器，其特征在于，所述铁电晶体管包括：半导体柱，由内向外依次围绕所述半导体柱设置的氧化物层、浮置金属层、铁电材料层和栅电极；所述半导体柱的一端为所述铁电晶体管的第一电极，所述半导体柱的另一端为所述铁电晶体管的第二电极；
    所述半导体柱的延伸方向与所述多层存储阵列的堆叠方向相同。
  3. 如权利要求2所述的存储器，其特征在于，以相邻的两层存储阵列为一第一存储阵列组或一第二存储阵列组，所述存储器包括至少一个所述第一存储阵列组和/或至少一个所述第二存储阵列组，且一层存储阵列仅属于一个所述存储阵列组；
    所述第一存储阵列组中的两层存储阵列中，其中一层存储阵列中存储单元中铁电晶体管的第一电极与另一层存储阵列中存储单元中铁电晶体管的第一电极相对，且属于同一所述第一存储阵列组中的两层存储阵列中相同位置的存储单元共用源线；
    所述第二存储阵列组中的两层存储阵列中，其中一层存储阵列中存储单元中铁电晶体管的第二电极与另一层存储阵列中存储单元中铁电晶体管的第二电极相对，且属于同一所述第二存储阵列组中的两层存储阵列中相同位置的存储单元共用位线。
  4. 如权利要求3所述的存储器，其特征在于，属于同一所述第一存储阵列组中的两层存储阵列中相同位置的位线互连；和/或
    属于同一所述第二存储阵列组中的两层存储阵列中相同位置的源线互连。
  5. 如权利要求3或4所述的存储器，其特征在于，所述存储器包括T层存储阵列，T为大于或等于4的偶数，所述T层存储阵列包括T/2个所述存储阵列组；
    所有所述存储阵列组均为第一存储阵列组或均为第二存储阵列组。
  6. 如权利要求3或4所述的存储器，其特征在于，所述存储器包括T层存储阵列，T为大于或等于3的奇数，所述T层存储阵列包括(T-1)/2个所述存储阵列组和一层第一 存储阵列，其中所述第一存储阵列不属于任一所述存储阵列组；
    所述存储阵列组均位于所述第一存储阵列的同一侧，或所述第一存储阵列的两侧均设置有所述存储阵列组。
  7. 如权利要求6所述的存储器，其特征在于，所述存储阵列组均位于所述第一存储阵列的同一侧，且与所述第一存储阵列相邻的存储阵列组为所述第一存储阵列组；所述第一存储阵列和与其相邻的所述存储阵列中相同位置的存储单元共用位线；或
    所述存储阵列组均位于所述第一存储阵列的同一侧，且与所述第一存储阵列相邻的存储阵列组为所述第二存储阵列组；所述第一存储阵列和与其相邻的所述存储阵列中相同位置的存储单元共用源线；或
    所述第一存储阵列的两侧均设置有所述存储阵列组，且与所述第一存储阵列相邻的存储阵列组均为所述第一存储阵列组；所述第一存储阵列和与其相邻的其中一层所述存储阵列中相同位置的存储单元共用位线；或
    所述第一存储阵列的两侧均设置有所述存储阵列组，且与所述第一存储阵列相邻的存储阵列组均为所述第二存储阵列组；所述第一存储阵列和与其相邻的其中一层所述存储阵列中相同位置的存储单元共用源线；或
    所述第一存储阵列的两侧均设置有所述存储阵列组，且与所述第一存储阵列相邻的存储阵列组分别为所述第一存储阵列组和所述第二存储阵列组；与所述第一存储阵列的所述第一存储阵列组中，与所述第一存储阵列相邻的一层存储阵列，以及所述第一存储阵列中相同位置的存储单元共用位线；与所述第一存储阵列的所述第二存储阵列组中，与所述第一存储阵列相邻的一层存储阵列，以及所述第一存储阵列中相同位置的存储单元共用源线。
  8. 如权利要求7所述的存储器，其特征在于，T为大于或等于5的奇数；
    所有所述存储阵列组均为第一存储阵列组；或
    所有所述存储阵列组均为第二存储阵列组；或
    所有所述存储阵列组中包括所述第一存储阵列组和第二存储阵列组；所有所述第一存储阵列组均位于所述第一存储阵列的第一侧，所有所述第二存储阵列组位于所述第一存储阵列的第二侧。
  9. 如权利要求4-8任一项所述的存储器，其特征在于，任意相邻两个所述第一存储阵列组中，属于不同所述第一存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用位线；和/或
    任意相邻两个第二存储阵列组中，属于不同所述第二存储阵列组中的相邻的两层存储阵列中相同位置的存储单元共用源线。
  10. 如权利要求1-9任一项所述的存储器，其特征在于，所有层存储阵列中相同位置的源线均互连，和/或所有层存储阵列中相同位置的位线均互连。
  11. 如权利要求5所述的存储器，其特征在于，T/2层存储阵列中的相同位置的字线通过第一走线互连，剩余T/2层存储阵列中的相同位置的字线通过第二走线互连；
    且对于属于同一存储阵列组中的两层存储阵列，相同位置的字线中，其中一条字线与所述第一走线连接，另一条字线与所述第二走线连接。
  12. 如权利要求6-8任一项所述的存储器，其特征在于，(T+1)/2层存储阵列中的相同位置的字线通过第一走线互连，剩余(T-1)/2层存储阵列中的相同位置的字线通过第二走线互连；
    且对于属于同一存储阵列组中的两层存储阵列，相同位置的字线中，其中一条字线与所述第一走线连接，另一条字线与所述第二走线连接。
  13. 如权利要求1或2所述的存储器，其特征在于，所述多层存储阵列中所有层所述存储阵列中相同位置的字线均互连。
  14. 如权利要求1-13任一项所述的存储器，其特征在于，还包括电路层，其中所述电路层包括：与各所述字线连接的字线控制电路，与各所述位线连接的位线控制电路和灵敏放大器电路，与各所述源线连接的源线控制电路；
    所述堆叠的多层存储阵列位于电路层的上方。
  15. 一种电子设备，其特征在于，包括处理器，以及与所述处理器耦合的、如权利要求1-14任一项所述的存储器。
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CN105308751A (zh) * 2013-05-17 2016-02-03 美光科技公司 具有铁电场效应晶体管存储器阵列的设备及相关方法
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CN110462740A (zh) * 2017-03-27 2019-11-15 美光科技公司 用于多层存储器阵列的多板线架构
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CN104380382A (zh) * 2012-03-26 2015-02-25 英特尔公司 三维存储器控制电路
CN105308751A (zh) * 2013-05-17 2016-02-03 美光科技公司 具有铁电场效应晶体管存储器阵列的设备及相关方法
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