WO2023137642A1 - 铁电存储器及其制造方法 - Google Patents

铁电存储器及其制造方法 Download PDF

Info

Publication number
WO2023137642A1
WO2023137642A1 PCT/CN2022/072830 CN2022072830W WO2023137642A1 WO 2023137642 A1 WO2023137642 A1 WO 2023137642A1 CN 2022072830 W CN2022072830 W CN 2022072830W WO 2023137642 A1 WO2023137642 A1 WO 2023137642A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
electrodes
ferroelectric memory
ferroelectric
terminal
Prior art date
Application number
PCT/CN2022/072830
Other languages
English (en)
French (fr)
Inventor
张恒
张禹
张敏
宋伟基
许俊豪
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2022/072830 priority Critical patent/WO2023137642A1/zh
Priority to CN202280004455.3A priority patent/CN116802734A/zh
Publication of WO2023137642A1 publication Critical patent/WO2023137642A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

Definitions

  • Embodiments of the present disclosure relate generally to memories, and more particularly to ferroelectric memories and methods of manufacturing the same.
  • Ferroelectric memory is a new type of random access memory, which can simultaneously have random access capability and power-off data guarantee capability of non-volatile memory.
  • ferroelectric memories generally include planar ferroelectric capacitors.
  • a ferroelectric capacitor typically includes a bottom electrode, a top electrode, and a ferroelectric layer positioned between the bottom electrode and the top electrode to form a sandwich structure.
  • the ferroelectric layer in the ferroelectric capacitor can have different polarization directions under positive and negative operating voltages, and the upper polarization direction and the lower polarization direction can represent 0 and 1 of stored data, respectively.
  • a read voltage is applied to the ferroelectric capacitor, and whether the ferroelectric layer is reversed is detected under the read voltage.
  • the ferroelectric layer is reversed, there will be charge inflow on the ferroelectric capacitor, and the sensitive amplifier will be used to amplify and sense the charge flow, and then judge the storage state.
  • the capacitance value of the ferroelectric capacitor is required to be large enough, so that when the data stored in the ferroelectric capacitor is read, the ferroelectric layer is reversed so that enough ferroelectric flipping charges flow through, thereby achieving a large enough storage window.
  • the area occupied by each bit cell ferroelectric capacitor is too large, which hinders the improvement of the storage density of ferroelectric memory.
  • Embodiments of the present disclosure provide a ferroelectric memory capable of increasing storage density and a manufacturing method thereof.
  • a ferroelectric memory includes a first electrode in the shape of a fin, and the first electrode extends along a first horizontal direction.
  • the second electrode at least partially covers the first sidewall of the first electrode and the second sidewall opposite to the first sidewall.
  • the ferroelectric layer is located between the first electrode and the second electrode.
  • the ferroelectric memory includes vertically arranged ferroelectric memory cells, so that the ferroelectric capacitance of the ferroelectric memory cells can expand in the vertical space. Therefore, on the plane, it can be reduced by advanced technology, so that the area on the chip occupied by the bit unit can be reduced, the storage density can be improved, and the cost of the storage chip can be reduced.
  • the vertical ferroelectric capacitor is formed on the sidewall of the first electrode, the area of the vertical ferroelectric capacitor will not be greatly reduced when the occupied area of the bit cell is compressed on a plane in an advanced process.
  • the large ferroelectric capacitor area can ensure that the window when the device is read is large enough.
  • the fin structure enables the ferroelectric capacitor on the first electrode to form a whole memory unit, so the effective ferroelectric area is further enlarged.
  • the ferroelectric memory further includes a first dielectric layer in the shape of a fin, the first dielectric layer extends along the first horizontal direction, and the first dielectric layer is located above the first electrode.
  • the ferroelectric memory further includes a second dielectric layer in the shape of a fin, the second dielectric layer extends along the first horizontal direction, and the second dielectric layer is located under the first electrode.
  • the first electrode is in contact with the ferroelectric layer.
  • the first electrode further includes a top wall located between the first side wall and the second side wall, and the second electrode also covers the top wall of the first electrode.
  • the ferroelectric memory further includes a first transistor, and the first transistor includes a first terminal, a second terminal and a control terminal.
  • the first terminal of the first transistor is coupled to the first electrode
  • the second terminal of the first transistor is coupled to the source line
  • the control terminal of the first transistor is coupled to the control signal line.
  • the ferroelectric memory further includes a second transistor, and the second transistor includes a first terminal, a second terminal and a control terminal.
  • the control terminal of the second transistor is coupled to the first electrode, the first terminal of the second transistor is coupled to the bit line, and the second terminal of the second transistor is coupled to the source line.
  • the first electrode is coupled to a word line.
  • the ferroelectric memory includes a plurality of first electrodes in fin form, each first electrode of the plurality of first electrodes extending along a first horizontal direction and spaced apart along a second horizontal direction perpendicular to the first horizontal direction.
  • Each of the plurality of second electrodes extends along a second horizontal direction and at least partially covers a first sidewall of the plurality of first electrodes and a second sidewall opposite to the first sidewall.
  • the plurality of second electrodes are spaced apart along the first horizontal direction.
  • Each ferroelectric layer of the plurality of ferroelectric layers is located between a corresponding first electrode of the plurality of first electrodes and a corresponding second electrode of the plurality of second electrodes.
  • An array of ferroelectric memory cells is formed by extending a plurality of fins in the horizontal direction, thereby increasing the storage capacity of the ferroelectric memory.
  • the ferroelectric memory further includes a first transistor including a first terminal, a second terminal and a control terminal.
  • a first terminal of the first transistor is coupled to each of the plurality of first electrodes, a second terminal of the first transistor is coupled to a source line, and a control terminal of the first transistor is coupled to a control signal line.
  • the second transistor includes a first terminal, a second terminal and a control terminal, the control terminal of the second transistor is coupled to each of the plurality of first electrodes, the first terminal of the second transistor is coupled to the bit line, and the second terminal of the second transistor is coupled to the source line.
  • each first electrode of the plurality of first electrodes is coupled to a corresponding word line.
  • each second electrode of the plurality of second electrodes is continuous or discontinuous between the plurality of first electrodes along the second horizontal direction.
  • the ferroelectric memory includes a plurality of first electrodes in the form of fins, each of the plurality of first electrodes is separated from each other by a dielectric layer along a vertical direction, and each of the plurality of first electrodes extends along a first horizontal direction.
  • Vertically integrated ferroelectric memories can be implemented by stacking and expanding vertically, which further increases storage density, and the implementation process of this vertically integrated manner is simpler.
  • the ferroelectric memory includes a plurality of first electrodes in the form of fins, each of the plurality of first electrodes extends along a first horizontal direction, wherein the plurality of first electrodes includes a plurality of groups of first electrodes extending along a second horizontal direction perpendicular to the first horizontal direction, and the first electrodes in each group of first electrodes are separated from each other by a dielectric layer along the vertical direction.
  • each first electrode of the plurality of first electrodes is electrically connected to a corresponding contact hole.
  • an apparatus includes a printed circuit board, and further includes a ferroelectric memory according to the first aspect of the present disclosure, wherein the ferroelectric memory is provided on the printed circuit board.
  • a method for manufacturing a ferroelectric memory In the method, a first electrode layer is formed; the first electrode layer is etched to form a plurality of first electrodes in fin form, and the plurality of first electrodes extend along a first horizontal direction; a ferroelectric layer is deposited to fill a plurality of first trenches between the plurality of first electrodes; the ferroelectric layer is etched to form a plurality of second trenches, and the plurality of second trenches extend along a second horizontal direction perpendicular to the first horizontal direction; and the second electrode layer is deposited to form second electrodes in the plurality of second trenches.
  • forming the first electrode layer includes forming a plurality of first electrode layers spaced apart from each other by a dielectric layer, and wherein the method further includes forming contact holes for respective first electrodes.
  • Figure 1A shows a schematic diagram of a device according to some embodiments of the present disclosure.
  • FIG. 1B shows a schematic diagram of a ferroelectric memory according to some embodiments of the present disclosure.
  • Figure 2 shows a schematic diagram of a memory array according to some embodiments of the present disclosure.
  • Figure 3 shows a perspective view of a ferroelectric memory cell according to some embodiments of the present disclosure.
  • FIG. 4 illustrates a cross-sectional view of a ferroelectric memory cell according to some embodiments of the disclosure.
  • Figure 5 shows a circuit diagram of a ferroelectric memory cell according to some embodiments of the present disclosure.
  • FIG. 6 shows a perspective view of a ferroelectric memory according to some embodiments of the present disclosure.
  • FIG. 7 shows a circuit diagram of a ferroelectric memory according to some embodiments of the present disclosure.
  • FIG. 8 shows a perspective view of a ferroelectric memory according to some embodiments of the present disclosure.
  • FIG. 9A-14C illustrate a method for fabricating a ferroelectric memory as shown in FIG. 8 according to some embodiments of the present disclosure.
  • Figure 15 shows a schematic diagram of a ferroelectric memory cell according to some embodiments of the present disclosure.
  • Figure 16 shows a schematic diagram of a ferroelectric memory according to some embodiments of the present disclosure.
  • Figure 17 shows a schematic diagram of a ferroelectric memory according to some embodiments of the present disclosure.
  • Figure 18 shows a schematic diagram of a ferroelectric memory according to some embodiments of the present disclosure.
  • 19-27G illustrate a method for fabricating a ferroelectric memory as shown in FIG. 18 according to some embodiments of the present disclosure.
  • the term “comprising” and its similar expressions should be interpreted as an open inclusion, that is, “including but not limited to”.
  • the term “based on” should be understood as “based at least in part on”.
  • the term “one embodiment” or “the embodiment” should be read as “at least one embodiment”.
  • the terms “first”, “second”, etc. may refer to different or the same object.
  • the term “and/or” means at least one of the two items associated with it.
  • the term “coupled” may indicate a direct connection between one component and another component, and may also include an indirect connection via other components.
  • a and/or B means A, B, or A and B.
  • Other definitions, both express and implied, may also be included below.
  • FIG. 1A shows a schematic diagram of a device 100 according to some embodiments of the present disclosure.
  • device 100 may include electronic devices such as computers, servers, laptops, desktop computers, mobile phones, cellular phones, personal digital assistants, wearable devices, or set-top boxes, and may be used in applications such as self-driving cars.
  • the device 100 may include a processor 102, which may perform various appropriate actions and processes according to computer program instructions.
  • processor 102 may include a cache (not shown) for caching computer program instructions and/or data.
  • various programs and data necessary for the operation of the device 100 can be stored.
  • Memory 104 may also store instructions executed by processor 102 during operation of device 100 and may store user data.
  • Processor 102 and memory 104 are connected to each other by bus 108 for communication.
  • device 100 also includes storage 106 in communication with bus 108 , which may be used to store various data as well as computer program instructions, which may be loaded into memory 104 for execution by processor 102 .
  • the device 100 may further include an input/output (Input/Output, I/O) device 110 (eg, a keyboard, a display), etc. in communication with the bus 108 .
  • I/O input/output
  • the device 100 may further include a transceiver 112, which may be connected to an antenna (not shown) for receiving and transmitting wireless signals. It should be understood that the scope of the present disclosure is not limited to embodiments having any or all of these components.
  • the storage device 106 is usually implemented by a non-volatile memory such as a magnetic disk and/or a solid state disk.
  • Ferroelectric memory is a new type of non-volatile memory technology that can be used to implement memory device 106 .
  • the cache in the processor 102 is usually implemented by a static random access memory (Static Random Access Memory, SRAM), wherein the SRAM is a volatile memory.
  • the memory 104 is usually implemented by a dynamic random access memory (Dynamic Random Access Memory, DRAM), wherein the DRAM is also a volatile memory.
  • DRAM dynamic random access memory
  • ferroelectric memory may also be used to implement memory 104 , and may even be used to implement a cache in processor 102 . It should be understood that the architecture of the device 100 of FIG. 1A is provided as an example only, and that in addition to the architecture of the device 100 , ferroelectric memory or ferroelectric memory cells may also be used in other scenarios or architectures.
  • FIG. 1B shows a schematic diagram of a ferroelectric memory 120 according to some embodiments of the present disclosure.
  • the ferroelectric memory 120 may be applied to the cache, the memory 104 and/or the storage device 106 in the processor 102 as shown in FIG. 1A .
  • the ferroelectric memory 120 may be disposed on a printed circuit board (Printed Circuit Board, PCB).
  • PCB printed Circuit Board
  • the ferroelectric memory 120 includes a storage array 121 , and the storage array 121 includes an array of bit cells, and the bit cells include ferroelectric memory cells and switches such as transistors.
  • the ferroelectric memory 120 also includes a row decoder 122 and a column decoder 123 that receive address signals from the controller 124 and select bit cells in the memory array 121 based on the address signals received from the controller 124.
  • the controller 124 generates an address signal AS, and controls the row decoder 122 and the column decoder 123 to read and write a bit cell addressed by the address signal.
  • the row decoder 122 and the column decoder 123 can bias the word line WL and the bit line BL, and select the corresponding word line WL and bit line BL, and then select the bit cells connected thereto. In this way, reading and writing to selected bit cells can be accomplished.
  • a read current flows through the ferroelectric memory cells of the bitcell, respectively.
  • the column decoder 123 electrically connects each selected bit line BL to the read stage 125 to perform a read operation.
  • read stage 125 may include circuits such as sense amplifiers.
  • a sense amplifier stage may compare the read current in a selected bit cell to a reference current to determine the data value stored in that bit cell.
  • the column decoder 123 may electrically connect each selected bit line BL to the writing stage 126 to perform a writing operation.
  • Write stage 126 may provide a write current.
  • FIG. 2 shows a schematic diagram of a memory array 200 according to some embodiments of the present disclosure.
  • the storage array 200 can be used to implement the storage array 121 as shown in FIG. 1B .
  • memory array 200 includes an array of bit cells 204 , where each bit cell 204 includes a ferroelectric memory cell 202 and a transistor 212 .
  • the transistor 212 may be realized by a metal oxide field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) and other transistors.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the gate of transistor 212 is coupled to word line 208 , which may be connected to row decoder 122 as shown in FIG. 1B .
  • a first terminal (eg, source) of transistor 212 is coupled to source line 210 , where source line 210 may be grounded.
  • a second terminal (eg, drain) of transistor 212 is coupled to ferroelectric memory cell 202 .
  • the ferroelectric memory cell 202 is further coupled to a bit line 206, wherein the bit line 206 may be connected to the column decoder 123 as shown in FIG. 1B.
  • FIG. 2 is only provided as a schematic circuit diagram and does not imply a physical arrangement of word lines, bit lines and source lines.
  • bit line 206 and source line 210 may be parallel to each other and perpendicular to word line 208 .
  • FIG. 2 shows an example configuration of the storage array 200, however, it should be understood that the storage array 200 may also have other suitable configurations.
  • FIG. 3-4 illustrate a ferroelectric memory cell 300 according to some embodiments of the present disclosure, wherein FIG. 3 is a perspective view of the ferroelectric memory cell 300 and FIG. 4 is a cross-sectional view of the ferroelectric memory cell 300 of FIG. 3 along the yz plane.
  • the ferroelectric memory cell 300 in FIGS. 3-4 is formed over a substrate (not shown), where the substrate extends in the xy plane.
  • the ferroelectric memory cell 300 includes a fin 320 extending along the x-axis direction (also referred to as the first horizontal direction).
  • the fin 320 includes a first electrode 322, a dielectric layer 324 above the first electrode 322, and a dielectric layer 326 below the first electrode 322.
  • the first electrode 322, the dielectric layer 324, and the dielectric layer 326 all present a fin shape.
  • the first element above the second element means that the first element is on the side of the second element away from the substrate, and the first element below the second element means that the first element is on the side of the second element close to the substrate.
  • the dielectric layer 324, the first electrode 322 and the dielectric layer 326 form a sandwich structure.
  • the first electrode 322 may include tungsten, TiN or other metals, and may also include heavily doped polysilicon.
  • dielectric layer 324 and dielectric layer 326 may be SiO 2 , SiNx or other dielectric materials.
  • the second electrode 360 at least partially covers the first sidewall and the second sidewall opposite to the first sidewall of the fin 320 , and the ferroelectric layer 340 is located between the fin 320 and the second electrode 360 . Sidewalls represent surfaces at a non-zero angle to the substrate, ie, surfaces at a non-zero angle to the xy plane.
  • the sidewalls are perpendicular to the xy plane, however, this is only provided as an example, and the sidewalls may also form other non-zero angles with the xy plane.
  • the ferroelectric layer 340 covers at least a portion of the fin 320 , eg, the ferroelectric layer 340 may cover at least a portion of the top and side walls of the fin 320 .
  • the ferroelectric layer 340 may at least partially cover the first sidewall and the second sidewall opposite to the first sidewall of the fin 320 .
  • the ferroelectric layer 340 may include a ferroelectric material such as hafnium zirconium oxide (HfZrO, HfLaOx and/or HfZrLaOx).
  • the second electrode 360 covers at least a portion of the ferroelectric layer 340 , eg, covers the top and side walls of the ferroelectric layer 340 .
  • the second electrode 360 may include metals such as TiN and/or W, or heavily doped polysilicon.
  • the second electrode 360 may include a stack of TiN and W.
  • ferroelectric capacitors are formed on both sides of the first electrode 322 in a symmetrical vertical distribution.
  • Two symmetrical vertical ferroelectric capacitors form an operating unit of the ferroelectric memory.
  • the ferroelectric capacitors are arranged vertically, so that the chip area occupied by the ferroelectric memory is greatly reduced.
  • two symmetrical ferroelectric capacitors constitute a bit unit, which enlarges the effective ferroelectric area.
  • the height of the fin structure can be extended vertically according to the process capability, so that the effective area of the ferroelectric capacitor can be further increased without increasing the occupied chip area, thereby expanding the storage window.
  • FIG. 5 shows a circuit diagram of a ferroelectric memory cell 300 according to some embodiments of the present disclosure.
  • the ferroelectric memory cell 300 includes a top electrode TE and a bottom electrode BE, wherein the top electrode TE corresponds to the second electrode 360 in FIGS. 3-4 , and the bottom electrode BE corresponds to the first electrode 322 in FIGS. 3-4 .
  • the bottom electrode BE of the ferroelectric memory cell 300 is connected to the gate terminal G2 of the transistor T2, the drain terminal D2 of the transistor T2 is connected to the bit line BL, and the source terminal S2 of the transistor T2 is connected to the source line SL.
  • the drain terminal D1 of the transistor T1 is connected to the bottom electrode BE, the source terminal S1 of the transistor T1 is connected to the source line SL, and the gate terminal G1 of the transistor T1 is connected to the control signal line CNTL.
  • the top electrode TE of the ferroelectric memory cell 300 is connected to the word line WL. It should be understood that although FIG. 5 uses the source, drain and gate of the transistor as an example for description, however, other suitable switches can also be used for the transistors T1 and T2, wherein the control terminal, the first terminal and the second terminal of the switch can replace the gate, drain and source respectively.
  • the transistor T1 is turned on by the control signal on the control signal line CNTL, and a write operation pulse is applied between the word line WL and the source line SL.
  • the pulse polarizes the ferroelectric capacitor in the ferroelectric memory cell 300 to implement data writing.
  • destructive reads can be used.
  • Transistor T1 is turned off by a control signal on control signal line CNTL, and a read voltage pulse is applied between word line WL and source line SL.
  • the ferroelectric capacitor in the ferroelectric memory unit 300 reverses under the read pulse, releases the corresponding charge, and changes the conduction state of the transistor T2. Apply a small voltage on the bit line BL to detect the current flowing through the transistor T2, and then read the original written state. After reading, write back the original stored state.
  • FIG. 6 shows a perspective view of a ferroelectric memory 301 according to some embodiments of the present disclosure.
  • the ferroelectric memory 301 includes a fin 320 extending along the x-axis direction, wherein the fin 320 includes a first electrode 322 , a dielectric layer 324 formed above the first electrode 322 , and a dielectric layer 326 formed below the first electrode 322 .
  • a plurality of ferroelectric layers 340 spaced apart from each other along the x-axis direction are formed on the fin 320 , wherein respective second electrodes 340 are respectively formed on the plurality of ferroelectric layers 340 , thereby forming a plurality of ferroelectric memory cells 300 . It should be understood that although FIG.
  • FIG. 6 only shows two ferroelectric memory cells 300 , this is only provided as an example, and more ferroelectric memory cells 300 may be arranged along the x-axis direction.
  • the ferroelectric memory cell 300 shown in FIGS. 3 and 4 is further expanded along the x-axis direction to form the ferroelectric memory 301 of FIG. 6 .
  • FIG. 7 shows a circuit diagram of a ferroelectric memory 301 according to some embodiments of the present disclosure.
  • Fig. 7 shows three ferroelectric memory cells 300-1, 300-2 and 300-3 (collectively referred to as ferroelectric memory cells 300), it should be understood that ferroelectric memory 301 may also include more or less ferroelectric memory cells.
  • each ferroelectric memory cell 300 includes a top electrode TE and a bottom electrode BE, wherein the top electrode TE corresponds to the second electrode 360 in FIG. 6 , and the bottom electrode BE corresponds to the first electrode 322 in FIG. 6 .
  • FIG. 7 shows a circuit diagram of a ferroelectric memory 301 according to some embodiments of the present disclosure.
  • Fig. 7 shows three ferroelectric memory cells 300-1, 300-2 and 300-3 (collectively referred to as ferroelectric memory cells 300), it should be understood that ferroelectric memory 301 may also include more or less ferroelectric memory cells.
  • each ferroelectric memory cell 300 includes a top electrode TE and a bottom
  • the first electrodes 322 of the plurality of ferroelectric memory cells 300 are formed in one fin, thus connecting the bottom electrodes BE of the plurality of ferroelectric memory cells 300 to each other.
  • the bottom electrodes BE of the plurality of ferroelectric memory cells 300 are also connected to the gate terminal G2 of the transistor T2, the drain terminal D2 of the transistor T2 is connected to the bit line BL, and the source terminal S2 of the transistor T2 is connected to the source line SL.
  • the drain terminal D1 of the transistor T1 is connected to the bottom electrode BE, the source terminal S1 of the transistor T1 is connected to the source line SL, and the gate terminal G1 of the transistor T1 is connected to the control signal line CNTL.
  • Top electrodes TE of the ferroelectric memory cells 300-1, 300-2, and 300-3 are connected to respective word lines WL1, WL2, and WL3, respectively.
  • the transistor T1 when performing a write operation on the ferroelectric memory cell 300-1, the transistor T1 is turned on by the control signal on the control signal line CNTL, and a write operation pulse is applied between the word line WL1 and the source line SL. The pulse polarizes the ferroelectric capacitor in the corresponding ferroelectric memory cell 300-1, enabling data writing.
  • a read operation on ferroelectric memory cell 300-1 destructive read may be employed.
  • the transistor T1 is turned off by a control signal on the control signal line CNTL, and a read voltage pulse is applied between the word line WL1 and the source line SL.
  • FIG. 8 shows a perspective view of a ferroelectric memory 301 according to some embodiments of the present disclosure.
  • the ferroelectric memory 301 includes a plurality of fins 320 , wherein each fin 320 extends along the x-axis direction and is spaced apart from each other along the y-axis direction (also referred to as the second horizontal direction).
  • Each fin 320 includes a first electrode 322 , a dielectric layer 324 formed above the first electrode 322 , and a dielectric layer 326 formed below the first electrode 322 . It should be understood that although only three fins 320 are shown in FIG. 7 , more fins 320 may be arranged along the y-axis direction.
  • the ferroelectric memory 301 shown in FIG. 8 is further expanded along the y-axis direction to form a plurality of fins 320 .
  • the second electrode 360 vertically intersects the first electrode 322 to form a crossbar structure.
  • a ferroelectric layer 340 is formed on each of the fins 320, and a second electrode 360 is formed on the ferroelectric layer 340 and connects the ferroelectric layers 340 to each other.
  • Each second electrode 360 is connected to a bit line WL, and each first electrode 322 may be connected to a bit line BL, thereby forming a memory array.
  • the second electrode 360 is continuous between the plurality of fins 320, connecting different fins together.
  • the second electrode 360 may be discontinuous between the plurality of fins 320 , ie, disconnected between different fins 320 .
  • the second electrodes 360 between different fins may be connected by other wires.
  • FIGS. 9A-14C illustrate a method for fabricating the ferroelectric memory 301 as shown in FIG. 8 according to some embodiments of the present disclosure.
  • a dielectric layer 428 , a first electrode layer 427 and a dielectric layer 426 are sequentially formed on a substrate (not shown) to form a sandwich structure.
  • Fig. 9A is a top view of the sandwich structure
  • Fig. 9B is a cross-sectional view taken along the dotted line B-B' shown in Fig. 9A.
  • dielectric layer 428 and/or dielectric layer 426 may be a dielectric material such as silicon oxide.
  • the first electrode layer 427 may be a metal layer or heavily doped polysilicon.
  • FIGS. 10A-10B etch along the x-axis direction to form a plurality of fins 420 .
  • the plurality of fins 420 extend along the x-axis direction and are spaced apart along the y-axis direction.
  • FIG. 10A is a top view of the ferroelectric memory
  • FIG. 10B is a cross-sectional view taken along the dotted line B-B' shown in FIG. 10A.
  • etching is performed by photolithography and non-selective etching processes.
  • the dielectric layer 430 is filled.
  • FIG. 11A is a top view of the ferroelectric memory
  • FIG. 11B is a cross-sectional view taken along the dotted line B-B' shown in FIG. 11A.
  • the dielectric layer 430 may be filled by a chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
  • CVD Chemical Vapor Deposition
  • dielectric layer 430 may be a low-k dielectric layer.
  • the dielectric layer 430 is etched along the y-axis direction to form trenches.
  • 12A is a top view of the ferroelectric memory
  • FIG. 12B is a cross-sectional view taken along the dotted line B-B' shown in FIG. 12A
  • FIG. 12C is a cross-sectional view taken along the dotted line C-C' shown in FIG. 12A.
  • the dielectric layer 430 may be etched by photolithography and selective etching processes.
  • a ferroelectric layer 440 is deposited.
  • 13A is a top view of the ferroelectric memory
  • FIG. 13B is a cross-sectional view taken along the dotted line B-B' shown in FIG. 13A
  • FIG. 13C is a cross-sectional view taken along the dotted line C-C' shown in FIG. 13A.
  • the ferroelectric layer 440 may be deposited by Atomic Layer Deposition (ALD).
  • ALD Atomic Layer Deposition
  • the ferroelectric layer 440 may include HfZrOx.
  • an electrode 450 is deposited.
  • 14A is a top view of the ferroelectric memory
  • FIG. 14B is a cross-sectional view taken along the dotted line B-B' shown in FIG. 14A
  • FIG. 14C is a cross-sectional view taken along the dotted line C-C' shown in FIG. 14A.
  • electrode 450 may be deposited by a CVD process.
  • the electrode 450 may include metal such as W.
  • CMP chemical mechanical polishing
  • CMP may stop on dielectric layer 430 or dielectric layer 426 .
  • FIG. 15 shows a schematic diagram of a ferroelectric memory cell 500 according to some embodiments of the present disclosure.
  • the fin 520 in the ferroelectric memory cell 500 only includes the first electrode 522 and does not include a dielectric layer.
  • a ferroelectric layer 520 covers at least a portion of the first electrode 522
  • a second electrode 560 covers the ferroelectric layer 520 , forming a single fin ferroelectric capacitor between the first electrode 522 and the second electrode 560 .
  • the two symmetrical vertical ferroelectric capacitor structures in the ferroelectric memory cell 300 are combined into a single fin ferroelectric capacitor structure.
  • expanding the ferroelectric memory cell 500 along the x-axis can form an array of ferroelectric memory cells similar to that shown in FIG. 6 .
  • FIG. 16 shows a schematic diagram of a ferroelectric memory 501 according to some embodiments of the present disclosure.
  • the ferroelectric memory 501 can be regarded as an array of ferroelectric memory cells formed by extending the ferroelectric memory cells 500 shown in FIG. 15 along the x-axis and the y-axis.
  • the ferroelectric memory 501 is similar to the ferroelectric memory 301 in FIG. 8 , except that, in the ferroelectric memory 501 , the fin 520 only includes the first electrode 522 instead of a dielectric layer.
  • FIG. 17 shows a schematic diagram of a ferroelectric memory 601 according to some embodiments of the present disclosure.
  • the ferroelectric memory 601 includes a fin 620 extending along the x-axis direction.
  • the fin 620 includes a first electrode 621, a dielectric layer 622, a first electrode 623, a dielectric layer 624, a first electrode 625, a dielectric layer 626, a first electrode 627 and a dielectric layer 628 stacked in sequence.
  • FIG. 17 shows four first electrodes and four dielectric layers, the ferroelectric memory 601 may also include other numbers of first electrodes and dielectric layers.
  • the ferroelectric memory 601 can be regarded as formed by further extending the ferroelectric memory cells along the z-axis direction.
  • the ferroelectric layer 640 covers at least a portion of the fin 620 , for example, the ferroelectric layer 640 may cover at least a portion of the top and side walls of the fin 620 .
  • the second electrode 660 covers at least a portion of the ferroelectric layer 640 , eg, covers the top and side walls of the ferroelectric layer 640 .
  • the first electrodes 621, 623, 625 and 627 may be drawn out through respective contact holes to be connected to corresponding bit lines.
  • FIG. 18 shows a schematic diagram of a ferroelectric memory 601 according to some embodiments of the present disclosure.
  • the ferroelectric memory 601 includes a plurality of fins 620 extending along the x-axis direction, and each fin 620 includes a first electrode 621, a dielectric layer 622, a first electrode 623, a dielectric layer 624, a first electrode 625, a dielectric layer 626, a first electrode 627 and a dielectric layer 628 stacked in sequence.
  • FIG. 18 shows that although FIG. 18 shows that each fin 610 includes four first electrodes and four dielectric layers, each fin 610 may also include other numbers of first electrodes and dielectric layers.
  • the ferroelectric memory 601 can be regarded as formed by further extending the ferroelectric memory cells along the z-axis direction. By stacking and expanding in the vertical direction, a three-dimensional integrated ferroelectric memory can be realized, which further increases the storage density, and the realization process of this three-dimensional integration method is simpler.
  • the ferroelectric layer 640 covers at least a portion of the fin 620 , for example, the ferroelectric layer 640 may cover at least a portion of the top and side walls of the fin 620 .
  • the second electrode 660 covers at least a portion of the ferroelectric layer 640 , eg, covers the top and side walls of the ferroelectric layer 640 .
  • the first electrodes 621, 623, 625 and 627 may be drawn out through respective contact holes to be connected to corresponding bit lines.
  • 19-27G illustrate a method for fabricating the ferroelectric memory 601 as shown in FIG. 18 according to some embodiments of the present disclosure.
  • a dielectric layer 728, a first electrode layer 727, a dielectric layer 726, a first electrode layer 725, a dielectric layer 724, a first electrode layer 723, a dielectric layer 722 and a first electrode layer 721 are sequentially formed on a substrate (not shown) to form a multilayer stack structure.
  • metal and dielectric layers may be deposited alternately to form a multilayer stack.
  • a stepped structure is formed by an etching modification method.
  • the step structure can be formed using etching modification methods known in the art.
  • etching is performed along the x-axis direction to form a plurality of fins 720 .
  • the plurality of fins 720 extends along the x-axis direction and is spaced apart along the y-axis direction.
  • etching can be performed by photolithography and non-selective etching processes.
  • 22A-22E show different views of the perspective view shown in FIG. 21, wherein, FIG. 22A is a top view of the structure shown in FIG. 21, FIG. 22B is a cross-sectional view of the structure shown in FIG. 21 along the dotted line B-B', and FIG. 22C is a cross-sectional view of the structure shown in FIG. ’ cross-sectional view.
  • the dielectric layer 730 is filled.
  • 23A is a top view of a ferroelectric memory
  • FIG. 23B is a cross-sectional view taken along the dotted line B-B' shown in FIG. 23A
  • FIG. 23C is a cross-sectional view taken along the dotted line C-C' shown in FIG. 23A
  • FIG. 23D is a cross-sectional view taken along the dotted line D-D' shown in FIG.
  • the dielectric layer 730 may be filled by a chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
  • CVD chemical Vapor Deposition
  • dielectric layer 730 may be a low-k dielectric layer.
  • the dielectric layer 730 is etched along the y-axis direction to form trenches extending along the y-axis direction.
  • 24A is a top view of a ferroelectric memory
  • FIG. 24B is a cross-sectional view taken along the dotted line B-B' shown in FIG. 24A
  • FIG. 24C is a cross-sectional view taken along the dotted line C-C' shown in FIG. Sectional view taken from F-F'.
  • the dielectric layer 730 can be etched by photolithography and selective etching processes.
  • a ferroelectric layer 740 is deposited.
  • Fig. 25A is a top view of the ferroelectric memory
  • Fig. 25B is a cross-sectional view taken along the dotted line F-F' shown in Fig. 13A.
  • Other cross-sectional views are the same as those in Fig. 24B-24E and are not shown again.
  • the ferroelectric layer 740 may be deposited by Atomic Layer Deposition (ALD).
  • ALD Atomic Layer Deposition
  • ferroelectric layer 740 may be HfZrOx.
  • electrode 750 is deposited.
  • Fig. 26A is a plan view of the ferroelectric memory
  • Fig. 26B is a cross-sectional view taken along the dotted line B-B' shown in Fig. 26A.
  • Other cross-sectional views are the same as those in Fig. 24B-24E and are not shown again.
  • electrode 750 may be deposited by a CVD process.
  • the electrode 750 may include metal such as W.
  • CMP chemical mechanical polishing
  • FIGS. 27A-27G a contact hole 760 is formed.
  • Figure 27A is a top view of a ferroelectric memory
  • Figure 27B is a cross-sectional view taken along the dotted line B-B' shown in Figure 27A
  • Figure 27C is a cross-sectional view taken along the dotted line C-C' shown in Figure 27A
  • Figure 27D is a cross-sectional view taken along the dotted line D-D' shown in Figure 27A
  • Figure 27E is a cross-sectional view taken along the dotted line E-E' shown in Figure 27A
  • Figure 27F is a cross-sectional view taken along the dotted line shown in Figure 27A
  • 27G is a cross-sectional view taken along the dotted line G-G' shown in FIG. 27A.
  • holes may be formed through photolithography and etching processes, and the contact holes 760 may be formed by filling metal in the holes. Contact holes 760 are used to connect to corresponding bit lines.

Abstract

本公开的实施例涉及铁电存储器及其制造方法。铁电存储器包括鳍形态的第一电极，第一电极沿着第一水平方向延伸。第二电极至少部分覆盖第一电极的第一侧壁和与第一侧壁相对的第二侧壁。铁电层位于第一电极与第二电极之间。该铁电存储器包括立式排布的铁电存储器单元，使得铁电存储器单元的铁电电容能够在纵向的空间上扩展，以提高存储密度，降低存储芯片的成本。

Description

铁电存储器及其制造方法 技术领域
本公开的实施例一般地涉及存储器，并且更具体地涉及铁电存储器及其制造方法。
背景技术
铁电存储器是一种新型的随机存取存储器，可以同时具备随机存取能力和非易失存储器的断电数据保证能力。目前，铁电存储器通常包括平面结构的铁电电容。铁电电容通常包括底电极、顶电极和位于底电极和顶电极之间的铁电层，以形成三明治结构。
铁电电容中的铁电层在正负操作电压下，可以具有不同的极化方向，上极化方向和下极化方向可以分别代表存储数据的0和1。在读取时，向铁电电容施加读电压，在读电压下检测铁电层是否发生反转。当铁电层发生反转时，铁电电容上会有电荷的流入，利用灵敏放大器对电荷流动进行放大感知，进而判断存储的状态。
为了保证放大电路能够准确识别出铁电电容中存储的0和1的状态，就要求铁电电容的电容值足够大，这样当读取铁电电容中存储的数据时，铁电层进行反转才会有足够多的铁电翻转电荷流过，从而实现足够大的存储窗口。在平面电容结构中，每一个位单元铁电电容占据的面积过大，阻碍了铁电存储器存储密度的提升。
发明内容
本公开的实施例提供了一种可以提升存储密度的铁电存储器及其制造方法。
根据本公开的第一方面，提供了一种铁电存储器。铁电存储器包括鳍形态的第一电极，第一电极沿着第一水平方向延伸。第二电极至少部分覆盖第一电极的第一侧壁和与第一侧壁相对的第二侧壁。铁电层位于第一电极与第二电极之间。
该铁电存储器包括立式排布的铁电存储器单元，使得铁电存储器单元的铁电电容能够在纵向的空间上扩展。因此，在平面上可以通过先进工艺进行缩小，使得能够压缩位单元占用的芯片上的面积，提高存储密度，降低存储芯片的成本。
由于立式的铁电电容形成在第一电极的侧壁上，在先进工艺中在平面上压缩位单元占用面积时，立式的铁电电容的面积不会被大幅减少。大的铁电电容面积可以保证器件读取时候的窗口足够大。另外，这种鳍式结构使得第一电极上的铁电电容构成了一个整体存储单元，因此，有效铁电面积得到了进一步的扩大。
在一些实施例中，铁电存储器还包括鳍形态的第一介质层，第一介质层沿着第一水平方向延伸，并且第一介质层位于第一电极上方。
在一些实施例中，铁电存储器还包括鳍形态的第二介质层，第二介质层沿着第一水平方向延伸，并且第二介质层位于第一电极下方。
在一些实施例中，第一电极与铁电层接触。
在一些实施例中，第一电极还包括位于第一侧壁与第二侧壁之间的顶壁，并且第二电极还覆盖第一电极的顶壁。
在一些实施例中，铁电存储器还包括第一晶体管，第一晶体管包括第一端、第二端和控 制端。第一晶体管的第一端耦接至第一电极，第一晶体管的第二端耦接至源线，并且第一晶体管的控制端耦接至控制信号线。铁电存储器还包括第二晶体管，第二晶体管包括第一端、第二端和控制端。第二晶体管的控制端耦接至第一电极，第二晶体管的第一端耦接至位线，并且第二晶体管的第二端耦接至源线。
在一些实施例中，第一电极耦接至字线。
在一些实施例中，铁电存储器包括鳍形态的多个第一电极，多个第一电极中的每个第一电极沿着第一水平方向延伸并且沿着与第一水平方向垂直的第二水平方向间隔开。多个第二电极中的每个第二电极沿着第二水平方向延伸并且至少部分覆盖多个第一电极的第一侧壁和与第一侧壁相对的第二侧壁。此外，多个第二电极沿着第一水平方向间隔开。多个铁电层中的每个铁电层位于多个第一电极中的相应第一电极与多个第二电极中的相应第二电极之间。
通过在水平方向上扩展多个鳍来形成铁电存储单元的阵列，从而提高铁电存储器的存储容量。
在一些实施例中，铁电存储器还包括第一晶体管，包括第一端、第二端和控制端。第一晶体管的第一端耦接至多个第一电极中的每个第一电极，第一晶体管的第二端耦接至源线，并且第一晶体管的控制端耦接至控制信号线。另外，第二晶体管包括第一端、第二端和控制端，第二晶体管的控制端耦接至多个第一电极中的每个第一电极，第二晶体管的第一端耦接至位线，并且第二晶体管的第二端耦接至源线。
在一些实施例中，多个第一电极中的每个第一电极耦接至相应的字线。
在一些实施例中，多个第二电极中的每个第二电极沿着第二水平方向在多个第一电极之间连续或者不连续。
在一些实施例中，铁电存储器包括鳍形态的多个第一电极，多个第一电极中的每个第一电极沿着垂直方向通过介质层彼此间隔开，多个第一电极中的每个第一电极沿着第一水平方向延伸。
通过在纵向上进行堆叠扩展，可以实现纵向方向上集成的铁电存储器，进一步提高了存储的密度，而且，这种纵向集成方式的实现工艺更简单。
在一些实施例中，铁电存储器包括鳍形态的多个第一电极，多个第一电极中的每个第一电极沿着第一水平方向延伸，其中，多个第一电极包括沿着与第一水平方向垂直的第二水平方向延伸的多组第一电极，每组第一电极中的第一电极沿着垂直方向通过介质层彼此间隔开。
通过在纵向上进行堆叠扩展，可以实现三维集成的铁电存储器，进一步提高了存储的密度，而且，这种三维集成方式的实现工艺更简单。
在一些实施例中，多个第一电极中的每个第一电极与相应的接触孔电连接。
根据本公开的第二方面，提供了一种设备。该设备包括印刷电路板，并且还包括根据本公开的第一方面的铁电存储器，其中，铁电存储器设置在印刷电路板上。
根据本公开的第三方面，提供了一种用于制造铁电存储器的方法。在该方法中，形成第一电极层；刻蚀第一电极层，以形成鳍形态的多个第一电极，多个第一电极沿着第一水平方向延伸；沉积铁电层，以填充多个第一电极之间的多个第一沟槽；刻蚀铁电层，以形成多个第二沟槽，多个第二沟槽沿着与第一水平方向垂直的第二水平方向延伸；以及沉积第二电极层，以在多个第二沟槽中形成第二电极。
在一些实施例中，形成第一电极层包括形成通过介质层彼此间隔开的多个第一电极层，并且其中方法还包括形成用于相应第一电极的接触孔。
提供发明内容部分是为了以简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本公开的关键特征或主要特征，也无意限制本公开的范围。
附图说明
通过结合附图对本公开示例性实施例进行更详细的描述，本公开的上述以及其他目的、特征和优势将变得更加明显，其中，在本公开示例性实施例中，相同的附图标记通常代表相同部件。
图1A示出了根据本公开的一些实施例的设备的示意图。
图1B示出了根据本公开的一些实施例的铁电存储器的示意图。
图2示出了根据本公开的一些实施例的存储阵列的示意图。
图3示出了根据本公开的一些实施例的铁电存储器单元的立体图。
图4示出了根据本公开的一些实施例的铁电存储器单元的截面图。
图5示出了根据本公开的一些实施例的铁电存储器单元的电路图。
图6示出了根据本公开的一些实施例的铁电存储器的立体图。
图7示出了根据本公开的一些实施例的铁电存储器的电路图。
图8示出了根据本公开的一些实施例的铁电存储器的立体图。
图9A-图14C示出了根据本公开的一些实施例的用于制造如图8所示的铁电存储器的方法。
图15示出了根据本公开的一些实施例的铁电存储器单元的示意图。
图16示出了根据本公开的一些实施例的铁电存储器的示意图。
图17示出了根据本公开的一些实施例的铁电存储器的示意图。
图18示出了根据本公开的一些实施例的铁电存储器的示意图。
图19-图27G示出了根据本公开的一些实施例的用于制造如图18所示的铁电存储器的方法。
根据通常的做法，附图中示出的各种特征部可能未按比例绘制。因此，为了清楚起见，可以任意地扩展或减小各种特征部的尺寸。另外，一些附图可能未描绘给定的系统、方法或设备的所有部件。最后，在整个说明书和附图中，类似的附图标号可用于表示类似的特征部。
具体实施例
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。术语“和/或”表示由其关联的两项的至少一项。术语“耦接”可以表示一个部件与另一部件之间的直接连接，也可以包括经由其他部件的间接连接。例如“A和/或B”表示A、B，或者A和B。下文还可能包括其他明确的和隐含的定义。
对方向或方位的任何参考仅旨在便于描述，而不以任何方式限制本公开的范围。例如“下部”、“上部”、“水平”、“竖直”、“上方”、“下方”、“朝上”、“朝下”、“顶部”和“底部”及其派生(例如“水平地”、“向上”、“向下”等)等相关术语在讨论中用来指代下文描述的或者在附图中示出的方位。这些相关术语仅仅是为了便于描述，而不要求装置以特定方位构造或操作。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
图1A示出了根据本公开的一些实施方式的设备100的示意图。仅作为示例，设备100可以包括计算机、服务器、便携式计算机、桌面计算机、移动电话、蜂窝电话、个人数字助理、可穿戴设备或机顶盒等电子设备，并且可以用于自动驾驶汽车等应用。如图1A所示，设备100可以包括处理器102，其可以根据计算机程序指令来执行各种适当的动作和处理。例如，处理器102可以包括缓存(未示出)，用于缓存计算机程序指令和/或数据。在存储器104中，可以存储设备100操作所需的各种程序和数据。存储器104还可以存储在设备100操作过程中由处理器102所执行的指令，并且可以存储用户数据。处理器102和存储器104通过总线108彼此连接，以实现通信。
如图1A所示，设备100还包括与总线108通信的存储装置106，其可以用于存储各种数据以及计算机程序指令，计算机程序指令可以被加载到存储器104，以由处理器102执行。另外，设备100还可以包括与总线108通信的输入/输出(Input/Output,I/O)设备110(例如，键盘、显示器)等。可选地，设备100还可以包括收发器112，收发器112可以与接收和发射无线信号的天线(未示出)连接。应当理解，本公开的范围不限于具有任何或所有这些部件的实施例。
存储装置106通常由磁盘和/或固态硬盘等非易失性存储器来实现。铁电存储器是一种新型非易失性存储技术，其可以用于实现存储装置106。处理器102中的缓存通常由静态随机存取存储器(Static Random Access Memory,SRAM)来实现，其中SRAM为易失性存储器。存储器104通常由动态随机存取存储器(Dynamic Random Access Memory,DRAM)来实现，其中DRAM也为易失性存储器。在一些实施例中，铁电存储器也可以用于实现存储器104，甚至可以用于实现处理器102中的缓存。应当理解，图1A的设备100的架构仅作为示例提供，除了设备100的架构之外，铁电存储器或铁电存储器单元也可以用于其他场景或架构中。
图1B示出了根据本公开的一些实施例的铁电存储器120的示意图。例如，铁电存储器120可以应用于如图1A所示的处理器102中的缓存、存储器104和/或存储装置106。例如，铁电存储器120可以设置在印刷电路板(Printed Circuit Board,PCB)上。如图2所示，铁电存储器120包括存储阵列121，存储阵列121包括位单元的阵列，位单元内包括铁电存储器单元以及晶体管等开关。
如图1B所示，铁电存储器120还包括行解码器122和列解码器123，行解码器122和列解码器123从控制器124接收地址信号，并且基于从控制器124接收到的地址信号来选择存储阵列121中的位单元。控制器124生成地址信号AS，并且控制行解码器122和列解码器123，以对通过地址信号寻址的位单元进行读取和写入。行解码器122和列解码器123可以偏置字线WL和位线BL，并选择相应的字线WL和位线BL，进而选择与其连接的位单元。以这种方式，可以实现对被选择的位单元的读取和写入。
在对选择的位单元进行读取的步骤期间，读电流分别流过该位单元的铁电存储器单元。 例如，在读取步骤期间，列解码器123将所选择的每条位线BL电连接到读取级125，以执行读取操作。例如，读取级125可以包括读出放大器等电路。读出放大器级可以将在所选择的位单元中的读电流与参考电流进行比较，以确定该位单元中存储的数据值。在写入步骤期间，列解码器123可以将所选择的每条位线BL电连接到写入级126，以执行写入操作。写入级126可以提供写入电流。
图2示出了根据本公开的一些实施例的存储阵列200的示意图。存储阵列200可以用于实现如图1B所示的存储阵列121。如图2所示，存储阵列200包括位单元204的阵列，其中每一个位单元204包括铁电存储器单元202和晶体管212。晶体管212可以由金属氧化物场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor,MOSFET)等晶体管来实现。如图2所示，晶体管212的栅极耦接到字线208，字线208可以与如图1B所示的行解码器122连接。晶体管212的第一端子(例如，源极)耦接到源线210，其中源线210可以接地。晶体管212的第二端子(例如，漏极)耦接到铁电存储器单元202。铁电存储器单元202又进一步耦接到位线206，其中位线206可以与如图1B所示的列解码器123连接。应当理解，图2仅作为电路示意图来提供，并不暗示字线、位线和源线的物理排布。例如，在一些实施例中，位线206和源线210可以彼此平行，并且与字线208垂直。图2示出了存储阵列200的一个示例配置，然而，应当理解，存储阵列200也可以具有其他适当的配置。
图3-图4示出了根据本公开的一些实施例的铁电存储器单元300，其中，图3为铁电存储器单元300的立体图，并且图4为图3的铁电存储器单元300沿yz平面的截面图。图3-图4中的铁电存储器单元300形成在衬底(未示出)上方，其中衬底在xy平面内延伸。如图3-图4所示，铁电存储器单元300包括沿x轴方向(也称第一水平方向)延伸的鳍320，鳍320包括第一电极322、位于第一电极322上方的介质层324和位于第一电极322下方的介质层326，因而，第一电极322、介质层324和介质层326均呈现鳍形态。第一元件在第二元件的上方指第一元件在第二元件的远离衬底一侧，第一元件在第二元件下方指第一元件在第二元件的靠近衬底一侧。
介质层324、第一电极322和介质层326形成三明治结构。例如，第一电极322可以包括钨、TiN或其他金属，也可以包括重掺杂的多晶硅。例如，介质层324和介质层326可以是SiO 2、SiNx或者其他介质材料。如图3-图4所示，第二电极360至少部分覆盖鳍320的第一侧壁和与第一侧壁相对的第二侧壁，并且铁电层340位于鳍320与第二电极360之间。侧壁表示与衬底呈非零角度的表面，即，与xy平面呈非零角度的表面。在图3-图4的实施例中，侧壁与xy平面垂直，然而，这仅是作为示例提供，侧壁也可以与xy平面呈其他非零角度。例如，铁电层340覆盖鳍320的至少一部分，例如，铁电层340可以覆盖鳍320的顶壁和侧壁的至少一部分。具体而言，铁电层340可以至少部分覆盖鳍320的第一侧壁和与第一侧壁相对的第二侧壁。例如，铁电层340可以包括氧化铪锆(HfZrO、HfLaOx和/或HfZrLaOx)等铁电材料。第二电极360覆盖铁电层340的至少一部分，例如，覆盖铁电层340的顶壁和侧壁。第二电极360可以包括TiN和/或W等金属，或者重掺杂的多晶硅。例如，第二电极360可以包括TiN和W的叠层。
在该鳍式结构的铁电存储器单元中，铁电电容形成在第一电极322的两侧，呈对称的立式分布。两个对称的立式铁电电容形成铁电存储器的一个操作单元。通过这种鳍式结构，将铁电电容设置为立式排布，使得铁电存储器占用的芯片面积大大压缩。另外，两个对称铁电电容，构成一个位单元，使得有效的铁电面积扩大。而且，鳍式结构的高度可以根据工艺能 力纵向扩展，这样在不增加占用芯片面积的前提下，铁电电容的有效面积能够进一步增加，进而扩大了存储的窗口。
图5示出了根据本公开的一些实施例的铁电存储器单元300的电路图。铁电存储器单元300包括顶电极TE和底电极BE，其中顶电极TE对应于图3-图4的第二电极360，底电极BE对应于图3-图4的第一电极322。铁电存储器单元300的底电极BE与晶体管T2的栅极端G2连接，晶体管T2的漏极端D2与位线BL连接，晶体管T2的源极端S2与源线SL连接。晶体管T1的漏极端D1与底电极BE连接，晶体管T1的源极端S1与源线SL连接，并且晶体管T1的栅极端G1与控制信号线CNTL连接。铁电存储器单元300的顶电极TE与字线WL连接。应当理解，尽管图5以晶体管的源极、漏极和栅极为例进行描述，然而，晶体管T1和T2也可以使用其他合适的开关，其中，该开关的控制端、第一端和第二端可以分别代替栅极、漏极和源极。
在写入操作时，晶体管T1被控制信号线CNTL上的控制信号导通，在字线WL与源线SL之间施加写操作的脉冲。该脉冲使得铁电存储器单元300中的铁电电容极化，实现数据写入。在读取操作时，可以采用破坏性读取。通过控制信号线CNTL上的控制信号将晶体管T1断开，并且在字线WL与源线SL之间施加读取的电压脉冲。铁电存储器单元300中的铁电电容在读脉冲下发生反转，释放对应的电荷，改变晶体管T2的导通状态。在位线BL上施加小电压，探测流经晶体管T2的电流，进而读取原来写入的状态。在读取之后，重新将原存储的状态写回。
图6示出了根据本公开的一些实施例的铁电存储器301的立体图。铁电存储器301包括沿着x轴方向延伸的鳍320，其中，鳍320包括第一电极322、形成在第一电极322上方的介质层324以及形成在第一电极322下方的介质层326。鳍320上形成沿着x轴方向彼此间隔开的多个铁电层340，其中，多个铁电层340上分别形成各自的第二电极340，从而形成多个铁电存储器单元300。应当理解，尽管图6仅示出了两个铁电存储器单元300，然而，这仅仅作为示例提供，可以沿着x轴方向布置更多个铁电存储器单元300。在图6的铁电存储器301中，将图3和图4所示的铁电存储器单元300沿着x轴方向进一步扩展，以形成图6的铁电存储器301。
图7示出了根据本公开的一些实施例的铁电存储器301的电路图。图7示出了三个铁电存储器单元300-1、300-2和300-3(统称为铁电存储器单元300)，应当理解，铁电存储器301也可以包括更多或更少的铁电存储器单元。如图7所示，每一个铁电存储器单元300包括顶电极TE和底电极BE，其中，顶电极TE对应于图6中的第二电极360，底电极BE对应于图6的第一电极322。在图6中，多个铁电存储器单元300的第一电极322形成在一个鳍中，因而，将多个铁电存储器单元300的底电极BE彼此连接。如图7所示，多个铁电存储器单元300的底电极BE还与晶体管T2的栅极端G2连接，晶体管T2的漏极端D2与位线BL连接，晶体管T2的源极端S2与源线SL连接。晶体管T1的漏极端D1与底电极BE连接，晶体管T1的源极端S1与源线SL连接，并且晶体管T1的栅极端G1与控制信号线CNTL连接。铁电存储器单元300-1、300-2和300-3的顶电极TE分别与各自的字线WL1、WL2和WL3连接。
例如，在对铁电存储器单元300-1执行写入操作时，晶体管T1由控制信号线CNTL上的控制信号导通，在字线WL1与源线SL之间施加写操作的脉冲。该脉冲使得相应的铁电存储器单元300-1中的铁电电容极化，实现数据写入。在对铁电存储器单元300-1还行读取操作 时，可以采用破坏性读取。首先，通过控制信号线CNTL上的控制信号将晶体管T1断开，在字线WL1与源线SL之间施加读取的电压脉冲。当铁电存储器单元300-1中的铁电电容在读脉冲下发生反转，释放对应的电荷改变晶体管T2的导通状态。在位线BL上施加小电压，探测流经晶体管T2的电流，进而读取原来写入的状态。读取之后，重新将原存储的状态写回。
图8示出了根据本公开的一些实施例的铁电存储器301的立体图。铁电存储器301包括多个鳍320，其中每一个鳍320沿着x轴方向延伸，并且沿着y轴方向(也称第二水平方向)彼此间隔开。每一个鳍320包括第一电极322、形成在第一电极322上方的介质层324以及形成在第一电极322下方的介质层326。应当理解，尽管图7仅示出了三个鳍320，然而，可以沿着y轴方向布置更多个鳍320。
与图6所示的铁电存储器301相比，图8所示的铁电存储器301沿着y轴方向进一步扩展，以形成多个鳍320。换言之，第二电极360与第一电极322垂直交叉，从而形成交叉杆(crossbar)结构。如图8所示，铁电层340形成在每一个鳍320上，第二电极360形成在铁电层340上，并将铁电层340彼此连接在一起。每一个第二电极360与一个位线WL连接，每一个第一电极322可以与一个位线BL连接，从而形成存储阵列。
在图8中，第二电极360在多个鳍320之间是连续的，将不同的鳍连接在一起。然而，在一些实施例中，第二电极360在多个鳍320之间可以是不连续的，即，在不同鳍320之间断开。在这种情况下，不同鳍之间的第二电极360可以通过其他导线进行连接。
图9A-图14C示出了根据本公开的一些实施例的用于制造如图8所示的铁电存储器301的方法。如图9A-图9B所示，在衬底(未示出)上依次形成介质层428、第一电极层427和介质层426，以形成三明治结构。图9A为该三明治结构的俯视图，图9B为沿着图9A所示的虚线B-B’截取的截面图。例如，介质层428和/或介质层426可以是氧化硅等介质材料。第一电极层427可以是金属层或者重掺杂的多晶硅。
如图10A-图10B所示，沿着x轴方向刻蚀，以形成多个鳍420。多个鳍420沿着x轴方向延伸，并且沿着y轴方向间隔开。图10A为铁电存储器的俯视图，并且图10B是沿着图10A所示的虚线B-B’截取的截面图。例如，通过光刻和非选择性刻蚀工艺来进行刻蚀。
如图11A-图11B所示，填充介质层430。图11A为铁电存储器的俯视图，并且图11B是沿着图11A所示的虚线B-B’截取的截面图。例如，可以通过化学气相衬底(Chemical Vapor Deposition,CVD)工艺来填充介质层430。例如，介质层430可以是低k介质层。
如图12A-图12C所示，沿着y轴方向刻蚀介质层430，以形成沟槽。图12A为铁电存储器的俯视图，图12B是沿着图12A所示的虚线B-B’截取的截面图，图12C是沿着图12A所示的虚线C-C’截取的截面图。例如，可以通过光刻和选择性刻蚀工艺来刻蚀介质层430。
如图13A-图13C所示，沉积铁电层440。图13A为铁电存储器的俯视图，图13B是沿着图13A所示的虚线B-B’截取的截面图，图13C是沿着图13A所示的虚线C-C’截取的截面图。例如，可以通过原子层沉积(Atomic Layer Deposition,ALD)来沉积铁电层440。例如，铁电层440可以包括HfZrOx。
如图14A-图14C所示，沉积电极450。图14A为铁电存储器的俯视图，图14B是沿着图14A所示的虚线B-B’截取的截面图，图14C是沿着图14A所示的虚线C-C’截取的截面图。例如，可以通过CVD工艺来沉积电极450。例如，电极450可以包括W等金属。在沉积电极450之后，可以进行化学机械抛光(Chemical Mechanical Polishing,CMP)。CMP可以停止在介质层430或介质层426上。
图15示出了根据本公开的一些实施例的铁电存储器单元500的示意图。与图3-图4所示的铁电存储器单元300不同，在图15中，铁电存储器单元500中的鳍520仅包括第一电极522，而不包括介质层。铁电层520覆盖第一电极522的至少一部分，并且第二电极560覆盖铁电层520，从而在第一电极522与第二电极560之间形成单个鳍式铁电电容。换言之，将铁电存储器单元300中的两个对称的立式铁电电容结构合并为单个鳍式铁电电容结构。在一些实施例中，将铁电存储器单元500沿着x轴扩展，可以形成类似于图6所示的铁电存储器单元的阵列。
图16示出了根据本公开的一些实施例的铁电存储器501的示意图。例如，铁电存储器501可以视为将如图15所示的铁电存储器单元500沿着x轴和y轴扩展所形成的铁电存储器单元的阵列。铁电存储器501与图8中的铁电存储器301相似，不同之处在于，在铁电存储器501中，鳍520仅包括第一电极522，而不包括介质层。
图17示出了根据本公开的一些实施例的铁电存储器601的示意图。铁电存储器601包括沿着x轴方向延伸的鳍620，鳍620包括依次堆叠的第一电极621、介质层622、第一电极623、介质层624、第一电极625、介质层626、第一电极627和介质层628。应当理解，尽管图17示出了四个第一电极和四个介质层，然而，铁电存储器601也可以包括其他数目的第一电极和介质层。铁电存储器601可以视为铁电存储器单元沿着z轴方向进一步扩展而形成的。
如图17所示，铁电层640覆盖鳍620的至少一部分，例如，铁电层640可以覆盖鳍620的顶壁和侧壁的至少一部分。第二电极660覆盖铁电层640的至少一部分，例如，覆盖铁电层640的顶壁和侧壁。第一电极621、623、625和627可以通过各自的接触孔引出，与相应的位线连接。
图18示出了根据本公开的一些实施例的铁电存储器601的示意图。铁电存储器601包括沿着x轴方向延伸的多个鳍620，每一个鳍620包括依次堆叠的第一电极621、介质层622、第一电极623、介质层624、第一电极625、介质层626、第一电极627和介质层628。应当理解，尽管图18示出了每一个鳍610包括四个第一电极和四个介质层，然而，每一个鳍610也可以包括其他数目的第一电极和介质层。铁电存储器601可以视为铁电存储器单元沿着z轴方向进一步扩展而形成的。通过在纵向上进行堆叠扩展，可以实现三维集成的铁电存储器，进一步提高了存储的密度，而且，这种三维集成方式的实现工艺更简单。
如图18所示，铁电层640覆盖鳍620的至少一部分，例如，铁电层640可以覆盖鳍620的顶壁和侧壁的至少一部分。第二电极660覆盖铁电层640的至少一部分，例如，覆盖铁电层640的顶壁和侧壁。第一电极621、623、625和627可以通过各自的接触孔引出，与相应的位线连接。
图19-图27G示出了根据本公开的一些实施例的用于制造如图18所示的铁电存储器601的方法。如图19所示，在衬底(未示出)上依次形成介质层728、第一电极层727、介质层726、第一电极层725、介质层724、第一电极层723、介质层722和第一电极层721，以形成多层堆叠结构。例如，可以交替沉积金属和介质层，以形成多层堆叠结构。
如图20所示，通过刻蚀修饰法形成台阶结构。可以使用本领域已知的刻蚀修饰法来形成台阶结构。
如图21所示，沿着x轴方向进行刻蚀，以形成多个鳍720。多个鳍720沿着x轴方向延伸，并且沿着y轴方向间隔开。例如，可以通过光刻和非选择性刻蚀工艺来进行刻蚀。图22A-图22E示出了图21所示的立体视图的不同视图，其中，图22A为图21所示的结构的俯视图， 图22B为图21所示的结构沿着虚线B-B’的截面图，图22C为图21所示的结构沿着虚线C-C’的截面图，图22D为图21所示的结构沿着虚线D-D’的截面图，图22E为图21所示的结构沿着虚线E-E’的截面图。
如图23A-图23E所示，填充介质层730。图23A为铁电存储器的俯视图，图23B为沿着图23A所示的虚线B-B’截取的截面图，图23C为沿着图23A所示的虚线C-C’截取的截面图，图23D是沿着图23A所示的虚线D-D’截取的截面图，图23E为沿着图23A所示的虚线E-E’截取的截面图。例如，可以通过化学气相衬底(Chemical Vapor Deposition,CVD)工艺来填充介质层730。例如，介质层730可以是低k介质层。
如图24A-图24C所示，沿着y轴方向刻蚀介质层730，以形成沿着y轴方向延伸的沟槽。图24A为铁电存储器的俯视图，图24B为沿着图24A所示的虚线B-B’截取的截面图，图24C是沿着图24A所示的虚线C-C’截取的截面图，图24D为沿着图24A所示的虚线D-D’截取的截面图，图24E为沿着图24A所示的虚线E-E’截取的截面图，图24F为沿着图24A所示的虚线F-F’截取的截面图。例如，可以通过光刻和选择性刻蚀工艺来刻蚀介质层730。
如图25A-图25B所示，沉积铁电层740。图25A为铁电存储器的俯视图，图25B是沿着图13A所示的虚线F-F’截取的截面图。其他截面图与图24B-图24E相同，不再示出。例如，可以通过原子层沉积(Atomic Layer Deposition,ALD)来沉积铁电层740。例如，铁电层740可以是HfZrOx。
如图26A-图26B所示，沉积电极750。图26A为铁电存储器的俯视图，图26B是沿着图26A所示的虚线B-B’截取的截面图。其他截面图与图24B-图24E相同，不再示出。例如，可以通过CVD工艺来沉积电极750。例如，电极750可以包括W等金属。在沉积电极750之后，可以进行化学机械抛光(Chemical Mechanical Polishing,CMP)。CMP可以停止在介质层730或介质层726上。
如图27A-图27G所示，形成接触孔760。图27A为铁电存储器的俯视图，图27B是沿着图27A所示的虚线B-B’截取的截面图，图27C是沿着图27A所示的虚线C-C’截取的截面图，图27D是沿着图27A所示的虚线D-D’截取的截面图，图27E是沿着图27A所示的虚线E-E’截取的截面图，图27F是沿着图27A所示的虚线F-F’截取的截面图，图27G是沿着图27A所示的虚线G-G’截取的截面图。例如，可以通过光刻和刻蚀工艺来形成孔，并且通过在孔中填充金属来形成接触孔760。接触孔760用于连接到相应的位线。
尽管已经详细地描述了本公开的实施例及其优势，但应该理解，在不脱离所附权利要求所限定的本公开的范围的情况下，可对本公开做出各种改变、替代和变化。而且，本申请的范围不旨在限于本说明书中所述的工艺、机器装置、制造、物质组成、工具、方法和步骤的具体实施例。本领域的技术人员通过本公开容易理解，根据本公开，可以利用已有的或今后将开发的、与本公开所述相应实施例执行基本相同的功能或者实现基本相同的结果的工艺、机器装置、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在将这些工艺、机器装置、制造、物质组成、工具、方法或步骤包括在它们的保护范围内。另外，每个权利要求组成单独的实施例，并且各个权利要求和实施例的组合都在本公开的范围内。

Claims (17)

  1. 一种铁电存储器，包括：
    鳍形态的第一电极，所述第一电极沿着第一水平方向延伸；
    第二电极，所述第二电极至少部分覆盖所述第一电极的第一侧壁和与所述第一侧壁相对的第二侧壁；以及
    铁电层，所述铁电层位于所述第一电极与所述第二电极之间。
  2. 根据权利要求1所述的铁电存储器，还包括鳍形态的第一介质层，所述第一介质层沿着所述第一水平方向延伸，并且所述第一介质层位于所述第一电极上方。
  3. 根据权利要求1或2所述的铁电存储器，还包括鳍形态的第二介质层，所述第二介质层沿着所述第一水平方向延伸，并且所述第二介质层位于所述第一电极下方。
  4. 根据权利要求1所述的铁电存储器，其中，所述第一电极与所述铁电层接触。
  5. 根据权利要求1所述的铁电存储器，其中，所述第一电极还包括位于所述第一侧壁与所述第二侧壁之间的顶壁，并且所述第二电极还覆盖所述第一电极的顶壁。
  6. 根据权利要求1-5中任一项所述的铁电存储器，还包括：
    第一晶体管，包括第一端、第二端和控制端，所述第一晶体管的第一端耦接至所述第一电极，所述第一晶体管的第二端耦接至源线，并且所述第一晶体管的控制端耦接至控制信号线；以及
    第二晶体管，包括第一端、第二端和控制端，所述第二晶体管的控制端耦接至所述第一电极，所述第二晶体管的第一端耦接至位线，并且所述第二晶体管的第二端耦接至所述源线。
  7. 根据权利要求6所述的铁电存储器，其中所述第一电极耦接至字线。
  8. 根据权利要求1-5中任一项所述的铁电存储器，包括：
    包括所述第一电极的鳍形态的多个第一电极，所述多个第一电极中的每个第一电极沿着所述第一水平方向延伸并且沿着与所述第一水平方向垂直的第二水平方向间隔开；
    包括所述第二电极的多个第二电极，所述多个第二电极中的每个第二电极沿着所述第二水平方向延伸并且至少部分覆盖所述多个第一电极的第一侧壁和与所述第一侧壁相对的第二侧壁，所述多个第二电极沿着所述第一水平方向间隔开；以及
    包括所述铁电层的多个铁电层，所述多个铁电层中的每个铁电层位于所述多个第一电极中的相应第一电极与所述多个第二电极中的相应第二电极之间。
  9. 根据权利要求8所述的铁电存储器，还包括：
    第一晶体管，包括第一端、第二端和控制端，所述第一晶体管的第一端耦接至所述多个第一电极中的每个第一电极，所述第一晶体管的第二端耦接至源线，并且所述第一晶体管的控制端耦接至控制信号线；以及
    第二晶体管，包括第一端、第二端和控制端，所述第二晶体管的控制端耦接至所述多个第一电极中的每个第一电极，所述第二晶体管的第一端耦接至位线，并且所述第二晶体管的第二端耦接至所述源线。
  10. 根据权利要求9所述的铁电存储器，其中所述多个第一电极中的每个第一电极耦接至相应的字线。
  11. 根据权利要求8-10中任一项所述的铁电存储器，其中所述多个第二电极中的每个第二电极沿着所述第二水平方向在所述多个第一电极之间连续或者不连续。
  12. 根据权利要求1-7中任一项所述的铁电存储器，包括：
    包括所述第一电极的鳍形态的多个第一电极，所述多个第一电极中的每个第一电极沿着垂直方向通过介质层彼此间隔开，所述多个第一电极中的每个第一电极沿着所述第一水平方向延伸。
  13. 根据权利要求1-7中任一项所述的铁电存储器，包括：
    包括所述第一电极的鳍形态的多个第一电极，所述多个第一电极中的每个第一电极沿着所述第一水平方向延伸，其中，所述多个第一电极包括沿着与所述第一水平方向垂直的第二水平方向延伸的多组第一电极，每组第一电极中的第一电极沿着垂直方向通过介质层彼此间隔开。
  14. 根据权利要求12或13所述的铁电存储器，其中所述多个第一电极中的每个第一电极与相应的接触孔电连接。
  15. 一种设备，包括：
    印刷电路板；以及
    根据权利要求1-14中任一项所述的铁电存储器，所述铁电存储器设置在所述印刷电路板上。
  16. 一种用于制造铁电存储器的方法，包括：
    形成第一电极层；
    刻蚀所述第一电极层，以形成鳍形态的多个第一电极，所述多个第一电极沿着第一水平方向延伸；
    沉积铁电层，以填充所述多个第一电极之间的多个第一沟槽；
    刻蚀所述铁电层，以形成多个第二沟槽，所述多个第二沟槽沿着与所述第一水平方向垂直的第二水平方向延伸；以及
    沉积第二电极层，以在所述多个第二沟槽中形成第二电极。
  17. 根据权利要求16所述的方法，其中形成所述第一电极层包括形成通过介质层彼此间隔开的多个第一电极层，并且其中所述方法还包括形成用于相应第一电极的接触孔。
PCT/CN2022/072830 2022-01-19 2022-01-19 铁电存储器及其制造方法 WO2023137642A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/072830 WO2023137642A1 (zh) 2022-01-19 2022-01-19 铁电存储器及其制造方法
CN202280004455.3A CN116802734A (zh) 2022-01-19 2022-01-19 铁电存储器及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/072830 WO2023137642A1 (zh) 2022-01-19 2022-01-19 铁电存储器及其制造方法

Publications (1)

Publication Number Publication Date
WO2023137642A1 true WO2023137642A1 (zh) 2023-07-27

Family

ID=87347658

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/072830 WO2023137642A1 (zh) 2022-01-19 2022-01-19 铁电存储器及其制造方法

Country Status (2)

Country Link
CN (1) CN116802734A (zh)
WO (1) WO2023137642A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109920794A (zh) * 2019-03-25 2019-06-21 中国科学院微电子研究所 一种三维铁电存储器及其制造方法
CN112002360A (zh) * 2019-05-09 2020-11-27 纳姆实验有限责任公司 铁电存储器和逻辑单元及操作方法
CN113054022A (zh) * 2020-02-27 2021-06-29 台湾积体电路制造股份有限公司 具有三维铁电电容器的铁电随机存取存储器
US20210408022A1 (en) * 2020-06-30 2021-12-30 Taiwan Semiconductor Manufacturing Co., Ltd. Ferroelectric random access memory devices and methods

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109920794A (zh) * 2019-03-25 2019-06-21 中国科学院微电子研究所 一种三维铁电存储器及其制造方法
CN112002360A (zh) * 2019-05-09 2020-11-27 纳姆实验有限责任公司 铁电存储器和逻辑单元及操作方法
CN113054022A (zh) * 2020-02-27 2021-06-29 台湾积体电路制造股份有限公司 具有三维铁电电容器的铁电随机存取存储器
US20210408022A1 (en) * 2020-06-30 2021-12-30 Taiwan Semiconductor Manufacturing Co., Ltd. Ferroelectric random access memory devices and methods

Also Published As

Publication number Publication date
CN116802734A (zh) 2023-09-22

Similar Documents

Publication Publication Date Title
US10026747B2 (en) Non-volatile memory device with first gate structure in memory cell region and second gate structure in peripheral circuit region and non-volatile memory system including the same
US20210111179A1 (en) 3d-ferroelectric random access memory (3d-fram)
TWI478292B (zh) 靜態隨機存取記憶裝置與結構
CN106796884B (zh) 具有增大的宽度的三端口位单元
US10878889B2 (en) High retention time memory element with dual gate devices
CN107533859B (zh) 源极线布局与磁隧道结（mtj）存储器位单元中的存取晶体管接触布置的解耦以促进减小的接触电阻
JP2018508991A (ja) ３ポートのビットセルのための金属層
KR20120123943A (ko) 반도체 소자, 반도체 모듈, 반도체 시스템 및 반도체 소자의 제조 방법
JP2013535839A (ja) 論理集積回路に適合するｍｒａｍデバイスおよび集積技法
CN111052379A (zh) 带有后端晶体管的铁电电容器
US11657867B2 (en) Semiconductor device, memory device, and electronic device
EP3958319B1 (en) Memory, forming method therefor and control method therefor
TW202218127A (zh) 微電子裝置、相關電子系統以及形成微電子裝置之方法
US20150228657A1 (en) Semiconductor device, module and system each including the same, and method for manufacturing the semiconductor device
JP2012043995A (ja) 半導体装置
US11362140B2 (en) Word line with air-gap for non-volatile memories
TW201803164A (zh) 用以使底部電極與垂直磁性穿隧接面（ｐｍｔｊ）裝置解耦的紋理斷裂層
WO2017052586A1 (en) High density memory array with self-aligned via
WO2023137642A1 (zh) 铁电存储器及其制造方法
KR20150040069A (ko) 테스트부를 갖는 반도체 장치, 이를 포함하는 전자 장치 및 그 테스트 방법
US20120256243A1 (en) Semiconductor device for reducing interconnect pitch
EP4016625A1 (en) Plate line architectures for 3d-ferroelectric random access memory (3d-fram)
WO2023039847A1 (zh) 阻变存储器单元、阻变存储器以及电子设备
US20130119461A1 (en) Semiconductor device having a buried gate and method for forming thereof
US20200243543A1 (en) 2s-1c 4f2 cross-point dram array

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280004455.3

Country of ref document: CN