WO2022166246A1 - 一种像素驱动电路、有源电致发光显示器及驱动方法 - Google Patents

一种像素驱动电路、有源电致发光显示器及驱动方法 Download PDF

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WO2022166246A1
WO2022166246A1 PCT/CN2021/123678 CN2021123678W WO2022166246A1 WO 2022166246 A1 WO2022166246 A1 WO 2022166246A1 CN 2021123678 W CN2021123678 W CN 2021123678W WO 2022166246 A1 WO2022166246 A1 WO 2022166246A1
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transistor
capacitor
voltage
light
circuit
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English (en)
French (fr)
Inventor
吴为敬
邹培安
刘淳
徐延港
梅相霖
徐苗
王磊
彭俊彪
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South China University of Technology SCUT
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South China University of Technology SCUT
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the invention relates to the field of optoelectronic display, in particular to a pixel driving circuit, an active electroluminescence display and a driving method.
  • micro light emitting diode (Micro LED) display technology Compared with traditional liquid crystal display (LCD) and organic light emitting diode display (OLED), micro light emitting diode (Micro LED) display technology has been widely used for its display advantages such as high brightness, high contrast, wide color gamut, long life, and nanosecond response speed. Known as the ultimate display technology. But at present, Micro LED display technology has encountered some technical challenges, including chip manufacturing, mass transfer, monolithic integration technology, colorization implementation scheme, driving circuit design, etc. Compared with OLED, Micro LED has very steep I-V characteristics, and the luminous efficiency decreases at low current density, and it will cause the color shift of Micro LED under different current driving, so its driving circuit cannot be copied. The driving circuit of OLED needs to be specially designed.
  • Micro LED display drive solutions which can be roughly divided into the following categories: passive drive solutions, CMOS active drive solutions, and TFT active drive solutions.
  • Passive driving means that the Micro LED does not emit light continuously during the display period of one frame, and its brightness is related to the duty cycle of the column strobe during the line scan period. With the improvement of the display screen resolution, the light-emitting time is getting shorter and shorter. , in order to improve the luminous brightness, the driving current can only be increased, which will increase the power consumption. Therefore, passive driving schemes can only be used on small-sized displays.
  • the active driving scheme can make the Micro LED emit light continuously, and CMOS or TFT can control the light emission of each pixel individually, which is suitable for high-resolution and large-scale displays.
  • the first object of the present invention is to provide a pixel driving circuit for an active electroluminescent display, which can shape the analog PWM pulse signal and ensure the display quality under low gray scale.
  • the second object of the present invention is to provide a driving method of a pixel driving circuit of an active electroluminescent display.
  • a third object of the present invention is to provide an active electroluminescent display.
  • the first purpose of the present invention adopts following technical scheme:
  • a pixel driving circuit of an active electroluminescent display comprising:
  • a current source comprising a drive transistor connected to the light-emitting element, providing drive currents having different amplitudes to the light-emitting element according to a voltage applied to a gate terminal of the drive transistor;
  • a current control circuit connected with the current source, for supplying voltages of different levels to the gate terminals of the drive transistors
  • a PWM generating circuit is used to generate a PWM pulse signal that controls the on-time of the light-emitting element
  • the shaping circuit is used to shape the PWM pulse signal
  • the PWM control circuit obtains the duration for controlling the driving current of the light-emitting element according to the shaped PWM pulse signal and the output voltage of the current control circuit.
  • the light-emitting element is a light-emitting diode or an organic light-emitting diode.
  • the PWM generating circuit includes a first capacitor, a second capacitor, a first transistor, a second transistor and a third transistor; the drain of the first transistor is connected to the first data signal line, and the source of the first transistor is connected to The first plate of the first capacitor, the gate of the first transistor is connected to the first scan control line; the drain of the second transistor is connected to the high-potential power supply, and the source of the second transistor is connected to the first electrode of the second capacitor plate and the drain of the third transistor, the gate of the second transistor is connected to the first scan control line; the source of the third transistor is connected to the low-potential power supply, and the gate of the third transistor is connected to the first plate of the first capacitor ; The second plate of the first capacitor is connected to the ramp signal data line; the second plate of the second capacitor is connected to the low-potential power supply.
  • the on-time of the first transistor is set according to the scanning signal of the gate of the first transistor, so as to control the voltage amplitude of the PWM pulse to charge the first capacitor;
  • the on-time of the second transistor is set according to the scanning signal of the gate of the second transistor, so as to control the voltage amplitude of the PWM pulse to charge the second capacitor;
  • the second data signal line starts to output a linear rising voltage signal, and loads it to the second plate of the first capacitor.
  • the voltage of the second plate of the first capacitor rises linearly.
  • the voltage of the first plate of the second capacitor will be discharged through the third transistor, thereby generating a PWM pulse signal. .
  • the PWM shaping circuit includes an inverter and a positive feedback circuit, one end of the positive feedback circuit is connected to the first plate of the second capacitor, the other end is connected to the input end of the inverter, and the output of the inverter is connected The terminal is connected to the PWM control circuit.
  • the inverter is composed of an N-type transistor, a P-type transistor, or a mixed-integrated transistor of the N-type and P-type.
  • the first transistor, the second transistor and the third transistor are all switching transistors.
  • the PWM control circuit includes a switching transistor, the gate of the switching transistor is connected to the output part of the inverter of the PWM shaping circuit, the drain is connected to the cathode part of the light-emitting element, and the source is connected to the drain part of the driving transistor.
  • the invention adopts a pre-charge and re-discharge type PWM generating circuit and a shaping circuit with a positive feedback circuit structure to realize microsecond level PWM rise and fall time control.
  • the PWM generation circuit pre-charges the storage capacitor to a high level through the upper transistor in the scan programming stage, then the ramp signal voltage rises slowly, and the lower transistor is gradually turned on to gradually discharge to a low level, thereby forming a PWM signal. Since the upper transistor is turned off when the capacitor discharges, the discharge speed is faster than that of the CMOS inverter structure.
  • the shaping circuit shapes the PWM signal through the structure of the inverter and the positive feedback circuit, connects the output part of the inverter to the input part of the positive feedback circuit, accelerates the discharge speed of the capacitor of the PWM generating circuit, and realizes the rise and fall of the microsecond level. time, so as to achieve precise constant current PWM control of the light-emitting element.
  • the second purpose of the present invention adopts following technical scheme:
  • a driving method for a pixel driving circuit of an active electroluminescent display comprising the following stages:
  • the light-emitting element emits light: the second data signal line starts to input a fixed voltage to the gate of the driving transistor, thereby controlling the current flowing in the light-emitting element; the PWM control circuit accepted by the PWM signal controls the duration of the current in the light-emitting element to realize the light-emitting element. of constant current PWM control.
  • the 3rd purpose of the present invention is to adopt following technical scheme:
  • An active light-emitting display includes pixel driving circuits arranged in an array.
  • the present invention utilizes pure N-type transistors or pure P-type transistors to achieve better PWM generation circuit effects than CMOS structures.
  • the pixel driving circuit of the present invention can realize microsecond-level PWM pulse width control, and can realize display control under low gray scale of the light-emitting element.
  • the driving method of the pixel circuit of the active electroluminescence display device of the present invention can adopt the scheme of scanning ramp, that is, the ramp signal is input after the scanning control signal of each row is input, which can realize a larger PWM pulse. width.
  • FIG. 1 is a structural block diagram of a pixel driving circuit of an active electroluminescent display of the present invention
  • Fig. 2 is the circuit diagram of Fig. 1;
  • FIG. 3 is a schematic diagram of an active electroluminescent display according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic diagram of a pixel driving circuit according to Embodiment 1 of the present invention.
  • Fig. 5 is the drive timing diagram of the circuit of Fig. 4 of the embodiment 1 of the present invention.
  • FIG. 6 is a schematic diagram of a pixel driving circuit according to Embodiment 2 of the present invention.
  • Fig. 7 is the drive timing chart of Fig. 7 of the present invention.
  • FIG. 8 is a schematic diagram of an active electroluminescent display according to Embodiment 3 of the present invention.
  • FIG. 9 is a schematic diagram of a pixel driving circuit according to Embodiment 3 of the present invention.
  • Fig. 10 is the driving timing diagram of Fig. 10 of the present invention.
  • FIG. 11 is a schematic diagram of an active electroluminescent display according to Embodiment 4 of the present invention.
  • FIG. 12 is a schematic diagram of a pixel driving circuit according to Embodiment 4 of the present invention.
  • FIG. 13 is a driving timing chart of Embodiment 4 of the present invention.
  • the structure of an active electroluminescent display is basically composed of a pixel array component Pixel, a scan driver Scan, a data input driver DATA, and a data input driver ba.
  • the pixel array components are connected to the scan lines SCAN arranged in rows, the first data signal lines and the second data signal lines arranged in columns, and the pixel array components also include a plurality of power lines for providing the necessary power for the pixel operation.
  • the first data signal line required for the operation of the pixel is used to control the pulse width of the PWM signal
  • the second data signal line is used to control the output current of the current source
  • the low-potential power supply VSS is also used for grounding
  • the high-potential power supply VDD is used to supply the
  • the pixel provides power supply
  • the first data signal line is the output of the data input driver DATA
  • the second data signal line is the output of the data input driver ba
  • the scan control line is output by the scan driver Scan
  • the ramp signal data line sweep generates the ramp data signal.
  • the pixel array component is composed of N ⁇ M pixel driving circuits, and the pixel driving circuits include
  • Light-emitting elements specifically light-emitting diodes or organic light-emitting diodes
  • a current source comprising a drive transistor connected to the light-emitting element, providing drive currents having different amplitudes to the light-emitting element according to a voltage applied to a gate terminal of the drive transistor;
  • a current control circuit connected with the current source, for supplying voltages of different levels to the gate terminals of the drive transistors
  • a PWM generating circuit is used to generate a PWM pulse signal that controls the on-time of the light-emitting element
  • the shaping circuit is used to shape the PWM pulse signal
  • the PWM control circuit obtains the duration for controlling the driving current of the light-emitting element according to the shaped PWM pulse signal and the output voltage of the current control circuit.
  • the PWM generating circuit includes a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2 and a third transistor T3; the drain of the first transistor T1 is connected to the first data signal line, and the first transistor
  • the source of T1 is connected to the first plate of the first capacitor C1, the gate of the first transistor T1 is connected to the first scan control line SCAN(N);
  • the drain of the second transistor T2 is connected to the high-potential power supply VDD, the first The source of the second transistor T2 is connected to the first plate of the second capacitor C2 and the drain of the third transistor T3, and the gate of the second transistor T2 is connected to the first scan control line SCAN(N);
  • the source is connected to the low-potential power supply VSS, the gate of the third transistor T3 is connected to the first plate of the first capacitor; the second plate of the first capacitor C2 is connected to the signal data line sweep; the second plate of the second capacitor The plate is connected to the low-potential power supply VSS.
  • the on-time of the first transistor is set according to the scanning signal of the gate of the first transistor, so as to control the voltage amplitude of the PWM pulse to charge the first capacitor;
  • the on-time of the second transistor is set according to the scanning signal of the gate of the second transistor, so as to control the voltage amplitude of the PWM pulse to charge the second capacitor;
  • the second data signal line starts to output a linear rising voltage signal, and loads it to the second plate of the first capacitor.
  • the voltage of the second plate of the first capacitor rises linearly.
  • the voltage of the first plate of the second capacitor will be discharged through the third transistor, thereby generating a PWM pulse signal. .
  • the shaping circuit includes an inverter and a positive feedback circuit, and specifically includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a ninth transistor T9 and a third capacitor C3.
  • the drain of the fourth transistor is connected to the high voltage.
  • the potential power supply VDD is connected, and its source is connected to the gate of the fifth transistor T5 and the first plate of the third capacitor C3 to form point C, and its gate is connected to the second scan control line SCAN(N+1).
  • the drain of the fifth transistor is connected to the high-potential power supply VDD, and the source of the fifth transistor is connected to the second plate of the third capacitor C3 to form point D, which is connected to the PWM control circuit.
  • the drain of the sixth transistor is connected to point D, the source of the sixth transistor is connected to the low-potential power supply VSS, the gate of the sixth transistor is connected to the drain of the ninth transistor and is connected to point B, and the source of the second transistor is connected to the third point.
  • the drain of the transistor is connected, and the source of the sixth transistor is connected to the second plate of the second power supply.
  • the source of the ninth transistor is connected to the low-potential power supply VSS.
  • the positive feedback circuit is the ninth transistor, and the inverter is the fourth, fifth and sixth transistors and the third capacitor.
  • the main function is to shape the PWM signal to reduce the rise and fall time of the PWM signal.
  • the shaping circuit may be further configured to, during the period when the second scan control line SCAN(N+1) of the gate terminal of the fourth switching transistor is turned on, use the power supply voltage to adjust the third capacitance of the third capacitor. One terminal charging.
  • the PWM control circuit only includes a seventh transistor T7, which is used to control the on-off of the current in the light-emitting element, the gate of which is connected to point D, the source is connected to the drain of the eighth transistor, and the drain is connected to the cathode of the light-emitting element.
  • the current source includes an eighth driving transistor T8, the eighth driving transistor operates in a saturation region, and the current control circuit is implemented by the second data signal Vba.
  • the current source is an eighth transistor, the current source is a driving transistor, and the other transistors are switching transistors.
  • the current source and the current control circuit are connected to jointly control the current flowing in the light-emitting element;
  • the PWM generation circuit and the shaping circuit can be connected through the second capacitor first plate and the drain of the ninth transistor, the PWM generation circuit, the shaping circuit Co-acting at the gate terminal of the seventh transistor, the voltage of the first plate of the first capacitor controls the duration of the current of the light-emitting element.
  • FIG. 5 is a timing chart illustrating a detailed operation of the pixel circuit according to Example Embodiment 1.
  • FIG. 5 shows the scan control lines Scan(n) and Scan(n+1), the data signal V DATA and the ramp signal data Vsweep applied to the pixel circuit, and the voltage at the gate of the third transistor T3 (point A) , the voltage at the first plate of the second capacitor C2 (point B), the voltage at the gate of the fifth transistor T5 (point C), the voltage at the gate of the seventh transistor T7 (point D), and the driving current Id according to time Variety.
  • the pixel circuit has completed four stages of initialization, inverter initialization, data loading and light-emitting element lighting.
  • the detailed operations of the pixel circuit in each stage are as follows:
  • the third transistor T3 is partially turned on, so that the potential of point B decreases slowly; at this time, when the potential of point B decreases to the stage of the threshold voltage VTH of the sixth transistor T6, the first The six transistors T6 are gradually turned off, and the voltage at point D is gradually increased.
  • the capacitive coupling effect of the third capacitor C3 the potential at point C rises with the potential at point D, and the fifth transistor T5 is in a better conduction state, thereby accelerating the potential at point D.
  • the ninth transistor T9 is gradually turned on, thereby accelerating the discharge process of the potential at point B, forming a positive feedback loop and accelerating the rising process of the potential at point D.
  • the light-emitting element emits light: in the data loading stage, the second data signal line changes from a low potential to a constant input voltage, and the potential at point D changes from a low potential to a high potential to load the gate of the seventh transistor T7, thereby making the first
  • the seven transistors are turned on, so that the light-emitting element, the seventh transistor T7 and the driving eighth transistor T8 form a path, and the second data signal line controls the driving of the eighth transistor T8 to form a constant current in the driving loop.
  • the structure of the active electroluminescent display of the second embodiment basically consists of a pixel array component Pixel, a scan driver Scan, a data input driver DATA, and a data input driver ba.
  • the pixel array components are all connected to the scan lines SCAN arranged in rows, the first data signal lines and the second signal data lines arranged in columns, and the pixel array components also include a plurality of power lines for providing the necessary power for the pixel operation.
  • the first data signal line required for the operation of the pixel is used to control the pulse width of the PWM signal
  • the second data signal line is used to control the output current of the current source
  • the low-potential power supply VSS is also used for grounding
  • the high-potential power supply VDD is used to supply the The pixel provides the power supply.
  • the display device of the active electroluminescence display is different from the first embodiment in that the CMOS structure is used as the design of the inverter, which reduces the power consumption of the pixel circuit during operation and achieves the effect of saving energy.
  • FIG. 6 is a circuit diagram of the pixel circuit of this example, including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 (P-type transistor), a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 , a first capacitor C1, a second capacitor C2, a high-potential power supply line VDD, a second data signal line ba, a low-potential power supply line VSS, a first data signal line DATA, a ramp data signal Vsweep, and a light-emitting element.
  • the first transistor T1 and the second transistor T2 are in response to the scan control line Scan(n) of the nth row, and the seventh transistor T7 is controlled by the second data signal Vba to output a constant current.
  • the seventh transistor is a driving transistor.
  • the PWM generation circuit may include: a first capacitor having a first terminal connected to a gate terminal of the third transistor and a source terminal of the first transistor; and a second capacitor having a drain terminal connected to the third transistor and a first terminal The first terminal of the source terminal of the two transistors.
  • the PWM generation circuit may be further configured to apply a pulse width control voltage to all of the scan control lines (SCAN(n)) of the nth row of the gate terminals of the first and second transistors during the period when the gate terminals of the first and second transistors are turned on. charging the first capacitor and applying the voltage charged into the first capacitor to the gate terminal of the third transistor; charging the second capacitor with the supply voltage, charging the second capacitor to the same level as the supply voltage same.
  • SCAN(n) scan control lines
  • the shaping circuit may be composed of an inverter and a positive feedback circuit, including: an eighth transistor having a gate segment connected to the drain terminal of the fourth transistor and the drain terminal of the fifth transistor; and having a gate segment connected to the fourth transistor and the drain terminal of the fifth transistor; The drain terminal of the gate terminal of five transistors; the fourth transistor is a P-type transistor, wherein the inverter is the fourth transistor T4 and the fifth transistor T5, and the positive feedback circuit is the eighth transistor T8.
  • the PWM control module may include a sixth transistor, the current source module may include a seventh drive transistor, the seventh drive transistor operates in a saturation region, and the current control circuit is implemented by the second data signal Vba.
  • the current source and the current control circuit are connected to jointly control the current flowing in the light-emitting element;
  • the PWM generation circuit and the shaping circuit can be connected through the first terminal of the second capacitor and the drain of the eighth feedback transistor, and the PWM generation circuit, shaping The circuit cooperates at the gate terminal of the sixth switching transistor to control the duration of the current of the light emitting element by the voltage of the first terminal of the first capacitor.
  • the current source is the seventh transistor T7.
  • FIG. 7 is a timing chart illustrating a detailed operation of the pixel circuit according to Example Embodiment 1.
  • FIG. 7 shows the main control signal Scan(n), the data signal lines DATA and Vsweep applied to the pixel circuit, the voltage at the gate of the third transistor T3 (point A), and the first plate of the second capacitor C2 Variation of the voltage at (point B) and the gate of the sixth transistor T6 (point C) and the driving current I d as a function of time.
  • the pixel circuit Under the control of these control signals and data signals, the pixel circuit has completed three stages of initialization, data loading and light-emitting element lighting. The detailed operations of the pixel circuit in each stage are as follows:
  • the third transistor T3 is partially turned on, so that the potential of point B decreases slowly; at this time, when the potential of point B decreases to the stage of the threshold voltage V TH of the transistor T5, the fifth transistor T5 is gradually turned off.
  • the fourth transistor When the threshold voltage VTH of T4 is reached, the fourth transistor is gradually turned on, and the voltage at point C gradually increases; when the voltage at point C reaches the threshold voltage VTH of the eighth transistor, the voltage at point B is discharged through the eighth transistor T8, thereby accelerating point B
  • the discharge process of the potential forms a positive feedback loop, which accelerates the rising process of the potential at point C.
  • the light-emitting element emits light: in the data loading stage, the second data signal line changes from a low potential to a constant input voltage, and the potential at point C changes from a low potential to a high potential to load the gate of the sixth transistor T6, thereby making the first
  • the seven transistors are turned on, so that the light-emitting element, the sixth transistor T6 and the seventh transistor T7 form a path, and the second data signal line controls the seventh transistor T7 to form a constant current in the driving loop.
  • the structure of an active electroluminescent display in Embodiment 3 basically consists of a pixel array component Pixel, a scan driver Scan, a data input driver DATA, and a data input driver ba.
  • the pixel array components are connected to the scan lines SCAN arranged in rows, the first data signal lines and the second data signal lines arranged in columns, and the pixel array components also include a plurality of power lines for providing the necessary power for the pixel operation.
  • the first data signal line required for the operation of the pixel is used to control the pulse width of the PWM signal
  • the second data signal line is used to control the output current of the current source
  • the low-potential power supply VSS is also used for grounding
  • the high-potential power supply VDD is used to supply the
  • the pixel provides power supply
  • the first data signal line is the output of the data input driver DATA
  • the second data signal line is the output of the data input driver ba
  • the scan control line is output by the scan driver Scan
  • the ramp signal data line sweep generates the ramp data signal.
  • the display device of the active electroluminescence display is different from the first embodiment in that the display device of the electroluminescence display uses a P-type transistor as the design of the inverter, and uses the method of discharging and then charging to avoid phase inversion.
  • the device generates a DC path during operation to reduce power consumption.
  • FIG. 9 is a circuit diagram showing a pixel array part formed on the display device shown in FIG. 8 .
  • the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 (PMOSFET), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a seventh transistor T8,
  • the fifth transistor T5 responds to the second scan control line Scan2(n) of the nth row
  • the seventh transistor T7 is controlled by the second data signal Vba and output constant current.
  • the seventh transistor is a driving transistor.
  • the PWM generation circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1 and a second capacitor C2, the first capacitor having a gate terminal connected to the third transistor and a source of the first transistor a first terminal of the terminal; and a second capacitor having a first terminal connected to the drain terminal of the third transistor and the source terminal of the second transistor.
  • the PWM generation circuit may be further configured to apply a pulse width control voltage to all the first scan control lines SCAN1(n) in the nth row of the gate terminals of the first and second transistors during the period when the gate terminals of the first and second transistors are turned on. charging the first capacitor and applying the voltage charged into the first capacitor to the gate terminal of the third transistor; charging the second capacitor with the supply voltage, charging the second capacitor to the same level as the supply voltage same.
  • the shaping circuit may be composed of an inverter and a positive feedback circuit, including: an eighth transistor having a gate segment connected to a drain terminal of the fourth transistor; and a drain terminal having a gate terminal connected to the fourth transistor; Three capacitors with a first terminal connected to the source terminal of the fifth transistor and the gate terminal of the eighth feedback transistor; the fourth and fifth transistors are P-type transistors.
  • the inverter is a fourth transistor, a fifth transistor and a third capacitor.
  • the positive feedback circuit is the eighth transistor T8.
  • the shaping circuit may be further configured to, during the period in which the second scan control line SCAN2(n) of the nth row of the gate terminal of the fifth transistor is turned on, use the power supply voltage to adjust the third capacitance of the third capacitor. One plate discharges.
  • the PWM control module may include a sixth transistor, the current source module may include a seventh drive transistor, the seventh drive transistor operates in a saturation region, and the current control circuit is implemented by the second data signal Vba.
  • the current source and the current control circuit are connected to jointly control the current flowing in the light-emitting element; the PWM generation circuit and the shaping circuit can be connected through the first terminal of the second capacitor and the drain of the eighth feedback transistor, and the PWM generation circuit and the shaping circuit can be connected. Co-acting at the gate terminal of the sixth transistor, the voltage at the first terminal of the first capacitor controls the duration of the current flow to the light emitting element.
  • FIG. 10 is a timing chart illustrating a detailed operation of a pixel circuit according to Example Embodiment 3.
  • FIG. 10 shows the main control signals Scan1(n) and Scan2(n), the data signals V DATA and Vsweep applied to the pixel circuit, the voltage at the gate of the third transistor T3 (point A), the second capacitor C2 The voltage at the first plate (point B) and the gate of the seventh transistor T7 (point C) and the driving current I d vary with time.
  • the pixel circuit has completed three stages of initialization, data loading and light-emitting element lighting. The detailed operations of the pixel circuit in each stage are as follows:
  • the scan control line Scan1(n) of the pixel in the nth row is set to a high level, and the scan control line Scan2(n) is set to a low level, and the first transistor T1, the second transistor T2 and the fifth transistor T5 are respectively turned on
  • the first plate of the first capacitor C1 of the pixel circuit is set to the data voltage V DATA
  • the first plate of the second capacitor C2 is configured to be the high-level power supply voltage VDD
  • One plate is configured to be the low-level power supply voltage VSS; at this time, the fourth transistor T4 is turned off, the potential of point C is configured to be VSS, and the level setting is completed.
  • the third transistor T3 is partially turned on, so that the potential of point B is slowly reduced; at this time, when the potential of point B is reduced to the stage of the threshold voltage VTH of the switching transistor T4 , the fourth transistor T4 is gradually turned on, and the voltage at point C gradually increases; due to the increase in the potential at point C, the ninth transistor T9 is gradually turned on, thereby accelerating the discharge process of the potential at point B, forming a positive feedback loop to accelerate the potential at point D. ascent process.
  • the light-emitting element emits light: in the data loading stage, Vba changes from a low potential to a constant input voltage, and the potential at point C changes from a low potential to a high potential to load the gate of the sixth transistor T6, so that the sixth switch transistor conducts
  • the light-emitting element, the sixth transistor T6 and the seventh transistor T7 form a path, and the second data signal Vba controls the seventh transistor T7 to form a constant current in the driving loop.
  • the device basically consists of a pixel array part Pixel, a scan driver Scan and a data input driver DATA.
  • the pixel array components are all connected with scan lines SCAN arranged in rows, first data signal lines DATA and second data signal lines arranged in columns, the pixel array components also include a plurality of power lines and control signals for providing the pixel Required for operation, a low-level power supply VSS, a high-level power supply VDD, a reference voltage Vref, and a control signal CV.
  • the first data line required for the operation of the pixel is used to control the pulse width of the PWM signal
  • the second data line acts on the drive transistor to provide a stable current to the light-emitting element
  • the low-potential power supply VSS is also used for grounding
  • the high-potential power supply VDD For supplying power to the pixel, the reference voltage Vref is used for a predetermined potential setting, and the control signal CV is used to separate the compensation phase and the light-emitting phase.
  • the display device of the active electroluminescence display realizes the compensation of the pulse width of the PWM signal and the compensation of the current flowing through the light-emitting element by using the multiplexing of the scan driver, which improves the display uniformity of the display device and reduces the The peripheral driver design of the display device is presented.
  • FIG. 12 is a circuit diagram showing a pixel array part formed on the display device shown in FIG. 11 .
  • the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, tenth transistor T10, eleventh transistor T11, twelfth transistor T12, thirteenth transistor T13, fourteenth transistor T14, fifteenth transistor T15, sixteenth transistor T16, first capacitor C1, second Capacitor C2, third capacitor C3, high-potential power supply VDD, second data signal line, low-potential power supply VSS, first data signal line, reference voltage Vref, control signal CV, light-emitting element.
  • the first transistor and the eleventh transistor respond to the scan control line of the n-1th row
  • the tenth transistor, the twelfth transistor and the thirteenth transistor respond to the scan control line of the nth row
  • the second transistor responds to the scan control line of the nth row.
  • the fourth transistor responds to the scan control line of row n+2
  • the fourteenth transistor, the fifteenth transistor and the sixteenth transistor respond to the control signal CV
  • the sixth transistor responds to the th Two data signals V ba .
  • the PWM generating circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a first capacitor C1 and a second transistor Capacitor C2: a first capacitor having a first plate connected to the gate terminal of the third transistor and the source of the first transistor and the source of the thirteenth transistor; and a second capacitor having a first plate connected to the second transistor the source and the first plate of the source terminal of the fifteenth transistor; the twelfth transistor with the gate connected to the gate of the thirteenth transistor, and the drain connected to the fourteenth transistor and the third transistor the source of the source.
  • the PWM generation circuit may be further configured to charge the first capacitor with an initialization voltage during a period when the scan control line SCAN(n-1) of the n-1th row of the gate terminal of the first transistor is turned on , and the voltage charged into the first capacitor is applied to the gate terminal of the third transistor; the nth row scan control line SACN(n) of the gate terminals of the twelfth and thirteenth transistors ) and is turned on, the data voltage is coupled to the first terminal of the first capacitor through the third transistor and the thirteenth transistor; the gate terminal of the second transistor obtains the n+1th row scan control line SCAN(n+ 1) During the conduction period, the first terminal of the second capacitor is charged with the power supply voltage, and the second capacitor is charged to be the same as the power supply voltage; The control signal CV is turned on. And the threshold voltage compensation design can be realized for the third transistor T3.
  • the shaping circuit may be composed of an inverter and a positive feedback circuit, including: a third capacitor having a first plate connected to the source of the fourth transistor and the gate of the fifth transistor; having a drain connected to the sixth transistor and the second plate of the gate of the ninth transistor; the gate of the sixth transistor is connected to the drain of the ninth feedback transistor.
  • the inverter includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a third capacitor C3.
  • the positive feedback circuit includes a ninth transistor T9.
  • the shaping circuit may be further configured to apply a power supply voltage to the third capacitor during the period when the scan signal SCAN(n+1) of the n+1th row of the gate terminal of the fourth transistor is turned on. The first terminal is charged.
  • the PWM control module may include a seventh transistor and a sixteenth transistor, the current source module may include an eighth drive transistor, the eighth drive transistor operates in a saturation region, and the current control circuit may include a fourth capacitor having a connection The first terminal to the source terminal of the eleventh transistor, the drain terminal of the tenth transistor, and the gate terminal of the eighth driving transistor.
  • the current source and the current control circuit are connected to jointly control the current flowing in the light-emitting element; the PWM generation circuit and the shaping circuit can be connected through the first terminal of the second capacitor and the drain of the ninth feedback transistor, and the PWM generation circuit and the shaping circuit can be connected. Co-acting at the gate terminal of the seventh transistor, the voltage at the first terminal of the first capacitor controls the duration of the current flow to the light emitting element.
  • the current source is the eighth transistor T8, which is specifically a driving transistor.
  • the current control circuit includes T10, T11, and C4, which can perform threshold voltage compensation design for T8.
  • FIG. 13 is a timing chart illustrating a detailed operation of a pixel circuit according to Example Embodiment 4.
  • FIG. 13 shows the main control signals (scan control lines) Scan(n-1), Scan(n), Scan(n+1) and Scan(n+2) applied to the pixel circuit, CV, first The data signal line, the second data signal line and Vsweep, the reference voltage Vref, the voltage at the gate of the third transistor T3 (point A), the voltage at the first plate of the second capacitor C2 (point B), the third capacitor C3 The voltage at the first plate (point C), the voltage at the gate of the seventh switching transistor T7 (point D), the voltage at the gate of the eighth transistor T8 (point E), and the change of the driving current I d according to time.
  • the pixel circuit has completed five stages of initialization, threshold voltage compensation stage, light-emitting initialization stage, data loading and light-emitting element lighting. The detailed operation of the pixel circuit in each stage
  • the scan control line Scan(n+1) of the n+1th row changes from low level to high level
  • the scan control line Scan(n) and the scan control line Scan(n+2) of the n+2th row are given a low level
  • the control signal CV continues to output a low level
  • the second transistor is turned on accordingly
  • the fourth transistor T4 the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are turned off accordingly
  • the potential of point B is configured as high level VDD, so that the sixth transistor T6 is turned on, and point D is configured to be low level
  • the scan control line Scan(n+2) of the n+2th row is changed from low level to high level.
  • the n-1th row The scan control line Scan(n-1), the scan control line Scan(n) of the nth row, and the scan control line Scan(n+1) of the n+1th row output a low level, so that the fourth transistor T4 is turned on , the third transistor is turned off, and point C is configured as a high level, thus completing the voltage configuration for the above points.
  • the scan control line Scan(n-1) of the n-1th row, the scan control line Scan(n) of the nth row, the scan control line Scan(n+1) of the n+1th row, and the n+th row The scan control line Scan(n+2) of the 2 rows outputs a low level, the control signal CV outputs a high level, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the transistors T10-T13 correspond to Turn off, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are turned on accordingly; the Vsweep voltage begins to increase linearly from a low level to a high level.
  • the third transistor T3 is partially turned on.
  • the sixth transistor T6 is gradually turned on, and the voltage of point D gradually increases; because the potential of point D rises , the ninth transistor T9 is gradually turned on, thereby accelerating the discharge process of the potential at point B, forming a positive feedback loop to accelerate the rising process of the potential at point D; at this time, the light-emitting time of the light-emitting element is:
  • the threshold voltage shift of the third transistor T3 has no influence on the light-emitting time of the light-emitting element.
  • the light-emitting element emits light: in the data loading stage, Vba changes from a low potential to a constant input voltage, and the potential at point C changes from a low potential to a high potential to load the gate of the seventh transistor T7, so that the seventh transistor is turned on , so that the light-emitting element, the sixteenth transistor T16, the seventh transistor T7 and the eighth transistor T8 form a path, and the second data signal Vba controls and drives the eighth transistor T8 to form a constant current in the drive loop; the voltage at point E at this time Keep it constant, it is Vba+V TH_T8 , so the light-emitting element emits the corresponding brightness, and the current flowing through the light-emitting element is:
  • V gs is the potential difference between the gate and the source of the eighth transistor T8, ⁇ n is the carrier mobility of the eighth transistor T8, C OX is the gate insulating layer capacitance of the eighth transistor T8, W/L is the aspect ratio of the driving transistor T8, Vba is the data voltage, Vth is the threshold voltage of the eighth transistor T8, and VDD is the applied power supply voltage.

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Abstract

一种像素驱动电路、有源电致发光显示器及驱动方法，像素驱动电路包括：发光元件；电流源，包括与发光元件相连接的驱动晶体管，根据施加在驱动晶体管栅极端子的电压向发光元件提供具有不同幅度的驱动电流；电流控制电路，与电流源连接，用于向驱动晶体管栅极端子提供不同电平的电压；PWM产生电路，用于产生控制发光元件导通时间的PWM脉冲信号；整形电路，用于对PWM脉冲信号进行整形；PWM控制电路，根据整形后的PWM脉冲信号获得用于控制发光元件驱动电流的持续时间。像素驱动电路在每一行的扫描控制信号输入之后随之就输入斜坡信号，能够实现较大的PWM脉宽。

Description

一种像素驱动电路、有源电致发光显示器及驱动方法 技术领域
本发明涉及光电显示领域，具体涉及一种像素驱动电路、有源电致发光显示器及驱动方法。
背景技术
相比于传统液晶显示(LCD)和有机发光二极管显示(OLED)，微发光二极管(Micro LED)显示技术凭借高亮度，高对比度，色域广，长寿命，纳秒级别响应速度的显示优势被誉为终极显示技术。但是目前Micro LED显示技术遇到了一些技术挑战，包括芯片制造，巨量转移，单片集成技术，彩色化实现方案，驱动电路设计等。由于Micro LED相比于OLED而言，Micro LED具有非常陡峭的I-V特性，在小电流密度下出现发光效率下降，且在不同电流驱动下会导致Micro LED色偏的问题，因此其驱动电路不能照搬OLED的驱动电路，需要重新专门设计。
目前，已经有不少研究团队和公司发表Micro LED的显示驱动方案，大致可以分为以下几类：无源驱动方案，CMOS有源驱动方案和TFT有源驱动方案。无源驱动是指Micro LED在一帧的显示周期不是持续发光的，其亮度与行扫描期间内列选通时的占空比有关，随着显示屏分辨率的提升，发光时间越来越短，为了提升发光亮度，只能增大驱动电流，这会造成功耗的增加。因此，无源驱动方案只能使用小尺寸的显示屏上。与之相反，有源驱动方案能够使得Micro LED持续发光，CMOS或TFT可以单独控制每一个像素发光，适用于高分辨率和大尺寸的显示。
尽管现有技术中有人提出了基于PWM(脉冲脉宽调制)的Micro LED的有源驱动方案，但是对于有源数字PWM驱动方案来说，由于用分子帧的方法表示灰度，所以能够表示的灰度的数量有限，并且产生错误的轮廓问题。而对于有源模拟PWM驱动方案来说，由于斜坡控制信号的斜率设置比较小，导致所产生的PWM信号的上升时间或下降时间比较长，使得Micro LED在低灰阶的显示会产生色偏、亮度不均匀等情况。
因此，需要对有源模拟PWM驱动产生的PWM信号进行整形，提高低灰阶显示情况下的色彩及亮度均匀性的问题。
发明内容
为了克服现有技术存在的缺点与不足，本发明的第一个目的提供一种有源电致发光显示器的像素驱动电路，可以对模拟PWM脉冲信号进行整形，保证低灰阶下的显示质量。
本发明的第二个目的是提供一种有源电致发光显示器的像素驱动电路的驱动方法。
本发明的第三个目的是提供一种有源电致发光显示器。
本发明的第一个目的采用如下技术方案：
一种有源电致发光显示器的像素驱动电路，包括：
发光元件；
电流源，包括与所述发光元件相连接的驱动晶体管，根据施加在驱动晶体管栅极端子的电压向发光元件提供具有不同幅度的驱动电流；
电流控制电路，与电流源连接，用于向驱动晶体管栅极端子提供不同电平的电压；
PWM产生电路，用于产生控制发光元件导通时间的PWM脉冲信号；
整形电路，用于对PWM脉冲信号进行整形；
PWM控制电路，根据上述整形后的PWM脉冲信号及电流控制电路输出电压获得用于控制发光元件驱动电流的持续时间。
进一步，所述发光元件为发光二极管或有机发光二极管。
进一步，所述PWM产生电路包括第一电容、第二电容、第一晶体管、第二晶体管及第三晶体管；所述第一晶体管的漏极连接第一数据信号线，第一晶体管的源极连接第一电容的第一极板，第一晶体管的栅极连接第一扫描控制线；所述第二晶体管的漏极连接着高电位电源，第二晶体管的源极连接第二电容的第一极板和第三晶体管的漏极，第二晶体管的栅极连接第一扫描控制线；所述第三晶体管的源极连接低电位电源，第三晶体管的栅极连接第一电容的第一极板；所述第一电容的第二极板连接斜坡信号数据线；所述第二电容的第二极板连接低电位电源。
进一步，根据所述第一晶体管栅极的扫描信号设置第一晶体管的导通时间，用于控制PWM脉冲的电压幅度对所述第一电容进行充电；
根据所述第二晶体管栅极的扫描信号设置第二晶体管的导通时间，用于控制PWM脉冲的电压幅度对所述第二电容进行充电；
在所有像素的第一电容和第二电容都接收到数据后，第二数据信号线开始输出线性的上升电压信号，并加载到第一电容的第二极板，通过第一电容的耦合效应，使得第一电容的第二极板的电压线性上升，在该电压达到第三晶体管的阈值电压V TH时，第二电容的第一极板的电压会通过第三晶体管放电，从而产生PWM脉冲信号。
进一步，PWM整形电路包括反相器及正反馈电路，所述正反馈电路一端与第二电容的第一极板连接，其另一端与反相器的输入端连接，所述反相器的输出端与PWM控制电路连接。
进一步，所述反相器由N型晶体管、P型晶体管或N型和P型混合集成的晶体管构成。
进一步，第一晶体管、第二晶体管及第三晶体管均为开关晶体管。
进一步，所述PWM控制电路包括开关晶体管，开关晶体管的栅极连接到PWM整形电路的反相器的输出部分，漏极连接至发光元件的阴极部分，源极连接至驱动晶体管的漏极部分。
本发明采用预充电再放电式的PWM产生电路和带正反馈电路结构的整形电路实现微秒级的 PWM上升下降时间控制。
所述PWM产生电路在扫描编程阶段通过上晶体管给存储电容预充电至高电位，然后斜坡信号电压缓慢上升，下晶体管逐渐导通使逐渐放电至低电平，从而形成PWM信号。由于电容放电时上晶体管已关断，放电速度相比于CMOS反相器结构速度快。所述整形电路通过反相器和正反馈电路结构对PWM信号进行整形，将反相器的输出部分连接到正反馈电路的输入部分，加速PWM产生电路的电容放电速度，实现微秒级的上升下降时间，从而实现对发光元件精确的恒流PWM控制。
本发明的第二个目的采用如下技术方案：
一种有源电致发光显示器的像素驱动电路的驱动方法，包括如下阶段：
(1)初始化：PWM产生电路上晶体管通过扫描信号打开，对电容进行充电，随后关闭，在电容上储存高电位。
(2)数据加载阶段：扫描信号控制晶体管，将数据电压储存在电容上，随后晶体管关闭，实现数据电压的储存。在此阶段还可通过驱动信号的设计实现对驱动晶体管和PWM产生电路的下晶体管的阈值电压补偿，数据加载完毕后，斜坡数据线sweep开始输入，并线性上升。
(3)发光元件发光：第二数据信号线开始输入固定电压到驱动晶体管栅极，从而控制发光元件中流过的电流；PWM信号接受的PWM控制电路控制发光元件中电流的持续时间，实现发光元件的恒定电流的PWM控制。
本发明的第三个目的是采用如下技术方案：
一种有源发光显示器，包括呈阵列排布的像素驱动电路。
本发明的有益效果：
1、本发明利用纯N型晶体管或纯P型晶体管实现比CMOS结构更优异的PWM产生电路效果。
2、本发明的像素驱动电路可以实现微秒级的PWM脉宽控制，并且能实现发光元件低灰阶下的显示控制。
3、本发明的有源电致发光显示装置的像素电路的驱动方法能够采用扫描式斜坡的方案，即在每一行的扫描控制信号输入之后随之就输入斜坡信号，能够实现较大的PWM脉宽。
附图说明
图1是本发明一种有源电致发光显示器的像素驱动电路的结构框图；
图2是图1的电路图；
图3是本发明实施例1的有源电致发光显示器示意图；
图4是本发明实施例1的像素驱动电路示意图；
图5是本发明实施例1图4电路的驱动时序图；
图6是本发明实施例2的像素驱动电路的示意图；
图7是本发明图7的驱动时序图；
图8是本发明实施例3的有源电致发光显示器的示意图；
图9是本发明实施例3的像素驱动电路的示意图；
图10是本发明图10的驱动时序图；
图11是本发明实施例4的有源电致发光显示器的示意图；
图12是本发明实施例4的像素驱动电路示意图；
图13是本发明实施例4的驱动时序图。
具体实施方式
下面结合实施例及附图，对本发明作进一步地详细说明，但本发明的实施方式不限于此。
实施例1
如图3所示，一种有源电致发光显示器的结构，该设备基本上由像素阵列部件Pixel、扫描驱动器Scan和数据输入驱动器DATA、数据输入驱动器ba。像素阵列部件都连接着以行排列的扫描线SCAN、以列排列的第一数据信号线和第二数据信号线，该像素阵列部件还包括多个电源线，用于提供该像素操作所需要的低电位电源VSS和高电位电源VDD。像素的操作所需要的第一数据信号线用于控制PWM信号脉宽，第二数据信号线用于控制电流源的输出电流，低电位电源VSS也用于接地，高电位电源VDD用于向该像素提供供电电源，第一数据信号线为数据输入驱动器DATA输出，第二数据信号线为数据输入驱动器ba输出，扫描控制线由扫描驱动器Scan输出，斜坡信号数据线sweep产生斜坡数据信号。
如图1及图2所示，像素阵列部件由N×M个像素驱动电路构成，像素驱动电路，包括
发光元件，具体为发光二极管或有机发光二极管
电流源，包括与所述发光元件相连接的驱动晶体管，根据施加在驱动晶体管栅极端子的电压向发光元件提供具有不同幅度的驱动电流；
电流控制电路，与电流源连接，用于向驱动晶体管栅极端子提供不同电平的电压；
PWM产生电路，用于产生控制发光元件导通时间的PWM脉冲信号；
整形电路，用于对PWM脉冲信号进行整形；
PWM控制电路，根据上述整形后的PWM脉冲信号及电流控制电路输出电压获得用于控制发光元件驱动电流的持续时间。
本实施例1中：
所述PWM产生电路包括第一电容C1、第二电容C2、第一晶体管T1、第二晶体管T2及第三晶体管T3；所述第一晶体管T1的漏极连接第一数据信号线，第一晶体管T1的源极连接第一电容C1的第一极板，第一晶体管T1的栅极连接第一扫描控制线SCAN(N)；所述第二晶体管T2的漏极连接着高电位电源VDD，第二晶体管T2的源极连接第二电容C2的第一极板和第三晶体管T3的漏极，第二晶体管T2的栅极连接第一扫描控制线SCAN(N)；所述第三晶体管T3的源极连接低电位电源VSS，第三晶体管T3的栅极连接第一电容的第一极板；所述第一电容C2的第二极板连接信号数据线sweep；所述第二电容的第二极板连接低电位电源VSS。
其工作过程为：
根据所述第一晶体管栅极的扫描信号设置第一晶体管的导通时间，用于控制PWM脉冲的电压幅度对所述第一电容进行充电；
根据所述第二晶体管栅极的扫描信号设置第二晶体管的导通时间，用于控制PWM脉冲的电压幅度对所述第二电容进行充电；
在所有像素的第一电容和第二电容都接收到数据后，第二数据信号线开始输出线性的上升电压信号，并加载到第一电容的第二极板，通过第一电容的耦合效应，使得第一电容的第二极板的电压线性上升，在该电压达到第三晶体管的阈值电压V TH时，第二电容的第一极板的电压会通过第三晶体管放电，从而产生PWM脉冲信号。
所述整形电路包括反相器及正反馈电路，具体包括第四晶体管T4、第五晶体管T5、第六晶体管T6、第九晶体管T9及第三电容C3，所述第四晶体管的漏极与高电位电源VDD连接，其源极与第五晶体管T5的栅极及第三电容C3的第一极板连接，形成C点，其栅极与第二扫描控制线SCAN(N+1)连接。
所述第五晶体管的漏极与高电位电源VDD连接，其源极与第三电容C3的第二极板连接，形成D点，D点与PWM控制电路连接。
所述第六晶体管的漏极与D点连接，其源极与低电位电源VSS连接，其栅极与第九晶体管的漏极连接于B点，B点与第二晶体管的源极与第三晶体管的漏极连接，第六晶体管的源极与第二电源的第二极板连接。
所述第九晶体管的源极与低电位电源VSS连接。
正反馈电路为第九晶体管，反相器为第四、第五、第六晶体管及第三电容。主要作用为对PWM信号整形，以减小PWM信号的上升下降时间。
所述整形电路可以进一步被配置为在所述第四开关晶体管的栅极端子的第二扫描控制线SCAN(N+1)而导通的期间，用电源电压对所述的第三电容的第一端子充电。
所述PWM控制电路仅包括第七晶体管T7，用于控制发光元件中电流的通断，其栅极与D点连接，源极与第八晶体管的漏极连接，漏极与发光元件的阴极连接。电流源包括第八驱动晶体 管T8，所述第八驱动晶体管工作在饱和区域，所述电流控制电路通过第二数据信号Vba实现。
所述电流源为第八晶体管，电流源为驱动晶体管，其他晶体管为开关晶体管。
所述电流源和电流控制电路连接共同控制发光元件中流过的电流；所述PWM产生电路和整形电路可以通过第二电容第一极板和第九晶体管的漏极连接，PWM产生电路、整形电路共同作用在第七晶体管的栅极端子，从而通过第一电容的第一极板的电压控制发光元件的电流的持续时间。
图5是说明根据示例实施例1的像素电路的详细操作的时序图。具体的图5示出了施加到像素电路的扫描控制线Scan(n)和Scan(n+1)、数据信号V DATA和斜坡信号数据Vsweep，第三晶体管T3的栅极处(A点)电压、第二电容C2的第一极板处(B点)电压、第五晶体管T5的栅极处(C点)电压和第七晶体管T7栅极处(D点)电压以及驱动电流Id根据时间的变化。像素电路在这些控制信号和数据信号的控制下，完成了初始化、反相器初始化、数据加载和发光元件发光四个阶段，每个阶段的像素电路的详细操作如下：
(1)初始化：第n行像素的扫描控制线Scan(N)给高电平，扫描控制线Scan(N+1)给低电平，第一晶体管T1和第二晶体管T2相应导通，第四晶体管T4关闭；此时，像素电路的第一电容C1的第一极板被设置成了数据电压V DATA，第二电容C2的第一极板被配置为高电平电源电压VDD；此时，第六晶体管T6的打开，D点电位被配置为VSS，完成了对这几点的电平设定。
(2)反相器初始化：第n行像素的扫描控制线Scan(N+1)给高电平，扫描控制线Scan(N)给低电平，第一晶体管T1和第二晶体管T2关闭，第四晶体管相应导通；此时像素电路的C点被配置为高电平电源电压VDD，由于第六晶体管始终处于打开状态，D点在此阶段被配置为VSS，从而在第三电容C3两端形成了VDD-VSS的电压差，完成对反向器的初始化。
(3)数据加载：第n行像素的扫描控制线Scan(N)和Scan(N+1)都处于低电平，第一晶体管T1、第二晶体管T2、第四晶体管T4关闭；Vsweep电压开始由低电平线性的增长为高电平，由于第一电容C1的电容耦合效应，第一电容C1的第一极板A点的电压为V A＝V DATA+V sweep-VSS，在A点电压还未达到第三晶体管T3的阈值电压VTH时，第三晶体管T3部分导通，使得B点电位缓慢降低；此时，当B点电位降低到第六晶体管T6的阈值电压VTH的阶段，第六晶体管T6逐渐关闭，D点的电压逐渐升高，第三电容C3由于电容耦合效应，使得C点的电位跟随D点的电位上升，第五晶体管T5导通状态更好，从而加速D点电位的上升；由于D点电位上升，第九晶体管T9逐渐导通，从而加速B点电位的放电过程，形成一个正反馈回路，加速D点电位的上升过程。
(4)发光元件发光：在数据加载阶段，第二数据信号线由低电位转变为输入恒定的电压，D点电位从低电位变为高电位加载到第七晶体管T7的栅极，从而使得第七晶体管导通，从而发光元件、第七晶体管T7和驱动第八晶体管T8形成通路，第二数据信号线控制驱动第八晶体管 T8在驱动回路中形成恒定的电流。
实施例2
如图3所示，本实施例2的有源电致发光显示器的结构，该设备基本上由像素阵列部件Pixel、扫描驱动器Scan和数据输入驱动器DATA、数据输入驱动器ba。像素阵列部件都连接着以行排列的扫描线SCAN、以列排列的第一数据信号线和第二信号数据线，该像素阵列部件还包括多个电源线，用于提供该像素操作所需要的低电位电源VSS和高电位电源VDD。像素的操作所需要的第一数据信号线用于控制PWM信号脉宽，第二数据信号线用于控制电流源的输出电流，低电位电源VSS也用于接地，高电位电源VDD用于向该像素提供供电电源。
该有源电致发光显示器的显示装置，与实施例1不同的是利用CMOS结构作为反相器的设计，送而减少了像素电路工作时的功耗，实现了节约能源的效果。
图6是本实例像素电路的电路图，包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4(P型晶体管)、第五晶体管T5、第六晶体管T6、第七晶体管T7、第一电容C1、第二电容C2、高电位电源线VDD、第二数据信号线ba、低电位电源线VSS、第一数据信号线DATA、斜坡数据信号Vsweep、发光元件。并且第一晶体管T1和第二晶体管T2响应于第n行扫描控制线Scan(n)，第七晶体管T7受控于第二数据信号Vba而输出恒定电流。
所述第七晶体管为驱动晶体管。
PWM产生电路可以包括：第一电容，具有连接到第三晶体管的栅极端子和第一晶体管的源极端子的第一端子；和第二电容，具有连接到第三晶体管的漏极端子和第二晶体管的源极端子的第一端子。
所述PWM产生电路可以进一步被配置为在所述第一晶体管和第二晶体管的栅极端子的第n行扫描控制线(SCAN(n))而导通的期间，用脉宽控制电压对所述第一电容充电，并且将充电到所述第一电容中的电压施加到所诉第三晶体管的栅极端子；用电源电压对所述第二电容充电，将第二电容充电到与电源电压相同。
整形电路可以由反相器和正反馈电路构成，包括：第八晶体管，具有连接至第四晶体管的漏极端子和第五晶体管的漏极端子的栅极段子；和具有连接至第四晶体管和第五晶体管的栅极端子的漏极端子；所述第四晶体管为P型晶体管，其中反相器为第四晶体管T4及第五晶体管T5，正反馈电路为第八晶体管T8。
所述PWM控制模块可以包括第六晶体管，电流源模块可以包括第七驱动晶体管，所述第七驱动晶体管工作在饱和区域，所述电流控制电路通过第二数据信号Vba实现。
所述电流源和电流控制电路连接共同控制发光元件中流过的电流；所述PWM产生电路和整形电路可以通过第二电容的第一端子和第八反馈晶体管的漏极连接，PWM产生电路、整形电路共同作用在第六开关晶体管的栅极端子，从而通过第一电容的第一端子的电压控制发光元件 的电流的持续时间。
本实施例中电流源为第七晶体管T7。
图7是说明根据示例实施例1的像素电路的详细操作的时序图。具体的图7示出了施加到像素电路的主控制信号Scan(n)、数据信号线DATA和Vsweep，第三晶体管T3的栅极处(A点)电压、第二电容C2的第一极板处(B点)电压和第六晶体管T6栅极处(C点)电压以及驱动电流I d根据时间的变化。像素电路在这些控制信号和数据信号的控制下，完成了初始化、数据加载和发光元件发光三个阶段，每个阶段的像素电路的详细操作如下：
(1)初始化：第n行像素的扫描控制线Scan(n)给高电平，第一晶体管T1和第二晶体管T2相应导通；此时，像素电路的第一电容C1的第一极板被设置成了数据电压V DATA，第二电容C2的第一极板被配置为高电平电源电压VDD；此时，第六晶体管T6的打开，C点电位被配置为VSS，完成了对这几点的电平设定。
(2)数据加载：第n行像素的扫描控制线Scan(n)处于低电平，第一晶体管T1、第二晶体管T2；Vsweep电压开始由低电平线性的增长为高电平，由于第一电容C1的电容耦合效应，第一电容C1的第一极板A点的电压为V A＝V DATA+V sweep-VSS，在A点电压还未达到第三开关晶体管T3的阈值电压V TH时，第三晶体管T3部分导通，使得B点电位缓慢降低；此时，当B点电位降低到晶体管T5的阈值电压V TH的阶段，第五晶体管T5逐渐关闭，当B点电位降低到晶体管T4的阈值电压V TH时，第四晶体管逐渐打开，C点的电压逐渐升高；C点电压达到第八晶体管的阈值电压V TH时，B点电压通过第八晶体管T8放电，从而加速B点电位的放电过程，形成一个正反馈回路，加速C点电位的上升过程。
(3)发光元件发光：在数据加载阶段，第二数据信号线由低电位转变为输入恒定的电压，C点电位从低电位变为高电位加载到第六晶体管T6的栅极，从而使得第七晶体管导通，从而发光元件、第六晶体管T6和第七晶体管T7形成通路，第二数据信号线控制第七晶体管T7在驱动回路中形成恒定的电流。
实施例3
如图8所示，本实施例3的一种有源电致发光显示器的结构，该设备基本上由像素阵列部件Pixel、扫描驱动器Scan和数据输入驱动器DATA、数据输入驱动器ba。像素阵列部件都连接着以行排列的扫描线SCAN、以列排列的第一数据信号线和第二数据信号线，该像素阵列部件还包括多个电源线，用于提供该像素操作所需要的低电位电源VSS和高电位电源VDD。像素的操作所需要的第一数据信号线用于控制PWM信号脉宽，第二数据信号线用于控制电流源的输出电流，低电位电源VSS也用于接地，高电位电源VDD用于向该像素提供供电电源，第一数据信号线为数据输入驱动器DATA输出，第二数据信号线为数据输入驱动器ba输出，扫描控制线由扫描驱动器Scan输出，斜坡信号数据线sweep产生斜坡数据信号。
该有源电致发光显示器的显示装置，与实施例1不同的是该电致发光显示器的显示装置，利用P型晶体管作为反相器的设计，并且使用先放电再充电的方式，避免反相器在工作过程中产生直流通路，降低功耗。
图9是显示形成在图8所示的显示装置上的像素阵列部件的电路图。参照图9，像素电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4(PMOSFET)、第五晶体管T5、第六晶体管T6、第七晶体管T7、第七晶体管T8、第一电容C1、第二电容C2、第三电容C3、高电位电源线VDD、第二数据信号Vba、低电位电源线线VSS、数据线DATA、数据线Vsweep、发光元件；并且第一晶体管T1和第二晶体管T2响应于第n行第一扫描控制线Scan1(n)，第五晶体管T5响应于第n行第二扫描控制线Scan2(n)、第七晶体管T7受控于第二数据信号Vba而输出恒定电流。
第七晶体管为驱动晶体管。
PWM产生电路可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第一电容C1及第二电容C2，第一电容，具有连接到第三晶体管的栅极端子和第一晶体管的源极端子的第一端子；和第二电容，具有连接到第三晶体管的漏极端子和第二晶体管的源极端子的第一端子。
所述PWM产生电路可以进一步被配置为在所述第一晶体管和第二晶体管的栅极端子的第n行第一扫描控制线SCAN1(n)而导通的期间，用脉宽控制电压对所述第一电容充电，并且将充电到所述第一电容中的电压施加到所诉第三晶体管的栅极端子；用电源电压对所述第二电容充电，将第二电容充电到与电源电压相同。
整形电路可以由反相器和正反馈电路构成，包括：第八晶体管，具有连接至第四晶体管的漏极端子的栅极段子；和具有连接至第四晶体管的栅极端子的漏极端子；第三电容，具有连接至第五晶体管的源极端子和第八反馈晶体管的栅极端子的第一端子；所述第四晶体管和第五晶体管为P型晶体管。
所述反相器为第四晶体管、第五晶体管及第三电容。正反馈电路为第八晶体管T8。
所述整形电路可以进一步被配置为在所述第五晶体管的栅极端子的第n行第二扫描控制线SCAN2(n)而导通的期间，用电源电压对所述的第三电容的第一极板放电。
所述PWM控制模块可以包括第六晶体管，电流源模块可以包括第七驱动晶体管，所述第七驱动晶体管工作在饱和区域，所述电流控制电路通过第二数据信号Vba实现。
所述电流源和电流控制电路连接共同控制发光元件中流过的电流；所述PWM产生电路和整形电路可以通过第二电容第一端子和第八反馈晶体管的漏极连接，PWM产生电路、整形电路共同作用在第六晶体管的栅极端子，从而通过第一电容的第一端子的电压控制发光元件的电流的持续时间。
图10是说明根据示例实施例3的像素电路的详细操作的时序图。具体的图10示出了施加到像素电路的主控制信号Scan1(n)和Scan2(n)、数据信号V DATA和Vsweep，第三晶体管T3的栅极处(A点)电压、第二电容C2的第一极板处(B点)电压和第七晶体管T7栅极处(C点)电压以及驱动电流I d根据时间的变化。像素电路在这些控制信号和数据信号的控制下，完成了初始化、数据加载和发光元件发光三个阶段，每个阶段的像素电路的详细操作如下：
(1)初始化：第n行像素的扫描控制线Scan1(n)给高电平，扫描控制线Scan2(n)给低电平，第一晶体管T1、第二晶体管T2和第五晶体管T5相应导通；此时，像素电路的第一电容C1的第一极板被设置成了数据电压V DATA，第二电容C2的第一极板被配置为高电平电源电压VDD，第三电容的第一极板被配置为低电平电源电压VSS；此时，第四晶体管T4关闭，C点电位被配置为VSS，完成了的电平设定。
(2)数据加载：第n行像素的扫描控制线Scan1(n)处于低电平、Scan2(n)处于高电平，第一晶体管T1、第二晶体管T2、第五晶体管T5关闭；Vsweep电压开始由低电平线性的增长为高电平，由于第一电容C1的电容耦合效应，第一电容C1的第一极板A点的电压为V A＝V DATA+V sweep-VSS，在A点电压还未达到第三晶体管T3的阈值电压V TH时，第三晶体管T3部分导通，使得B点电位缓慢降低；此时，当B点电位降低到开关晶体管T4的阈值电压V TH的阶段，第四晶体管T4逐渐打开，C点的电压逐渐升高；由于C点电位上升，第九晶体管T9逐渐导通，从而加速B点电位的放电过程，形成一个正反馈回路，加速D点电位的上升过程。
(3)发光元件发光：在数据加载阶段，Vba由低电位转变为输入恒定的电压，C点电位从低电位变为高电位加载到第六晶体管T6的栅极，从而使得第六开关晶体管导通，从而发光元件、第六晶体管T6和第七晶体管T7形成通路，第二数据信号V ba控制第七晶体管T7在驱动回路中形成恒定的电流。
实施例4
如图11所示，本实施例4的有源电致发光显示器的显示装置的一般结构。该设备基本上由像素阵列部件Pixel、扫描驱动器Scan和数据输入驱动器DATA。像素阵列部件都连接着以行排列的扫描线SCAN、以列排列的第一数据信号线DATA和第二数据信号线，该像素阵列部件还包括多个电源线和控制信号，用于提供该像素操作所需要，低电位电源VSS、高电位电源VDD、参考电压Vref和控制信号CV。像素的操作所需要的第一数据线用于控制PWM信号的脉宽，第二数据线作用于驱动晶体管用于向发光元件提供稳定的电流，低电位电源VSS也用于接地，高电位电源VDD用于向该像素提供供电电源，参考电压Vref用于预定的电势设置、控制信号CV用于分隔补偿阶段和发光阶段。该有源电致发光显示器的显示装置，利用对扫描驱动器的复用实现了对于PWM信号的脉宽的补偿以及对发光元件流过的电流的补偿，提升了显示装置的显示的均匀性，减少了显示装置的外围的驱动设计。
图12是显示形成在图11所示的显示装置上的像素阵列部件的电路图。参照图12，像素电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第一电容C1、第二电容C2、第三电容C3、高电位电源VDD、第二数据信号线、低电位电源VSS、第一数据信号线、参考电压Vref、控制信号CV、发光元件。并且第一晶体管和第十一晶体管响应于第n-1行的扫描控制线，第十晶体管、第十二晶体管和第十三晶体管响应于第n行的扫描控制线，第二晶体管响应与第n+1行的扫描控制线，第四晶体管响应与第n+2行的扫描控制线，第十四晶体管、第十五晶体管和第十六晶体管响应于控制信号CV，第六晶体管响应于第二数据信号V ba。
PWM产生电路包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第一电容C1及第二电容C2：第一电容，具有连接到第三晶体管的栅极端子和第一晶体管的源极和第十三晶体管的源极的第一极板；和第二电容，具有连接到第二晶体管的源极和第十五晶体管的源极端子的第一极板；第十二晶体管，具有连接至第十三晶体管的栅极的栅极，和连接至第十四晶体管的漏极和第三晶体管的源极的源极。
所述PWM产生电路可以进一步被配置为在所述第一晶体管栅极端子的第n-1行扫描控制线SCAN(n-1)而导通的期间，用初始化电压对所述第一电容充电，并且将充电到所述第一电容中的电压施加到所诉第三晶体管的栅极端子；所述第十二晶体管和第十三晶体管的栅极端子的第n行扫描控制线SACN(n)而导通的期间，数据电压通过第三晶体管和第十三晶体管耦合到第一电容的第一端子；所述第二晶体管的栅极端子得到第n+1行扫描控制线SCAN(n+1)导通的期间，用电源电压给第二电容的第一端子充电，将第二电容充电到与电源电压相同；通过第二所述第十四晶体管和第十五晶体管的栅极端子的控制信号CV而导通。并能对第三晶体管T3实现阈值电压补偿设计。
整形电路可以由反相器和正反馈电路构成，包括：第三电容，具有连接到第四晶体管的源极和第五晶体管的栅极的第一极板；具有连接到第六晶体管的漏极和第九晶体管的栅极的第二极板；所述第六晶体管的栅极连接至所述第九反馈晶体管的漏极。
所述反相器包括第四晶体管T4、第五晶体管T5、第六晶体管T6及第三电容C3。所述正反馈电路包括第九晶体管T9。
所述整形电路可以进一步被配置为在所述第四晶体管的栅极端子的第n+1行扫描信号SCAN(n+1)而导通的期间，用电源电压对所述的第三电容的第一端子充电。
所述PWM控制模块可以包括第七晶体管和第十六晶体管，电流源模块可以包括第八驱动晶 体管，所述第八驱动晶体管工作在饱和区域，所述电流控制电路可以包括第四电容，具有连接至第十一晶体管的源极端子、第十晶体管的漏极端子和第八驱动晶体管的栅极端子的第一端子。
所述电流源和电流控制电路连接共同控制发光元件中流过的电流；所述PWM产生电路和整形电路可以通过第二电容第一端子和第九反馈晶体管的漏极连接，PWM产生电路、整形电路共同作用在第七晶体管的栅极端子，从而通过第一电容的第一端子的电压控制发光元件的电流的持续时间。
本实施例中电流源为第八晶体管T8，具体为驱动晶体管。
电流控制电路包括T10,T11,C4作用可以对T8进行阈值电压补偿设计。
图13是说明根据示例实施例4的像素电路的详细操作的时序图。具体的图13示出了施加到像素电路的主控制信号(扫描控制线)Scan(n-1)、Scan(n)、Scan(n+1)和Scan(n+2)，CV，第一数据信号线、第二数据信号线和Vsweep，参考电压Vref、第三晶体管T3的栅极处(A点)电压、第二电容C2的第一极板处(B点)电压、第三电容C3的第一极板处(C点)电压、第七开关晶体管T7栅极处(D点)电压和第八晶体管T8栅极处(E点)电压以及驱动电流I d根据时间的变化。像素电路在这些控制信号和数据信号的控制下，完成了初始化、阈值电压补偿阶段、发光初始化阶段、数据加载和发光元件发光五个阶段，每个阶段的像素电路的详细操作如下：
(1)初始化：第n-1行的扫描控制线Scan(n-1)给高电平，第一晶体管T1和第十一晶体管相应导通；第n行的扫描控制线Scan(n)、第n+1行的扫描控制线Scan(n+1)、第n+2行的扫描控制线Scan(n+2)给低电平，控制信号CV给低电平，第二晶体管T2、第四晶体管T4、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管、第十五晶体管T15、第十六晶体管关闭；像素电路中的A点和E点被设置成了参考电压Vref，完成了对A点和E点的电平重置。
(2)阈值电压锁存阶段：第n行的扫描控制线Scan(n)给高电平，第n-1行的扫描控制线Scan(n-1)、第n+1行的扫描控制线Scan(n+1)、第n+2行的扫描控制线Scan(n+2)给低电平，控制信号CV持续给低电平，第十晶体管T10、第十二晶体管T12、第十三晶体管T13相应导通；第一晶体管T1、第二晶体管T2、第四晶体管T4、第十一晶体管T11、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16相应关闭；此时，A点通过第十二晶体管T12和第十三晶体管T13向V DATA放电，直到A点的电压为V A＝V DATA+V TH_T3；E点通过第十晶体管T10和第八晶体管T8向VSS放电，知道E点的电压为V E＝V TH_T8，从而将第十三晶体管T3和驱动晶体管T8的阈值电压分别锁存在A点和E点。
(3)发光初始化：第n+1行的扫描控制线Scan(n+1)由低电平变为高电平，第n-1行的扫描控制线Scan(n-1)、第n行的扫描控制线Scan(n)、第n+2行的扫描控制线Scan(n+2)给低电平， 控制信号CV持续输出低电平，第二晶体管相应导通，第一晶体管T1、第四晶体管T4、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16相应关闭；B点电位被配置为高电平VDD，使得第六晶体管T6打开，D点被配置为低电平；随后第n+2行的扫描控制线Scan(n+2)由低电平变为高电平第n-1行的扫描控制线Scan(n-1)、第n行的扫描控制线Scan(n)、第n+1行的扫描控制线Scan(n+1)输出低电平，从而使得第四晶体管T4打开，第三晶体管关闭，C点被配置为高电平，从而完成对以上几点的电压配置。
(4)第n-1行的扫描控制线Scan(n-1)、第n行的扫描控制线Scan(n)、第n+1行的扫描控制线Scan(n+1)、第n+2行的扫描控制线Scan(n+2)输出低电平，控制信号CV输出高电平，第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、晶体管T10～T13相应关闭，第十四晶体管T14、第十五晶体管T15、第十六晶体管T16相应导通；Vsweep电压开始由低电平线性的增长为高电平，由于第一电容C1的电容耦合效应，第一电容C1的第一极板A点的电压为V A＝V DATA+V TH_T3+V sweep-VSS，在A点电压还未达到第三晶体管T3的阈值电压V TH_T3时，第三晶体管T3部分导通，使得B点电位缓慢降低；此时，当B点电位降低到第六晶体管T6的阈值电压V TH的阶段，第六晶体管T6逐渐打开，D点的电压逐渐升高；由于D点电位上升，第九晶体管T9逐渐导通，从而加速B点电位的放电过程，形成一个正反馈回路，加速D点电位的上升过程；此时发光元件的发光时间为：
Figure PCTCN2021123678-appb-000001
能保证第三晶体管T3的阈值电压漂移对发光元件的发光时间没有影响。
(5)发光元件发光：在数据加载阶段，Vba由低电位转变为输入恒定的电压，C点电位从低电位变为高电位加载到第七晶体管T7的栅极，从而使得第七晶体管导通，从而发光元件、第十六晶体管T16、第七晶体管T7和第八晶体管T8形成通路，第二数据信号V ba控制驱动第八晶体管T8在驱动回路中形成恒定的电流；此时E点的电压维持恒定，为Vba+V TH_T8，所以发光元件发出相应的亮度，而且流过发光元件的电流为：
Figure PCTCN2021123678-appb-000002
其中，V gs为第八晶体管T8的栅极和源极之间的电势差，μ n为第八晶体管T8的载流子迁移 率，C OX为第八晶体管T8的栅绝缘层电容，W/L为驱动晶体管T8的宽长比，V ba为数据电压，V th为第八晶体管T8的阈值电压，VDD为所加的电源电压。从上式可以看出，流过发光元件的电流与第八晶体管T8的阈值电压V th_T8和发光元件的开启电压无关，所以该像素电路在驱动晶体管阈值电压漂移和发光元件的情况下，能保持流过发光元件的电流恒定，并且能保证第三晶体管T3的阈值电压漂移对发光元件的发光时间没有影响。
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受所述实施例的限制，其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。

Claims (10)

  1. 一种有源电致发光显示器的像素驱动电路，其特征在于，包括：
    发光元件；
    电流源，包括与所述发光元件相连接的驱动晶体管，根据施加在驱动晶体管栅极端子的电压向发光元件提供具有不同幅度的驱动电流；
    电流控制电路，与电流源连接，用于向驱动晶体管栅极端子提供不同电平的电压；
    PWM产生电路，用于产生控制发光元件导通时间的PWM脉冲信号；
    整形电路，用于对PWM脉冲信号进行整形；
    PWM控制电路，根据上述整形后的PWM脉冲信号及电流控制电路输出电压获得用于控制发光元件驱动电流的持续时间。
  2. 根据权利要求1所述的像素驱动电路，其特征在于，所述发光元件为发光二极管或有机发光二极管。
  3. 根据权利要求1所述的像素驱动电路，其特征在于，所述PWM产生电路包括第一电容、第二电容、第一晶体管、第二晶体管及第三晶体管；所述第一晶体管的漏极连接第一数据信号线，第一晶体管的源极连接第一电容的第一极板，第一晶体管的栅极连接第一扫描控制线；所述第二晶体管的漏极连接着高电位电源，第二晶体管的源极连接第二电容的第一极板和第三晶体管的漏极，第二晶体管的栅极连接第一扫描控制线；所述第三晶体管的源极连接低电位电源，第三晶体管的栅极连接第一电容的第一极板；所述第一电容的第二极板连接斜坡信号数据线；所述第二电容的第二极板连接低电位电源。
  4. 根据权利要求3所述的像素驱动电路，其特征在于，
    根据所述第一晶体管栅极的扫描信号设置第一晶体管的导通时间，用于控制PWM脉冲的电压幅度对所述第一电容进行充电；
    根据所述第二晶体管栅极的扫描信号设置第二晶体管的导通时间，用于控制PWM脉冲的电压幅度对所述第二电容进行充电；
    在所有像素的第一电容和第二电容都接收到数据后，第二数据信号线开始输出线性的上升电压信号，并加载到第一电容的第二极板，通过第一电容的耦合效应，使得第一电容的第二极板的电压线性上升，在该电压达到第三晶体管的阈值电压V TH时，第二电容的第一极板的电压会通过第三晶体管放电，从而产生PWM脉冲信号。
  5. 根据权利要求4所述的像素驱动电路，其特征在于，PWM整形电路包括反相器及正反馈电路，所述正反馈电路一端与第二电容的第一极板连接，其另一端与反相器的输入端连接，所述反相器的输出端与PWM控制电路连接。
  6. 根据权利要求5所述的像素驱动电路，其特征在于，所述反相器为N型晶体管、P型晶体管或N型和P型混合集成的晶体管。
  7. 根据权利要求3所述的像素驱动电路，其特征在于，第一晶体管、第二晶体管及第三晶体管均为开关晶体管。
  8. 根据权利要求1-6任一项所述的像素驱动电路，其特征在于，所述PWM控制电路包括开关晶体管，开关晶体管的栅极连接到PWM整形电路的反相器的输出部分，漏极连接至发光元件的阴极部分，源极连接至驱动晶体管的漏极部分。
  9. 一种有源电致发光显示器的像素驱动电路的驱动方法，其特征在于，包括如下步骤：
    (1)初始化：第n行像素的扫描控制线给高电平，第一晶体管和第二晶体管相应导通，数据电压通过第一晶体管传输到第一电容的第一极板，第二电容的第一极板通过第二晶体管被设置为高电平；
    (2)数据加载阶段：第n行像素的扫描控制线处于低电平，第一晶体管、第二晶体管关闭；斜坡信号数据线开始由低电平线性的增长为高电平，由于第一电容的电容耦合效应，第一电容的第一极板的电压为V DATA+V sweep-VSS，在电压还未达到第三晶体管的阈值电压V TH时，第三晶体管部分导通，使得第二电容的第一极板电位缓慢降低；此时，当此电位降低到反相器的阈值电压时，反相器的输出电压逐渐升高；反相器的输出电压达到反馈晶体管的阈值电压V TH时，第二电容的第一极板电压通过反馈晶体管放电，从而加速第二电容的第一极板的放电过程，形成一个正反馈回路，加速反相器输出电位的上升过程；
    (3)发光元件发光：在所有阶段中第二数据信号线持续输入恒定的电压；在数据加载阶段，反相器输出电位从低电位变为高电位加载到驱动回路开关晶体管的栅极，从而使得开关晶体管导通，从而发光元件、开关晶体管和驱动晶体管形成通路，第二数据信号线控制驱动晶体管在驱动回路中形成恒定的电流。
  10. 一种有源发光显示器，其特征在于，包括呈阵列排布的如权利要求1-8任一项所述的像素驱动电路。
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