WO2022165817A1 - 场效应管及其制造方法 - Google Patents

场效应管及其制造方法 Download PDF

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Publication number
WO2022165817A1
WO2022165817A1 PCT/CN2021/075884 CN2021075884W WO2022165817A1 WO 2022165817 A1 WO2022165817 A1 WO 2022165817A1 CN 2021075884 W CN2021075884 W CN 2021075884W WO 2022165817 A1 WO2022165817 A1 WO 2022165817A1
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Prior art keywords
trench
substrate
gate
channel
layer
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PCT/CN2021/075884
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English (en)
French (fr)
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袁晓龙
沈健
姚国峰
柳玉平
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2021/075884 priority Critical patent/WO2022165817A1/zh
Priority to CN202180004267.6A priority patent/CN114127949A/zh
Publication of WO2022165817A1 publication Critical patent/WO2022165817A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Definitions

  • the embodiments of the present application relate to the technical field of semiconductors, and in particular, to a field effect transistor and a method for manufacturing the same.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • Fin Field-Effect Transistor In the field of digital chip manufacturing, Fin Field-Effect Transistor (FinFET) technology is a typical solution and is widely used in the industry.
  • one of the technical problems solved by the embodiments of the present invention is to provide a field effect transistor and a manufacturing method thereof, which can reduce the device layout area of the field effect transistor under the condition of ensuring the requirements of device characteristics.
  • a field effect transistor includes: a substrate provided with a source electrode and a drain electrode, and a carrier transport channel is formed between the source electrode and the drain electrode channel, wherein the carrier transport channel forms a channel surface with at least one trench at the surface of the substrate; a gate dielectric layer covers the channel surface with at least one trench; a gate electrode, disposed on the gate dielectric layer, wherein the gate is surrounded by gate spacers, the at least one trench extends beyond the coverage area of the gate, the at least one trench The extension range does not exceed the coverage area of the gate spacer.
  • a method for manufacturing a field effect transistor comprising: forming a channel surface of a carrier transport channel having at least one groove on a surface of a substrate, wherein , the carrier transport channel is located between the source electrode and the drain electrode in the substrate; a gate dielectric layer is formed to cover the surface of the channel having at least one groove; in the gate dielectric layer On top of that, a gate is formed.
  • the channel surface of the carrier transport channel has at least one groove, which increases the effective width of the carrier transport channel.
  • the projected area of the carrier transport channel on the substrate is reduced, thereby reducing the device layout area of the field effect transistor.
  • a carrier transport channel with uniform effective length is provided for the channel on the substrate surface and the trench channel, so the device has a good electrical model characterization its electrical capabilities.
  • the extension range of at least one trench does not exceed the coverage area of the gate spacer, it is avoided that the trench is filled with a dielectric during the manufacturing process of the field effect transistor, and the source PN junction or the source PN junction or the The increase of the outer surrounding area of the drain PN junction leads to the increase of the junction capacitance of the PN junction, and also avoids the increase of the parasitic capacitance from the gate to the source or the parasitic capacitance from the gate to the drain. The occurrence of problems such as adverse effects on the field effect transistor, thereby reducing the performance difference between the field effect transistor and the traditional field effect transistor.
  • FIG. 1 is a schematic perspective view of a field effect transistor according to a first embodiment of the present application
  • FIG. 2 is a schematic plan view of a field effect transistor according to an example of the first embodiment of the application
  • 3A is a schematic cross-sectional view of a field effect transistor according to another example of the first embodiment of the present application.
  • 3B is a schematic cross-sectional view of another example of a field effect transistor according to the first embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of a field effect transistor according to another example of the first embodiment of the present application.
  • FIG. 5A is a schematic diagram of an exemplary trench arrangement manner of the field effect transistor according to the first embodiment of the present application.
  • FIG. 5B is a schematic diagram of another example of a trench arrangement manner of the field effect transistor according to the first embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a method for manufacturing a field effect transistor according to a second embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a method for manufacturing a field effect transistor according to an example of the second embodiment of the present application.
  • FIG. 8 is a schematic diagram of a manufacturing method of the field effect transistor of FIG. 7 of the present application.
  • FIG. 9 is a schematic flowchart of a manufacturing method of a field effect transistor according to another example of the second embodiment of the present application.
  • FIG. 10 is a schematic diagram of a method for manufacturing the field effect transistor of FIG. 9 of the present application.
  • FIG. 1 is a schematic perspective view of a field effect transistor according to a first embodiment of the present application.
  • FIG. 1 shows a field effect transistor of a first embodiment.
  • the field effect transistor includes a substrate 10 , a carrier transfer channel 20 and a gate 30 .
  • the carrier transport channel 20 forms a channel surface having at least one groove 21 at the surface of the substrate 10 .
  • FIG. 2 is a plan view of FIG. 1 .
  • 3A, 3B and 4 are cross-sectional views taken along the section line A-A', section line B-B' and section line C-C' in FIGS. 1 and 2, respectively.
  • stub AA' and stub BB' are along the length of the carrier transport channel 20, and stub AA' passes through the non-trench portion in the channel surface, Stub BB' passes through the trench portion in the channel surface.
  • the stub C-C' is along the width direction of the carrier transport channel 20.
  • the substrate 10 is provided with a source electrode 11 and a drain electrode 12 , and a carrier transport channel 20 is formed between the source electrode 11 and the drain electrode 12 .
  • the carrier transport channel 20 includes source electrodes on both sides in the length direction, respectively. 11 and drain 12.
  • the source electrode 11 and the drain electrode 12 are formed by the source doped region and the drain doped region through doping.
  • FIG. 2 also shows the gate spacer 33, the gate 30 and the gate dielectric layer 40 are surrounded by the gate spacer 33 (spacer, may also be referred to as a gate spacer), the extension of at least one trench 21 Beyond the coverage area of the gate 30 , the extension of the at least one trench 21 does not exceed the coverage area of the gate spacer 33 .
  • a gate dielectric layer 40 covers the surface of the channel having at least one trench 21 .
  • the gate dielectric layer 40 is formed along the channel surface such that the channel surface is on one side of the gate dielectric layer 40 .
  • the gate 30 is disposed on the gate dielectric layer 40 .
  • the gate 30 is formed along the other side of the gate dielectric layer 40 .
  • Corresponding low-doped regions 13 are also included in the vicinity of the source electrode 11 and the drain electrode 12 , and the carrier concentration in the low-doped region of the source electrode 11 is smaller than that of the source electrode 11 .
  • the carrier concentration in the low-doped region of the drain 12 is smaller than that of the drain 12 .
  • the oxide layer 30 and the low-doped region 13 are located at a deeper position in the substrate than the example of FIG. 3A .
  • the length L of the carrier transport channel 20 may be the distance between the low-doped regions 13 .
  • the depth of the source electrode 11 and the drain electrode 12 in the direction perpendicular to the surface of the substrate 10 is the PN junction depth Hpn.
  • the trench 21 includes a bottom wall and two side walls, and the depth Htr of the trench 21 in the direction perpendicular to the surface of the substrate 10 is the distance between the bottom wall of the trench 21 and the surface of the substrate 10 .
  • the width Wtr of the trench 21 is the distance between the two side walls in the width direction.
  • carrier transport channels 20 are located between device isolation trenches 15 .
  • the carrier transport channel 20 is formed with a channel surface at the surface of the substrate 10 , and the channel surface includes a portion having the groove 21 and a portion not having the groove 21 .
  • the gate dielectric layer 40 may be interposed between the carrier transport channel 20 and the gate 30 .
  • the gate is made of polysilicon material, and the gate dielectric layer is silicon oxide; or the gate is made of polysilicon material, and the gate dielectric layer is silicon oxynitride; or the gate is made of metal material, and the gate dielectric layer is It includes a layered high dielectric constant material layer and silicon oxide, and the silicon oxide layer is interposed between the substrate and the high dielectric constant material layer.
  • the gate 30 is formed using a polysilicon (PolySiON) gate process technology, and the gate dielectric layer 40 may be formed of silicon oxide as the gate dielectric.
  • the gate 30 is formed using a High-K Metal Gate (HKMG) technology, the gate 30 includes a metal ion blocking layer, an etching protection layer, a work function adjustment layer, a gate composed of extremely metal electrode layers.
  • the channel surface of the carrier transport channel has at least one groove, which increases the effective width in the carrier transport channel.
  • the projected area of the carrier transport channel on the surface of the substrate is reduced, thereby reducing the device layout area of the field effect transistor.
  • a carrier transport channel with uniform effective length is provided for the channel on the substrate surface and the trench channel, so the device has a good electrical model characterization its electrical capabilities.
  • the extension range of at least one trench does not exceed the coverage area of the gate spacer, it is avoided that the trench is filled with a dielectric during the manufacturing process of the field effect transistor, and the source PN junction or the source PN junction or the The increase of the outer surrounding area of the drain PN junction leads to the increase of the junction capacitance of the PN junction, and also avoids the increase of the parasitic capacitance from the gate to the source or the parasitic capacitance from the gate to the drain. The occurrence of problems such as adverse effects on the field effect transistor, thereby improving the performance of the field effect transistor.
  • the field effect transistor may further include a Halo ion implantation region.
  • each of the at least one trench (eg, in the case of one trench, each trench refers to the trench; in the case of multiple trenches, each trench The trench refers to each of the plurality of trenches) including two sidewalls that are substantially perpendicular to the surface of the substrate, and a bottom wall connected between the two sidewalls and having a height difference with the surface of the substrate, the trenches
  • the channel surface includes two sidewalls, a bottom wall, and a top surface that is substantially flush with the surface of the substrate, wherein a gate dielectric layer overlies the channel surface with substantially the same thickness.
  • the surface of the channel includes two side walls of each of the multiple trenches, a bottom wall, and a top surface that is substantially flush with the surface of the substrate.
  • the carrier transport channel has a length direction between the source electrode and the drain electrode, and at least one trench extends in the length direction to form an extension range. Since the trench is formed in the carrier transport channel in the length direction between the source and the drain, any cross section in the length direction of the carrier transport channel has an increased size due to the trench. The effective width of the carrier transport channel, thus improving the performance of the carrier transport channel.
  • the extension length of the at least one trench is greater than the length of the gate in the length direction. Since the extension length of the trench is greater than the length of the gate, the migration of carriers in the carrier transport channel is more stable and reliable, thereby further improving the performance of the carrier transport channel.
  • the channel length at the trench is equal to the channel length at the substrate surface, so that there are no two channel lengths formed after the trench is introduced, which is beneficial for subsequent Extraction and establishment of an integrated circuit simulation program (Simulation program with integrated circuit emphasis, SPICE) model. Otherwise, it will make the model complicated and difficult to converge.
  • SPICE Simulation program with integrated circuit emphasis
  • the substrate may be implemented as a silicon substrate with trenches longer than polysilicon, or trenches longer than dummy gates in the HKMG process (ie, removed in a process flow after gate formation) part) length.
  • FIG. 5A shows one example groove arrangement
  • FIG. 5B shows another example groove arrangement.
  • the two FETs are short-circuited in series due to the common source or drain of one end.
  • the gate spacing of two adjacent devices is very close.
  • the trenches protrude from both sides of the gate spacers, possible polysilicon etching residues during the manufacturing process may lead to shorts between the gates of the device (as shown by the shaded portion in FIG. 5A ).
  • the pitch is too small, trench elongation due to process errors may cause shorts, as shown in Figure 5A.
  • the trench will be filled with a dielectric in the subsequent process flow, resulting in a change in the conductive cross-sectional area of the source or drain. small, so that the on-resistance of the entire device becomes larger when it is working.
  • the outer surrounding area of the source PN junction or the drain PN junction will increase, which will directly lead to an increase in the junction capacitance of the PN junction and also increase the gate electrode. An increase in the parasitic capacitance to the source, or the parasitic capacitance from the gate to the drain, adversely affects the device.
  • the gate spacers form the first spacer portion and the second spacer portion in the length direction, and the extension length of at least one trench is greater than the inner wall and the second side of the first spacer portion
  • the distance between the inner walls of the wall portion and the extension length of the at least one groove is smaller than the distance between the outer wall of the first side wall portion and the outer wall of the second side wall portion. Due to the above-mentioned length setting, the short-circuit phenomenon between the channels when the devices are densely arranged in the chip layout, such as in the case of sharing source and drain regions, is avoided, as shown in FIG. 5B .
  • the length of the trench is not greater than the distance between the gate spacers on both sides, it is avoided that the trench is filled with a dielectric during the fabrication process of the FET, and the conductive cross-sectional area of the source or drain is prevented from changing. Small, thus avoiding the increase of the on-resistance of the entire FET during operation.
  • the length of the trench is not greater than the distance between the gate sidewalls on both sides, the outer surrounding area of the source PN junction or the drain PN junction will not be increased, and the increase of the junction capacitance of the PN junction is avoided, and the The adverse effect on the field effect transistor caused by the increase of the parasitic capacitance from the gate to the source or the increase of the parasitic capacitance from the gate to the drain is avoided.
  • the depth of the trench in a direction perpendicular to the surface of the substrate, is not greater than the depth of the PN junction formed by the source, and the depth of the trench is not greater than the depth of the PN junction formed by the drain . Since the depth of the trench is not greater than the depth of the source PN junction, and the depth of the trench is not greater than the depth of the drain PN junction, the performance of the channel of the field effect transistor is guaranteed.
  • the surface of the substrate is recessed in a direction perpendicular to the surface of the substrate to form the bottom wall of the trench, and the difference between the dopant ion concentration at the surface of the substrate and the dopant ion concentration at the bottom wall is less than 20%. Since the difference between the dopant ion concentration at the top surface of the substrate and the dopant ion concentration at the bottom of the trench is less than 20%, the uniformity of the dopant ion concentration at the carrier transport channel is ensured, and the field effect is further ensured performance of the channel of the tube.
  • n is the number of at least one trench; H tr is the depth of the trench; W is the width of the device channel in the layout.
  • the effective width of the channel increases with the increase of the number of trenches, so it can be achieved by increasing the number of trenches
  • the effective width of the channel is greatly increased, thereby improving the channel performance of the field effect transistor, or the desired channel performance can be achieved by forming the number of specific trenches.
  • n can be rounded to W/(2*Wmin), or can take a value within a range not exceeding the above-mentioned integer according to circuit design requirements.
  • n can be any positive integer, and 2 grooves are illustrated in the embodiment. Appropriate n can be taken depending on design requirements and desired channel performance.
  • FIG. 6 is a schematic flowchart of a method for manufacturing a field effect transistor according to a second embodiment of the present application.
  • the manufacturing method of the field effect transistor of FIG. 6 includes:
  • 610 Based on the surface of the substrate, form a channel surface with at least one trench of a carrier transport channel, wherein the carrier transport channel is located in the substrate between the source and the drain.
  • 620 Form a gate dielectric layer covering the surface of the channel having at least one trench. It should be understood that the oxide layer may be formed based on the surface of the channel such that the surface of the channel is on one side of the oxide layer.
  • a gate is formed. It should be understood that the gate may be formed along the other side of the oxide layer.
  • the channel surface of the carrier transport channel has at least one groove, which increases the effective width in the carrier transport channel.
  • the projected area of the carrier transport channel on the surface of the substrate is reduced, thereby reducing the device layout area of the field effect transistor.
  • the method further includes: forming a device isolation trench around the carrier transport channel based on the surface of the substrate.
  • forming a channel surface of the carrier transport channel having at least one trench based on the surface of the substrate comprising: depositing a first hard mask layer and a first light based on the surface of the substrate etching layer; plasma etching and photolithography processing are performed on the first hard mask layer and the first photolithography layer, and a channel surface with at least one groove is formed at the region of the carrier transport channel.
  • a device isolation trench around the carrier transport channel comprising: depositing a second lithography layer based on the first hard mask layer and the first lithography layer processed by plasma and lithography;
  • the carrier transport channel, the second photolithography layer and the first hard mask layer are subjected to photolithography and plasma etching treatment, and the etching groove is subjected to oxide filling, chemical mechanical polishing and planarization treatment, and the first hard mask layer is Wet removal to finally form device isolation trenches.
  • the hard mask layer can make the layout pattern match the shape of the trench obtained by the etching process, a channel surface with at least one trench can be reliably formed. Additionally, depositing a photolithographic layer on the etched hard mask layer enables the formation of device isolation trenches without altering the surface of the channel having at least one trench.
  • forming a channel surface of the carrier transport channel with at least one groove based on the surface of the substrate includes: forming a device isolation trench based on the surface of the substrate; region, a channel surface having at least one trench forming a carrier transport channel.
  • forming the device isolation trenches based on the surface of the substrate includes: depositing a second photolithography layer and a second hard mask layer based on the surface of the substrate; and performing an integral process of the device isolation trenches based on the device layout .
  • the device isolation trenches may be formed by performing photolithography and plasma etching processes on the second photolithography layer and the second hard mask layer around the device active region. Then, oxide filling, chemical mechanical polishing and planarization treatment of the etched grooves may be performed, and wet removal of the second hard mask layer may be performed.
  • forming a channel surface of the carrier transport channel with at least one trench comprising: depositing a first hard mask layer and a first photolithography layer based on the region surrounded by the device isolation trench; Plasma etching and photolithography are performed on the first hard mask layer and the first photolithography layer to form a channel surface with at least one trench having a carrier transport channel.
  • the photolithography layer can ensure the reliability of the photolithography process, and the hard mask layer can make the layout pattern match the shape of the device isolation trench obtained by the etching process, the device isolation trench is reliably formed.
  • continuing to deposit the hardmask layer and the photolithography layer on the processed photolithography layer enables the formation of at least one trench without altering the device isolation trenches.
  • trench-type channels are used for trench-type channels.
  • the formation process of the trench trench can be deeply compatible with the manufacturing process of standard field effect transistors.
  • the trench trench can be fabricated by a similar double-depth shallow trench isolation (STI) process.
  • STI shallow trench isolation
  • embedded source technology or embedded drain technology can be introduced to enhance the carrier mobility of the carrier transport channel.
  • embedded SiGe process in a P-type MOS transistor increases holes
  • the mobility of the N-type MOS tube is increased by the use of an embedded silicon-carbon (embedded SiC) process to increase the mobility of electrons.
  • a stress memory technology can be used after the gate is formed to conduct stress to the carrier transport channel to adjust the mobility of carriers.
  • FIG. 7 is a schematic flowchart of a method for manufacturing a field effect transistor according to an example of the second embodiment of the present application.
  • the manufacturing method of Figure 7 includes:
  • a hard mask layer and a photolithography layer on the surface of the substrate.
  • a layer of oxide 52 and a layer of nitride 51 may be deposited as an etching hard mask before the device isolation trench is formed, and the photolithography layer may be a combination of amorphous carbon, dielectric anti-reflection film, and photoresist.
  • 720 Perform photolithography and plasma etching on the hard mask layer and the photolithography layer to form a channel surface having at least one trench. Specifically, a combination of photolithography and plasma etching processes can be used to transfer the layout pattern to the substrate to form the trench 21 of the trench-type channel, as shown in Fig. 8(a).
  • a channel protection surface Form a channel protection surface. Specifically, a layer of thin oxide 56 may be further formed to protect the surface of the channel in subsequent processes, and a Rapid Thermal Oxidation (RTO) process may be used.
  • RTO Rapid Thermal Oxidation
  • a photolithography layer on the hard mask layer after the etching process deposit a photolithography layer on the hard mask layer after the etching process. Specifically, it is possible to continue to use the previously deposited hard mask, and then deposit the film layers required by the photolithography process in the standard STI process, such as amorphous carbon 53 , nitrogen-free dielectric anti-reflection film 54 , and photoresist film combination 55 , as shown in Figure 8(b).
  • the device isolation trench 15 (eg, STI) may be formed by a combination of photolithography and plasma etching processes, as shown in FIG. 8( c ). It should be understood that the device isolation trench not only surrounds the carrier transport channel, but also surrounds the device.
  • isolation trenches and the trench trenches with oxide. Specifically, a thick layer of silicon dioxide is deposited at the device isolation trench and the channel trench, and its height is higher than the height of the hard mask at this time, and it is planarized by a chemical mechanical polishing process, as shown in Figure 8(d). ).
  • FIG. 9 is a schematic flowchart of a method for manufacturing a field effect transistor according to another example of the second embodiment of the present application.
  • the manufacturing method of the field effect transistor of FIG. 9 includes:
  • a photolithographic layer and a hard mask layer on the surface of the substrate can be deposited first, and then the film layers required for the photolithography process, such as amorphous carbon 53 , nitrogen-free dielectric anti-reflection film 54 , and photoresist film combination 55 , can be deposited after the hard mask layer.
  • the film layers required for the photolithography process such as amorphous carbon 53 , nitrogen-free dielectric anti-reflection film 54 , and photoresist film combination 55 , can be deposited after the hard mask layer.
  • CMOS complementary Metal-Oxide-Semiconductor
  • 950 Form a thin oxide layer in the channel trench. Specifically, a furnace tube process, in-situ steam generation (ISSG) process or RTO process is used to form a thin layer of oxide 56 for repairing the surface defects of the substrate introduced by the aforementioned process steps, as shown in FIG. 10 ( d) shown.
  • ISSG in-situ steam generation
  • RTO reactive oxygen species

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Abstract

本申请实施例提供一种场效应管及其制造方法。所述场效应管包括：基板，设置有源极和漏极，所述源极与所述漏极之间形成载流子传输沟道，其中，所述载流子传输沟道在所述基板的表面处形成具有至少一个沟槽的沟道表面；栅极电介质层，覆盖于所述具有至少一个沟槽的沟道表面；栅极，设置于所述栅极电介质层之上，其中，所述栅极和所述栅极电介质层被栅极侧墙包围，所述至少一个沟槽的延伸范围超过所述栅极的覆盖区域，所述至少一个沟槽的延伸范围不超过所述栅极侧墙的覆盖区域。在本发明实施例的方案中，在保证器件特性需求的情况下，减小了场效应管的器件版图面积。

Description

场效应管及其制造方法 技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种场效应管及其制造方法。
背景技术
通常，在诸如金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，MOSFET)的器件的制造工艺中，在保证器件电学性能以及满足芯片电路设计要求的情况下，有效缩小器件在硅片上的面积能够带来较大的成本收益。
在数字芯片制造领域中，鳍式场效应晶体管(Fin Field-Effect Transistor，FinFET)技术为一种典型的解决方案并被业界广泛采用。
但是，在模拟芯片的领域中，诸如MOSFET的场效应管的器件尺寸往往比数字芯片中的器件尺寸大很多。因此，如何减少场效应管的器件版图面积成为急需解决的问题。
发明内容
有鉴于此，本发明实施例所解决的技术问题之一在于提供一种场效应管及其制造方法，能够在保证器件特性需求的情况下，减小场效应管的器件版图面积。
根据本发明实施例的第一方面，提供了一种场效应管，场效应管包括：基板，设置有源极和漏极，所述源极与所述漏极之间形成载流子传输沟道，其中，所述载流子传输沟道在所述基板的表面处形成具有至少一个沟槽的沟道表面；栅极电介质层，覆盖于所述具有至少一个沟槽的沟道表面；栅极，设置于所述栅极电介质层之上，其中，所述栅极被栅极侧墙包围，所述至少一个沟槽的延伸范围超过所述栅极的覆盖区域，所述至少一个沟槽的延伸范围不超过所述栅极侧墙的覆盖区域。
根据本发明实施例的第二方面，提供了一种场效应管的制造方法，所述方法包括：在基板的表面上形成载流子传输沟道的具有至少一个沟槽的沟道表面，其中，所述载流子传输沟道在所述基板中位于源极和漏极之间；形成栅极电介质层，覆盖于所述具有至少一个沟槽的沟道表面；在所述栅极电介质层之上，形成栅极。
在本发明实施例的方案中，载流子传输沟道的沟道表面具有至少一个沟槽，增大了载流子传输沟道的有效宽度，因此在保证器件特性需求的情况下，减小了载流子传输沟道在基板上的投影面积，从而减小了场效应管的器件版图面积。此外，由于至少一个沟槽的延伸范围超过栅极的覆盖区域，对于基板表面上沟道与沟槽沟道提供了有效长度均一的载流子传输沟道，因此该器件具有良好的电学模型表征其电性的能力。由于至少一个沟槽的延伸范围不超过所述栅极侧墙的覆盖区域，因此，避免了沟槽处在场效应管的制造工艺中被填入电介质的情况发生，避免了由于源极PN结或漏极PN结的外包围面积增大而导致PN结的结电容增大的情况发生，并且还避免了由于栅极到源极的寄生电容、或栅极到漏极的寄生电容的增大而为场效应管带来的不利影响等问题的发生，从而减小了此场效应管与传统场效应管的性能差异。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比值绘制的。附图中：
图1为本申请的第一实施例的场效应管的示意性立体图；
图2为本申请的第一实施例的一个示例的场效应管的示意性平面图；
图3A为本申请的第一实施例的另一示例的场效应管的示意性截面图；
图3B为本申请的第一实施例的另一示例的场效应管的示意性截面图；
图4为本申请的第一实施例的另一示例的场效应管的示意性截面图；
图5A为本申请的第一实施例的场效应管的一个示例的沟槽设置方式的示意图；
图5B为本申请的第一实施例的场效应管的另一示例的沟槽设置方式的示意图；
图6为本申请的第二实施例的场效应管的制造方法的示意性流程图；
图7为本申请的第二实施例的一个示例的场效应管的制造方法的示意性流程图；
图8为本申请的图7的场效应管的制造方法的示意图；
图9为本申请的第二实施例的另一示例的场效应管的制造方法的示意性流程图；以及
图10为本申请的图9的场效应管的制造方法的示意图。
具体实施方式
图1为本申请的第一实施例的场效应管的示意性立体图。图1示出了第一实施例的场效应管。场效应管包括基板10、载流子传输沟道20和栅极30。载流子传输沟道20在基板10的表面处形成具有至少一个沟槽21的沟道表面。图2为图1的平面图。图3A、图3B和图4分别为沿图1和图2中的截线A-A’、截线B-B’和截线C-C’截取得到截面图。
如图2所示，截线A-A’和截线B-B’沿着载流子传输沟道20的长度方向，并且截线A-A’经过沟道表面中的非沟槽部分，截线B-B’经过沟道表面中的沟槽部分。截线C-C’沿着载流子传输沟道20的宽度方向。基板10设置有源极11和漏极12，源极11与漏极12之间形成载流子传输沟道20，换言之，载流子传输沟道20在长度方向上的两侧分别包括源极11和漏极12。源极11和漏极12通过经由掺杂的源极掺杂区和漏极掺杂区形成。应理解，图示的两侧源极11和漏极12仅仅为示例性的，并且两者可以进行对调，即，当一侧为源极时，另一侧为漏极。图2还示出了栅极侧墙33，栅极30和栅极电介质层40被栅极侧墙33(spacer，也可以被称为栅极间隔层)包围，至少一个沟槽21的延伸范围超过栅极30的覆盖区域，至少一个沟槽21的延伸范围不超过栅极侧墙33的覆盖区域。
如图3A的截面图所示，栅极电介质层40覆盖于具有至少一个沟槽21的 沟道表面。换言之，栅极电介质层40沿沟道表面形成，使得沟道表面位于栅极电介质层40的一侧。栅极30设置于栅极电介质层40之上。换言之，栅极30沿栅极电介质层40的另一侧形成。在源极11和漏极12附近还包括相应的低掺杂区13，源极11的低掺杂区中的载流子浓度小于源极11的载流子浓度。漏极12的低掺杂区中的载流子浓度小于漏极12的载流子浓度。
如图3B的截面图所示，由于截线B-B’经过沟道表面中的沟槽部分，因此氧化层30以及低掺杂区13相比于图3A的示例在基板中处于更深的位置。另外，在长度方向上，载流子传输沟道20的长度L可以为低掺杂区13之间的距离。源极11和漏极12在垂直于基板10的表面的方向上的深度为PN结深度Hpn。
如图4所示，沟槽21包括底壁和两个侧壁，沟槽21在垂直于基板10的表面的方向上的深度Htr为沟槽21的底壁与基板10的表面之间的距离。沟槽21的宽度Wtr为两个侧壁在宽度方向上的距离。如图所示，载流子传输沟道20位于器件隔离槽15之间。
具体而言，载流子传输沟道20在基板10的表面处形成有沟道表面，沟道表面包括具有沟槽21的部分和不具有沟槽21的部分。栅极电介质层40可以介于载流子传输沟道20与栅极30之间。
在本发明的另一实现方式中，栅极为多晶硅材料，栅极电介质层为硅氧化物；或者栅极为多晶硅材料，栅极电介质层为硅氮氧化物；或者栅极为金属材料，栅极电介质层包括层叠设置的高介电常数材料层和硅氧化物，且硅氧化物层介于基板与高介电常数材料层之间。
具体而言，作为一个示例，栅极30采用多晶硅(PolySiON)栅极工艺技术形成，栅极电介质层40可以由硅的氧化物构成，作为栅极电介质。作为另一示例，如果栅极30使用高介电常数金属栅极(High-K Metal Gate,HKMG)技术形成，则栅极30包括金属离子阻挡层，刻蚀保护层，功函数调节层，栅极金属电极层组合而成。-
在本发明实施例的方案中，载流子传输沟道的沟道表面具有至少一个沟槽，增大了载流子传输沟道中的有效宽度，因此在保证器件特性需求的情况下，减 小了载流子传输沟道在基板的表面上的投影面积，从而减小了场效应管的器件版图面积。此外，由于至少一个沟槽的延伸范围超过栅极的覆盖区域，对于基板表面上沟道与沟槽沟道提供了有效长度均一的载流子传输沟道，因此该器件具有良好的电学模型表征其电性的能力。由于至少一个沟槽的延伸范围不超过所述栅极侧墙的覆盖区域，因此，避免了沟槽处在场效应管的制造工艺中被填入电介质的情况发生，避免了由于源极PN结或漏极PN结的外包围面积增大而导致PN结的结电容增大的情况发生，并且还避免了由于栅极到源极的寄生电容、或栅极到漏极的寄生电容的增大而为场效应管带来的不利影响等问题的发生，从而提高了场效应管的性能。
此外，根据沟道长度、阈值电压、漏电流等需求，场效应管还可以包括Halo离子注入区。
在本发明的另一实现方式中，至少一个沟槽中的每一沟槽(例如，对于一个沟槽的情况，每一沟槽是指该沟槽；对于多个沟槽的情况，每一沟槽是指多个沟槽中的每个沟槽)包括与基板的表面大致垂直的两个侧壁、以及连接在两个侧壁之间并与基板的表面具有高度差的底壁，沟道表面包括两个侧壁、底壁以及与基板的表面大致平齐的顶面，其中，栅极电介质层以大致相同的厚度覆盖于沟道表面上。应理解，在多个沟槽的情况下，沟道表面包括多个沟槽各自的两个侧壁、底壁以及与基板的表面大致平齐的顶面。
在本发明的另一实现方式中，载流子传输沟道在源极与漏极之间具有长度方向，至少一个沟槽在长度方向上延伸，形成延伸范围。由于沟槽在源极与漏极之间的长度方向上形成在载流子传输沟道中，因此在载流子传输沟道的长度方向上的任一截面，都具有因沟槽而增大了载流子传输沟道的有效宽度，因此提高了载流子传输沟道的性能。
在本发明的另一实现方式中，至少一个沟槽的延伸长度大于栅极在长度方向上的长度。由于沟槽的延伸长度大于栅极的长度，因此载流子传输沟道中的载流子的迁移更加稳定和可靠，从而进一步提高了载流子传输沟道的性能。
此外，由于沟槽的延伸长度大于栅极的长度，使得沟槽处的沟道长度与基板表面处的沟道长度相等，使得引入了沟槽后并没有形成两种沟道长度，有利 于后续的集成电路模拟程序(Simulation program with integrated circuit emphasis,SPICE)模型的提取与建立。反之，则会使模型变得复杂和难以收敛。
在一个示例中，基板可以实现为硅基板，沟槽的长度大于多晶硅，或者，沟槽的长度大于HKMG工艺中的假(Dummy)栅极(即，在栅极形成之后的工艺流程中会去除的部分)的长度。
图5A示出了一个示例的沟槽设置方式，并且图5B示出了另一示例的沟槽设置方式。在诸如共用源漏区等情况下，例如，在芯片电路中使用诸如反相器的器件时，由于两个场效应管共用一端的源极或漏极而串联短接。此时相邻两个器件的栅极间距很近。一方面，沟槽如果突出栅极侧墙的两侧，制造过程中可能的多晶硅刻蚀残留导致器件栅极间短接(如图5A中的阴影部分所示)。另一方面，由于间距太小，工艺误差导致的沟槽伸长可能会导致短接，如图5A所示。
从电性角度而言，一方面，沟槽长度如果突出栅极侧墙的两侧，则会导致沟槽在后续工艺流程中被填入电介质，进而导致源极或漏极的导电截面积变小，使得整个器件工作时导通电阻变大。另一方面，沟槽长度如果突出栅极侧墙的两侧，则会增加源极PN结或漏极PN结的外包围面积，直接导致PN结的结电容增大，同时也会增加栅极到源极的寄生电容、或栅极到漏极的寄生电容的增大，给器件带来不利影响。因此，如果沟槽长度突出栅极侧墙的两侧时，会导致器件的性能变差。因此，在本发明的一个示例中，栅极侧墙在长度方向上形成第一侧墙部和第二侧墙部，至少一个沟槽的延伸长度大于第一侧墙部的内壁和第二侧墙部的内壁之间的距离，至少一个沟槽的延伸长度小于第一侧墙部的外壁和第二侧墙部的外壁之间的距离。由于上述的长度设置，因此避免了诸如共用源漏区等情况下的芯片版图中器件密集排布时的沟道之间的短接现象，如图5B所示。
此外，由于沟槽的长度不大于两侧的栅极侧墙之间的距离，避免了沟槽处在场效应管的制造工艺中被填入电介质进而导致的源极或漏极的导电截面积变小，从而避免了整个场效应管在工作时导通电阻变大。
此外，由于沟槽的长度不大于两侧的栅极侧墙之间的距离，不会增加源极 PN结或漏极PN结的外包围面积，避免了PN结的结电容增大，同时也避免了栅极到源极的寄生电容、或栅极到漏极的寄生电容的增大而为场效应管带来的不利影响。
在本发明的另一实现方式中，在垂直于基板的表面的方向上，沟槽的深度不大于源极形成的PN结的深度，并且沟槽的深度不大于漏极形成的PN结的深度。由于沟槽的深度不大于源极PN结的深度，并且沟槽的深度不大于漏极PN结的深度，因此保证了场效应管的沟道的性能。
具体而言，基板的表面在垂直于基板的表面的方向上凹陷形成沟槽的底壁，基板的表面处的掺杂离子浓度与底壁处的掺杂离子浓度之间的差异小于20％。由于基板的顶面处的掺杂离子浓度与沟槽的底部的掺杂离子浓度之间的差异小于20％，保证载流子传输沟道处掺杂离子浓度的均一性，进一步保证了场效应管的沟道的性能。
在本发明的另一实现方式中，底壁经由沟槽的两个侧壁连结到基板的表面，载流子传输沟道的有效宽度W eff通过如下公式确定：W eff＝2n*H tr+W。n为至少一个沟槽的个数；H tr为沟槽的深度；W为版图中器件沟道的宽度。
由于根据上述公式所指示的关系，对于一定的沟道在基板上的投影宽度，沟道的有效宽度随着沟槽的个数的增大而增大，因此能够通过增大沟槽的个数极大地增大沟道的有效宽度，进而提高场效应管的沟道的性能，或者，可以通过形成特定沟槽的个数达到期望的沟道的性能。
应理解，由于单个沟槽的加工宽度Wmin受限于光刻工艺时的衍射极限，n的数量会被该指标限制。在一个示例中，n可以为W/(2*Wmin)取整，或者根据电路设计要求在不超过上述整数的范围内取值。
还应理解，n可以为任意正整数，在实施例中图示了2个沟槽。取决于设计要求以及期望的沟道性能，可以取适当的n。
图6为本申请的第二实施例的场效应管的制造方法的示意性流程图。图6的场效应管的制造方法包括：
610：基于基板的表面，形成载流子传输沟道的具有至少一个沟槽的沟道表面，其中，载流子传输沟道位于基板中位于源极和漏极之间。
620：形成栅极电介质层，覆盖于具有至少一个沟槽的沟道表面。应理解，可以基于沟道表面，形成氧化物层，使得沟道表面位于氧化物层的一侧。
630：在栅极电介质层之上，形成栅极。应理解，可以沿氧化物层的另一侧形成栅极。
在本发明实施例的方案中，载流子传输沟道的沟道表面具有至少一个沟槽，增大了载流子传输沟道中的有效宽度，因此在保证器件特性需求的情况下，减小了载流子传输沟道在基板的表面上的投影面积，从而减小了场效应管的器件版图面积。
在本发明的另一示例中，该方法还包括：基于基板的表面，围绕载流子传输沟道，形成器件隔离槽。经由上述加工，提高了场效应管的性能的可靠性。
在本发明的另一示例中，基于基板的表面，形成载流子传输沟道的具有至少一个沟槽的沟道表面，包括：基于基板的表面，沉积第一硬掩模层和第一光刻层；对第一硬掩模层和第一光刻层进行等离子刻蚀和光刻处理，在载流子传输沟道的区域处形成具有至少一个沟槽的沟道表面。基于基板的表面，围绕载流子传输沟道，形成器件隔离槽，包括：基于经由等离子和光刻处理的第一硬掩模层和第一光刻层，沉积第二光刻层；围绕载流子传输沟道，对第二光刻层以及第一硬掩模层进行光刻和等离子刻蚀处理，并对刻槽进行氧化物填充、化学机械研磨平坦化处理，第一硬掩模层的湿法去除，最终形成器件隔离槽。
由于硬掩模层能够使得版图图案与刻蚀处理得到的沟槽的形状更加匹配，从而可靠地形成了具有至少一个沟槽的沟道表面。另外，在经由刻蚀处理的硬掩模层上沉积光刻层能够在不改变具有至少一个沟槽的沟道表面的同时形成器件隔离槽。
在本发明的另一示例中，基于基板的表面，形成载流子传输沟道的具有至少一个沟槽的沟道表面，包括：基于基板的表面，形成器件隔离槽；基于器件隔离槽包围的区域，形成载流子传输沟道的具有至少一个沟槽的沟道表面。
由于基于基板的表面围绕载流子传输沟道，形成至少一个沟槽，因此实现了沟槽的加工精度。
在本发明的另一示例中，基于基板的表面，形成器件隔离槽，包括：基于 基板的表面，沉积第二光刻层和第二硬掩模层；基于器件版图，执行器件隔离槽整体工艺。可以围绕器件有源区，对第二光刻层和第二硬掩模层进行光刻和等离子刻蚀处理，形成器件隔离槽。然后，可以对刻槽进行氧化物填充、化学机械研磨平坦化处理，第二硬掩模层的湿法去除。基于器件隔离槽包围的区域，形成载流子传输沟道的具有至少一个沟槽的沟道表面，包括：基于器件隔离槽包围的区域，沉积第一硬掩模层和第一光刻层；对第一硬掩模层和第一光刻层进行等离子刻蚀和光刻处理，形成具有载流子传输沟道的具有至少一个沟槽的沟道表面。
由于对光刻层能够保证光刻处理的可靠性，硬掩模层能够使得版图图案与刻蚀处理得到的器件隔离槽的形状更加匹配，因此，可靠地形成了器件隔离槽。另外，在经由处理的光刻层上继续沉积硬掩模层和光刻层，能够在不改变器件隔离槽的同时形成至少一个沟槽。
应理解，本发明实施例用于沟槽型沟道。沟槽型沟道的形成工艺可以与标准场效应管的制造工艺深度兼容，例如，可采用类似双深度浅槽隔离(shallow trench isolation，STI)工艺制造沟槽型沟道。
此外，可以引入嵌入式源极技术或嵌入式漏极技术来增强载流子传输沟道的载流子迁移率，例如，P型MOS管中使用嵌入式锗硅(embedded SiGe)工艺增加空穴的迁移率，N型MOS管中使用嵌入式碳硅(embedded SiC)工艺来增加电子的迁移率。
此外，可以在栅极形成后使用应力记忆技术(Stress Memorization Technique，SMT)，将应力传导至载流子传输沟道处，调节载流子的迁移率。
图7为本申请的第二实施例的一个示例的场效应管的制造方法的示意性流程图。图7的制造方法包括：
710：在基板的表面上沉积硬掩模层和光刻层。具体而言，可以在器件隔离槽形成之前首先沉积一层氧化物52和一层氮化物51作为刻蚀硬掩模，光刻层可以为非定性碳，电介质减反膜，光刻胶组合。
720：对硬掩模层和光刻层进行光刻和等离子体刻蚀处理，形成具有至少一个沟槽的沟道表面。具体而言，可以利用光刻与等离子刻蚀工艺组合将版图图 形传递至基板形成沟槽型沟道的沟槽21，如图8(a)所示。
730：形成沟道保护表面。具体而言，可以继续形成一层薄氧化物56在后续工艺中保护沟道表面，可采用快速热氧化(Rapid Thermal Oxidation，RTO)工艺。
740：在经由刻蚀处理后的硬掩模层上沉积光刻层。具体而言，可以继续利用之前沉积的硬掩模，之后沉积标准的STI工艺中光刻工艺需要的膜层，例如非定型碳53、无氮电介质减反膜54、光刻胶膜系组合55，如图8(b)所示。
750：基于基板的表面，围绕载流子传输沟道，对光刻层和上述经由刻蚀处理后的硬掩模层进行光刻和等离子刻蚀处理，形成器件隔离槽。具体而言，可以经过光刻与等离子刻蚀工艺组合形成器件隔离槽15(例如，STI)，如图8(c)所示。应理解，器件隔离槽不仅围绕载流子传输沟道，而且还围绕器件。
760：利用氧化物填充隔离沟槽和沟道沟槽。具体而言，器件隔离槽与沟道沟槽处沉积一层厚度较厚的二氧化硅，其高度高于此时硬掩模的高度，通过化学机械研磨工艺进行平坦化，如图8(d)。
770：去除沟道沟槽中氧化物。具体而言，与常规工艺相比引入一次额外光刻工艺，在沟槽型沟道的沟槽处打开光刻胶，利用等离子体刻蚀与湿法刻蚀组合的方式将沟道沟槽处的氧化物去除，如图8(e)。
780：去除硬掩模层和光刻层。具体而言，可以利用湿法刻蚀将硬掩模层去除，进行后续标准工艺，如图8(f)。
图9为本申请的第二实施例的另一示例的场效应管的制造方法的示意性流程图。图9的场效应管制造方法包括：
910：在基板的表面上沉积光刻层和硬掩模层。具体而言，可以先沉积硬掩模层，然后再硬掩模层之后沉积光刻工艺需要的膜层，例如非定型碳53、无氮电介质减反膜54、光刻胶膜系组合55。
920：根据设计的器件版图，执行器件隔离槽工艺。具体而言，可以围绕载流子传输沟道，对光刻层和硬掩模层进行光刻和等离子刻蚀处理，形成器件隔离槽。然后可以采用氧化物填充器件隔离槽，执行化学机械研磨平坦化处理，并且湿法刻蚀去除上述硬掩模层。具体而言，可以利用标准互补金属氧化物半 导体(Complementary Metal-Oxide-Semiconductor，CMOS)工艺形成器件隔离槽15，如图10(a)所示。
930：继续沉积硬掩模层和光刻层。具体而言，对于硬掩模层，可以重新沉积一层氧化物52与一层氮化物51，如图10(b)所示。
940：对硬掩模层和光刻层进行等离子刻蚀和光刻处理，形成具有至少一个沟槽的沟道表面。具体而言，可以利用光刻与等离子体刻蚀工艺将沟槽型沟道沟槽版图图案传递至基板，如图10(c)所示。
950：在沟道沟槽中形成薄氧化物层。具体而言，利用炉管工艺、现场水汽生成(in-situ steam generation，ISSG)工艺或者RTO工艺形成一层薄氧化物56，用于修复基板因前述工艺步骤引入的表面缺陷，如图10(d)所示。
960：去除硬掩模层和光刻层。具体而言，使用湿法刻蚀工艺去除硬掩模以及上述薄氧化物薄膜，如图10(e)所示。然后，可以进行后续离子注入，栅极氧化物形成等标准CMOS工艺流程，如图10(f)所示。
需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (14)

  1. 一种场效应管，其特征在于，包括：
    基板，设置有源极和漏极，所述源极与所述漏极之间形成载流子传输沟道，其中，所述载流子传输沟道在所述基板的表面处形成具有至少一个沟槽的沟道表面，
    栅极电介质层，覆盖于所述具有至少一个沟槽的沟道表面；
    栅极，设置于所述栅极电介质层之上，其中，所述栅极和栅极电介质层被栅极侧墙包围，所述至少一个沟槽的延伸范围超过所述栅极的覆盖区域，所述至少一个沟槽的延伸范围不超过所述栅极侧墙的覆盖区域。
  2. 根据权利要求1所述的场效应管，其特征在于，所述载流子传输沟道在所述源极与所述漏极之间具有长度方向，所述至少一个沟槽在所述长度方向上延伸，形成所述延伸范围。
  3. 根据权利要求2所述的场效应管，其特征在于，所述至少一个沟槽的延伸长度大于所述栅极在所述长度方向上的长度。
  4. 根据权利要求3所述的场效应管，其特征在于，所述栅极侧墙在所述长度方向上形成第一侧墙部和第二侧墙部，所述至少一个沟槽的延伸长度大于所述第一侧墙部的内壁和所述第二侧墙部的内壁之间的距离，所述至少一个沟槽的延伸长度小于所述第一侧墙部的外壁和所述第二侧墙部的外壁之间的距离。
  5. 根据权利要求1所述的场效应管，其特征在于，在垂直于所述基板的表面的方向上，所述沟槽的深度不大于所述源极形成的PN结的深度，并且所述沟槽的深度不大于所述漏极形成的PN结的深度。
  6. 根据权利要求5所述的场效应管，其特征在于，所述基板的表面在垂直于所述基板的表面的方向上凹陷形成所述沟槽的底壁，所述基板的表面处的掺杂离子浓度与所述底壁处的掺杂离子浓度之间的差异小于20％。
  7. 根据权利要求1-6中任一项所述的场效应管，其特征在于，所述载流子传输沟道的有效宽度W eff通过如下公式确定：W eff＝2n*H tr+W，其中，n为所述至少一个沟槽的个数；H tr为所述沟槽的深度；W为版图中器件沟道的宽度。
  8. 根据权利要求1-7任一项所述的场效应管，其特征在于，所述栅极为多晶硅材料，所述栅极电介质层为硅氧化物；或者
    所述栅极为多晶硅材料，所述栅极电介质层为硅氮氧化物；或者
    所述栅极为金属材料，所述栅极电介质层包括层叠设置的高介电常数材料层和硅氧化物，且所述硅氧化物层介于所述基板与所述高介电常数材料层之间。
  9. 根据权利要求1-8任一项所述的场效应管，其特征在于，每一沟槽包括与所述基板的表面大致垂直的两个侧壁、以及连接在所述两个侧壁之间并与所述基板的表面具有高度差的底壁，所述沟道表面包括所述两个侧壁、所述底壁以及与所述基板的表面大致平齐的顶面，其中，所述栅极电介质层以大致相同的厚度覆盖于所述沟道表面上。
  10. 一种场效应管的制造方法，其特征在于，包括：
    基于基板的表面，形成载流子传输沟道的具有至少一个沟槽的沟道表面，其中，所述载流子传输沟道位于所述基板中位于源极和漏极之间；
    形成栅极电介质层，覆盖于所述具有至少一个沟槽的沟道表面；
    在所述栅极电介质层之上，形成栅极。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：
    基于所述基板的表面，围绕所述载流子传输沟道，形成器件隔离槽。
  12. 根据权利要求11所述的方法，其特征在于，所述基于基板的表面，形成载流子传输沟道的具有至少一个沟槽的沟道表面，包括：
    基于所述基板的表面，沉积第一硬掩模层和第一光刻层；
    对所述第一硬掩模层和第一光刻层进行等离子刻蚀和光刻处理，在所述载流子传输沟道的区域处形成具有所述至少一个沟槽的沟道表面，
    其中，所述基于所述基板的表面，围绕所述载流子传输沟道，形成器件隔离槽，包括：
    基于经由等离子和光刻处理的第一硬掩模层和第一光刻层，沉积第二光刻层；
    围绕所述载流子传输沟道，对所述第二光刻层和第一硬掩模进行光刻和等离子体刻蚀处理，并对刻槽进行氧化物填充、化学机械研磨平坦化处理，第一硬掩模层的湿法去除，最终形成所述器件隔离槽。
  13. 根据权利要求10所述的方法，其特征在于，所述基于基板的表面，形成载流子传输沟道的具有至少一个沟槽的沟道表面，包括：
    基于所述基板的表面，形成器件隔离槽；
    基于所述器件隔离槽包围的区域，形成所述载流子传输沟道的具有至少一个沟槽的沟道表面。
  14. 根据权利要求13所述的方法，其特征在于，所述基于所述基板的表面，形成器件隔离槽，包括：
    基于所述基板的表面，沉积第二光刻层和第二硬掩模层；
    基于器件版图，围绕器件有源区，对所述第二光刻层和第二硬掩模层进行光刻和等离子刻蚀处理，并对刻槽进行氧化物填充、化学机械研磨平坦化处理，第二硬掩模层的湿法去除，最终形成所述器件隔离槽，
    其中，所述基于所述器件隔离槽包围的区域，形成所述载流子传输沟道的具有至少一个沟槽的沟道表面，包括：
    基于所述器件隔离槽包围的区域，沉积第一硬掩模层和第一光刻层；
    对所述第一硬掩模层和第一光刻层进行等离子刻蚀和光刻处理，形成具有所述载流子传输沟道的具有至少一个沟槽的沟道表面。
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