WO2022160923A1 - 场效应晶体管器件及改善其短沟道效应和输出特性的方法 - Google Patents

场效应晶体管器件及改善其短沟道效应和输出特性的方法 Download PDF

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WO2022160923A1
WO2022160923A1 PCT/CN2021/134782 CN2021134782W WO2022160923A1 WO 2022160923 A1 WO2022160923 A1 WO 2022160923A1 CN 2021134782 W CN2021134782 W CN 2021134782W WO 2022160923 A1 WO2022160923 A1 WO 2022160923A1
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channel
region
field effect
effect transistor
drain
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PCT/CN2021/134782
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English (en)
French (fr)
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王明湘
陈乐凯
张冬利
王槐生
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苏州大学
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Definitions

  • the invention specifically relates to a field effect transistor device and a method for improving its short channel effect and output characteristics, belonging to the technical field of semiconductor devices.
  • the gate length (corresponding to the channel length) of field effect transistors is constantly shrinking.
  • VLSI chips based on submicron or even 10 nanometer gate length devices have been mass-produced.
  • the short-channel effect makes the threshold voltage and sub-threshold characteristics of small-sized devices deteriorate in an all-round way. Specifically, the threshold voltage of the device is no longer constant, but decreases with the decrease of the channel length, and increases with the increase of the drain voltage of the device. decrease; the sub-threshold region slope of the device transfer characteristics is also degraded at the same time.
  • the methods to improve the short-channel effect of field effect transistor devices mainly include fin field effect transistor FinFET, silicon-on-insulator SOI, lightly doped drain (LDD) structure and metal source-drain Schottky barrier transistor (SB MOSFET), etc. .
  • FinFET fin field effect transistor
  • SOI silicon-on-insulator SOI
  • LDD lightly doped drain
  • SB MOSFET metal source-drain Schottky barrier transistor
  • the difficulty of this solution lies in the SOI silicon
  • the cost of the chip is very high, and the chip of the 10-nanometer technology node based on the SOI solution has also been mass-produced.
  • the lightly doped drain LDD is placed near the drain channel and the source and drain regions far from the channel are still heavily doped.
  • the drain PN junction formed by the lightly doped region reduces the influence of the drain voltage on the channel.
  • the working current of the Schottky barrier transistor is the tunneling current of the Schottky barrier between the metal source and the semiconductor channel, which is not sensitive to the short channel effect. And it is difficult to take into account the suppression of the off-state current of the device.
  • the kink effect that appears on the output characteristic curve of short-channel devices has also received a lot of attention.
  • the higher drain voltage makes the drain terminal of the device deplete and forms a high electric field region, where the carriers are prone to collision ionization effect, and coupled with the parasitic bipolar transistor of the MOS device to amplify , so that the drain current increases rapidly with the increase of the drain voltage, forming the so-called kink current, and the output characteristic curve of the device is greatly warped, which seriously affects the normal output characteristics.
  • the commonly used methods to improve the kink effect mainly include increasing the device channel length and lightly doped drain (LDD) structure.
  • LDD lightly doped drain
  • Increasing the channel length can reduce the influence of the carriers generated by the impact ionization of the drain on the source, weaken the parasitic transistor effect and alleviate the kink effect.
  • increasing the channel length will correspondingly reduce the output current of the device.
  • the LDD structure can reduce the peak electric field strength in the drain depletion region, weaken the impact ionization effect of carriers, and thus suppress the kink effect, but the LDD structure will introduce additional parasitic resistance, reducing the field effect mobility and on-state current of the device. .
  • the main purpose of the present invention is to provide a field effect transistor device and a method for improving its short channel effect and output characteristics.
  • the technical scheme adopted in the present invention includes:
  • a field effect transistor device includes an active layer, the active layer includes a source region, a drain region, and a channel region between the source region and the drain region;
  • an effective channel and an equivalent source and/or an equivalent drain remote from the effective channel are formed in the channel region, and the field effect transistor device passes through the effective channel, and An equivalent source electrode and/or an equivalent drain electrode communicate with the source region and the drain region to form an operating current.
  • a conductive region that is not connected to the source region and the drain region is formed in the channel region;
  • the conductive region When the conductive region communicates with the source region, the conductive region constitutes the equivalent source; and/or,
  • the conductive region When the conductive region communicates with the drain region, the conductive region constitutes the equivalent drain.
  • it includes a first gate disposed on one surface of the active layer, and the vertical projections of the first gate and the conductive region on the channel region overlap; wherein, The first gate can control the channel region and form a channel therein, and the portion of the channel that does not overlap with the vertical projection of the conductive region on the channel region constitutes the effective channel Road; and/or,
  • the conductive region is spaced from the effective channel in the thickness direction of the channel region.
  • the conductance of the conductive region when the device is turned on, is greater than the conductance of the rest of the channel except the effective channel, so that at least one of the conductive region and the effective channel can be connected to the other injecting carriers; preferably, the conductance of the conductive region is at least three times greater than the conductance of the rest of the channel except the effective channel;
  • the field effect transistor device is a planar structure device or a vertical structure device.
  • the conductance per unit length of the effective channel in the channel is greater than the conductance per unit length of the remaining part of the channel except the effective channel; preferably,
  • the field effect transistor device includes a gate insulating layer disposed between the first gate electrode and the channel region, wherein the thickness of the portion corresponding to the effective channel in the gate insulating layer is smaller than that of the rest of the gate insulating layer thickness; and/or,
  • the portion of the gate insulating layer corresponding to the effective channel and the remaining portion of the gate insulating layer are made of materials with different work functions; and/or,
  • the part of the first gate corresponding to the effective channel and the rest of the first gate are made of materials with different work functions; preferably,
  • the conductance per unit length of the effective channel in the channel is at least three times greater than the conductance per unit length of the remainder of the channel except the effective channel.
  • the method further includes a second gate disposed on a surface of the active layer adjacent to a side surface of the conductive region, and the second gate can control the formation of the conductive region in the channel region.
  • the conductive region is formed by carriers introduced by doping on the surface of the channel region on a side away from the effective channel.
  • it further includes an insulating layer disposed on a surface of the active layer away from the effective channel, and the conductive region is insulated adjacent to the channel region by the injected charges in the insulating layer through electrostatic induction.
  • the charge carriers generated at the layer constitute.
  • the method further includes a semiconductor material layer disposed on a surface of the active layer away from the effective channel, the active layer and the semiconductor material layer form a heterostructure, and the conductive region is formed by a distribution a two-dimensional electron gas channel or a two-dimensional hole gas channel in the heterostructure; and/or,
  • the conductive region is composed of a two-dimensional electron gas channel or a two-dimensional hole gas channel formed by performing surface treatment on a surface of the channel region away from the effective channel.
  • the source region and the drain region are doped semiconductor or Schottky metal source and drain; and/or,
  • the gate of the field effect transistor device is a metal-insulating layer-semiconductor MOS structure gate or a Schottky junction gate; and/or,
  • the active layer includes at least two semiconductor materials that vary along its thickness direction or planar extension direction.
  • the present application also provides a method for improving the short channel effect and output characteristics of a field effect transistor device, the method comprising arranging an equivalent source electrode and/or an equivalent drain electrode away from the effective channel of the device in a channel region of the device, When the device is turned on, the effective channel communicates with the source region and the drain region of the device through the equivalent source and/or the equivalent drain to form a working current.
  • an effective channel, and an equivalent source and an equivalent drain away from the effective channel can be formed in the channel region, so that the source region and the drain region are connected to form a working current;
  • the equivalent drain (source) connected to the drain (source) region is structurally far away from the effective channel, which can reduce the influence of the drain voltage on the effective channel; and reduce the leakage of the device during saturation operation.
  • the peak electric field in the terminal depletion region thereby suppressing the short-channel effect of the device and improving the output characteristics of the device.
  • FIG. 1 is a schematic diagram of a state in which an equivalent source electrode, an equivalent drain electrode, and an effective channel are formed when a field effect transistor device is turned on according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a field effect transistor device in an on state according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a state in which a conductive region is formed in a field effect transistor device according to an embodiment of the present invention
  • 4 to 8 are schematic structural diagrams of field effect transistor devices according to various embodiments of the present invention.
  • 9 to 16 are schematic diagrams of the principles of fabricating conductive regions in various embodiments of the present invention.
  • 20 is a schematic structural diagram of a field effect transistor device with an interval between the effective channel and the vertical projection of the conductive region on the channel region according to an embodiment of the present invention
  • Figures 21 to 22 are the comparison diagrams of the transfer characteristics of the SOI device applying the solution of the present invention and the common SOI device;
  • FIG. 23 to FIG. 24 are comparison diagrams of the output characteristics of the SOI device applying the solution of the present invention and the common SOI device.
  • the field effect transistor device 100 includes an active layer 10 , and the active layer 10 includes a source region 101 , a drain region 102 , and a channel region 103 .
  • the source region 101 and the drain region 102 are located on both sides of the active layer 10 respectively, and the channel region 103 is located between the source region 101 and the drain region 102 .
  • an effective channel 1041 and an equivalent source 1051 and an equivalent drain 1052 far away from the effective channel 1041 are formed in the channel region 103 of the field effect transistor.
  • the effect transistor device 100 communicates with the source region 101 and the drain region 102 through the effective channel 1041 , the equivalent source 1051 , and the equivalent drain 1052 to form an operating current.
  • the distance between the effective channel 1041 and the equivalent source electrode 1051 and the equivalent drain electrode 1052 mentioned in this application may mean that there is an interval in the thickness direction of the channel region 103, or the channel region 103 There is a space between the thickness direction of the channel region 103 and the vertical projection of the channel region 103 .
  • the source region 101 in the active region is used to provide carriers when the device is turned on, and the drain region 102 is used to collect the carriers provided by the source region 101 .
  • the equivalent source 1051 mentioned refers to the structure in which the carriers provided by the source region 101 are directly injected into the effective channel 1041
  • the “effective channel 1041 ” mentioned in this application refers to the channel that contributes the main carrier path when the device is turned on.
  • a first gate electrode 20 may be disposed on one surface of the active layer 10 , and the vertical projection of the first gate electrode 20 on the active layer 10 is different from the source region 101 and the drain region 102 . There is no interval. Therefore, when a gate bias is applied to the first gate 20 to turn on the device, a channel 104 can be controlled to be formed under the first gate 20 , and the channel 104 is correspondingly connected to the source region 101 from a structural point of view and drain region 102 .
  • the arrangement of the equivalent source electrode 1051 and the equivalent drain electrode 1052 is equivalent to shortening the length of the part of the channel that can conduct the operating current, that is, a gap is created between the effective channel 1041 and the source region 101 and the drain region 102 .
  • the equivalent drain 1052 in communication with the drain region 102 is far away from the effective channel 1041 in structure, reducing the influence of the drain potential on the effective channel 1041, while the equivalent source 1051 in communication with the source region 101 Structurally away from the effective channel 1041, the influence of the drain terminal potential on the effective channel 1041 is also reduced, so as to improve the short-channel effect of the device.
  • a conductive region A that is not connected to the source region 101 and the drain region 102 may be formed in the channel region 103 .
  • this part of the conductive region A constitutes an equivalent source 1051 ;
  • this part of the conductive region A constitutes an equivalent drain 1052 .
  • the conductance of the conductive region A is set to be greater than the conductance of the remaining portion 1042 of the channel 104 except the effective channel 1041, so that carriers can be injected between the conductive region A and the effective channel 1041.
  • the carriers of the source region 101 will be attracted by the equivalent source 1051 with greater conductance, and will not be directly injected into the remaining part 1042 of the channel 104 that is directly connected to the source region 101; similarly, in the effective channel Carriers transported in the channel 1041 are also attracted by the equivalent drain 1052 and do not continue transporting through the remaining portion 1042 in the channel 104 .
  • the carriers provided by the source region 101 enter the equivalent source 1051 and are injected into the effective channel 1041 from the end of the equivalent source 1051 away from the source region 101;
  • the carriers of the channel 1041 will be injected into the equivalent drain 1052 at one end adjacent to the equivalent drain 1052 , and finally injected into the drain region 102 .
  • the conductance of the conductive region A can be set to be at least greater than that in the channel 104 except the effective channel 1041
  • the conductance of the rest of the outer portion 1042 is three times that of 1042.
  • the distance between the conductive region A and the effective channel 1041 in the thickness direction of the channel region 103 is According to the specific design of different devices, the interval can be set to 5nm-10 ⁇ m, or more preferably 10nm-1 ⁇ m, or more preferably 10nm-100nm, to ensure the normal injection of carriers and the performance of the device.
  • the "carriers” mentioned in this application refer to the charge particles that can move freely in the corresponding polarity channel/conductive region A.
  • the electrons in the N-type channel or the P The holes in the N-type channel are called “carriers” here, and correspondingly, the holes in the N-type channel or the electrons in the P-type channel are not called “carriers” here. Therefore, The polarities of the effective channel 1041 and the conductive region A in the present application are set to be the same, so that the carrier interaction between the two channels can ultimately substantially contribute to the operating current of the device.
  • FIG. 4 another embodiment of the field effect transistor device 200 of the present application is introduced.
  • the field effect transistor device 200 communicates with the source region 101 and the drain region 102 through the effective channel 1041 and the equivalent source electrode 1051 to form an operating current.
  • the effect of the drain terminal potential on the potential near the source terminal of the channel region 103 is reduced only by the setting of the equivalent source electrode 1051 , thereby improving the short channel effect of the device.
  • the active channel 1041 is directly connected to the drain region 102 .
  • the carriers provided by the source region 101 enter the equivalent source 1051 and are injected into the effective channel 1041 from the end of the equivalent source 1051 away from the source region 101; The carriers are injected back into the drain region 102 again. That is, in this embodiment, only the conductive region injects carriers unidirectionally into the effective channel 1041 .
  • FIG. 5 another embodiment of the field effect transistor device 300 of the present application is introduced.
  • the field effect transistor device 300 communicates with the source region 101 and the drain region 102 through the effective channel 1041 and the equivalent drain 1052 to form an operating current.
  • the effect of the drain terminal potential on the effective channel 1041 is reduced only by the setting of the equivalent drain 1052, thereby improving the short-channel effect of the device.
  • the active channel 1041 is directly connected to the source region.
  • the carriers provided by the source region 101 enter the effective channel 1041 , and are injected into the equivalent drain 1052 from the end of the effective channel 1041 away from the source region 101 , and then injected back into the drain region 102 . That is, in this embodiment mode, only the effective channel 1041 injects carriers into the conductive region unidirectionally.
  • the conductance per unit length of the effective channel in the channel can be set to be greater than the conductance per unit length of the rest of the channel except the effective channel.
  • FIG. 6 another embodiment of the field effect transistor device 400 of the present application is introduced.
  • Field effect transistor device 400 includes active layer 10 including source region 101 , drain region 102 , and channel region 103 .
  • the source region 101 and the drain region 102 are located on both sides of the active layer 10 respectively, and the channel region 103 is located between the source region 101 and the drain region 102 .
  • the insulating layer 30 and the first gate electrode 20 are sequentially disposed above the channel region, and the thickness of the gate insulating layer 1041 corresponding to the effective channel 104 is smaller than the thickness of the remaining part of the gate insulating layer 1042 . That is, the gate insulating layer 1042 of the corresponding part of the equivalent source electrode 1051 and the equivalent drain electrode 1052 is thickened, so that the resistance of the corresponding gate of the remaining part of the channel 1042 other than the effective channel 1041 to the corresponding part of the channel 1042 can be weakened. modulation capability, thereby increasing the conductance of the corresponding portion of the channel 1042.
  • the material of the insulating layer corresponding to the effective channel and the rest of the insulating layer may be adjusted to be different, so that the conductance of the effective channel in the channel is greater than the conductance of the rest of the channel.
  • FIG. 7 another embodiment of the field effect transistor device 500 of the present application is introduced.
  • Field effect transistor device 500 includes active layer 10 including source region 101 , drain region 102 , and channel region 103 .
  • the source region 101 and the drain region 102 are located on both sides of the active layer 10 respectively, and the channel region 103 is located between the source region 101 and the drain region 102 .
  • the first gate 20 is disposed above the channel region 103 , and the part 201 of the first gate 20 corresponding to the effective channel 1041 and the remaining part 202 are made of different materials, so that the effective channel in the first gate 20 is made of different materials.
  • the corresponding part 201 and the remaining part 202 of 201 have different modulation capabilities for the correspondingly formed channels, and the conductance of the effective channel 1041 is realized to be greater than the conductance of the remaining parts 1042 of the channel 104 except the effective channel 1041 .
  • the portion 201 of the first gate 20 corresponding to the effective channel 1041 can be made of a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or adjusted Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with smaller work function obtained by the compound composition are used as gate materials; the rest 202 can be doped with metals with larger work function such as gold, platinum, or P-type doping ( P+) polysilicon, or ITO, RuO 2 , WN, MoN, etc. with larger work function obtained by adjusting the composition of the compound are used as gate materials.
  • a metal with a smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or adjusted Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. with smaller work function obtained by the compound composition are used as gate materials
  • the rest 202 can be do
  • the part 201 of the first gate 20 corresponding to the effective channel 1041 can be made of a metal with a larger work function, such as gold, platinum, or P-type doped (P+) polysilicon, or a higher work function obtained by adjusting the composition of the compound.
  • ITO, RuO2, WN, MoN, etc. with large work function are used as gate materials;
  • the rest 202 can be obtained by using metals with small work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or by adjusting the composition of the compound.
  • the smaller work functions of Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. are used as gate materials.
  • the first gate electrode 20 may also be provided only on one side surface of the channel region of the portion between the equivalent source electrode 1051 and the equivalent drain electrode 1052 . In this way, even when a bias voltage capable of turning on the device is applied on the first gate 20, a channel that structurally connects the source and drain regions will not be formed under the first gate 20 (as shown in FIG. 8 ). , the channel 1041 formed by the first gate 20 at this time is not connected to the source region 101 and the drain region 102). That is, the first gate 20 controls the channel 1041 formed in the channel region 103 to be the above-mentioned "effective channel".
  • the conductive region A is formed by carriers introduced by doping on the surface of the channel region 103A on the side away from the effective channel 1041A.
  • the doping concentration of the interface can be changed by doping the surface of the channel region 103A away from the effective channel 1041A with donor atoms, such as phosphorus, arsenic, etc.; refer to FIG. 10
  • the doping concentration of the interface can be changed by doping the surface of the channel region 103A away from the effective channel 1041A with acceptor atoms, such as boron.
  • the field effect transistor device 100B further includes an insulating layer 40B disposed on the surface of the active layer 10B away from the effective channel 1041B. One side surface of the area is formed.
  • FIG. 11 if it is an N-type device, it can be realized by injecting positive charges, such as H + , holes locally in the insulating layer 40B; referring to FIG. 12 , if it is a P-type device, it can be realized by injecting positive charges in the insulating layer 40B; Local injection of negative charges, eg, F ⁇ , Cl ⁇ , electrons, etc. in layer 40B is achieved. In this way, a high density of fixed charges is formed in the insulating layer 40B, and through electrostatic induction, carriers of the conductive region A are generated in the channel region 103B adjacent to the insulating layer 40B. It should be noted that the "local" here refers to a part of the insulating layer 40B corresponding to the channel region where the conductive region A needs to be formed.
  • charges are preferably injected into the insulating layer 40B closer to the channel region 103B, so that the conductive region A formed in the channel region 103B can store more carriers.
  • a "double insulating layer" structure can also be used, which specifically includes a charge trapping layer disposed on the surface of the channel region 103B, and a conventional insulating layer covering the charge trapping layer.
  • the charge trapping layer can be made of materials that are easier to store charges, or nanoparticles of metals or semiconductors can be introduced therein to store charges more stably, thereby ensuring the stability and controllability of carriers in the conductive region.
  • the field effect transistor device 100C includes a semiconductor material layer 40C disposed on the active layer 10C, the semiconductor material layer 40C and the active layer 10C form a heterostructure, and the conductive region A is composed of two distributed in the heterostructure.
  • a two-dimensional electron gas channel or a two-dimensional hole gas channel is formed.
  • the semiconductor material layer 40C and the active layer 10C have different band gap widths, and the semiconductor material layer 40C can be divided into two parts respectively connected to the source region 101C and the drain region 102C, so that the formed two-dimensional electron gas The channel does not conduct the source and drain regions.
  • a two-dimensional electron gas channel or a two-dimensional hole gas channel can also be formed by, for example, performing surface treatment on the channel region 103C, which are known to those skilled in the art to form a two-dimensional Alternative embodiments of electron gas channels or two-dimensional hole gas channels should all fall within the scope of the present application.
  • the semiconductor material layer 40C mentioned here may be a barrier layer, and the barrier layer may be doped or intrinsic.
  • a field effect transistor device 100D is fabricated as a device including at least two gates.
  • the field effect transistor device 100D includes a first gate insulating layer 30D and a first gate electrode 20D which are sequentially arranged on one side surface of the active layer 10D, and a first gate insulating layer 30D and a first gate 20D which are sequentially arranged on the side surface of the active layer 10D adjacent to the conductive region A.
  • the second gate 50D is correspondingly divided into two parts, a vertical projection of one part on the active layer 10D is connected to the source region 101D, and the vertical projection of the other part on the active layer 10D is connected to the drain region 102D.
  • a suitable bias voltage is applied to the two parts of the second gate electrode 50D, a conductive region A connected to the source region 101D and a conductive region connected to the drain region 102D can be respectively formed at corresponding positions in the channel region 103D A.
  • the absolute value of the bias voltage applied on the second gate 50D should be greater than the absolute value of the turn-on voltage applied to the device.
  • the absolute value of the bias voltage applied on the second gate 50D should be greater than the absolute value of the turn-on voltage applied to the device.
  • a positive bias voltage greater than that of the first gate 20D is applied to the second gate 50D; if it is a P-type device, an absolute value greater than that of the first gate is applied to the second gate 50D Negative bias for pole 20D.
  • the field effect transistor device 100E is fabricated to include at least two gate electrodes similarly to Embodiment 4. As shown in FIG. But the difference is that in this embodiment, in order to make the conductance of the conductive region A be greater than the conductance of the part 1042E of the channel 104E except the effective channel 1041E, the first gate 20E and the The second gate 50E. That is, the difference between the work functions of the first gate 20E and the active layer 10E and the difference between the work functions of the second gate 50E and the active layer 10E are not equal.
  • the first gate 20E can be made of a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO with a larger work function obtained by adjusting the composition of the compound.
  • a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or ITO, RuO with a larger work function obtained by adjusting the composition of the compound. 2.
  • WN, MoN, etc. as gate materials;
  • the second gate 50E can use metals with smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or adjust the compound composition to obtain smaller Work function Ru-Hf, WN, HfN, TiN, TaN, TaSiN, etc. are used as gate materials.
  • the first gate 20E can use metals with smaller work function such as aluminum, hafnium, titanium, or N-type doped (n+) polysilicon, or Ru- with smaller work function obtained by adjusting the composition of the compound Hf, WN, HfN, TiN, TaN, TaSiN, etc. are used as gate materials;
  • the second gate 50E can be obtained by using a metal with a larger work function such as gold, platinum, or P-type doped (P+) polysilicon, or by adjusting the composition of the compound ITO, RuO 2 , WN, MoN, etc. with larger work function are used as gate materials.
  • the work function difference between the first gate 20E and the active layer 10E can be set to be greater than zero ( ⁇ ms>0V), so that the channel 104E is an enhancement type channel; at the same time, a second gate can be set
  • the work function difference between the electrode 50E and the active layer 10E is less than zero ( ⁇ ms ⁇ 0V), so that when the device is turned off, the conductive region A can also form a certain number of carriers under the bias voltage applied thereon.
  • the work function difference between the first gate 20E and the active layer can be set to be less than zero ( ⁇ ms ⁇ 0V), so that the channel 104E is an enhancement type channel; at the same time, the second gate 50E is set to have The work function difference of the source layer 10E is greater than zero ( ⁇ ms>0V), so that when the device is turned off, the conductive region A can also form a certain number of carriers under the action of the bias voltage applied thereon.
  • the field effect transistor device 100F is fabricated to include at least two gate electrodes 20F, 50F similarly to Embodiment 4. As shown in FIG. But the difference is that in this embodiment, in order to make the conductance of the conductive region A be greater than the conductance of the part 1042F of the channel 104F except the effective channel 1041F, the capacitance per unit area of the second gate insulating layer 40F can be set to be greater than that of the first gate Capacitance per unit area of the insulating layer 30F.
  • the dielectric constant of the first gate insulating layer 30F and the second gate insulating layer 40F can be achieved by adjusting the dielectric constant of the first gate insulating layer 30F and the second gate insulating layer 40F, or the thicknesses of the first gate insulating layer 30F and the second gate insulating layer 40F.
  • the first gate insulating layer 30F and the second gate insulating layer 40F are equal, only the dielectric constant factor of the gate insulating layer may be considered, and the dielectric constant of the second gate insulating layer 40F may be set higher than that of the first gate insulating layer 40F.
  • the dielectric constant of the layer 30F is sufficient.
  • the first gate insulating layer 30F can be made of silicon dioxide, and the second gate insulating layer 40F can be made of a high dielectric constant dielectric such as hafnium dioxide, aluminum oxide, and the like.
  • the thickness of the gate insulating layer 40F is set to be smaller than that of the first gate insulating layer 30F.
  • the second gate in the above-mentioned Embodiments 4 to 6 may also be directly floating or grounded, so as to avoid excessive device connection terminals and increase the complexity of the device application.
  • the field effect transistor devices described in the above embodiments/embodiments may be either planar structure devices or vertical structure devices.
  • SOI device TFT device
  • a planar top-gate structure TFT device 100G includes a light-transmitting insulating substrate 40G, an active layer 10G, a gate dielectric layer 30G, and a gate electrode 20G sequentially disposed on the substrate 40G.
  • Two sides of the active layer 10G are respectively doped to form a source region 101G and a drain region 102G, and the source electrode and the drain electrode are respectively externally connected; the channel region 103G is located between the source region 101G and the drain region 102G.
  • Positive charge regions 60G are respectively formed on both sides of the source region 101G and the drain region 102G on the substrate 40G by means of ion implantation or the like.
  • the positive charge region 60G and the gate 20G have an overlapping portion between the vertical projections of the channel region 103G.
  • the positive charge region of the overlapping portion can be formed in the channel region 103G with the source region 101G and the source region 101G, respectively.
  • the two-dimensional electron gas 70G connected to the drain region 102G, where the two-dimensional electron gas 70G also constitutes a conductive region.
  • a channel is formed under the gate 20G, and the portion of the channel that is vertically projected between the conductive regions constitutes an actual effective channel.
  • a planar bottom gate structure TFT device 100H includes a light-transmitting insulating substrate 40H, a gate electrode 20H, a gate dielectric layer 30H, and an active layer 10H sequentially disposed on the substrate 40H.
  • the upper metal source electrode 501H and the metal drain electrode 502H are respectively provided on both sides of the active layer 10H.
  • the active layer 10H can be made of an amorphous IGZO metal oxide semiconductor layer.
  • the source electrode 501H and the drain electrode 502H are connected to the active layer 10H. Ohmic contacts are formed between the layers 10H.
  • the part of the active layer under the source electrode 501H and the drain electrode 502H constitutes the source region and the drain region respectively, and the channel region is located between the source region and the drain region.
  • the positively charged regions 60H of the source electrode 501H and the drain electrode 502H, respectively, are connected by ion implantation in the passivation layer overlying the device.
  • the positive charge region 60H and the gate 20H have an overlapping portion between the vertical projections of the channel region.
  • the positive charge region of the overlapping portion can be formed in the channel region respectively with the source region and the drain region.
  • the connected two-dimensional electron gas 70H, where the two-dimensional electron gas 70H also constitutes a conductive region.
  • a channel is formed over the gate 20H, and the portion of the channel that is vertically projected between the conductive regions 70H constitutes the actual effective channel.
  • the source region 101I and the drain region 102I are located below and above the active layer 10I, respectively.
  • An equivalent source electrode 1051I connected to the source region 101I and an equivalent drain electrode 1052I connected to the drain region 102I are formed in the channel region 103I.
  • the gate 20I controls the formation of a channel 104I connecting the source region 101I and the drain region 102I in the channel region 103I of the device, however, only the channel 104I has only The part that does not overlap with the vertical projection of the equivalent source electrode 1051I and the equivalent drain electrode 1052I on the channel region 103I constitutes the effective channel 1041I for transmitting the working current when the device is turned on, that is, the channel 104I.
  • the remaining portion 1042I is not used to transmit the operating current when the device is turned on.
  • the source region and the drain region in the device may be a common heavily doped semiconductor source and drain, or may be a Schottky metal source and drain of a metal-semiconductor structure;
  • the gate may be It is a common metal-insulating layer-semiconductor MOS structure gate, or a Schottky junction gate with a metal-semiconductor structure;
  • the active layer can be composed of a single semiconductor material, or it can include a direction along its thickness or plane. At least two semiconductor materials are varied to form a composite channel.
  • the equivalent source electrode and the equivalent drain electrode may be formed spontaneously, or may be formed by gate control of the corresponding structure.
  • the superimposed vertical projection of the effective channel, the equivalent source and/or the equivalent drain on the channel region connects the source region and the drain region, thereby ensuring that the effective channel and the The carriers of the equivalent source and/or the equivalent drain can be injected unidirectionally or bidirectionally at least in the thickness direction, and a carrier path from the source region to the drain region is constructed.
  • the carriers of the equivalent source and/or the equivalent drain can be injected unidirectionally or bidirectionally at least in the thickness direction, and a carrier path from the source region to the drain region is constructed.
  • the present application does not exclude that in some special embodiments, if the vertical projection of the effective channel, equivalent source and/or equivalent drain superimposed on the channel region 103J fails to connect the device
  • the path flowing to the equivalent drain 1052J, the injection direction of carriers between the effective channel 1041J, the equivalent source 1051J, and the equivalent drain 1052J forms an angle with the thickness direction of the channel region 103J, such an embodiment It should also fall within the protection scope of this application.
  • the present application also provides specific embodiments of a method for improving the short-channel effect and output characteristics of a field effect transistor device.
  • the method includes arranging an equivalent source electrode and/or an equivalent drain electrode far from the effective channel of the device in the channel region of the device, so that when the device is turned on, the effective channel passes through the equivalent source electrode and/or an equivalent drain communicates the source and drain regions of the device to form an operating current.
  • the comparison object of the above device is a conventional SOI device, the channel length of which is the same as the effective channel length of the device of the present invention, and the related parameters such as channel material and gate are kept the same.
  • the material of the channel region is Si, the thickness is 0.05 ⁇ m;
  • the P-type doping concentration in the channel region is 1E17cm -3 ;
  • the gate insulating layer is made of SiO 2 with a thickness of 17nm;
  • the N-type doping concentration in the source and drain regions is 1E20cm -3 ;
  • the fixed positive charge surface density at the back interface of the channel forming the equivalent source and drain is 1E14cm -2 ;
  • Drain voltage Vd 2V or 0.1V
  • the V kink of the conventional SOI device is 0.60V, while the V kink of the equivalent drain, equivalent source and equivalent source-drain devices are 1.10V, 0.99V and 1.26V respectively.
  • the device of the invention can effectively reduce the carrier collision ionization effect when the device is working, suppress the KINK current, and improve the output characteristics of the device. Meanwhile, it is observed from FIGS. 23 and 24 that the output current of the device of the present invention is comparable to that of the conventional SOI device without any drop.
  • an effective channel, and an equivalent source and an equivalent drain far away from the effective channel can be formed in the channel region, thereby connecting the source region and the drain region to form a working
  • the equivalent drain (source) connected to the drain (source) region is structurally far away from the effective channel, which can reduce the effect of the drain voltage on the effective channel, thereby improving the short channel of the device Road effect.
  • the device of the present invention reduces the peak electric field in the depletion region of the channel and drain end of the device under the saturated working state, and greatly reduces the load of the depletion region of the drain end of the device through the setting of the equivalent source electrode and the equivalent drain electrode.
  • the impact ionization effect of the carrier suppresses the kink current of the output characteristic of the device and improves the output characteristic of the device.
  • the device of the present invention can suppress the hot carrier degradation effect of the device and improve the reliability of the device.

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Abstract

本发明提供了一种场效应晶体管器件及利用其改善短沟道效应和输出特性的方法，其中该场效应晶体管器件包括有源层，该有源层包括源极区域、漏极区域以及位于源极区域和漏极区域之间的沟道区域；当器件开启时，沟道区域内形成有有效沟道以及远离有效沟道的等效源极和/或等效漏极，该场效应晶体管器件通过有效沟道、以及等效源极和/或等效漏极连通源极区域和漏极区域以形成工作电流。

Description

场效应晶体管器件及改善其短沟道效应和输出特性的方法
本发明要求2021年01月27日向中国专利局提交的、申请号为202110110414.X、发明名称为“场效应晶体管器件及改善其短沟道效应和输出特性的方法”的中国专利申请的优先权，该申请的全部内容通过引用结合在本文中。
技术领域
本发明具体涉及一种场效应晶体管器件及改善其短沟道效应和输出特性的方法，属于半导体器件技术领域。
背景技术
随着集成电路技术的发展，场效应晶体管的栅长(对应沟道长度)在不断缩小，目前基于亚微米甚至10纳米以下栅长器件的VLSI芯片已经量产。对于这类小尺寸器件，如何应对其短沟道效应是器件技术的重要挑战。短沟道效应使得小尺寸器件的阈值电压和亚阈值特性全面劣化，具体表现为器件阈值电压不再是常数，而是随沟道长度的减小而降低，并随器件漏端电压的增加而降低；器件转移特性的亚阈值区斜率也同时劣化。
目前改善场效应晶体管器件短沟道效应的方法主要包括鳍式场效应晶体管FinFET，绝缘层上硅SOI、轻掺杂漏(LDD)结构和金属源漏肖特基势垒晶体管(SB MOSFET)等。①FinFET的沟道区为3D鳍型薄片，栅极是三面围栅结构，两个侧栅增强了栅极对沟道的控制，有效地抑制了短沟道效应，该方案中器件制备工艺较平面型器件复杂得多，目前22nm以下技术节点的芯片较多采用FinFET方案。②SOI技术，在硅沟道层和背衬底之间引入埋氧化层，在沟道层很薄全耗尽的条件下，可以有效抑制源漏之间的泄漏电流，该方案的难点在于SOI硅片的成本非常高，目前基于SOI方案的10纳米级技术节点的芯片也已经量产。③轻掺杂漏LDD设置于漏端沟道附近而远离沟道的源漏区域仍然是重掺杂，该轻掺杂区形成的漏端PN结减小了漏端电压对于沟道的影响，是亚微米级短沟道器件的主流技术方案，该方案中器件的开态电流和场效应迁移率受到LDD影响均有一定程度的下降。④肖特基势垒晶体管的工作电流为金属源极与半导体沟道间肖特基势垒的隧穿电流，对短沟道效应不敏感，该方案工艺难度比较大，势垒材料的选择有限而且很难兼顾对于器件关态电流的抑制。
另一方面，短沟道器件的输出特性曲线上出现的kink效应也受到很多关注。器件工 作于饱和工作状态时，较高的漏极电压使得器件漏端耗尽并形成高电场区，载流子在此容易发生碰撞离化效应，并与MOS器件寄生的双极型晶体管耦合放大，使漏极电流随漏极电压增大而迅速增加，形成所谓的kink电流，器件的输出特性曲线大幅度翘曲，严重影响正常的输出特性。
常用的改善kink效应的方法主要包括增加器件沟道长度和轻掺杂漏(LDD)结构。增加沟道长度可以减小漏端碰撞离化产生的载流子对于源端的影响，削弱寄生晶体管效应并缓解kink效应。但是沟道长度增加会相应的降低器件的输出电流。LDD结构可以降低漏端耗尽区内的峰值电场强度，减弱载流子碰撞离化效应，从而抑制kink效应，但是LDD结构会引入额外的寄生电阻，降低器件的场效应迁移率和开态电流。
发明内容
本发明的主要目的在于提供一种场效应晶体管器件及改善其短沟道效应和输出特性的方法。
为实现前述发明目的，本发明采用的技术方案包括：
一种场效应晶体管器件，包括有源层，所述有源层包括源极区域、漏极区域以及位于所述源极区域和漏极区域之间的沟道区域；
当器件开启时，所述沟道区域内形成有有效沟道以及远离所述有效沟道的等效源极和/或等效漏极，所述场效应晶体管器件通过所述有效沟道、以及等效源极和/或等效漏极连通所述源极区域和漏极区域以形成工作电流。
一实施例中，所述沟道区域中形成有不连通所述源极区域和漏极区域的导电区；其中，
当所述导电区与所述源极区域连通时，所述导电区构成所述等效源极；和/或，
当所述导电区与所述漏极区域连通时，所述导电区构成所述等效漏极。
一实施例中，包括设置于所述有源层一侧表面上的第一栅极，所述第一栅极和所述导电区在所述沟道区域上的垂直投影有交叠；其中，所述第一栅极可控制所述沟道区域并于其中形成沟道，所述沟道中与所述导电区在所述沟道区域上垂直投影之间不交叠的部分构成所述有效沟道；和/或，
所述导电区与所述有效沟道在所述沟道区域的厚度方向上有间隔。
一实施例中，当器件开启时，所述导电区的电导大于所述沟道中除有效沟道外其余部分的电导，以使所述导电区和有效沟道的至少其中之一可向其中另一注入载流子；优选地，所述导电区的电导至少大于所述沟道中除有效沟道外其余部分电导的三倍；
和/或，所述场效应晶体管器件为平面结构器件或垂直结构器件。
一实施例中，当器件开启时，所述沟道中有效沟道的单位长度电导大于所述沟道中除有效沟道外其余部分的单位长度电导；优选地，
所述场效应晶体管器件包括设置于所述第一栅极和沟道区域之间的栅绝缘层，其中，所述栅绝缘层中与所述有效沟道对应部分的厚度小于其余部分栅绝缘层的厚度；和/或，
所述栅绝缘层中与所述有效沟道对应部分和其余部分栅绝缘层由不同功函数的材质制成；和/或，
所述第一栅极中与所述有效沟道对应的部分和第一栅极的其余部分由不同功函数的材质制成；优选地，
当器件开启时，所述沟道中有效沟道的单位长度电导至少大于所述沟道中除有效沟道外其余部分的单位长度电导的三倍。
一实施例中，还包括设置于所述有源层临近导电区一侧表面的第二栅极，所述第二栅极可控制所述沟道区域中形成所述导电区。
一实施例中，所述导电区由所述沟道区域在远离所述有效沟道一侧表面掺杂引入的载流子形成。
一实施例中，还包括设置于所述有源层远离所述有效沟道一侧表面的绝缘层，所述导电区由所述绝缘层中的注入电荷通过静电感应在所述沟道区域临近绝缘层处生成的载流子构成。
一实施例中，还包括设置于所述有源层远离所述有效沟道一侧表面的半导体材料层，所述有源层与所述半导体材料层形成异质结构，所述导电区由分布于所述异质结构中的二维电子气沟道或二维空穴气沟道构成；和/或，
所述导电区由对所述沟道区域远离所述有效沟道的一侧表面进行表面处理形成的二维电子气沟道或二维空穴气沟道构成。
一实施例中，所述源极区域和漏极区域为掺杂半导体或肖特基金属源漏；和/或，
所述场效应晶体管器件的栅极为金属-绝缘层-半导体MOS结构栅极或者肖特基结栅极；和/或，
所述有源层包括沿其厚度方向或者平面延伸方向变化的至少两种半导体材料。
本申请还提供一种改善场效应晶体管器件短沟道效应和输出特性的方法，所述方法包括在器件的沟道区域设置远离器件有效沟道的等效源极和/或等效漏极，以使器件开启时，所述有效沟道通过所述等效源极和/或等效漏极连通器件的源极区域和漏极区域以形成工作电流。
与现有技术相比，本发明的优点至少在于：
通过将器件设置成在开启时，能够于沟道区域中形成有效沟道、以及远离有效沟道 的等效源极和等效漏极，从而连通源极区域和漏极区域以形成工作电流；这样，与漏极(源极)区域连通的等效漏极(源极)在结构上远离有效沟道，可以减小漏端电压对有效沟道的影响；并减小了器件饱和工作时漏端耗尽区内的峰值电场，从而抑制了器件的短沟道效应，并改善了器件的输出特性。
附图说明
图1为本发明一实施方式场效应晶体管器件在开启状态时形成等效源极、等效漏极、和有效沟道的状态示意图；
图2为本发明一实施方式场效应晶体管器件在开启状态时的结构示意图；
图3为本发明一实施方式场效应晶体管器件形成导电区的状态示意图；
图4至图8是本发明各实施方式场效应晶体管器件的结构示意图
图9至图16是本发明各实施例中制作导电区的原理示意图；
图17至图19为应用本发明方案的SOI器件的结构示意图；
图20是本发明一实施方式场效应晶体管器件有效沟道和导电区在沟道区域上的垂直投影之间具有间隔的结构示意图；
图21至图22至是应用本发明方案的SOI器件与普通SOI器件的转移特性对比图；
图23至图24是应用本发明方案的SOI器件与普通SOI器件的输出特性对比图。
具体实施方式
体现本发明特征与优点的典型实施例将在以下的说明中详细叙述。应理解的是本发明能够在不同的实施例上具有各种的变化，其皆不脱离本发明的范围，且其中的说明及图示在本质上是当作说明之用，而非用以限制本发明。
除非另有定义，本说明书所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。
参图1，介绍本申请场效应晶体管器件100的一具体实施方式。在本实施方式中，该场效应晶体管器件100包括有源层10，该有源层10包括源极区域101、漏极区域102、以及沟道区域103。
源极区域101和漏极区域102分别位于有源层10的两侧，沟道区域103位于该源极区域101和漏极区域102之间。配合图1示出的器件开启时的示意图，场效应晶体管的沟道区域103内此时形成有有效沟道1041以及远离该有效沟道1041的等效源极1051和等效漏极1052，场效应晶体管器件100通过该有效沟道1041、等效源极1051、和等效 漏极1052连通源极区域101和漏极区域102以形成工作电流。
本申请中提及的有效沟道1041与等效源极1051、等效漏极1052之间的“远离”可以是指在沟道区域103厚度方向上具有间隔，又或是在沟道区域103的厚度方向以及在沟道区域103的垂直投影之间都具有间隔。
在一个典型的场效应晶体管器件100中，有源区中的源极区域101用于提供器件开启时的载流子，而漏极区域102用于收集源极区域101提供的载流子。对应的，在本申请中，所提到的等效源极1051是指将源极区域101提供的载流子直接注入有效沟道1041的结构，而等效漏极1052是指从有效沟道1041直接接收载流子并注入漏极区域102的结构。
配合参照图2，本申请中提到的“有效沟道1041”是指器件在开启时，贡献主要载流子通路的沟道。以本实施方式为例，有源层10的一侧表面可以设置有第一栅极20，并且第一栅极20在有源层10上的垂直投影与源极区域101、漏极区域102之间没有间隔。因此，在对第一栅极20施加栅极偏压以使器件开启时，第一栅极20下方可以被控制形成有一沟道104，并且该沟道104从结构角度对应连接至源极区域101和漏极区域102。但是从功能角度而言，该沟道中只有与等效源极1051、等效漏极1052在沟道区域103上垂直投影之间不交叠的部分才用于传输工作电流，也因此只有这部分的沟道才会被称之为这里的“有效沟道1041”。
等效源极1051和等效漏极1052的设置相当于缩短了沟道中可以导通工作电流部分的长度，也即有效沟道1041与源极区域101和漏极区域102之间产生了间隔。并且，与漏极区域102连通的等效漏极1052在结构上远离有效沟道1041，减小了漏端电势对有效沟道1041的影响，而与源极区域101连通的等效源极1051在结构上远离有效沟道1041，同样减小了漏端电势对有效沟道1041的影响，以改善器件的短沟道效应。
配合参照图3，在等效源极1051和等效漏极1052的具体制备中，可以通过在沟道区域103形成不连通源极区域101和漏极区域102的导电区A，当导电区A与源极区域101连通时，这部分导电区A即构成等效源极1051；当导电区A与漏极区域102连通时，这部分导电区A即构成等效漏极1052。
当器件开启时，导电区A的电导被设置为大于沟道104中除有效沟道1041外其余部分1042的电导，以使得导电区A和有效沟道1041之间可以互相注入载流子。这样，源极区域101的载流子会被电导更大的等效源极1051所吸引，而不会直接注入沟道104中与源极区域101直接连接的其余部分1042；同样，在有效沟道1041中传输的载流子也会被等效漏极1052所吸引，而不会继续经沟道104中的其余部分1042传输。在本实施方式工作电流的形成中，源极区域101提供的载流子进入等效源极1051，并由等效源极 1051远离源极区域101的一端注入有效沟道1041；流经有效沟道1041的载流子又会在临近等效漏极1052的一端注入等效漏极1052，最终注入漏极区域102。
为了实现这里的等效源极1051、等效漏极1052、以及有效沟道1041之间的载流子注入设置，导电区A的电导可以被设置为至少大于沟道104中除有效沟道1041外其余部分1042电导的三倍。并且，由于载流子在上述的“注入”过程中，会在沟道区域103的厚度方向上流过，因此，本实施方式中导电区A和有效沟道1041在沟道区域103厚度方向上的间隔根据不同器件的具体设计可以设置为5nm～10μm、或更优选的10nm～1μm、或更优选的10nm～100nm，以保证载流子的正常注入和器件的性能。
需要说明的是，本申请中所提及的“载流子”是指在相应极性沟道/导电区A中能够自由移动的电荷微粒，通常地，我们将N型沟道中的电子或者P型沟道中的空穴称之为这里的“载流子”，相应地，N型沟道中的空穴或者P型沟道中的电子则不被称之为这里的“载流子”，因此，本申请中有效沟道1041和导电区A的极性被设置为相同，以使得两个沟道之间的载流子交互能够最终实质地贡献器件的工作电流。
参图4，介绍本申请场效应晶体管器件200的又一实施方式。
与上述实施方式不同的是，本实施方式中在器件开启时，沟道区域103内此时未形成等效漏极。场效应晶体管器件200通过有效沟道1041、等效源极1051连通源极区域101和漏极区域102以形成工作电流。
在本实施方式中，相当于只通过等效源极1051的设置减弱了漏端电势对沟道区域103源端附近电势的影响，从而改善器件的短沟道效应。对应地，有效沟道1041直接连接到漏极区域102。
在载流子传输中，源极区域101提供的载流子进入等效源极1051，并由等效源极1051远离源极区域101的一端注入有效沟道1041；流经有效沟道1041的载流子再注入回漏极区域102。也即，本实施方式中，只有导电区向有效沟道1041单向地注入载流子。
参图5，介绍本申请场效应晶体管器件300的又一实施方式。
与上述实施方式不同的是，本实施方式中在器件开启时，沟道区域103内此时未形成等效源极。场效应晶体管器件300通过有效沟道1041、等效漏极1052连通源极区域101和漏极区域102以形成工作电流。
在本实施方式中，相当于只通过等效漏极1052的设置减弱了漏端电势对有效沟道1041的影响，从而改善器件的短沟道效应。对应地，有效沟道1041直接连接到源极区域。
在载流子传输中，源极区域101提供的载流子进入有效沟道1041，并由有效沟道1041远离源极区域101的一端注入等效漏极1052，并再注入回漏极区域102。也即，本实施 方式中，只有有效沟道1041单向地向导电区注入载流子。
在上述的实施方式中，已经示出了由栅极控制形成的沟道中的一部分构成有效沟道的结构。在这样的结构中，为了进一步改善器件的短沟道效应，可以设置沟道中有效沟道的单位长度电导大于沟道中除有效沟道外其余部分的单位长度电导。以下介绍一些相应的实施方式。
参图6，介绍本申请场效应晶体管器件400的又一实施方式。
场效应晶体管器件400包括有源层10，该有源层包括源极区域101、漏极区域102、以及沟道区域103。源极区域101和漏极区域102分别位于有源层10的两侧，沟道区域103位于该源极区域101和漏极区域102之间。
沟道区域上方依次设置有绝缘层30和第一栅极20，并且，有效沟道104对应的栅绝缘层1041厚度小于其余部分栅绝缘层1042厚度。也即，将等效源极1051和等效漏极1052对应部分的栅绝缘层1042加厚，这样，可以减弱有效沟道1041之外其余部分沟道1042对应栅极对相应部分沟道1042的调制能力，从而使得相应部分沟道1042的电导增加。
可配合地，还可以通过调整绝缘层与有效沟道对应部分和其余部分绝缘层的材质不同，以使沟道中有效沟道的电导大于剩余部分的电导。
参图7，介绍本申请场效应晶体管器件500的又一实施方式。
场效应晶体管器件500包括有源层10，该有源层10包括源极区域101、漏极区域102、以及沟道区域103。源极区域101和漏极区域102分别位于有源层10的两侧，沟道区域103位于该源极区域101和漏极区域102之间。
沟道区域103上方设置有第一栅极20，并且，第一栅极20中与有效沟道1041对应部分201和其余部分202由不同材质制成，从而使得第一栅极20中有效沟道201对应部分201和剩余部分202对对应形成的沟道具有不同的调制能力，而实现有效沟道1041的电导大于沟道104中除有效沟道1041外其余部分1042的电导。
具体地，如果是N型器件，第一栅极20中与有效沟道1041对应部分201可以采用较小功函数的金属如铝、铪、钛，或N型掺杂(n+)多晶硅，或调整化合物组分获得的较小功函数的Ru-Hf，WN，HfN，TiN，TaN，TaSiN等作为栅极材料；其余部分202可以采用较大功函数的金属如金、铂，或P型掺杂(P+)多晶硅，或调整化合物组分获得的较大功函数的ITO、RuO 2、WN、MoN等等作为栅极材料。如果是P型器件，第一栅极20中与有效沟道1041对应部分201可以采用较大功函数的金属如金、铂，或P型掺杂(P+)多晶硅，或调整化合物组分获得的较大功函数的ITO、RuO2、WN、MoN等作为栅极材料；其余部分202可以采用较小功函数的金属如铝、铪、钛，或N型掺杂(n+) 多晶硅，或调整化合物组分获得的较小功函数的Ru-Hf，WN，HfN，TiN，TaN，TaSiN等作为栅极材料。
参图8，在一些替换的实施方式中，还可以只在等效源极1051和等效漏极1052之间部分的沟道区域一侧表面设置第一栅极20。这样，即使在第一栅极20上施加可以使得器件开启的偏压时，第一栅极20下方也不会形成从结构上连接源极区域和漏极区域的沟道(如图8所示，第一栅极20此时控制形成的沟道1041并不连接源极区域101和漏极区域102)。也即第一栅极20控制在沟道区域103中形成的沟道1041都为上述的“有效沟道”。
以下以一些具体的实施例介绍本申请中导电区的形成方式：
实施例1
导电区A由沟道区域103A在远离有效沟道1041A一侧表面掺杂引入的载流子形成。
对应地，参照图9，如果是N型硅基器件100A，可以通过在沟道区域103A远离有效沟道1041A的表面掺杂施主原子，例如磷、砷等改变界面的掺杂浓度；参照图10，如果是P型硅基器件100A，可以通过在沟道区域103A远离有效沟道1041A的表面掺杂受主原子，例如硼，改变界面的掺杂浓度。
实施例2
配合参图11和图12，场效应晶体管器件100B还包括设置于有源层10B远离有效沟道1041B一侧表面的绝缘层40B，导电区A由绝缘层40B中的注入电荷通过静电感应在沟道区域的一侧表面形成。
对应地，参图11，如果是N型器件，可以通过在该绝缘层40B中的局部注入正电荷，例如H +、空穴实现；参图12，如果是P型器件，可以通过在该绝缘层40B中的局部注入负电荷，例如F -、Cl -、电子等实现。通过这样的方式，使得绝缘层40B中形成高密度的固定电荷，并通过静电感应，在沟道区域103B临近绝缘层40B处生成导电区A的载流子。需要说明的是，这里的“局部”是指绝缘层40B中与沟道区域中对应需要形成导电区A的部分区域。
在具体的电荷注入过程中，优选地将电荷注入绝缘层40B中更加临近沟道区域103B的位置，以使得沟道区域103B中形成的导电区A能够储存更多的载流子。当然，在一些其它替换的实施例中，还可以采用“双绝缘层”的结构，具体包括一设置于沟道区域103B表面的电荷俘获层、以及覆盖于电荷俘获层上的常规绝缘层，该电荷俘获层可以采用更易存储电荷的材质、或者于其中引入金属或半导体的纳米粒子，以更稳定地存储电荷，从而保证导电区中载流子的稳定可控。
实施例3
参图13，场效应晶体管器件100C包括设置在有源层10C上的半导体材料层40C，该半导体材料层40C与有源层10C组成异质结构，导电区A由分布于异质结构中的二维电子气沟道或二维空穴气沟道形成。
具体地，半导体材料层40C和有源层10C具有不同的带隙宽度，半导体材料层40C可以分为分别与源极区域101C和漏极区域102C连接的两部分，从而使得形成的二维电子气沟道不会导通源漏极区域。
当然，在一些替换的实施例中，还可以例如通过对沟道区域103C进行表面处理以形成二维电子气沟道或二维空穴气沟道，这些本领域技术人员习知的形成二维电子气沟道或二维空穴气沟道的替换实施例都应当属于本申请的保护范围之内。并且，这里所说的半导体材料层40C可以为势垒层，该势垒层可以是含有掺杂或者是本征的。
实施例4
参图14，场效应晶体管器件100D制作为至少包括两个栅极的器件。具体地，场效应晶体管器件100D包括依次设置于有源层10D一侧表面的第一栅绝缘层30D和第一栅极20D、以及依次设置于有源层10D临近导电区A一侧表面的第二栅绝缘层40D和第二栅极50D。
第二栅极50D相应地分为两部分，一部分在有源层10D上的垂直投影连接源极区域101D，另一部分在有源层10D上的垂直投影连接漏极区域102D。这样，当在这两部分第二栅极50D上施加合适的偏压时，即可在沟道区域103D中对应位置分别形成连通源极区域101D的导电区A和连通漏极区域102D的导电区A。
在该实施例中，第二栅极50D上施加的偏压绝对值应当大于器件被施加的开启电压绝对值。对应地，如果是N型器件，则在第二栅极50D上施加大于第一栅极20D的正偏压；如果是P型器件，则在第二栅极50D上施加绝对值大于第一栅极20D的负偏压。
实施例5
参图15，场效应晶体管器件100E制作为与实施例4类似的至少包括两个栅极。但不同的是，本实施例中，为了使得导电区A的电导能够大于沟道104E中除有效沟道1041E外部分1042E的电导，可以通过采用不同功函数栅极材料的第一栅极20E和第二栅极50E。也即：第一栅极20E与有源层10E的功函数差、和第二栅极50E与有源层10E的功函数差不相等来实现。
对应地，如果是N型器件，第一栅极20E可以采用较大功函数的金属如金、铂，或P型掺杂(P+)多晶硅，或调整化合物组分获得的较大功函数的ITO、RuO 2、WN、MoN等作为栅极材料；第二栅极50E可以采用较小功函数的金属如铝、铪、钛，或N型掺杂(n+)多晶硅，或调整化合物组分获得的较小功函数的Ru-Hf，WN，HfN，TiN，TaN， TaSiN等作为栅极材料。如果是P型器件，第一栅极20E可以采用较小功函数的金属如铝、铪、钛，或N型掺杂(n+)多晶硅，或调整化合物组分获得的较小功函数的Ru-Hf，WN，HfN，TiN，TaN，TaSiN等作为栅极材料；第二栅极50E可以采用较大功函数的金属如金、铂，或P型掺杂(P+)多晶硅，或调整化合物组分获得的较大功函数的ITO、RuO 2、WN、MoN等等作为栅极材料。
优选地，在N型器件中，可以设置第一栅极20E与有源层10E的功函数差大于零(Φms>0V)，从而使得沟道104E为增强型沟道；同时，设置第二栅极50E与有源层10E的功函数差小于零(Φms＜0V)，使得导电区A在器件关闭状态时，也能够在其上施加的偏压作用下形成一定数量的载流子。在P型器件中，可以设置第一栅极20E与有源层的功函数差小于零(Φms＜0V)，从而使得沟道104E为增强型沟道；同时，设置第二栅极50E与有源层10E的功函数差大于零(Φms>0V)，使得导电区A在器件关闭状态时，也能够在其上施加的偏压作用下形成一定数量的载流子。
实施例6
参图16，场效应晶体管器件100F制作为与实施例4类似的至少包括两个栅极20F、50F。但不同的是，本实施例中，为了使得导电区A的电导能够大于沟道104F中除有效沟道1041F外部分1042F的电导，可以设置第二栅绝缘层40F的单位面积电容大于第一栅绝缘层30F的单位面积电容。
具体地，可以通过调控第一栅绝缘层30F和第二栅绝缘层40F的介电常数，或者第第一栅绝缘层30F和第二栅绝缘层40F的厚度来实现。
例如，在第一栅绝缘层30F和第二栅绝缘层40F厚度相等时，可以只考虑栅绝缘层的介电常数因素，设置第二栅绝缘层40F的介电常数高于的第一栅绝缘层30F的介电常数即可。示范性地，第一栅绝缘层30F可以采用二氧化硅，第二栅绝缘层40F可以采用高介电常数的介质如二氧化铪、氧化铝等。
又例如，在第一栅绝缘层30F和第二栅绝缘层40F材质相同时，可以只考虑栅绝缘层厚度因素，设置第二栅绝缘层40F的厚度小于第一栅绝缘层30F的厚度。
在具体的器件应用中，上述实施例4至6中的第二栅极还可以是直接浮置或接地，避免过多的器件连接端增加器件应用的复杂度。
并且，以上各实施例中形成导电区的方式还可以是彼此结合地进行应用，以达到更佳的实施效果。
上述各实施方式/实施例介绍的场效应晶体管器件可以是平面结构器件，也可以是垂直结构器件。以下将以一种SOI器件(TFT器件)为例，示范性地说明本申请的方案在应用于SOI器件时的具体设置。
实施例7
参图17，为平面型顶栅结构TFT器件100G，并包括透光绝缘衬底40G、以及依次设置于衬底40G上有源层10G、栅介质层30G、以及栅极20G。有源层10G两侧分别掺杂形成源极区域101G和漏极区域102G，并分别外接源电极和漏电极；沟道区域103G位于源极区域101G和漏极区域102G之间。
衬底40G上通过离子注入等方式，在源极区域101G和漏极区域102G两侧分别形成正电荷区域60G。正电荷区域60G与栅极20G在沟道区域103G的垂直投影之间具有交叠部分，相对应的，该交叠部分的正电荷区域可以在沟道区域103G中形成分别与源极区域101G和漏极区域102G连接的二维电子气70G，这里的二维电子气70G也即构成了导电区。
当器件开启时，栅极20G下方形成沟道，沟道中垂直投影位于导电区之间的部分构成实际的有效沟道。
实施例8
参图18，为平面型底栅结构TFT器件100H，并包括透光绝缘衬底40H、以及依次设置于衬底40H上的栅极20H、栅介质层30H、以及有源层10H。本实施例中，有源层10H两侧分别设置有上层金属源电极501H和金属漏电极502H，有源层10H可以采用非晶IGZO金属氧化物半导体层，源电极501H和漏电极502H与有源层10H之间形成欧姆接触。源电极501H、漏电极502H下方的部分有源层也即分别构成源极区域、漏极区域，沟道区域则位于源极区域和漏极区域之间。
通过在器件上层覆盖的钝化层中离子注入分别连接源电极501H和漏电极502H的正电荷区域60H。正电荷区域60H与栅极20H在沟道区域的垂直投影之间具有交叠部分，相对应的，该交叠部分的正电荷区域可以在沟道区域中形成分别与源极区域和漏极区域连接的二维电子气70H，这里的二维电子气70H也即构成了导电区。
当器件开启时，栅极20H上方形成沟道，沟道中垂直投影位于导电区70H之间的部分构成实际的有效沟道。
实施例9
参图19，为垂直结构SOI器件100I，并包括衬底60I、依次设置于衬底60I上的埋绝缘层50I和有源层10I、设置在有源层10I一侧的栅绝缘层30I、栅极20I。在远离衬底60I的方向上，源极区域101I和漏极区域102I分别位于有源层10I的下方和上方。沟道区域103I中形成有源极区域101I连通的等效源极1051I、以及与漏极区域102I连通的等效漏极1052I。
当在器件的栅极20I施加偏压使器件开启时，栅极20I控制在器件的沟道区域103I 中形成连接源极区域101I和漏极区域102I的沟道104I，但是，沟道104I中只有与等效源极1051I、等效漏极1052I在沟道区域103I上垂直投影之间不交叠的部分才构成用于器件开启时传输工作电流的有效沟道1041I，也即沟道104I中的剩余部分1042I并不用于传输器件开启时的工作电流。
在上述的各实施方式/实施例中，器件中的源极区域和漏极区域可以为常见的重掺杂半导体源漏，也可以是金属-半导体结构的肖特基金属源漏；栅极可以是常见的金属-绝缘层-半导体MOS结构栅极，也可以是金属半导体结构的肖特基结栅极；有源层可以是单一半导体材料构成，也可以是包括沿其厚度方向或者平面延伸方向变化的至少两种半导体材料以形成复合沟道。
并且，等效源极和等效漏极可以是自发形成的，也可以是通过相应结构的栅极控制形成。
总体而言，在上述的实施例中，有效沟道、等效源极和/或等效漏极在沟道区域上叠加的垂直投影连通源极区域和漏极区域，从而保证有效沟道与等效源极和/或等效漏极的载流子能够至少在厚度方向上发生单向或者双向的注入，并构建源极区域到漏极区域的载流子通路。当然，参照图20，本申请并不排除在一些特别的实施例中，如果有效沟道、等效源极和/或等效漏极在沟道区域103J上叠加的垂直投影并未能够连通器件100J的源极区域101J和漏极区域102J，而是具有一个“适当的间隔”，该间隔并未能完全切断载流子自等效源极1051J流向有效沟道1041J、以及自有效沟道1041J流向等效漏极1052J的通路，载流子在有效沟道1041J、等效源极1051J、等效漏极1052J之间的注入方向与沟道区域103J厚度方向呈一夹角，这样的实施方式也应当属于本申请的保护范围之内。
本申请还提供一种改善场效应晶体管器件短沟道效应和输出特性的方法的具体实施方式。在本实施方式中，该方法包括在器件的沟道区域设置远离器件有效沟道的等效源极和/或等效漏极，以使器件开启时，有效沟道通过所述等效源极和/或等效漏极连通器件的源极区域和漏极区域以形成工作电流。
由于这里的改善短沟道效应和输出特性的方法与上述场效应晶体管器件的结构实施方式实质上相对应，因此其可以部分或者全部地借鉴上述结构实施方式中的内容，在此不再赘述。
以下为应用本申请上述实施方式/实施例的SOI器件进行仿真验证的结果。在仿真中，将只设置等效源极、只设置等效漏极、和同时设置等效源极和等效漏极的器件分别称为等效源器件、等效漏器件和等效源漏器件。在仿真例中，上述器件的比较对象为常规SOI器件，其沟道长度和本发明器件的有效沟道长度相同，沟道材料和栅极等相关参数均保持一致。
仿真例1
仿真软件：Silvaco TCAD；
仿真中器件结构示意图如图21所示，具体参数如下：
①沟道区域材料均为Si，厚度0.05μm；
②沟道区P型掺杂浓度为1E17cm -3；
③栅绝缘层材料均为SiO 2，厚度17nm；
④常规SOI器件，沟道长度L＝0.1μm；
⑤发明器件的表观栅长L g＝0.2μm；
⑥发明器件的有效沟道长度L eff＝0.1μm；
⑦等效源器件，等效源极长度0.1μm；
⑧等效漏器件，等效源极长度0.1μm；
⑨等效源漏器件，等效源极和等效漏极长度均为0.05μm；
⑩源极、漏极区域N型掺杂浓度为1E20cm -3；
Figure PCTCN2021134782-appb-000001
形成等效源漏的沟道背界面处固定正电荷面密度为1E14cm -2；
Figure PCTCN2021134782-appb-000002
漏端电压Vd＝2V或0.1V；
参图21和图22，为本发明器件与常规SOI器件的转移特性对比图。从图21中可以看出，在Vd＝2V时，常规SOI器件亚阈值摆幅SS为479mV/dec。与之相比，等效漏器件(SS＝291mV/dec)和等效源器件(SS＝308mV/dec)的亚阈值摆幅均显著减小，而等效源漏器件(SS＝245mV/dec)亚阈值摆幅的改善尤为显著。比较图21和图22可以发现，常规SOI器件由于短沟道效应，Vd＝2V时器件阈值电压显著减小(Vd＝2V时阈值电压-0.36V相比于Vd＝0.1V时阈值电压0.17V减小了0.53V)，与之相比，本发明器件阈值电压的变化小得多(等效漏、等效源和等效源漏器件的阈值电压减小量分别仅为0.18V、0.14V和0.04V)。与此同时，本发明器件的场效应迁移率和常规SOI器件相比，仅有轻微下降(Vd＝2V时等效漏、等效源和等效源漏器件的迁移率分别为常规SOI器件迁移率的99.7％、94.9％和96.1％)。因此，本申请提供的各实施方式/实施例，能够在几乎不牺牲器件性能条件下有效改善器件的短沟道效应。
参图23和图24，为本发明器件与常规SOI器件的输出特性对比图。从图中可以看出，无论在Vg＝2V还是4V时，本发明器件的输出特性曲线都更为平坦，工作范围更宽。输出特性中对应于KINK电流显著发生的Vd值为V kink，V kink越大，则器件漏端耗尽区内的载流子碰撞离化效应越微弱，器件越难以发生kink电流效应。以Vg＝4V为例(图24)，常规SOI器件的V kink＝0.60V,而等效漏、等效源和等效源漏器件的V kink分别为1.10V,0.99V和1.26V，说明本发明器件能够有效减小器件工作时的载流子碰撞离化效应，抑制 KINK电流，改善器件的输出特性。同时，从图23和24观察，本发明器件的输出电流与常规SOI器件相当，没有任何下降。
本申请通过上述实施方式，具有以下有益的技术效果：
1)通过将器件设置成在开启时，能够于沟道区域中形成有效沟道、以及远离有效沟道的等效源极和等效漏极，从而连通源极区域和漏极区域以形成工作电流；这样，与漏极(源极)区域连通的等效漏极(源极)在结构上远离有效沟道，可以减小漏端电压对有效沟道的影响，从而改善了器件的短沟道效应。
2)本发明器件通过等效源极和等效漏极的设置，降低了器件在饱和工作状态下沟道漏端耗尽区中的峰值电场，大幅度减小器件漏端耗尽区的载流子碰撞离化效应，抑制了器件输出特性的kink电流，改善器件的输出特性。同时，本发明器件可以抑制器件的热载流子退化效应，提高器件的可靠性。
应理解的是，本发明所描述的实施方式仅出于示例性目的，并非用以限制本发明的保护范围，本领域技术人员可在本发明的范围内作出各种其他替换、改变和改进，因而，本发明不限于上述实施方式，而仅由权利要求限定。

Claims (21)

  1. 一种场效应晶体管器件，包括有源层，其特征在于，所述有源层包括源极区域、漏极区域以及位于所述源极区域和漏极区域之间的沟道区域；
    当器件开启时，所述沟道区域内形成有有效沟道以及远离所述有效沟道的等效源极和/或等效漏极，所述场效应晶体管器件通过所述有效沟道、以及等效源极和/或等效漏极连通所述源极区域和漏极区域以形成工作电流。
  2. 根据权利要求1所述的场效应晶体管器件，其特征在于，所述沟道区域中形成有不连通所述源极区域和漏极区域的导电区；其中，
    当所述导电区与所述源极区域连通时，所述导电区构成所述等效源极；
    当所述导电区与所述漏极区域连通时，所述导电区构成所述等效漏极。
  3. 根据权利要求2所述的场效应晶体管器件，其特征在于，包括设置于所述有源层一侧表面上的第一栅极，所述第一栅极和所述导电区在所述沟道区域上的垂直投影有交叠；其中，所述第一栅极可控制所述沟道区域并于其中形成沟道，所述沟道中与所述导电区在所述沟道区域上垂直投影之间不交叠的部分构成所述有效沟道。
  4. 根据权利要求2所述的场效应晶体管器件，其特征在于，所述导电区与所述有效沟道在所述沟道区域的厚度方向上有间隔。
  5. 根据权利要求3所述的场效应晶体管器件，其特征在于，当器件开启时，所述导电区的电导大于所述沟道中除有效沟道外其余部分的电导，以使所述导电区和有效沟道的至少其中之一可向其中另一注入载流子。
  6. 根据权利要求5所述的场效应晶体管器件，其特征在于，当器件开启时，所述导电区的电导至少大于所述沟道中除有效沟道外其余部分电导的三倍。
  7. 根据权利要求3所述的场效应晶体管器件，其特征在于，当器件开启时，所述沟道中有效沟道的单位长度电导大于所述沟道中除有效沟道外其余部分的单位长度电导。
  8. 根据权利要求7所述的场效应晶体管器件，其特征在于，当器件开启时，所述沟道中有效沟道的单位长度电导至少大于所述沟道中除有效沟道外其余部分的单位长度电导的三倍。
  9. 根据权利要求7或8所述的场效应晶体管器件，其特征在于，所述场效应晶体管器件包括设置于所述第一栅极和沟道区域之间的栅绝缘层，其中，所述栅绝缘层中与所述有效沟道对应部分的厚度小于其余部分栅绝缘层的厚度。
  10. 根据权利要求7或8所述的场效应晶体管器件，其特征在于，所述栅绝缘层中与所述有效沟道对应部分和其余部分栅绝缘层由不同材质制成。，
  11. 根据权利要求7或8所述的场效应晶体管器件，其特征在于，所述第一栅极中与所述有效沟道对应的部分和第一栅极的其余部分由不同功函数的材质制成。
  12. 根据权利要求2至8任一项所述的场效应晶体管器件，其特征在于，还包括设置于所述有源层临近导电区一侧表面的第二栅极，所述第二栅极可控制所述沟道区域中形成所述导电区。
  13. 根据权利要求2至8任一项所述的场效应晶体管器件，其特征在于，所述导电区由所述沟道区域在远离所述有效沟道一侧表面掺杂引入的载流子形成。
  14. 根据权利要求2至8任一项所述的场效应晶体管器件，其特征在于，还包括设置于所述有源层远离所述有效沟道一侧表面的绝缘层，所述导电区由所述绝缘层中的注入电荷通过静电感应在所述沟道区域临近绝缘层处生成的载流子构成。
  15. 根据权利要求2至8任一项所述的场效应晶体管器件，其特征在于，还包括设置于所述有源层远离所述有效沟道一侧表面的半导体材料层，所述有源层与所述半导体材料层形成异质结构，所述导电区由分布于所述异质结构中的二维电子气沟道或二维空穴气沟道构成。
  16. 根据权利要求2至8任一项所述的场效应晶体管器件，其特征在于，所述导电区由对所述沟道区域远离所述有效沟道的一侧表面进行表面处理形成的二维电子气沟道或二维空穴气沟道构成。
  17. 根据权利要求1至8任一项所述的场效应晶体管器件，其特征在于，所述源极区域和漏极区域为掺杂半导体或肖特基金属源漏。
  18. 根据权利要求1至8任一项所述的场效应晶体管器件，其特征在于，所述场效应晶体管器件的栅极为金属-绝缘层-半导体MOS结构栅极或者肖特基结栅极。
  19. 根据权利要求1至8任一项所述的场效应晶体管器件，其特征在于，所述有源层包括沿其厚度方向或者平面延伸方向变化的至少两种半导体材料。
  20. 根据权利要求1至8任一项所述的场效应晶体管器件，其特征在于，所述场效应晶体管器件为平面结构器件或垂直结构器件。
  21. 一种改善场效应晶体管器件短沟道效应和输出特性的方法，其特征在于，所述方法包括在器件的沟道区域设置远离器件有效沟道的等效源极和/或等效漏极，以使器件开启时，所述有效沟道通过所述等效源极和/或等效漏极连通器件的源极区域和漏极区域以形成工作电流。
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