WO2022160907A1 - 加成法制作封装电路的工艺和封装电路 - Google Patents

加成法制作封装电路的工艺和封装电路 Download PDF

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Publication number
WO2022160907A1
WO2022160907A1 PCT/CN2021/133491 CN2021133491W WO2022160907A1 WO 2022160907 A1 WO2022160907 A1 WO 2022160907A1 CN 2021133491 W CN2021133491 W CN 2021133491W WO 2022160907 A1 WO2022160907 A1 WO 2022160907A1
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insulating material
layer
photoresist
circuit
circuit pattern
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PCT/CN2021/133491
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English (en)
French (fr)
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张志强
张金强
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武汉光谷创元电子有限公司
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Publication of WO2022160907A1 publication Critical patent/WO2022160907A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/146—By vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143—Masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Definitions

  • the invention relates to circuit board fabrication and chip packaging technology, in particular to a process for fabricating a packaging circuit by an additive method and a packaging circuit prepared therefrom.
  • the packaging substrate mainly uses organic polymer materials such as BT and modified FR-4 as insulating materials, and is pressed with copper foil to produce circuit board circuit patterns, which are used to support IC chips and conduct current between the chip and the PCB circuit board. and signal.
  • organic polymer materials such as BT and modified FR-4 as insulating materials
  • circuit board circuit patterns which are used to support IC chips and conduct current between the chip and the PCB circuit board. and signal.
  • the line width/line spacing of the packaging substrate has developed to the stage of 25/25m, 15/15 ⁇ m, 8/8 ⁇ m and 5/5 ⁇ m. Facing the development trend and requirements of fine lines, the mainstream processes currently adopted by domestic and foreign manufacturers include improved semi-additive method (MSAP process) and semi-additive method (SAP process).
  • the MSAP process mainly uses thin copper foil/carrier copper foil with an R z value of about 2-3 ⁇ m (for example, 2 ⁇ m thin copper and 18 ⁇ m carrier copper foil from Mitsui Co., Japan) and insulating substrates to make package substrates and circuits.
  • the design of the foil reduces the etching amount of the line etching process, but the line width/line spacing is difficult to exceed 20/20 ⁇ m.
  • the SAP process includes chemical immersion nickel gold wet copper coating or sputtering dry copper coating, etc.
  • the surface of the insulating substrate and the hole wall are coated with copper of about 0.5 ⁇ m, which further reduces the copper thickness than the MSAP process and reduces the amount of line etching.
  • the above process mainly cuts the wafer into a single IC chip, and then implements back-end packaging with the packaging substrate, which can only be applied to traditional BGA and CSP packaging.
  • WLP and the subsequent development of PLP packaging technology use pin rerouting (RDL, Redistribution Layer) technology and temporary carriers to complete all or most of the steps of the manufacturing process on the wafer , and finally the wafer is directly cut and separated into several independent devices, without the need for a traditional packaging substrate to support and connect the chips.
  • RDL technology can change the original design of the line I/O, increase the I/O spacing, provide a large bump area, reduce the stress between the substrate and the component, and increase the reliability of the component.
  • WLP and PLP packaging technologies require line width/line spacing to be less than 10/10 ⁇ m.
  • the present invention is made in view of the above problems, and its purpose is to provide a process for manufacturing a packaged circuit by an additive method and a packaged circuit.
  • the smooth, low-roughness metallization and high bond between the line and the insulating material, without increasing the amount of fine line etching, can improve the processability of the packaged circuit.
  • the first technical solution provides a process for making a packaged circuit by an additive method, which includes the following steps: (a) covering the surface of the insulating material with a photoresist with a negative image of the circuit; ( b) forming a conductive seed layer by PVD ion plating in the exposed areas of the insulating material not covered by the photoresist; (c) forming a conductor thickening layer on the conductive seed layer; (d) stripping the photoresist, to form a surface circuit pattern; and, (e) electrically connecting the surface circuit pattern with the electronic component using solder bumps or conductor posts.
  • the exposed area of the insulating material includes a hole opened on the surface of the insulating material, and a conductive seed layer is formed on the hole wall of the hole.
  • the third technical solution is that in the above-mentioned first solution, the PVD ion plating utilizes Ni or Ni-Cr alloy as the target material, and the charged particles escaping from the target material are implanted under the surface of the exposed area to form the ion implantation layer, and /or deposit charged particles escaping from the target onto the surface of the exposed area to form a plasma deposited layer.
  • a fourth technical solution is that, in the above-mentioned first solution, copper is used to form a thickened conductor layer by pattern plating, the solder bumps are solder balls, and the conductor posts are copper posts.
  • step (a) includes: before covering the photoresist, the surface of the insulating material is treated by PVD ion plating to form a pretreatment layer;
  • step (d) includes: After stripping the photoresist, the pretreatment layer other than the surface circuit pattern is removed by micro-etching.
  • the insulating material is an insulating base material of a circuit board, and includes a composite material of BT resin or epoxy resin and glass fiber, and the electronic component is a chip. contact pads.
  • a seventh technical solution is, in any one of the above-mentioned first to fifth solutions, the insulating material is a photosensitive resin covering the surface of the PCB or the package substrate; the electronic component is a contact pad of the chip; the process includes: Before step (a), the photosensitive resin is exposed and developed to form blind holes, and then baked to cure the photosensitive resin.
  • the eighth technical solution is that, in the above seventh solution, a conductive seed layer and a conductor thickened layer are formed on the hole wall of the blind hole, so as to connect the circuit pattern of the PCB or package substrate on the side of the insulating material with the circuit pattern on the insulating material.
  • the contact pads on the other side are electrically connected.
  • a ninth technical solution is that, in the above seventh solution, the photosensitive resin includes photosensitive epoxy resin or photosensitive PI resin, and is provided with one or more layers.
  • a tenth technical solution is that in any one of the above-mentioned first to fifth solutions, before covering the photoresist, the process further includes: arranging the chips on the carrier, and covering the surface of the chip with an insulating material, so as to cover the chip sandwiched between a carrier and insulating material; opening holes in the insulating material to expose the contact pads of the chip; and roughening or PVD ion plating on the surface of the insulating material.
  • the insulating material is PI or BCB resin
  • the electronic component is a circuit pattern of a PCB or a package substrate.
  • the evaporating material particles have high kinetic energy after ionization, bombarding the workpiece at high speed, not only the deposition speed is fast, but also can penetrate the surface of the workpiece, inject into the matrix to form a deep diffusion layer, and adhere to each other very firmly.
  • the evaporating material particles move along the direction of the electric field in the electric field in the form of charged ions. Any part where the electric field exists can obtain a good coating, which is not restricted by the direction. Seams and other complex structures.
  • the ion-plating coating has a dense structure, no pinholes, no bubbles, and uniform thickness.
  • the above-mentioned metallized film process can reduce or at least not increase the etching amount of fine lines, achieve line width/line spacing below 10/10 ⁇ m, and at the same time realize high bonding force and smooth interface between lines and insulating materials, which can improve packaging. Circuit fabrication and processing capabilities.
  • a twelfth technical solution provides a packaged circuit including an insulating material, a surface circuit pattern formed on the insulating material, and electronic circuits electrically connected to the surface circuit pattern via solder bumps or conductor posts A component, wherein the surface circuit pattern includes a conductive seed layer formed on the surface of the insulating material or the wall of the hole, and a thickened layer of conductors formed on the conductive seed layer, the conductive seed layer including being located below the surface of the insulating material or the wall of the hole ion implantation layer, and/or a plasma deposited layer on the surface of the insulating material or on the walls of the pores.
  • the conductive seed layer includes Ni or Ni-Cr alloy
  • the conductor thickening layer is mainly composed of copper
  • the solder bumps are solder balls
  • the conductor posts are copper posts.
  • a fourteenth technical solution is that, in the above-mentioned twelfth or thirteenth solution, the insulating material is a photosensitive resin covering the surface of the PCB or the package substrate, and the electronic component is the contact pad of the chip.
  • the fifteenth technical solution is that in the twelfth or thirteenth solution, the insulating material covers the chips arranged on the carrier and sandwiches the insulating material and the carrier, and the electronic component is a circuit pattern of a PCB or a package substrate .
  • the bonding force between the insulating material and the surface circuit pattern is very high, which can reach 0.6-1.5N/mm, such as 0.8N/mm, 1.0N/mm and 1.2N/mm.
  • the surface circuit pattern will have a uniform and dense structure without defects such as pinholes, bubbles and cracks, and the minimum line width/line spacing can be reached Below 15/15 ⁇ m, even 10/10 ⁇ m, 8/8 ⁇ m.
  • FIG. 1 is a general flow chart showing the process of making a packaged circuit according to the additive method of the present invention.
  • 3(a) to 3(c) show various examples of conductive seed layers.
  • 5(a) to 5(f) are schematic diagrams showing cross-sectional structure changes in the process according to the third embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional view showing a packaged circuit with two RDL wiring layers produced by the process of the third embodiment.
  • FIG. 1 is a general flow chart showing the process of making a packaged circuit according to the additive method of the present invention. Specifically, the process mainly includes the following steps: covering the surface of the insulating material with a photoresist with a negative image of the circuit; in the exposed area of the insulating material not covered by the photoresist, forming a conductive layer by PVD ion plating a seed layer; forming a conductor thickening layer on the conductive seed layer; stripping the photoresist to form a surface circuit pattern; and electrically connecting the surface circuit pattern with the electronic components using solder bumps or conductor posts.
  • rigid substrates can be used, such as organic polymer rigid plates such as LCP, PTFE, CTFE, FEP, PPE, synthetic rubber plates, glass fiber cloth/ceramic filler reinforced plates, or ceramic plates, glass plates, etc.
  • Flexible substrates can also be used, such as PI, PTO, PC, PSU, PES, PPS, PS, PE, PP, PEI, PTFE, PEEK, PA, PET, PEN, LCP, PPA and other polymer films.
  • BT resin commonly used in PCB or composite insulating material of epoxy resin and glass fiber, or photosensitive epoxy resin or photosensitive PI resin commonly used in SLC surface laminar flow circuit, or PI or photosensitive PI resin commonly used in RDL wiring layer can be used.
  • the photoresist is mainly composed of photoinitiator, photoresist resin, monomer, solvent and other additives. It can transfer the required fine pattern from the mask to the to-be-to-be through photochemical reaction, through photolithography processes such as exposure and development.
  • the substrate is processed and used to protect the underlying substrate in subsequent processes.
  • the photoresist left on the surface of the insulating material has a circuit negative, ie, a pattern complementary to the final surface circuit pattern.
  • the surface of the insulating material can be pre-treated, such as roughening treatment, Hall source treatment, etc., to enhance the adhesion between the photoresist and the insulating material.
  • the exposed areas of the insulating material that are not covered by the photoresist are the areas in which the surface circuit patterns will be formed.
  • the exposed area includes a portion of the surface of the insulating material, and may also include through holes or blind holes opened in the surface.
  • the hole wall and the surface of the insulating material are continuous and integral, which is equivalent to a part of the surface.
  • the holes may be formed by mechanical drilling, punching, laser drilling, plasma etching, reactive ion etching, and the like.
  • ultraviolet laser drilling has the advantages of short wavelength, short pulse, excellent beam quality, high precision, high peak power, etc., and can significantly reduce the thermal effect and prevent the edge of the hole from being damaged by heat, so it is especially suitable for ultra-fine drilling.
  • Micropores up to 2-5 ⁇ m.
  • PVD ion plating refers to the partial ionization of the gas or the evaporated material by gas discharge under vacuum conditions, and under the bombardment of the gas ions or the evaporated material ions, the evaporated material or its reactant is deposited on the substrate in the form of charge transfer.
  • the method for completing the coating specifically includes magnetron sputtering ion plating, reactive ion plating, hollow cathode discharge ion plating (hollow cathode evaporation method), multi-arc ion plating (cathode arc ion plating) and the like.
  • the evaporation source is connected to the anode, the workpiece is connected to the cathode, and high-voltage direct current is applied to generate arc discharge between the evaporation source and the workpiece; under the action of the discharge electric field, part of the inert argon gas in the vacuum chamber is ionized, forming plasma around the workpiece Dark area; positively charged argon ions are attracted by the negative high voltage of the cathode, bombarding the surface of the workpiece, splashing out the particles and stains on the surface of the workpiece, so that the surface of the workpiece is fully cleaned; It melts and evaporates, enters the glow discharge area and is ionized; the positively charged evaporative ions are attracted by the cathode and rush to the workpiece together with the argon ions, and bombard the surface of the workpiece violently at a high speed, which is equivalent to a high-speed warhead shot from the barrel , which can penetrate deep into the substrate and form a
  • the evaporating material particles are only evaporated to the workpiece surface with an energy of about 1eV, the interface diffusion depth formed between the workpiece surface and the coating layer is only a few hundred angstroms, and there is almost no transition layer between the two.
  • the ionized evaporating material particles have high kinetic energy, bombarding the workpiece at high speed, not only the deposition speed is fast, but also can penetrate the surface of the workpiece, inject into the matrix to form a deep diffusion layer, and adhere to each other particularly firmly.
  • the evaporating material particles move along the direction of the electric field in the electric field in the form of charged ions. Any part where the electric field exists can obtain a good coating, which is not restricted by the direction.
  • the ion-plating coating has a dense structure, no pinholes, no bubbles, and uniform thickness. It can also repair defects such as tiny cracks and pits on the surface of the workpiece, so it can effectively improve the surface quality and physical and mechanical properties of the workpiece.
  • ion plating itself has the effect of ion bombardment cleaning, which continues to the entire coating process, which can greatly simplify the cleaning of substrates.
  • the depth of the charged particles of the evaporation into the surface of the workpiece can be simply adjusted, and then the bonding force between the substrate and the conductive layer can be adjusted.
  • voltages in the range of 1 kV to 1000 kV such as 10 kV, 50 kV, 100 kV, 200 kV, 500 kV, etc., can be used to cause evaporative charged particles to penetrate below the surface of the workpiece to a depth of, for example, 100 nm.
  • a doping structure which can also be called an ion implantation layer.
  • the outer surface of the ion implantation layer is flush with the surface of the substrate, while the inner surface is deep into the interior of the substrate, ie below the surface of the substrate.
  • voltages of tens to hundreds of volts can also be used to cause the evaporative charged particles to be deposited on the surface of the workpiece at a higher velocity in a certain direction, rather than penetrating deep below the surface.
  • the conductive layer deposited on the surface of the workpiece may be referred to as a plasma deposited layer. Both the ion implantation layer and the plasma deposition layer have certain conductivity and can be collectively referred to as conductive seed layers to assist subsequent electroplating.
  • PVD ion plating uses high-energy ions to bombard the surface of the workpiece, converts electrical energy into heat energy on the surface of the workpiece, and promotes the diffusion and chemical reaction of the surface tissue.
  • the entire workpiece, especially the core is not affected by high temperature, so this process has a wide range of applications and can be used for various metals, alloys, and certain synthetic materials, insulating materials, heat-sensitive materials and high-melting-point materials.
  • the used evaporative material is a conductive material, which can include metals such as Ti, Cr, Ni, Cu, Ag, Al, Au, V, Zr, Mo, Nb, In, Sn, Tb, etc., oxides such as In 2 O 3 , SnO 2 , TiO 2 , WO 3 , MoO 3 and Ga 2 O 3 , etc., sulfides such as CdS, ZnS, etc., nitrides such as TiN, etc., carbides such as WC, VC, Cr 4 C 3 and so on.
  • Multiple ion implantation layers and/or plasma deposition layers with different properties can be formed on the workpiece substrate in stages using the same target material and using different accelerating voltages.
  • a higher accelerating voltage can be used to make the conductive material particles penetrate into the interior of the workpiece substrate, and then a lower accelerating voltage can be used, and then the conductive material particles can be deposited on the surface of the workpiece substrate, forming an inner to outer A conductive seed layer consisting of an ion-implanted layer and a plasma-deposited layer.
  • the conductor thickening layer is designed to quickly and efficiently thicken the surface circuit pattern to improve the conductivity and meet the requirements of conducting current and signals.
  • Conductive metals such as Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb or their Alloy between, plated onto the previously formed conductive seed layer to form the conductor thickening layer.
  • the electroplating method has fast coating speed and low cost, and can be applied to a wide range of materials, especially Cu, Ni, Sn, Ag, etc.
  • the thickness and even the conductivity of the conductor thickened layer can be adjusted by changing parameters such as coating time, and can reach 1 ⁇ m-100 ⁇ m, such as 5 ⁇ m, 10 ⁇ m, 50 ⁇ m, etc. Since a uniform and dense conductive seed layer has been previously formed on the surface of the substrate by ion plating, it is easy to form a uniform and dense thickened conductor layer on the conductive seed layer by the above method.
  • the photoresist is stripped. At this time, the exposed area of the insulating material that is not covered by the photoresist will retain the conductive seed layer and the conductor thickening layer formed previously, and the hidden area covered by the photoresist will expose the insulating material itself.
  • a surface circuit pattern complementary to the pattern of the photoresist is formed on the surface of the photoresist. Then, the entire surface of the insulating material can also be quickly micro-etched to remove the conductive substances originally located under the photoresist and ensure the integrity and accuracy of the surface circuit patterns.
  • Solder bumps can be implemented with small spherical conductive materials, usually solder balls, and gold, silver, copper, cobalt, etc., as needed. After the chip fabrication process is completed, UBM contact pads may be formed on the contact pads of the chip, and then solder bumps may be deposited on the UBM contact pads. When the die to which the solder bumps are attached is flip-chip and aligned with the circuit board, the electrical connection between the die and the circuit board is easily achieved. Flip-chip technology based on solder bumps has many advantages over traditional wire bonding, such as smaller package size, faster device speed, higher reliability and heat dissipation.
  • conductor posts such as copper posts
  • Solder bumps or conductor posts can realize interconnection between circuit boards, between chips, or between circuit boards and chips.
  • the package substrate is used as the substrate for chip support and circuit connection
  • PVD ion plating is used to metallize the surface or holes of the package substrate
  • the package substrate formed with the surface circuit pattern and the contact pads of the chip are Electrical connections are made to complete the circuit package.
  • FIG. 2( a ) shows an insulating material 10 used as an insulating base material of a circuit board.
  • the insulating material may include BT resin, or a composite insulating material of epoxy resin and glass fiber.
  • the epoxy resin is preferably an epoxy resin with high heat resistance, that is, an epoxy resin having a Tg value (glass transition temperature) of more than 170°C.
  • Tg glass transition temperature
  • the insulating material 10 is shown in the figures as having a flat surface, but may also have through holes or blind holes or the like opening in the surface, as described above. At this time, the hole wall of the through hole or the blind hole is continuous with the surface of the insulating material, and may correspond to a part of the surface.
  • the surface of the insulating material 10 may be treated, such as roughening treatment, Hall source treatment, etc., to enhance the adhesion between the photoresist and the insulating material.
  • positively charged argon ions are attracted by the negative cathode high voltage to bombard the surface of the insulating material 10, and the particles and stains on the surface of the material are splashed out, so that the surface is fully cleaned.
  • the positively charged evaporite ions are attracted by the cathode and violently bombard the surface of the insulating material together with the argon ions to form a pretreatment layer 12 with certain conductivity on the surface, as shown in Figure 2(b ) shown.
  • micro-etching must be performed after stripping the photoresist to remove the pretreatment layer 12 under the photoresist, as shown in FIG. 2(f).
  • a photoresist 14 is covered on the surface of the insulating material 10 , and a part of the photoresist 14 is removed by photolithography processes such as exposure and development to form a photoresist 14 with a negative circuit image. That is, the photoresist 14 has a pattern complementary to the desired surface circuit pattern. At this time, the exposed areas of the insulating material 10 that are not covered by the photoresist 14 will correspond to the desired surface circuit pattern.
  • a conductive seed layer 16 is formed in the exposed regions of the insulating material 10 that are not covered by the photoresist 14 through the aforementioned PVD ion plating.
  • the conductive seed layer 16 is shown as being formed only on the surface of the insulating material 10 , but may actually be formed on the surface and hole walls of the photoresist 14 , and is omitted for clarity.
  • Ni or Ni-Cr alloy (Ni80%-Cr20%) is used as the target, and by adjusting the process parameters such as voltage and current, the charged particles escaping from the target are injected under the surface of the exposed area to An ion implantation layer is formed to a thickness of about 10 nm to 50 nm, or charged particles are deposited on the surface of the exposed area to form a plasma deposited layer of a thickness of about 100 nm to 500 nm.
  • Ti is usually used as a sputtering bottom layer, resulting in the use of hydrofluoric acid HF in the subsequent etching process, and hydrofluoric acid is very harmful to the human body and also causes serious pollution to the environment.
  • the present invention uses Ni or Ni-Cr alloy to form a conductive seed layer, only a small amount of Cr is used to improve the corrosion resistance of the packaged circuit, the life and reliability of the circuit can be improved, and at the same time, serious environmental pollution can be avoided.
  • the previously formed conductive diameter layer 16 usually has a relatively thin thickness and poor conductivity, which is difficult to meet the requirements of the circuit board for transmitting power and signals.
  • a conductor thickening layer 18 is formed on the conductive seed layer 16 by pattern plating. At this time, pattern plating can be performed with copper in an electroplating bath to thicken the conductive seed layer 16 to meet the required conductivity.
  • the conductor thickening layer 18 is shown as having a lower outer surface than the outer surface of the photoresist 14 , but its outer surface may also be flush with or higher than the outer surface of the photoresist 14 .
  • the photoresist 14 is peeled off, thereby forming a surface circuit pattern 20, as shown in FIG. 2(f).
  • the entire surface of the insulating material 10 must be micro-etched rapidly to remove the pre-treatment layer 12 hidden under the photoresist and ensure the surface circuit pattern. The accuracy of 20 will not cause a short circuit.
  • part of the thickened conductor layer 18 is also etched away, but the overall conductivity is not affected.
  • the conductive thickened layer 18 over the photoresist 14 is also peeled off together with the photoresist 14, and the conductive seed layer 16 and the conductor thickened layer in the exposed area are also peeled off.
  • the thick layer 18 remains to form the final surface circuit pattern 20 .
  • the surface circuit patterns 20 of the circuit board are electrically connected to the contact pads 26 of the chip 24 by using solder bumps or conductor posts 22 .
  • the contact pads 26 of the chip correspond to the "electronic component" of the present invention.
  • a Ni-Au layer or other conventional surface treatment layers may be formed on the surface of the surface circuit pattern 20 by arc or electroless plating to enhance the connection between the solder bumps or conductor posts 22 and the surface circuit pattern 20 .
  • the chip 24 is shown in an upside-down state, that is, with the active area of the chip (contact pad 26) facing the substrate, and through the solder bumps or conductor posts 22 arranged on the chip, the connection with the circuit board is realized. interconnected.
  • the chip is mounted on the circuit board in an upside-down manner, and then I/O is drawn out from the chip to the surrounding, which can greatly shorten the interconnection length, reduce the RC delay, and effectively improve the electrical performance.
  • 3(a) to 3(c) show various examples of conductive seed layers that may be used as the conductive seed layer 16 shown in FIGS. 2(d) to 2(g).
  • PVD ion plating uses very high accelerating voltages, such as voltages in the range of 1kV-1000kV, to inject charged particles under the surface of the insulating material at very high speeds to form ions Implant layer 161 .
  • the outer surface of the ion implantation layer 161 is flush with the surface of the insulating material, and the inner surface is deep into the insulating material.
  • the ion implantation layer 161 may include one or more layers, which may be composed of the same or different materials.
  • charged particles are forcibly injected into the insulating material at a high speed, which is equivalent to laying down a large number of foundation piles.
  • the bonding force between the insulating material and the conductive layer (such as the plasma deposition layer or the conductor thickening layer) formed on the ion implantation layer can be very high, for example, more than 0.5N/mm, or even 0.7-1.5N/mm.
  • the target particles are usually nano-scale, and move along the direction of the electric field in the electric field in the form of charged ions during ion plating, so that good plating can be obtained wherever there is an electric field.
  • the charged ions are not only able to follow straight lines, but can evenly coat complex structures such as inner holes, grooves and slits of the workpiece along the lines of force.
  • the ion implantation layer has a dense structure, no pinholes, no bubbles, and a uniform thickness, and can also ensure that the conductive layer (such as a plasma deposition layer or a thick conductor layer) formed thereon has good uniformity and density. , and is not prone to defects such as pinholes, cracks or falling off.
  • the conductive layer such as a plasma deposition layer or a thick conductor layer
  • a plasma deposition layer 162 is also formed over the ion implantation layer 161 .
  • PVD ion plating uses a voltage of tens to hundreds of V, so that charged particles are deposited on the surface of the insulating material at a higher speed in a certain direction under the action of an electric field, rather than penetrating below the surface.
  • the plasma deposited layer 162 may have a thickness of 100 nm-500 nm, such as 200 nm, 300 nm, 400 nm, and the like.
  • a conventional magnetron sputtering method may be used to form a sputtered deposition layer on the ion implantation layer 161 , and the sputtered deposition layer and the ion implantation layer 161 together constitute a conductive seed layer.
  • the plasma deposited layer 162 or sputter deposited layer may comprise one or more layers, which may be composed of the same or different materials.
  • the plasma-deposited layer 162 or sputter-deposited layer may be composed of the same material as the conductive material (eg, Ni or Ni-Cr alloy) implanted inside the insulating material, or it may be composed of the conductive material and the conductor thickening layer material (eg, copper) ) to provide a good transition between the ion implantation layer 161 and the conductor thickening layer 18.
  • the conductive material eg, Ni or Ni-Cr alloy
  • the conductor thickening layer material eg, copper
  • the ion implantation layer 161 is not formed, but the plasma deposition layer 162 is formed directly on the surface of the insulating material.
  • PVD ion plating uses a voltage of tens to hundreds of V, so that the charged particles of the target material are directly deposited on the surface of the insulating material at a high speed in a certain direction under the action of an electric field, and diffusion is formed at the interface.
  • the diffusion layer is relatively thin, but due to the directionality and speed of the charged particles, it can still ensure that the insulating material and the conductive layer have a large binding force and are not easy to fall off.
  • the nano-scale charged particles move along the direction of the electric field in the electric field, and are evenly plated around the surface of the insulating material to form a dense, pinhole-free, bubble-free, and uniform-thickness plasma deposition layer, which can also ensure the subsequent formation on the surface of the insulating material.
  • the conductor thickening layer on the top has good uniformity and compactness, and is not prone to defects such as pinholes, cracks or falling off.
  • the package circuit formed by the process of the above-mentioned first embodiment includes an insulating material 10, a surface circuit pattern 20 formed on the insulating material 10, and the surface circuit via solder bumps or conductor posts 22.
  • the electronic components to which the pattern 20 is electrically connected are the contact pads 26 of the chip 24 .
  • the surface circuit pattern 20 includes a conductive seed layer 16 formed on the surface of the insulating material or the wall of the hole, and a conductor thickened layer 18 formed on the conductive seed layer 16.
  • the conductive seed layer 16 further includes the insulating material 10.
  • the bonding force between the insulating material in the above packaged circuit and the surface circuit pattern can reach 0.6-1.5N/mm, such as 0.8N/mm, 1.0N/mm and 1.2N/mm.
  • the surface circuit pattern of the packaged circuit has a uniform and dense structure without defects such as pinholes, bubbles and cracks. 8 ⁇ m.
  • the workpiece In contrast, in conventional vacuum evaporation, the workpiece is clamped in a vacuum hood. After being heated by electricity, the evaporating material is melted and evaporated, and the evaporating material particles gain a certain kinetic energy and adhere to the surface of the workpiece along random directions to form a film. .
  • the coating layer formed in this way has neither strong chemical bonding nor diffusion connection with the workpiece surface, and the adhesion performance is very poor.
  • the bonding force can only reach about 0.4-0.5N/mm, which is far lower than that of ion plating.
  • the minimum line width/spacing of the packaged circuit made by the traditional MSAP and SAP process can only reach 18/18 ⁇ m at most, which is far less than the above-mentioned value of ion plating.
  • PVD ion plating is performed on the surface or hole wall of the photosensitive insulating medium in the surface laminar flow circuit (SLC, Surface Laminar Circuit) structure provided on a conventional circuit board or a package substrate, and the photosensitive insulating medium is formed on the The surface circuit pattern is then electrically connected with the contact pads of the chip to complete the circuit package.
  • SLC Surface Laminar Circuit
  • FIG. 4( a ) shows a conventional PCB or package substrate 28 with a wiring pattern 30 .
  • the illustrated PCB or package substrate 28 includes two layers of substrates and is provided with through holes penetrating the two layers of substrates, and the circuit patterns 30 are formed between the two layers of substrates, on the outer surfaces of the two layers of substrates, and on the walls of the through holes. superior. It should be understood, however, that any other form of PCB circuit board or package substrate is feasible.
  • the insulating material 10 is covered on the surface of the PCB or the package substrate 28 to form a laminated structure.
  • the insulating material 10 may be a photosensitive resin, such as a photosensitive epoxy resin or a photosensitive PI resin.
  • the photosensitive resin contains photosensitive or photosensitive components, which are used for photosensitive fabrication of blind holes, and at the same time as the insulating medium layer of the circuit board.
  • the photosensitive resin and the PCB or the package substrate 28 may be bonded together by rolling or coating under a certain vacuum.
  • the photosensitive resin is subjected to pattern exposure and development to produce blind holes 32, and then high temperature baking is performed to cure the photosensitive resin into an insulating medium layer, thereby obtaining an insulating material surface with blind holes.
  • the hole wall of the blind hole is continuous and integral with the outer surface of the insulating material, and can be equivalent to a part of the surface of the insulating material.
  • a photoresist is coated on the surface of the insulating material 10 provided with the blind holes 32 , followed by pattern exposure and development, so that the blind holes 32 and the circuit patterns 20 corresponding to the final surface are formed.
  • the surface part is exposed, and then the conductive seed layer 16 is formed on the surface part and the hole wall of the blind hole by PVD ion plating, and then the conductor thickening layer 18 is formed on the conductive seed layer 16 by pattern electroplating copper, and finally stripped photolithography glue to form the surface circuit pattern 20 composed of the conductive seed layer 16 and the conductor thickened layer 18 .
  • the insulating material 10 on which the surface circuit pattern 20 is formed may be referred to as a surface laminar current circuit (SLC), and can be directly electrically connected to electronic components and encapsulated.
  • the formation process of the conductive seed layer 16 and the conductor thickened layer 18 may refer to the first embodiment, that is, the steps shown in FIG. 2( b ) to FIG. 2( f ).
  • the surface of the PCB or package substrate 28 may be pre-treated as shown in FIG. After the photoresist 14, the pretreatment layer 12 previously covered by the photoresist is removed by micro-etching.
  • the conductive seed layer 16 may include any one of the structures shown in FIG. 3( a ), FIG. 3( b ) or FIG. 3( c ).
  • the steps shown in FIGS. 4(b) and 4(c) can also be repeated, that is, on the surface of the first SLC wiring layer 33, sequentially covering the photosensitive resin insulating material and coating photoresist for pattern exposure. and development, using PVD ion plating to form a conductive seed layer 16, using patterned copper plating to form a conductor thickening layer 18, and then peeling off the photoresist to obtain a second SLC wiring layer 33 formed with a surface circuit pattern, as shown in Figure 4 (d). ) shown in.
  • the second SLC wiring layer 33 is used for electrical connection and packaging with electronic components.
  • the insulating material 10 is shown in FIGS. 4(b) to 4(d) as being provided only on the upper surface of the PCB or package substrate 28, it should be understood that when forming the laminate structure, it may be The upper and lower surfaces of the substrate 28 are provided with insulating materials 10, which are laminated in the order of photosensitive resin-inner layer core board-photosensitive resin, and then surface circuit patterns 20 are formed on the upper and lower surfaces. method to obtain a 1+n+1 structure. Repeat the above-mentioned "photosensitive resin-inner-layer core board-photosensitive resin" lamination to produce packaged circuit structures of 2+n+2, 3+n+3 or 4+n+4 structures.
  • the surface circuit patterns 20 in the SLC wiring layer 33 are electrically connected to the contact pads 26 of the chip 24 using solder bumps or conductor posts 22 .
  • the contact pads 26 of the chip correspond to the "electronic component" of the present invention.
  • the conductive seed layer 16 and the conductor thickening layer 18 formed on the hole wall of the blind hole can connect the circuit pattern 30 of the PCB or package substrate 28 on one side of the insulating material with the circuit pattern 30 of the chip 24 on the other side of the insulating material.
  • the contact pads 26 are electrically connected.
  • a Ni-Au layer or other conventional surface treatment layers may be formed on the surface of the surface circuit pattern 20 by arc or electroless plating to enhance the connection between the solder bumps or conductor posts 22 and the surface circuit pattern 20 .
  • the chip 24 is also shown in the inverted state as in the first embodiment, ie with the active areas of the chip (contact pads 26) facing the substrate. The interconnection between the chip and the SLC wiring layer is achieved through solder bumps or conductor posts 22 arranged on the chip.
  • SLC wiring layers form the basis of the currently popular low-cost organic packaging substrates, constructed using, in turn, a dielectric layer made of photosensitive resin followed by a copper-plated conductor plane, where the circuit build-up layers are connected vertically through microvias to support applications such as flip-chip Heterogeneous integration such as installation.
  • the package circuit formed by the process of the second embodiment includes an insulating material 10, a surface circuit pattern 20 formed on the insulating material 10, and the surface circuit via solder bumps or conductor posts 22. Electronic components to which the pattern 20 is electrically connected.
  • the insulating material is a photosensitive resin covering the surface of the PCB or package substrate, and the electronic component is the contact pad 26 of the chip 24.
  • the surface circuit pattern 20 constitutes a part of the SLC wiring layer 33, and includes the conductive seed layer 16 formed on the surface of the insulating material or the wall of the hole, and the conductor thickened layer 18 formed on the conductive seed layer 16, the conductive seed layer 16 in turn includes an ion implantation layer 161 located below the surface or hole walls of the insulating material 10 and/or a plasma deposited layer 162 located above the surface or hole walls of the insulating material 10 .
  • the packaged circuit has excellent heat resistance, and the bonding force between the insulating material (ie, the photosensitive resin) and the surface circuit pattern is very high, which can reach 0.6. -1.5N/mm, such as 0.8N/mm, 1.0N/mm and 1.2N/mm, etc.
  • the surface circuit pattern has a uniform and dense structure without defects such as pinholes, bubbles and cracks, and the minimum line width/line spacing can reach below 15/15 ⁇ m, even 10/10 ⁇ m, 8/8 ⁇ m.
  • FIGS. 5(a) to 5(e) are schematic diagrams showing cross-sectional structure changes in the process according to the third embodiment of the present invention.
  • the chip is covered with an insulating material, and then the surface of the insulating material is metallized by PVD ion plating to form a surface circuit pattern, and finally The surface circuit pattern is electrically connected with the circuit pattern of the PCB or package substrate to complete the circuit package.
  • RDL Redistribution Layer
  • Figure 5(a) shows a chip of the RDL process. Specifically, a plurality of chips 24 are arranged on a carrier 34 so that the contact pads 26 of the chips 24 are exposed on the surface of the carrier 34 to facilitate subsequent electrical connections.
  • the insulating material 10 is covered to sandwich the chip 24 between the carrier 34 and the insulating material 10 .
  • the insulating material 10 and the surface of the chip 24 can be closely attached together by rolling or coating under a certain vacuum.
  • the insulating material 10 may be PI (polyimide) or BCB (bisphenylcyclobutene) resin, and the thickness is about 5 ⁇ m.
  • the insulating material 10 is then opened to expose only the contact pads 26 of the chip 24 .
  • the hole wall of the hole opened in the insulating material 10 is continuous and integral with the outer surface thereof, and may correspond to a part of the surface of the insulating material.
  • a photoresist 14 is coated, followed by pattern exposure and development, so that the contact pads 26 of the chip 24 and the desired surface
  • the surface portion corresponding to the circuit pattern 20 ie, the portion where the photoresist 14 does not exist on the right side in the figure
  • the thickness of the photoresist can be 5 ⁇ m-10 ⁇ m.
  • the illustrated hole wall of the photoresist 14 and the hole wall of the insulating material 10 are aligned with each other, but may not be aligned with each other.
  • the aperture in photoresist 14 may be smaller than the aperture in insulating material 10 as long as a portion of contact pad 26 is exposed.
  • the surface of the insulating material 10 may be processed, such as roughening treatment, Hall source treatment, etc., to enhance the adhesion between the photoresist and the insulating material.
  • PVD ion plating can be performed on the surface of the insulating material 10 to form the pretreatment layer 12 as shown in FIG. 2(b), and after the photoresist 14 is peeled off, it is removed by micro-etching before being covered by the photoresist The pretreatment layer 12.
  • the conductive seed layer 16 may also include any one of the structures shown in FIG. 3( a ), FIG. 3( b ) or FIG. 3( c ).
  • the photoresist is peeled off to form a surface circuit pattern 20 composed of the conductive seed layer 16 and the conductor thickened layer 18 .
  • the insulating material 10 on which the surface circuit pattern 20 is formed can be referred to as an RDL wiring layer, and can be directly electrically connected to electronic components and encapsulated.
  • the part of the RDL wiring layer that is directly connected to the contact pads 26 can be used to conduct the chip electrodes and electronic components, while the parts that are not directly connected to the contact pads 26 (ie, the several pillars shown on the right side of the figure) are used for Rewire to form part of the wiring pattern.
  • the formation process of the conductive seed layer 16 and the conductor thickened layer 18 may refer to the first embodiment, that is, the steps shown in FIG. 2( b ) to FIG. 2( f ).
  • the surface circuit pattern 20 of the RDL wiring layer is electrically connected to the circuit pattern 30 of the PCB or package substrate 28 by using solder bumps or conductor posts 22 .
  • the wiring pattern 30 of the package substrate 28 corresponds to the "electronic component" of the present invention.
  • a Ni-Au layer or other conventional surface treatment layer may be formed on the surface of the circuit pattern 30 by arc or electroless plating to enhance the connection between the solder bump or the conductor post 22 and the circuit pattern 30 .
  • the chip 24 is also shown in an inverted state as in the first and second embodiments, with the active areas of the chip (contact pads 26 ) facing the PCB or package substrate 28 .
  • the RDL process is essentially adding one or several wiring layers on the original wafer, first depositing a layer of dielectric for isolation, then exposing the contact pads of the wafer chip, and then depositing a new metal layer to achieve the wiring.
  • Contact redistribution at the wafer level can be done efficiently, and the redistribution layer can help reroute the wires to the desired area, and also help achieve higher contact densities and lower Line width/line spacing.
  • the package circuit formed by the process of the third embodiment includes an insulating material 10 , a surface circuit pattern 20 formed on the insulating material 10 , and the surface circuit via solder bumps or conductor posts 22 .
  • Electronic components to which the pattern 20 is electrically connected The insulating material 10 covers and sandwiches the chips 24 arranged on the carrier 34 between the insulating material and the carrier, and the electronic component is the circuit pattern 30 of the PCB or the package substrate 28 .
  • the surface circuit pattern 20 constitutes a part of the RDL wiring layer, including the conductive seed layer 16 formed on the surface of the insulating material or the wall of the hole, and the conductor thickened layer 18 formed on the conductive seed layer 16.
  • the conductive seed layer 16 is in turn It includes an ion implantation layer 161 located below the surface of the insulating material 10 or the wall of the hole, and/or a plasma deposited layer 162 located above the surface of the insulating material 10 or the wall of the hole.
  • the steps shown in FIGS. 5(b) to 5(e) can also be repeated.
  • the photoresist 14 On the surface of the first RDL wiring layer, sequentially cover the insulating material 10, coat the photoresist 14 for pattern exposure and development, The conductive seed layer 16 is formed by PVD ion plating, the conductor thickening layer 18 is formed by patterned copper electroplating, and then the photoresist is peeled off to obtain a second RDL wiring layer formed with a surface circuit pattern. The second RDL wiring layer and electronic components are used. Make electrical connections and packaging.
  • FIG. 6 shows a package circuit including two RDL wiring layers 36, wherein the second RDL wiring layer 36 on the lower side and the first RDL wiring layer 36 on the upper side are electrically connected to each other, and the wiring paths are re-planned so that the first RDL wiring layer 36 on the lower side is electrically connected to each other.
  • the surface circuit patterns of the two RDL wiring layers 36 are different from those of the first RDL wiring layer 36 and the chip 24 .
  • the packaged circuit has excellent heat resistance, and the bonding force between the insulating material (ie, the photosensitive resin) and the surface circuit pattern is very high, which can reach 0.6. -1.5N/mm, such as 0.8N/mm, 1.0N/mm and 1.2N/mm, etc.
  • the surface circuit pattern has a uniform and dense structure without defects such as pinholes, bubbles and cracks, and the minimum line width/line spacing can reach below 15/15 ⁇ m, even 10/10 ⁇ m, 8/8 ⁇ m.

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Abstract

一种加成法制作封装电路的工艺和封装电路。加成法制作封装电路的工艺包括以下步骤：(a)在绝缘材料(10)的表面上，覆盖带有电路负像的光刻胶(14)；(b)在所述绝缘材料(10)的未被所述光刻胶(14)覆盖的暴露区域中，通过PVD离子镀形成导电籽晶层(16)；(c)在所述导电籽晶层(16)上形成导体加厚层(18)；(d)剥离所述光刻胶(14)，以形成表面电路图案(20)；以及，(e)利用焊料凸点或导体柱(22)，将所述表面电路图案(20)与电子构件电连接。

Description

加成法制作封装电路的工艺和封装电路 技术领域
本发明涉及电路板制作和芯片封装技术，尤其涉及一种加成法制作封装电路的工艺和由此制得的封装电路。
背景技术
封装基板主要以BT、改性FR-4等有机高分子材料作为绝缘材料，与铜箔压合后制出电路板线路图形，用以支撑IC芯片，导通芯片与PCB电路板之间的电流及信号。随着电子产品朝高性能、小型化发展，封装基板的线宽/线距目前发展到25/25m、15/15μm、8/8μm、5/5μm的阶段。面对精细线路的发展趋势和要求，国内外厂家目前采用的主流工艺包括改良型半加成法(MSAP工艺)和半加成法(SAP工艺)。
MSAP工艺主要借助R z值约2-3μm的薄铜箔/载体铜箔(例如，日本三井公司的2μm薄铜和18μm载体铜箔)与绝缘基材制成封装基板和线路，凭借2μm薄铜箔的设计，减少了线路蚀刻过程的蚀刻量，但线宽/线距难以突破20/20μm。SAP工艺包括化学沉镍金湿法覆铜或溅射法干法覆铜等，对绝缘基材的表面和孔壁覆铜0.5μm左右，比MSAP工艺进一步减薄铜，减少了线路蚀刻量，但是线宽/线距也很难提升至15/15μm以下。
从芯片封装技术看，上述工艺主要将圆晶片切割成单个IC芯片，再与封装基板实施后道封装，只能应用于传统的BGA和CSP封装。WLP及后续发展的PLP封装技术(包括扇入和扇出两种形式)借助引脚重新布线(RDL，Redistribution Layer)技术和临时载具等，在晶圆上完成制作工序的全部或大部分步骤，最后将晶圆直接切割分离成若干独立器件，而不需要传统的封装基板来支撑和连接芯片。其中，RDL技术可以改变线路I/O原有的设计，加大I/O间距，提供大的凸点面积，降低基板与元件间的应力，并增加元件可靠性。
在现有技术中，WLP和PLP封装技术要求线宽/线距为10/10μm以下。线宽/线距设计越小，线路可靠性越是依赖于线路与绝缘基材间的结合力。如何实现一种线路结合力高、且不增加精细线路蚀刻量的工艺，是现有封装电路亟需解决的问题。
发明内容
本发明是鉴于上述问题做出的，其目的在于，提供一种加成法制作封装电路的工艺和封装电路，该工艺能够实现10/10μm以下的线宽/线距，同时实现绝缘材料界面的光滑、低粗糙度的金属化以及线路与绝缘材料之间的高结合力，不增加精细线路蚀刻量，能够提高封装电路的加工能力。
根据本发明的一方面，第一技术方案提供一种加成法制作封装电路的工艺，其包括以下步骤：(a)在绝缘材料的表面上，覆盖带有电路负像的光刻胶；(b)在绝缘材料的未被光刻胶覆盖的暴露区域中，通过PVD离子镀形成导电籽晶层；(c)在导电籽晶层上形成导体加厚层；(d)剥离光刻胶，以形成表面电路图案；以及，(e)利用焊料凸点或导体柱，将表面电路图案与电子构件电连接。
第二技术方案为，在上述第一方案中，绝缘材料的暴露区域包括在绝缘材料的表面开口的孔，在孔的孔壁上形成有导电籽晶层。
第三技术方案为，在上述第一方案中，PVD离子镀利用Ni或Ni-Cr合金作为靶材，将从靶材逸出的带电粒子注入到暴露区域的表面下方以形成离子注入层，和/或将从靶材逸出的带电粒子沉积到暴露区域的表面上以形成等离子体沉积层。
第四技术方案为，在上述第一方案中，通过图形电镀，利用铜形成导体加厚层，焊料凸点为焊锡球，并且导体柱为铜柱。
第五技术方案为，在上述第一方案中，步骤(a)包括：在覆盖光刻胶之前，通过PVD离子镀对绝缘材料的表面进行处理，以形成前处理层；步骤(d)包括：在剥离光刻胶之后，通过微蚀去除表面电路图案以外的前处理层。
第六技术方案为，在上述第一至第五方案的任一者中，绝缘材料为电路板的绝缘基材，并包括BT树脂或环氧树脂与玻纤的复合材料，电子构件为芯片的接触焊盘。
第七技术方案为，在上述第一至第五方案的任一者中，绝缘材料为覆盖在PCB或封装基板的表面上的光敏树脂；电子构件为芯片的接触焊盘；该工艺包括：在步骤(a)之前，对光敏树脂进行曝光、显影，以形成盲孔，再进行烘烤，以使光敏树脂固化。
第八技术方案为，在上述第七方案中，在盲孔的孔壁上形成导电籽晶层和导体加厚层，以将位于绝缘材料一侧的PCB或封装基板的线路图案与位于绝缘材料另一侧的接触焊盘电连接。
第九技术方案为，在上述第七方案中，光敏树脂包括光敏环氧树脂或光敏PI树脂，并设有一层或多层。
第十技术方案为，在上述第一至第五方案的任一者中，在覆盖光刻胶之前，该工艺还包括：将芯片排列在载体上，并用绝缘材料覆盖芯片的表面，以将芯片夹在载体与绝缘材料之间；对绝缘材料开孔，以露出芯片的接触焊盘；以及在绝缘材料的表面上进行粗糙处理或PVD离子镀。
第十一技术方案为，在上述第十方案中，绝缘材料为PI或BCB树脂，电子构件为 PCB或封装基板的线路图案。
PVD离子镀中，蒸发料粒子在电离后具有很高的动能，高速轰击工件，不但沉积速度快，而且能穿透工件表面，注入基体形成很深的扩散层，彼此粘附得特别牢固。蒸发料粒子以带电离子形式在电场中沿着电力线方向运动，凡是存在电场的部位均能获得良好镀层，不受方向制约，因而绕镀能力强，非常适合于镀覆内孔、凹槽和窄缝等复杂结构。离子镀的镀层组织致密、无针孔、无气泡、厚度均匀，还能修补工件表面的微小裂纹和麻点等缺陷，故可有效地改善工件的表面质量和物理机械性能。此外，离子镀本身具有离子轰击清洗作用，该作用延续到整个镀膜过程，可以大幅地简化基材清洗作业。因此，上述金属化薄膜工艺能够减少或至少不增加精细线路的蚀刻量，实现10/10μm以下的线宽/线距，同时实现线路与绝缘材料之间的高结合力及光滑界面，能够提高封装电路的制作加工能力。
根据本发明的另一方面，第十二技术方案提供一种封装电路，其包括绝缘材料、形成于绝缘材料上的表面电路图案、以及经由焊料凸点或导体柱与表面电路图案电连接的电子构件，其中表面电路图案包括在绝缘材料的表面或孔壁形成的导电籽晶层、以及在导电籽晶层上形成的导体加厚层，导电籽晶层包括位于绝缘材料的表面或孔壁下方的离子注入层、和/或位于绝缘材料的表面或孔壁上的等离子体沉积层。
第十三技术方案为，在上述第十二方案中，导电籽晶层包括Ni或Ni-Cr合金，导体加厚层主要由铜组成，焊料凸点为焊锡球，并且导体柱为铜柱。
第十四技术方案为，在上述第十二或第十三方案中，绝缘材料为覆盖在PCB或封装基板的表面上的光敏树脂，电子构件为芯片的接触焊盘。
第十五技术方案为，在上述第十二或第十三方案中，绝缘材料将排列于载体上的芯片覆盖并夹在该绝缘材料与载体之间，电子构件为PCB或封装基板的线路图案。
在上述的封装电路中，绝缘材料与表面电路图案之间的结合力很高，可以达到0.6-1.5N/mm，例如0.8N/mm、1.0N/mm和1.2N/mm等。而且，由于存在包括离子注入层和/或等离子体沉积层的导电籽晶层，表面电路图案将具有均匀致密的组织结构，没有针孔、气泡和裂纹等缺陷，最小线宽/线距可达到15/15μm以下，甚至10/10μm、8/8μm。
附图说明
在参照附图阅读以下的详细描述之后，本发明的特征、方面和优点将更容易被理解。为清楚起见，附图不一定按比例绘制，而是有些部分可能被夸大以示出具体细节。在附图中，相同的参考标号表示相同或相似的部分。
图1是表示根据本发明的加成法制作封装电路的工艺的总体流程图。
图2(a)至2(g)表示根据本发明的第一实施例的工艺中的剖面结构变化示意图。
图3(a)至3(c)示出导电籽晶层的各种示例。
图4(a)至4(e)表示根据本发明的第二实施例的工艺中的剖面结构变化示意图。
图5(a)至5(f)表示根据本发明的第三实施例的工艺中的剖面结构变化示意图。
图6是表示通过第三实施例的工艺制得的带有两个RDL布线层的封装电路的剖面示意图。
参考标号：
10 绝缘材料
12 前处理层
14 光刻胶
16 导电籽晶层
161 离子注入层
162 等离子体沉积层
18 导体加厚层
20 表面电路图案
22 焊料凸点或导体柱
24 芯片
26 接触焊盘
28 PCB或封装基板
30 线路图案
32 盲孔
33 SLC布线层
34 载体
36 RDL布线层。
具体实施方式
以下，将参照附图详细地描述本发明的实施方式。应当注意，这些描述仅举例说明了本发明的示例性实施例，并不意图限制本发明的保护范围。例如，在本发明的一个附图或实施例中描述的特征可以与在另一个附图或实施例中描述的其它特征相结合。
图1是表示根据本发明的加成法制作封装电路的工艺的总体流程图。具体而言，该工艺主要包括以下步骤：在绝缘材料的表面上，覆盖带有电路负像的光刻胶；在绝缘材料的 未被光刻胶覆盖的暴露区域中，通过PVD离子镀形成导电籽晶层；在导电籽晶层上形成导体加厚层；剥离光刻胶，以形成表面电路图案；以及，利用焊料凸点或导体柱，将表面电路图案与电子构件电连接。
作为绝缘材料，可以使用刚性基板，如LCP、PTFE、CTFE、FEP、PPE、合成橡胶板、玻纤布/陶瓷填料增强板等有机高分子刚性板，或者陶瓷板、玻璃板等。还可以使用挠性基板，例如PI、PTO、PC、PSU、PES、PPS、PS、PE、PP、PEI、PTFE、PEEK、PA、PET、PEN、LCP、PPA等高分子薄膜。更具体而言，可以采用PCB常用的BT树脂、或环氧树脂与玻纤的复合绝缘材料，或者SLC表面层流电路常用的光敏环氧树脂或光敏PI树脂，或者RDL布线层常用的PI或BCB树脂，等等。
光刻胶主要由光引发剂、光刻胶树脂、单体、溶剂和其他助剂等组成，可以通过光化学反应，经过曝光、显影等光刻工序，将需要的微细图形从掩模版转移到待加工基片，并用于在后续工艺中保护下方的基材。经曝光显影后，留在绝缘材料表面上的光刻胶具有电路负像，也就是与最终表面电路图案互补的图案。在覆盖光刻胶之前，可以对绝缘材料的表面进行前处理，如粗糙化处理、霍尔源处理等，以增强光刻胶与绝缘材料之间的黏合力。
绝缘材料的未被光刻胶覆盖的暴露区域是将会在其中形成表面电路图案的区域。暴露区域包括绝缘材料的表面的一部分，还可以包括在该表面开口的通孔或盲孔。在开设有通孔或盲孔的情况下，孔壁与绝缘材料的表面连续成一体，相当于表面的一部分。可以通过机械钻孔、冲孔、激光打孔、等离子体刻蚀、反应离子刻蚀等方式形成孔。其中，紫外激光打孔具有短波长、短脉冲、光束质量优异、高精度、高峰值功率等优点，而且能够显著减少热效应，防止孔边缘受热损害，因而特别适用于超精细打孔加工，形成孔径达2-5μm的微孔。
PVD离子镀是指在真空条件下，通过气体放电使气体或被蒸发物部分电离，在气体离子或被蒸发物离子的轰击下，以电荷传递形式使蒸发物或其反应物沉积在基片上以完成镀膜的方法，具体包括磁控溅射离子镀、反应离子镀、空心阴极放电离子镀(空心阴极蒸镀法)、多弧离子镀(阴极电弧离子镀)等。具体过程如下：蒸发源接阳极，工件接阴极，通以高压直流电，在蒸发源与工件之间产生弧光放电；在放电电场作用下，真空室内的部分惰性氩气被电离，在工件周围形成等离子暗区；带正电荷的氩离子受到阴极负高压的吸引，轰击工件表面，将工件表层的粒子和污渍轰溅出，使工件表面得到充分清洗；随后接通蒸发源交流电源，使蒸发物粒子熔化蒸发，进入辉光放电区并电离；带正电荷的蒸发物离子在阴极吸引下，随氩离子一同冲向工件，以很高的速度猛烈轰击工件表面，相当于从枪管射出的高速弹 头，可以穿入基体深处，在工件上形成附着牢固的扩散镀层。
在普通真空镀膜中，蒸发料粒子仅以约1eV能量向工件表面蒸镀，工件表面与镀层之间形成的界面扩散深度仅为几百埃，两者间几乎没有过渡层。而在PVD离子镀中，蒸发料粒子电离后具有很高的动能，高速轰击工件，不但沉积速度快，而且能穿透工件表面，注入基体形成很深的扩散层，彼此粘附得特别牢固。蒸发料粒子以带电离子形式在电场中沿着电力线方向运动，凡是存在电场的部位均能获得良好镀层，不受方向制约，因而绕镀能力强，非常适合于镀覆内孔、凹槽和窄缝等复杂结构。离子镀的镀层组织致密、无针孔、无气泡、厚度均匀，还能修补工件表面的微小裂纹和麻点等缺陷，故可有效地改善工件的表面质量和物理机械性能。此外，离子镀本身具有离子轰击清洗作用，该作用延续到整个镀膜过程，可以大幅地简化基材清洗作业。
通过改变蒸发源阳极与工件阴极之间的电压及电流、真空度、注入剂量等工艺参数，可以简单地调节蒸发物带电粒子进入工件表面的深度，进而调节基材与导电层间的结合力。例如，可采用1kV-1000kV范围内的电压，如10kV、50kV、100kV、200kV、500kV等，使蒸发物带电粒子进入工件的表面下方，直至例如100nm的深度。此时，注入的粒子与工件基材的分子之间形成稳定的化学键，二者共同构成掺杂结构，又可称为离子注入层。离子注入层的外表面与基材表面齐平，而内表面深入到基材的内部，即位于基材表面下方。备选地，还可以采用数十至数百V的电压，使蒸发物带电粒子沿一定方向以较高速度沉积在工件表面上，而不是穿入到表面下方深处。沉积在工件表面上的导电层可以称为等离子体沉积层。离子注入层和等离子体沉积层都具有一定的导电性，可以统称为导电籽晶层，以辅助后续电镀。
PVD离子镀利用高能离子轰击工件表面，使电能在工件表面转换成热能，促进了表层组织的扩散作用和化学反应。然而，整个工件特别是心部并未受高温影响，因此这种工艺的应用范围广，可用于各种金属、合金以及某些合成材料、绝缘材料、热敏材料和高熔点材料等。所使用的蒸发物(即靶材)为导电材料，可以包括金属如Ti、Cr、Ni、Cu、Ag、Al、Au、V、Zr、Mo、Nb、In、Sn、Tb等，氧化物如In 2O 3、SnO 2、TiO 2、WO 3、MoO 3和Ga 2O 3等，硫化物如CdS、ZnS等，氮化物如TiN等，碳化物如WC、VC、Cr 4C 3等。可以使用相同的靶材，分阶段利用不同的加速电压，在工件基材上形成性质不同的多个离子注入层和/或等离子体沉积层。也可以使用不同的靶材，分阶段利用相同或不同的加速电压，在工件基材上形成性质不同的多个离子注入层和/或等离子体沉积层。例如，可以先采用较大的加速电压，使导电材料粒子深入到工件基材的内部，然后采用较低的加速电压，接着使导 电材料粒子沉积到工件基材的表面上，形成从内到外由离子注入层和等离子体沉积层组成的导电籽晶层。
导体加厚层旨在快速、高效地加厚表面电路图案，以提高导电率，满足传导电流及信号的要求。可以采用电镀、化学镀、真空蒸发镀、溅射等方法，将导电金属如Al、Mn、Fe、Ti、Cr、Co、Ni、Cu、Ag、Au、V、Zr、Mo、Nb或者它们之间的合金，镀覆到先前形成的导电籽晶层上，以形成导体加厚层。其中，电镀法的镀膜速度快、成本低，可应用的材料范围非常广，尤其适用于Cu、Ni、Sn、Ag等。导体加厚层的厚度乃至导电率可以通过改变镀膜时间等参数来调节，可以达到1μm-100μm，如5μm、10μm、50μm等。由于先前已通过离子镀在基材表面上形成了均匀致密的导电籽晶层，所以容易通过上述方法在导电籽晶层上形成均匀致密的导体加厚层。
在导电层被加厚到一定程度后，剥离光刻胶。此时，绝缘材料的未被光刻胶覆盖的暴露区域将保留先前形成的导电籽晶层和导体加厚层，被光刻胶覆盖的隐藏区域则会暴露出绝缘材料本身，从而在绝缘材料的表面上形成与光刻胶的图案互补的表面电路图案。然后，还可以对绝缘材料的整个表面快速地进行微蚀处理，以去除原来位于光刻胶下方的导电物质，确保表面电路图案的完整性和准确性。
焊料凸点可以通过小的球形导电材料实现，通常可采用焊锡球，还可以根据需要采用金、银、铜、钴等。当芯片制作工序完成后，可以在芯片的接触焊盘上形成UBM触垫，然后在UBM触垫上淀积焊料凸点。当粘有焊料凸点的晶粒被倒置(Flip-Chip)并与电路板对齐时，很容易实现晶粒与电路板之间的电连接。相比传统的引线连接，基于焊料凸点的芯片倒装技术有诸多优势，例如更小的封装尺寸、更快的器件速度、更高的可靠性和散热能力。对于高密度互联及细间距的应用，可以采用导体柱，如铜柱，因为其在连接时能够很好地保持原始形态，不易发生变形。焊料凸点或导体柱可以实现电路板之间、芯片之间、或者电路板与芯片之间的互联互通。
下面，将详细地描述采用上述工艺的三个具体实施例。应当注意，在以下的描述中，实施例的序号仅为了方便描述，而不代表实施例的优劣。而且，对各个实施例的描述有所侧重，某个实施例中没有详述的部分可以参见其它实施例的相关描述。
<第一实施例>
图2(a)至2(g)表示根据本发明的第一实施例的工艺中的剖面结构变化示意图。在该实施例中，将封装基板作为芯片支撑和电路连接的衬底，采用PVD离子镀对封装基板的表面或孔进行金属化，然后将形成有表面电路图案的封装基板与芯片的接触焊盘电连接，以完成电路 封装。
图2(a)示出用作电路板的绝缘基材的绝缘材料10。绝缘材料可以包括BT树脂，或者环氧树脂与玻纤的复合绝缘材料。其中，环氧树脂优选为高耐热性的环氧树脂，即Tg值(玻璃化转变温度)大于170℃的环氧树脂。绝缘基材的Tg高，则电路板的机械强度、粘接性、稳定性、耐热性、耐潮湿性、耐化学性等性能也会改善。绝缘材料10在图中示出为具有平坦表面，但也可以具有在表面开口的通孔或盲孔等，如上文所述。此时，通孔或盲孔的孔壁与绝缘材料的表面连续，可以相当于该表面的一部分。
可以对绝缘材料10的表面进行处理，例如粗糙化处理、霍尔源处理等，以增强光刻胶与绝缘材料之间的黏合力。在一个示例中，通过PVD离子镀，使带正电荷的氩离子受到阴极负高压的吸引而轰击绝缘材料10的表面，将材料表层的粒子和污渍轰溅出，使表层得到充分清洗。在另一示例中，使带正电荷的蒸发物离子在阴极吸引下，随氩离子一同猛烈地轰击绝缘材料的表面，在表面上形成具有一定导电性的前处理层12，如图2(b)所示。在这种情况下，必须在剥离光刻胶之后进行微蚀，以去除光刻胶下方的前处理层12，如图2(f)所示。
然后如图2(c)所示，在绝缘材料10的表面上覆盖光刻胶14，并通过曝光、显影等光刻工序将其一部分去除，以形成带有电路负像的光刻胶14。即，光刻胶14具有与需要的表面电路图案互补的图案。此时，绝缘材料10的未被光刻胶14覆盖的暴露区域将对应于需要的表面电路图案。
接着如图2(d)所示，通过上述的PVD离子镀，在绝缘材料10的未被光刻胶14覆盖的暴露区域中，形成导电籽晶层16。导电籽晶层16在图中示出为仅形成于绝缘材料10的表面上，但是实际上也可形成于光刻胶14的表面和孔壁上，为清楚起见而省略。PVD离子镀中，将Ni或Ni-Cr合金(Ni80％-Cr20％)用作靶材，通过调节电压和电流等工艺参数，将从靶材逸出的带电粒子注入到暴露区域的表面下方以形成厚度约10nm-50nm的离子注入层，或者将带电粒子沉积到暴露区域的表面上以形成厚度约100nm-500nm的等离子体沉积层。现有技术通常使用Ti作为溅射打底层，导致后续的蚀刻过程需要用到氢氟酸HF，而氢氟酸对人体有很大的危害，也会对环境造成严重污染。本发明使用Ni或Ni-Cr合金形成导电籽晶层，仅用少量Cr来提高封装电路的耐腐蚀性，可以提高电路寿命和可靠性，同时避免严重污染环境。
先前形成的导电直径层16通常具有较薄的厚度，导电性欠佳，难以满足电路板传输电力、信号的要求。为此，紧接着如图2(e)所示，通过图形电镀，在导电籽晶层16上形成 导体加厚层18。此时，可以在电镀槽中用铜进行图形电镀，加厚导电籽晶层16，以满足所需要的导电率。导体加厚层18在图中示出为具有比光刻胶14的外表面更低的外表面，但其外表面也可以与光刻胶14的外表面齐平或更高。
之后，剥离光刻胶14，从而形成表面电路图案20，如图2(f)所示。在如图2(b)所示形成有前处理层12的情况下，必须对绝缘材料10的表面整体进行快速微蚀，以去除隐藏在光刻胶下方的前处理层12，确保表面电路图案20的准确性，不至于产生短路。此时，导体加厚层18也会被蚀刻掉一部分，但不影响整体的导电性。在导体加厚层18高于光刻胶14外表面的情况下，光刻胶14上方的导体加厚层18也连同光刻胶14一起被剥离，而暴露区域中的导电籽晶层16和导体加厚层18则保留下来，构成最终的表面电路图案20。
最后如图2(g)所示，利用焊料凸点或导体柱22，将电路板的表面电路图案20与芯片24的接触焊盘26电连接。在此，芯片的接触焊盘26相当于本发明的“电子构件”。可以先通过电弧或化学镀方式，在表面电路图案20的表面上形成Ni-Au层或者其他常规的表面处理层，以增强焊料凸点或导体柱22与表面电路图案20之间的连接。图中示出的芯片24处于倒置的状态，即，使芯片的有源区(接触焊盘26)面对基板，通过芯片上排列的焊料凸点或导体柱22，来实现与电路板间的互联。芯片以倒置方式安装到电路板，然后从芯片向四周引出I/O，能够大幅缩短互联长度，减小RC延迟，有效地提高电性能。
图3(a)至3(c)示出导电籽晶层的各种示例，可以用作图2(d)至图2(g)所示的导电籽晶层16。
在图3(a)所示的示例中，PVD离子镀采用很高的加速电压，例如1kV-1000kV范围内的电压，使带电粒子以很高的速度注入到绝缘材料的表面下方，以形成离子注入层161。离子注入层161的外表面与绝缘材料的表面齐平，而内表面深入到绝缘材料内部。离子注入层161可包括一层或多层，它们可由相同或不同的材料组成。在离子注入时，带电粒子以很高的速度强行地注入到绝缘材料内部，相当于打下数量众多的基桩。由于基桩的存在，在绝缘材料与后续形成于离子注入层上的导电层(如等离子体沉积层或导体加厚层)之间的结合力可达到很高，例如0.5N/mm以上，甚至0.7-1.5N/mm。靶材粒子通常为纳米级，在离子镀时以带电离子形式在电场中沿着电力线方向运动，因而凡是存在电场的部位均能获得良好镀层。带电离子不是仅能沿直线，而是能够沿电力线均匀地绕镀到工件的内孔、凹槽和窄缝等复杂结构上。因此，离子注入层的组织致密、无针孔、无气泡、厚度均匀，还能够确保后续形成于其上的导电层(如等离子体沉积层或导体加厚层)具有良好的均匀度和致密性，不容易出现针孔、裂缝或脱落等缺陷。
在图3(b)所示的示例中，还在离子注入层161的上方形成了等离子体沉积层162。为此，PVD离子镀采用数十至数百V的电压，使带电粒子在电场作用下沿一定方向以较高速度沉积在绝缘材料表面上，而不是穿入到表面下方。等离子体沉积层162可具有100nm-500nm的厚度，如200nm、300nm、400nm等。还可以代替等离子体沉积，使用常规的磁控溅射等方式在离子注入层161上形成溅射沉积层，由溅射沉积层和离子注入层161共同构成导电籽晶层。等离子体沉积层162或溅射沉积层可包括一层或多层，它们可由相同或不同的材料组成。此外，等离子体沉积层162或溅射沉积层可以由与注入绝缘材料内部的导电材料(如Ni或Ni-Cr合金)相同的材料组成，或者由该导电材料与导体加厚层材料(如铜)的复合材料组成，以在离子注入层161与导体加厚层18之间提供良好的过渡。
在图3(c)所示的示例中，未形成离子注入层161，而是直接在绝缘材料表面上形成等离子体沉积层162。为此，如上所述，PVD离子镀采用数十至数百V的电压，使靶材带电粒子在电场作用下沿一定方向以较高速度直接沉积在绝缘材料的表面上，在界面处形成扩散层。该扩散层较薄，但由于带电粒子的方向性和速度，仍能确保绝缘材料与导电层之间具有较大的结合力而不容易脱落。纳米级的带电粒子在电场中沿电力线方向运动，均匀地绕镀到绝缘材料的表面各处，形成致密、无针孔、无气泡、厚度均匀的等离子体沉积层，也能够确保后续形成于其上的导体加厚层具有良好的均匀度和致密性，不容易出现针孔、裂缝或脱落等缺陷。
通过上述第一实施例的工艺形成的封装电路如图2(g)所示，包括绝缘材料10、形成于绝缘材料10上的表面电路图案20、以及经由焊料凸点或导体柱22与表面电路图案20电连接的电子构件，该电子构件为芯片24的接触焊盘26。其中，表面电路图案20包括在绝缘材料的表面或孔壁形成的导电籽晶层16、和在导电籽晶层16上形成的导体加厚层18，导电籽晶层16又包括位于绝缘材料10的表面或孔壁下方的离子注入层161、和/或位于绝缘材料10的表面或孔壁上方的等离子体沉积层162。
对上述的封装电路进行测试，在封装电路样品的外面包覆铝箔，一同压在300℃锡槽的融化的锡上，10秒一次，共压三次，即30秒，查看样品是否会产生气泡分层。试验显示，封装电路没有出现气泡分层的现象，表明电路板的绝缘材料与表面电路图案之间，具有很高的结合力和优异的耐热性能。对封装电路进行拉伸试验，显示一直拉到快要断裂时，表面电路图案仍随绝缘材料一起发生塑性延伸，未发生起皮或剥落现象，这也表明表面电路图案牢固地附着在绝缘材料上，两者间具有很高的结合力。进一步的剥离强度试验表明，上述封装电路中的绝缘材料与表面电路图案间的结合力可以达到0.6-1.5N/mm，例如0.8N/mm、 1.0N/mm和1.2N/mm等。此外，从外观上看，封装电路的表面电路图案具有均匀致密的组织结构，没有针孔、气泡和裂纹等缺陷，最小线宽/线距可以达到15/15μm以下，甚至10/10μm、8/8μm。
相比之下，在常规的真空蒸镀中，工件夹固在真空罩内，在通电加热后，蒸发料熔化蒸发，蒸发料粒子获得一定动能，沿着随机方向附着在工件表面上堆积成膜。这样形成的镀膜层与工件表面既无牢固的化学结合，又无扩散连接，附着性能很差。当将如此得到的封装电路外包铝箔压在300℃锡槽的熔融锡上进行测试时，三次后显现出明显的气泡分层现象，表明绝缘材料与表面电路图案间的结合力较弱。该结合力仅能达到0.4-0.5N/mm左右，远低于离子镀的结合力。此外，通过传统的MSAP、SAP工艺制得的封装电路，其最小线宽/间距最多仅能达到18/18μm，远比不上离子镀的上述数值。
<第二实施例>
图4(a)至4(e)表示根据本发明的第二实施例的工艺中的剖面结构变化示意图。在该实施例中，对设在常规电路板或封装基板上的表面层流电路(SLC，Surface Laminar Circuit)结构中的光敏绝缘介质的表面或孔壁进行PVD离子镀，在光敏绝缘介质上形成表面电路图案，然后将表面电路图案与芯片的接触焊盘电连接，以完成电路封装。
图4(a)示出具有线路图案30的常规PCB或封装基板28。图示的PCB或封装基板28包括两层基板，并且设有贯穿这两层基板的通孔，线路图案30形成于两层基板之间、两层基板的外表面上、以及通孔的孔壁上。但应当理解，任何其他形式的PCB电路板或封装基板都是可行的。
接着如图4(b)所示，在PCB或封装基板28的表面上覆盖绝缘材料10，形成叠层结构。绝缘材料10可以是光敏树脂，例如光敏环氧树脂或光敏PI树脂。光敏树脂含有感光或光敏成分，以用于感光制作盲孔，同时作为电路板的绝缘介质层。在形成叠层结构时，可以在一定真空下采用辊压或涂覆方式，将感光树脂与PCB或封装基板28贴合在一起。之后对感光树脂进行图形曝光和显影，制作出盲孔32，再进行高温烘烤，以使感光树脂固化成绝缘介质层，得到具有盲孔的绝缘材料表面。盲孔的孔壁与绝缘材料的外表面连续成一体，可以相当于绝缘材料表面的一部分。
然后，如图4(c)所示，在设有盲孔32的绝缘材料10的表面上涂覆光刻胶，随后进行图形曝光、显影，使盲孔32和与最终表面电路图案20对应的表面部位露出，接着利用PVD离子镀在该表面部位和盲孔的孔壁上形成导电籽晶层16，再通过图形电镀铜在导电籽晶层16上方形成导体加厚层18，最后剥离光刻胶，以形成由导电籽晶层16和导体加厚层 18构成的表面电路图案20。形成有表面电路图案20的绝缘材料10可称为表面层流电路(SLC)，能够与电子构件直接电连接并进行封装。导电籽晶层16和导体加厚层18的形成过程可参照第一实施例，即图2(b)至图2(f)所示的步骤。例如，在覆盖绝缘材料10之前，可以如图2(b)所示地对PCB或封装基板28的表面进行前处理，以形成前处理层12来增加与绝缘材料10的黏合力，而在剥离光刻胶14之后，通过微蚀来去除之前被光刻胶覆盖的前处理层12。此外，导电籽晶层16可包括图3(a)、图3(b)或图3(c)所示的任一种结构。
可选地，还可以重复图4(b)和4(c)所示的步骤，即，在第一SLC布线层33的表面上，依次覆盖光敏树脂绝缘材料、涂覆光刻胶进行图形曝光和显影、利用PVD离子镀形成导电籽晶层16、利用图形电镀铜形成导体加厚层18，然后剥离光刻胶而得到形成有表面电路图案的第二SLC布线层33，如图4(d)中所示。利用第二SLC布线层33与电子构件进行电连接及封装。
尽管绝缘材料10在图4(b)至图4(d)中示出为仅设在PCB或封装基板28的上表面上，但应理解，在形成叠层结构时，也可以在PCB或封装基板28的上下两个表面均设置绝缘材料10，按照感光树脂-内层芯板-感光树脂的顺序进行叠层，然后在上、下两侧的表面上均形成表面电路图案20，通过加成法工艺得到1+n+1结构。重复上述的“感光树脂-内层芯板-感光树脂”叠层制作，可得到2+n+2、3+n+3或4+n+4等结构的封装电路结构。
最后，如图4(e)所示，利用焊料凸点或导体柱22，将SLC布线层33中的表面电路图案20与芯片24的接触焊盘26电连接。在此，芯片的接触焊盘26相当于本发明的“电子构件”。其中，在盲孔的孔壁上形成的导电籽晶层16和导体加厚层18可以将位于绝缘材料一侧的PCB或封装基板28的线路图案30与位于绝缘材料另一侧的芯片24的接触焊盘26电连接。可以先通过电弧或化学镀方式，在表面电路图案20的表面上形成Ni-Au层或者其他常规的表面处理层，以增强焊料凸点或导体柱22与表面电路图案20之间的连接。图中示出的芯片24也像第一实施例中那样处于倒置状态，即，使芯片的有源区(接触焊盘26)面对基板。通过芯片上排列的焊料凸点或导体柱22，实现芯片与SLC布线层之间的互联。SLC布线层构成当前流行的低成本有机封装衬底的基础，依次使用光敏树脂制成的介电层和镀铜的导体平面来构建，其中电路堆积层通过微孔垂直连接，以支持诸如芯片倒装之类的异构集成。
通过上述第二实施例的工艺形成的封装电路如图4(e)所示，包括绝缘材料10、形成于绝缘材料10上的表面电路图案20、以及经由焊料凸点或导体柱22与表面电路图案20电连接的电子构件。其中，绝缘材料为覆盖在PCB或封装基板的表面上的光敏树脂，电子构 件为芯片24的接触焊盘26。表面电路图案20构成SLC布线层33的一部分，并包括在绝缘材料的表面或孔壁形成的导电籽晶层16、以及在导电籽晶层16上形成的导体加厚层18，导电籽晶层16又包括位于绝缘材料10的表面或孔壁下方的离子注入层161、和/或位于绝缘材料10的表面或孔壁上方的等离子体沉积层162。
对上述的封装电路进行测试表明，与第一实施例中同样地，该封装电路具有优异的耐热性能，绝缘材料(即光敏树脂)与表面电路图案之间的结合力很高，可以达到0.6-1.5N/mm，例如0.8N/mm、1.0N/mm和1.2N/mm等。而且，表面电路图案具有均匀致密的组织结构，没有针孔、气泡和裂纹等缺陷，最小线宽/线距可以达到15/15μm以下，甚至10/10μm、8/8μm。
<第三实施例>
图5(a)至5(e)表示根据本发明的第三实施例的工艺中的剖面结构变化示意图。在该实施例中，以重布线层(RDL，Redistribution Layer)工艺的芯片为起点，在芯片上覆盖绝缘材料，进而通过PVD离子镀对绝缘材料的表面进行金属化处理，形成表面电路图案，最后将表面电路图案与PCB或封装基板的电路图案电连接，以完成电路封装。
图5(a)示出RDL工艺的芯片。具体而言，将多个芯片24排布在一个载体34上，使得芯片24的接触焊盘26在载体34的表面上露出，以便于后续的电连接。
如图5(b)所示，在芯片24的接触焊盘26暴露在外的一侧，覆盖绝缘材料10，以将芯片24夹在载体34与该绝缘材料10之间。此时，可以在一定真空下采用辊压或涂覆方式，使绝缘材料10与芯片24的表面紧密贴合在一起。绝缘材料10可以为PI(聚酰亚胺)或者BCB(双苯环丁烯)树脂，厚度为大约5μm。然后对绝缘材料10开孔，仅使芯片24的接触焊盘26露出。开设于绝缘材料10的孔的孔壁与其外表面连续成一体，可以相当于绝缘材料表面的一部分。
接着如图5(c)所示，在设有孔的绝缘材料10的表面上，涂覆光刻胶14，随后进行图形曝光、显影，使得芯片24的接触焊盘26、以及与期望的表面电路图案20相对应的表面部位(即，图中右侧不存在光刻胶14的部位)露出来。光刻胶的厚度可以为5μm-10μm。图示的光刻胶14的孔壁与绝缘材料10的孔壁彼此互相对齐，但也可以彼此并不对齐。例如，光刻胶14中的孔径可以小于绝缘材料10中的孔径，只要能够使接触焊盘26的一部分露出即可。在涂覆光刻胶14之前，可以先对绝缘材料10的表面进行处理，例如粗糙化处理、霍尔源处理等，以增强光刻胶与绝缘材料之间的黏合力。例如，可以先对绝缘材料10的表面进行PVD离子镀处理，如图2(b)所示形成前处理层12，而在剥离光刻胶14之后，通过微 蚀来去除之前被光刻胶覆盖的前处理层12。此外，导电籽晶层16也可包括图3(a)、图3(b)或图3(c)所示的任一种结构。
然后如图5(d)所示，通过PVD离子镀，在接触焊盘26的透过绝缘材料10和光刻胶14中的孔露出的部位、以及绝缘材料10的未被光刻胶14覆盖的暴露区域中，形成导电籽晶层16，再利用图形电镀铜，在导电籽晶层16上方形成导体加厚层18。
然后如图5(e)所示，剥离光刻胶，以形成由导电籽晶层16和导体加厚层18构成的表面电路图案20。形成有表面电路图案20的绝缘材料10可称为RDL布线层，能够与电子构件直接地电连接并进行封装。RDL布线层中与接触焊盘26直接相连的部分可用于导通芯片电极与电子构件，而未与接触焊盘26直接相连的部分(即图中右侧显示的若干个柱体)则用于重新布线，构成布线图案的一部分。导电籽晶层16和导体加厚层18的形成过程可参照第一实施例，即图2(b)至图2(f)所示的步骤。
最后如图5(f)所示，利用焊料凸点或导体柱22使RDL布线层的表面电路图案20与PCB或封装基板28的线路图案30电连接。在此，封装基板28的线路图案30相当于本发明的“电子构件”。可以先通过电弧或化学镀方式，在线路图案30的表面上形成Ni-Au层或者其他常规的表面处理层，以增强焊料凸点或导体柱22与线路图案30之间的连接。图中示出的芯片24也像第一和第二实施例那样处于倒置状态，使芯片的有源区(接触焊盘26)面对着PCB或封装基板28。RDL工艺实质上就是在原来的晶圆上添加一个或几个布线层，首先淀积一层电介质用于隔离，接着使晶圆芯片的接触焊盘裸露，再淀积新的金属层来实现重新布线。晶圆水平上的触点再分布可以高效地进行，而再布线层则可以帮助重新规划连线路径，使线路落到期望的区域上，也有助于获得更高的触点密度和更低的线宽/线距。
通过上述第三实施例的工艺形成的封装电路如图5(f)所示，包括绝缘材料10、形成于绝缘材料10上的表面电路图案20、以及经由焊料凸点或导体柱22与表面电路图案20电连接的电子构件。其中，绝缘材料10将排列于载体34上的芯片24覆盖并夹在该绝缘材料与载体之间，电子构件为PCB或封装基板28的线路图案30。表面电路图案20构成RDL布线层的一部分，包括在绝缘材料的表面或孔壁形成的导电籽晶层16、以及在导电籽晶层16上形成的导体加厚层18，导电籽晶层16又包括位于绝缘材料10的表面或孔壁下方的离子注入层161、和/或位于绝缘材料10的表面或孔壁上方的等离子体沉积层162。
可选地，还可以重复图5(b)至5(e)所示的步骤，在第一RDL布线层的表面上，依次覆盖绝缘材料10、涂覆光刻胶14进行图形曝光和显影、利用PVD离子镀形成导电籽晶层16、利用图形电镀铜形成导体加厚层18，然后剥离光刻胶，得到形成有表面电路图案的第 二RDL布线层，利用第二RDL布线层与电子构件进行电连接及封装。图6示出包括两个RDL布线层36的封装电路，其中下侧的第二RDL布线层36与上侧的第一RDL布线层36彼此电连接，对连线路径进行了重新规划，使第二RDL布线层36的表面电路图案不同于第一RDL布线层36和芯片24中。
对上述的封装电路进行测试表明，与第一实施例中同样地，该封装电路具有优异的耐热性能，绝缘材料(即光敏树脂)与表面电路图案之间的结合力很高，可以达到0.6-1.5N/mm，例如0.8N/mm、1.0N/mm和1.2N/mm等。而且，表面电路图案具有均匀致密的组织结构，没有针孔、气泡和裂纹等缺陷，最小线宽/线距可以达到15/15μm以下，甚至10/10μm、8/8μm。
上文的描述仅提及本发明的若干特定的实施例。本发明并不限于这些实施例。本领域技术人员将理解，在不脱离本发明的要旨的范围内，可以对这些实施例进行各种显而易见的修改、调整及替换，以使其适合于特定的情形。实际上，本发明的保护范围由各权利要求请求保护的技术方案来限定，并且还包括本领域技术人员可预想到的其它等同方案。

Claims (15)

  1. 一种加成法制作封装电路的工艺，包括以下步骤：
    (a)在绝缘材料的表面上，覆盖带有电路负像的光刻胶；
    (b)在所述绝缘材料的未被所述光刻胶覆盖的暴露区域中，通过PVD离子镀形成导电籽晶层；
    (c)在所述导电籽晶层上形成导体加厚层；
    (d)剥离所述光刻胶，以形成表面电路图案；以及
    (e)利用焊料凸点或导体柱，将所述表面电路图案与电子构件电连接。
  2. 根据权利要求1所述的工艺，其特征在于，所述绝缘材料的暴露区域包括在所述绝缘材料的表面开口的孔，在所述孔的孔壁上形成有所述导电籽晶层。
  3. 根据权利要求1所述的工艺，其特征在于，PVD离子镀利用Ni或Ni-Cr合金作为靶材，将从所述靶材逸出的带电粒子注入到所述暴露区域的表面下方以形成离子注入层，和/或将从所述靶材逸出的带电粒子沉积到所述暴露区域的表面上以形成等离子体沉积层。
  4. 根据权利要求1所述的工艺，其特征在于，
    通过图形电镀，利用铜形成所述导体加厚层；
    所述焊料凸点为焊锡球；并且
    所述导体柱为铜柱。
  5. 根据权利要求1所述的工艺，其特征在于，
    步骤(a)包括：在覆盖光刻胶之前，通过PVD离子镀对所述绝缘材料的表面进行处理，以形成前处理层；
    步骤(d)包括：在剥离光刻胶之后，通过微蚀去除所述表面电路图案以外的所述前处理层。
  6. 根据权利要求1至5中的任一项所述的工艺，其特征在于，所述绝缘材料为电路板的绝缘基材，并包括BT树脂或环氧树脂与玻纤的复合材料，所述电子构件为芯片的接触焊盘。
  7. 根据权利要求1至5中的任一项所述的工艺，其特征在于，
    所述绝缘材料为覆盖在PCB或封装基板的表面上的光敏树脂；
    所述电子构件为芯片的接触焊盘；
    所述工艺包括：在步骤(a)之前，对所述光敏树脂进行曝光、显影，以形成盲孔，再进行烘烤，以使所述光敏树脂固化。
  8. 根据权利要求7所述的工艺，其特征在于，在所述盲孔的孔壁上形成所述导电籽晶层和所述导体加厚层，以将位于所述绝缘材料一侧的所述PCB或封装基板的线路图案与位于所述绝缘材料另一侧的所述接触焊盘电连接。
  9. 根据权利要求7所述的工艺，其特征在于，所述光敏树脂包括光敏环氧树脂或光敏PI树脂，并设有一层或多层。
  10. 根据权利要求1至5中的任一项所述的工艺，其特征在于，在覆盖光刻胶之前，还包括：
    将芯片排列在载体上，并用所述绝缘材料覆盖所述芯片的表面，以将所述芯片夹在所述载体与所述绝缘材料之间；
    对所述绝缘材料开孔，以露出所述芯片的接触焊盘；以及
    在所述绝缘材料的表面上进行粗糙处理或PVD离子镀。
  11. 根据权利要求10所述的工艺，其特征在于，所述绝缘材料为PI或BCB树脂，所述电子构件为PCB或封装基板的线路图案。
  12. 一种封装电路，包括绝缘材料、形成于所述绝缘材料上的表面电路图案、以及经由焊料凸点或导体柱与所述表面电路图案电连接的电子构件，其中所述表面电路图案包括在所述绝缘材料的表面或孔壁形成的导电籽晶层、以及在所述导电籽晶层上形成的导体加厚层，所述导电籽晶层包括位于所述绝缘材料的表面或孔壁下方的离子注入层、和/或位于所述绝缘材料的表面或孔壁上的等离子体沉积层。
  13. 根据权利要求12所述的工艺，其特征在于，
    所述导电籽晶层包括Ni或Ni-Cr合金；
    所述导体加厚层主要由铜组成；
    所述焊料凸点为焊锡球；并且
    所述导体柱为铜柱。
  14. 根据权利要求12或13所述的工艺，其特征在于，所述绝缘材料为覆盖在PCB或封装基板的表面上的光敏树脂，所述电子构件为芯片的接触焊盘。
  15. 根据权利要求12或13所述的工艺，其特征在于，所述绝缘材料将排列于载体上的芯片覆盖并夹在该绝缘材料与所述载体之间，所述电子构件为PCB或封装基板的线路图案。
PCT/CN2021/133491 2021-01-29 2021-11-26 加成法制作封装电路的工艺和封装电路 WO2022160907A1 (zh)

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