WO2022160436A1 - 一种应用于陀螺控制系统的SoC芯片结构 - Google Patents

一种应用于陀螺控制系统的SoC芯片结构 Download PDF

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WO2022160436A1
WO2022160436A1 PCT/CN2021/082556 CN2021082556W WO2022160436A1 WO 2022160436 A1 WO2022160436 A1 WO 2022160436A1 CN 2021082556 W CN2021082556 W CN 2021082556W WO 2022160436 A1 WO2022160436 A1 WO 2022160436A1
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module
subsystem
speed bus
control system
bus
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PCT/CN2021/082556
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French (fr)
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武春风
刘林涛
白明顺
秦勇
莫尚军
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航天科工微电子系统研究院有限公司
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/24—Pc safety
    • G05B2219/24215—Scada supervisory control and data acquisition

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  • the invention relates to a SoC chip structure in the precision control field, and more particularly, to a SoC chip structure applied to a gyro control system.
  • the control system of the gyro is mainly realized by discrete devices such as FPGA+/ADC/DAC.
  • discrete devices such as FPGA+/ADC/DAC.
  • FPGA+/ADC/DAC discrete devices
  • Figure 1 the control system of the gyro
  • the purpose of the present invention is to overcome the deficiencies of the prior art, provide a SoC chip structure applied to the gyro control system, realize the monolithic and low power consumption of the gyro control and processing system, and solve the discrete device of the gyro control and processing system.
  • Solution development is complex and bulky.
  • a SoC chip structure applied to a gyro control system including a bus, a bridge, a CPU subsystem, a memory subsystem, a control output subsystem, an input sampling subsystem, a peripheral subsystem and a clock reset subsystem, and the bus includes a high-speed bus and low-speed bus; high-speed bus and low-speed bus are connected by bridge; described CPU subsystem is connected with high-speed bus, and high-speed bus is connected with memory subsystem and bridge respectively; described control output subsystem is connected with low-speed bus, and low-speed bus is connected with bridge the input sampling subsystem is connected with the low-speed bus; the peripheral subsystem is connected with the low-speed bus; the clock reset subsystem is connected with the low-speed bus; the control output subsystem includes a DAC module and a synchronous output module; Both the DAC module and the synchronization output module are connected to the low-speed bus.
  • control output subsystem includes two bus interfaces for receiving the control information transmitted by the CPU subsystem through the bus, decomposing the control information, and transmitting the data to the three-way DAC module and the synchronous output module.
  • the input sampling subsystem includes a three-way ADC module and a three-way filter; the three-way ADC and the three-way filter are both connected with a low-speed bus, and the input end of the three-way ADC is connected to the three-way filter. connected to the output.
  • the CPU subsystem includes a central processing unit, a wake-up interrupt controller and a debug interface; the wake-up interrupt controller is connected to the central processing unit for completing wake-up and interrupt control functions; the debug interface is connected to the central processing unit. Connection is used to realize the function of chip debugging; the CPU subsystem works as a master device on the high-speed bus, and connects and communicates with other subsystems through the high-speed bus.
  • the memory subsystem includes a DMA module, an SRAM module and an eflash module; the DMA module, the SRAM module and the eflash module are all connected to a high-speed bus.
  • the peripheral subsystem includes a UART module, a SPI module, a GPIO module, and a TIMERS module; the UART module, the SPI module, the GPIO module, and the TIMERS module are all general-purpose modules, and the UART module, the SPI module, and the GPIO module are all general-purpose modules. and TIMERS modules are connected to the low speed bus.
  • the clock reset subsystem includes a PLL module, a POR module and a CLK/RST module; the PLL module and the POR module are a general-purpose on-chip phase-locked loop and a power-on reset circuit module, and the PLL module is used to realize 3, 4, etc. frequency multiplication function; the CLK/RST module is used to realize the shaping and filtering processing function of the clock and reset signals.
  • off-chip three-way signals pass through the on-chip three-way filter and the three-way ADC module in turn.
  • the DAC module includes a three-way DAC module.
  • the invention realizes the monolithic and low power consumption of the gyro control system, and solves the problems of high system development complexity, large volume and unfavorable miniaturization of the gyro in the integrated realization scheme of the discrete components of the gyro control system; specifically, the CPU controls the DAC.
  • the module and the synchronous output module are output to the gyro braking subsystem, and then the ADC integrated on the chip realizes the signal conversion in the gyro control system; and then the 32-bit RISC CPU performs data analysis and processing, so as to realize the loop control of the gyro control system.
  • the SoC chip based on the invention can not only meet the application requirements of the gyro control system, but also meet the application requirements of similar precision control fields.
  • the three-way ADC module is used for data acquisition in the three directions of X, Y, and Z
  • the three-way DAC module is also used for signal driving in the three directions of X, Y, and Z
  • the synchronization is also used.
  • the output module plays the role of synchronous control in the gyro control system, and realizes the monolithic and low power consumption of the gyro control system while realizing the loop control of the gyro control system.
  • FIG. 1 is a schematic structural diagram of an existing gyro control system
  • FIG. 2 is a schematic structural diagram of an SoC chip applied to a gyro control system according to an embodiment of the present invention.
  • a SoC chip structure applied to a gyro control system includes a bus, a bridge, a CPU subsystem, a memory subsystem, a control output subsystem, an input sampling subsystem, a peripheral subsystem and a clock reset subsystem, the bus includes a high-speed bus and a low-speed bus; the high-speed bus and the low-speed bus are connected through a bridge; the CPU subsystem is connected with the high-speed bus, and the high-speed bus is respectively connected with the memory subsystem and the bridge; the control output subsystem is connected to The low-speed bus is connected, and the low-speed bus is connected with the bridge; the input sampling subsystem is connected with the low-speed bus; the peripheral subsystem is connected with the low-speed bus; the clock reset subsystem is connected with the low-speed bus; the control output subsystem includes A three-way DAC module and a synchronous output module; the three-way DAC module and the synchronous output module are all connected with a low-speed bus.
  • control output subsystem includes two bus interfaces for receiving the control information transmitted by the CPU subsystem through the bus, decomposing the control information, and transmitting the data to the three-way DAC module and the synchronous output module.
  • the input sampling subsystem includes a three-way ADC module and a three-way filter; the three-way ADC and the three-way filter are both connected with a low-speed bus, and the input end of the three-way ADC is connected to the three-way filter. connected to the output.
  • the CPU subsystem includes a central processing unit, a wake-up interrupt controller and a debug interface; the wake-up interrupt controller is connected to the central processing unit for completing wake-up and interrupt control functions; the debug interface is connected to the central processing unit. Connection is used to realize the function of chip debugging; the CPU subsystem works as a master device on the high-speed bus, and connects and communicates with other subsystems through the high-speed bus.
  • the memory subsystem includes a DMA module, an SRAM module and an eflash module; the DMA module, the SRAM module and the eflash module are all connected to a high-speed bus.
  • the peripheral subsystem includes a UART module, a SPI module, a GPIO module, and a TIMERS module; the UART module, the SPI module, the GPIO module, and the TIMERS module are all general-purpose modules, and the UART module, the SPI module, and the GPIO module are all general-purpose modules. and TIMERS modules are connected to the low speed bus.
  • the clock reset subsystem includes a PLL module, a POR module and a CLK/RST module; the PLL module and the POR module are a general-purpose on-chip phase-locked loop and a power-on reset circuit module, and the PLL module is used to realize 3, 4, etc. frequency multiplication function; the CLK/RST module is used to realize the shaping and filtering processing function of the clock and reset signals.
  • off-chip three-way signals pass through the on-chip three-way filter and the three-way ADC module in turn.
  • the DAC module includes a three-way DAC module.
  • the gyro control system includes a DAC module and a synchronization output, ADC signal acquisition and CPU processing.
  • a preferred embodiment of the SoC chip structure applied to the gyro control system of the present invention includes a CPU subsystem (CPU Subsystem), a memory subsystem (Memory Subsystem), a bus (AHB Bus and APB Bus), Bridge (Bridge), Control Output Subsystem (Output Subsystem), Input Sampling Subsystem (Sample Subsystem), General Peripheral Subsystem (Peripheral Subsystem) and Clock Reset Subsystem (CLK/RST Subsystem).
  • CPU Subsystem CPU Subsystem
  • Memory Subsystem memory subsystem
  • APB Bus APB Bus
  • Bridge Bridge
  • Control Output Subsystem Output Subsystem
  • Input Sampling Subsystem Sample Subsystem
  • General Peripheral Subsystem Peripheral Subsystem
  • Clock Reset Subsystem CLK/RST Subsystem
  • the CPU subsystem acts as the master device on the bus AHB Bus, and is connected to the memory subsystem (Memory Subsystem) and bridge (Bridge) through the AHB Bus.
  • the AHB Bus is connected to the APB Bus through a bridge.
  • the control output subsystem (Output Subsystem), the input sampling subsystem (Sample Subsystem), the general peripheral subsystem (Peripheral Subsystem) and the clock reset subsystem (CLK/RST Subsystem) are connected through the bus APB Bus.
  • the CPU subsystem includes a central processing unit (CPU), a wake-up interrupt controller (WIC) and a debug interface (SWD).
  • the WIC is connected to the CPU to complete wake-up and interrupt control functions.
  • the SWD is connected with the CPU to realize the chip debugging function.
  • the CPU Subsystem works as a master device on the AHB Bus, and connects and communicates with other subsystems through the AHB Bus.
  • Memory Subsystem includes DMA, SRAM and eflash.
  • DMA, SRAM and eflash are common modules, and each module in the Memory Subsystem is connected to the AHB Bus.
  • Control output subsystem includes three-way DAC module and synchronous output module. Each module in the Output Subsystem is connected to the APB Bus.
  • the input sampling subsystem contains ADC blocks and filters. Each module in the Sample Subsystem is connected to the APB Bus, and the input of the ADC is connected to the filter, which has good scalability and can meet the application requirements of different servo control systems.
  • the general peripheral subsystem includes UART, SPI, GPIO and TIMERS.
  • UART, SPI, GPIO, and TIMERS are all general-purpose modules, and each module in the Peripheral Subsystem is connected to the APB Bus.
  • the general peripheral subsystem can realize the control and information exchange of the chip to other systems of the gyro, as well as the information exchange with the host computer.
  • the clock reset subsystem includes PLL (Phase Locked Loop), POR (Power On Reset) and CLK/RST.
  • PLL and POR are general-purpose on-chip phase-locked loop and power-on reset circuit modules, respectively.
  • PLL realizes frequency multiplication functions such as 3 and 4.
  • CLK/RST implements functions such as shaping and filtering of clock and reset signals, thereby providing a clean and reliable clock and reset signal for the system.
  • the DAC and the synchronous output module are output to the gyro braking subsystem first, then the ADC integrated on the chip realizes the signal conversion in the gyro control system, and then the 32-bit RISC CPU performs data analysis and processing, thereby
  • the loop control of the gyro control system is realized, which effectively solves the problems of high system development complexity and large volume of the integrated implementation scheme of discrete components of the gyro control system.
  • the invention realizes the low power consumption and monolithicization of the gyro control system by implementing low power consumption design and monolithic integration of high-performance analog circuit units such as high-precision ADCs required by the gyro control system, and solves the problem of the integration of discrete devices in the gyro control system.
  • the problems of high system development complexity, large volume, and unfavorable miniaturization of the gyro make the SoC chip based on the invention not only meet the application requirements of the gyro control system, but also meet the application requirements of similar precision control fields.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
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Abstract

本发明公开了一种应用于陀螺控制系统的SoC芯片结构，包括总线、桥、CPU子系统、存储器子系统、控制输出子系统、输入采样子系统、外设子系统和时钟复位子系统，总线包括高速总线和低速总线；高速总线与低速总线通过桥连接等；本发明先通过DAC和同步输出模块输出给陀螺制动分系统，再由片内集成的ADC实现陀螺控制系统中的信号转换，再由32位RISC CPU进行数据的分析处理，从而实现陀螺控制系统的环路控制等，有效解决了陀螺控制系统分立器件集成实现方案的系统开发复杂度高、体积大的问题。

Description

一种应用于陀螺控制系统的SoC芯片结构 技术领域
本发明涉及精密控制领域SoC芯片结构，更为具体的，涉及一种应用于陀螺控制系统的SoC芯片结构。
背景技术
目前，陀螺的控制系统主要采用FPGA+/ADC/DAC等分立器件实现的方式。如国内外公司和相关单位在进行陀螺控制系统研发设计时，采用的是FPGA+ADC/DAC芯片等分立器件集成的方案，如图1所示。这主要是因为目前还没有针对陀螺控制系统的应用需求而开发的专用控制SoC芯片，所以只能采用分立器件二次集成方案，这增加了陀螺系统研发的复杂度，并且分立器件集成实现的控制系统体积大，使得陀螺的微型化遭遇瓶颈。
发明内容
本发明的目的在于克服现有技术的不足，提供一种应用于陀螺控制系统的SoC芯片结构，实现了陀螺控制与处理系统的单片化和低功耗，解决了陀螺控制与处理系统分立器件方案开发复杂度高、体积大的问题。
本发明的目的是通过以下方案实现的：
一种应用于陀螺控制系统的SoC芯片结构，包括总线、桥、CPU子系统、存储器子系统、控制输出子系统、输入采样子系统、外设子系统和时钟复位子系统，所述总线包括高速总线和低速总线；高速总线与低速总线通过桥连接；所述CPU子系统与高速总线连接，高速总线分别与存储器子 系统和桥连接；所述控制输出子系统与低速总线连接，低速总线与桥连接；所述输入采样子系统与低速总线连接；所述外设子系统与低速总线连接；所述时钟复位子系统与低速总线连接；所述控制输出子系统包括DAC模块和同步输出模块；所述DAC模块和同步输出模块均与低速总线连接。
进一步地，所述控制输出子系统包括两个总线接口，用于接收CPU子系统通过总线传递过来的控制信息，并进行控制信息的分解并传递数据给三路DAC模块和同步输出模块。
进一步地，所述输入采样子系统包括三路ADC模块和三路滤波器；所述三路ADC和三路滤波器均与低速总线连接，并且所述三路ADC的输入端与三路滤波器的输出端相连。
进一步地，所述CPU子系统包括中央处理器、唤醒中断控制器和调试接口；所述唤醒中断控制器与中央处理器连接，用于完成唤醒和中断控制功能；所述调试接口与中央处理器连接，用于实现芯片调试功能；所述CPU子系统以高速总线上主设备的方式工作，通过高速总线与其他子系统连接与通信。
进一步地，所述存储器子系统包括DMA模块、SRAM模块和eflash模块；所述DMA模块、SRAM模块和eflash模块均与高速总线连接。
进一步地，所述外设子系统包括UART模块、SPI模块、GPIO模块和TIMERS模块；所述UART模块、SPI模块、GPIO模块和TIMERS模块均为通用模块，所述UART模块、SPI模块、GPIO模块和TIMERS模块均与低速总线连接。
进一步地，所述时钟复位子系统包括PLL模块、POR模块和CLK/RST模块；所述PLL模块、POR模块为通用片上锁相环和上电复位电路模块，所述PLL模块用于实现3、4等倍频功能；所述CLK/RST模块用于实现对时钟和复位信号的整形滤波处理功能。
进一步地，片外三路信号依次通过片内三路滤波器和三路ADC模块。
进一步地，所述DAC模块包括三路DAC模块。
本发明的有益效果是：
本发明实现了陀螺控制系统的单片化和低功耗，解决了陀螺控制系统分立器件集成实现方案的系统开发复杂度高、体积大、不利于陀螺微型化的问题；具体的，CPU控制DAC模块和同步输出模块输出给陀螺制动分系统，再由片内集成的ADC实现陀螺控制系统中的信号转换；再由32位RISC CPU进行数据的分析处理，从而实现陀螺控制系统的环路控制，从而实现了陀螺控制系统的单片化和低功耗，使得基于该发明的SoC芯片不但可以满足陀螺控制系统的应用需求，还能满足类似精密控制领域的应用需求。
在本发明的实施例中，三路ADC模块用于X、Y、Z三个方向的数据采集，并且三路DAC模块还用于X、Y、Z三个方向的信号驱动，同时还利用同步输出模块在陀螺控制系统中起到同步控制的作用，实现陀螺控制系统的环路控制的同时，实现陀螺控制系统的单片化和低功耗。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有陀螺控制系统的结构示意图；
图2为本发明实施例一种应用于陀螺控制系统的SoC芯片结构示意图。
具体实施方式
本说明书中所有实施例公开的所有特征，或隐含公开的所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以以任何方式组合和/或扩展、替换。
如图1，2所示，一种应用于陀螺控制系统的SoC芯片结构，包括总线、桥、CPU子系统、存储器子系统、控制输出子系统、输入采样子系统、外设子系统和时钟复位子系统，所述总线包括高速总线和低速总线；高速总线与低速总线通过桥连接；所述CPU子系统与高速总线连接，高速总线分别与存储器子系统和桥连接；所述控制输出子系统与低速总线连接，低速总线与桥连接；所述输入采样子系统与低速总线连接；所述外设子系统与低速总线连接；所述时钟复位子系统与低速总线连接；所述控制输出子系统包括三路DAC模块和同步输出模块；所述三路DAC模块和同步输出模块均与低速总线连接。
进一步地，所述控制输出子系统包括两个总线接口，用于接收CPU子系统通过总线传递过来的控制信息，并进行控制信息的分解并传递数据给三路DAC模块和同步输出模块。
进一步地，所述输入采样子系统包括三路ADC模块和三路滤波器；所述三路ADC和三路滤波器均与低速总线连接，并且所述三路ADC的输入端与三路滤波器的输出端相连。
进一步地，所述CPU子系统包括中央处理器、唤醒中断控制器和调试接口；所述唤醒中断控制器与中央处理器连接，用于完成唤醒和中断控制功能；所述调试接口与中央处理器连接，用于实现芯片调试功能；所述CPU子系统以高速总线上主设备的方式工作，通过高速总线与其他子系统连接 与通信。
进一步地，所述存储器子系统包括DMA模块、SRAM模块和eflash模块；所述DMA模块、SRAM模块和eflash模块均与高速总线连接。
进一步地，所述外设子系统包括UART模块、SPI模块、GPIO模块和TIMERS模块；所述UART模块、SPI模块、GPIO模块和TIMERS模块均为通用模块，所述UART模块、SPI模块、GPIO模块和TIMERS模块均与低速总线连接。
进一步地，所述时钟复位子系统包括PLL模块、POR模块和CLK/RST模块；所述PLL模块、POR模块为通用片上锁相环和上电复位电路模块，所述PLL模块用于实现3、4等倍频功能；所述CLK/RST模块用于实现对时钟和复位信号的整形滤波处理功能。
进一步地，片外三路信号依次通过片内三路滤波器和三路ADC模块。
进一步地，所述DAC模块包括三路DAC模块。
在本发明的其他实施例中，陀螺控制系统包括DAC模块和同步输出、ADC信号采集和CPU处理组成。
如图2所示，本发明一种应用于陀螺控制系统的SoC芯片结构的较佳实施方式包括CPU子系统(CPU Subsystem)、存储器子系统(Memory Subsystem)、总线(AHB Bus和APB Bus)、桥(Bridge)、控制输出子系统(Output Subsystem)、输入采样子系统(Sample Subsystem)、通用外设子系统(Peripheral Subsystem)和时钟复位子系统(CLK/RST Subsystem)。
CPU子系统(CPU Subsystem)作为总线AHB Bus上的主设备，通过AHB Bus和存储器子系统(Memory Subsystem)、桥(Bridge)连接。AHB Bus通过桥(Bridge)和APB Bus连接。控制输出子系统(Output Subsystem)、输入采样子系统(Sample Subsystem)、通用外设子系统(Peripheral Subsystem) 和时钟复位子系统(CLK/RST Subsystem)通过总线APB Bus连接。
CPU子系统(CPU Subsystem)包括中央处理器(CPU)、唤醒中断控制器(WIC)和调试接口(SWD)。WIC与CPU相连，完成唤醒和中断控制功能。SWD与CPU相连，实现芯片调试功能。CPU Subsystem以AHB Bus总线上主设备的方式工作，通过AHB Bus与其他子系统连接与通信。
存储器子系统(Memory Subsystem)包括DMA、SRAM和eflash。DMA、SRAM和eflash为通用模块，Memory Subsystem中的每个模块都与AHB Bus连接。
控制输出子系统(Output Subsystem)包括三路DAC模块和同步输出模块。Output Subsystem中的每个模块都与APB Bus连接。
输入采样子系统(Sample Subsystem)包含ADC模块和滤波器。Sample Subsystem中的每个模块都与APB Bus连接，并且ADC的输入和滤波器相连，具有较好的扩展性，可满足不同的伺服控制系统的应用需求。
通用外设子系统(Peripheral Subsystem)包括UART、SPI、GPIO和TIMERS。UART、SPI、GPIO和TIMERS都为通用模块，Peripheral Subsystem中的每个模块都与APB Bus连接。通用外设子系统可实现本芯片对陀螺其他系统的控制和信息交互，以及和上位机的信息交互等操作。
时钟复位子系统(CLK/RST Subsystem)包括PLL(Phase Locked Loop)、POR(Power On Reset)和CLK/RST。PLL、POR分别为通用片上锁相环和上电复位电路模块，PLL实现3、4等倍频功能。CLK/RST实现对时钟和复位信号的整形滤波处理等功能，从而为系统提供一个干净、可靠的时钟和复位信号。
本发明实施例中，先通过DAC和同步输出模块输出给陀螺制动分系统，再由片内集成的ADC实现陀螺控制系统中的信号转换，再由32位RISC  CPU进行数据的分析处理，从而实现陀螺控制系统的环路控制等，有效解决了陀螺控制系统分立器件集成实现方案的系统开发复杂度高、体积大的问题。通过采用本发明实施例SoC芯片结构，不但可以实现陀螺系统的控制，还可以覆盖大部分精密测量领域的伺服控制应用需求。
本发明通过将陀螺控制系统需求的高精度ADC等高性能模拟电路单元进行低功耗设计及单片集成，实现了陀螺控制系统的低功耗和单片化，解决了陀螺控制系统分立器件集成实现方案的系统开发复杂度高、体积大、不利于陀螺微型化的问题使得基于该发明的SoC芯片不但可以满足陀螺控制系统的应用需求，还能满足类似精密控制领域的应用需求。

Claims (9)

  1. 一种应用于陀螺控制系统的SoC芯片结构，其特征在于，包括总线、桥、CPU子系统、存储器子系统、控制输出子系统、输入采样子系统、外设子系统和时钟复位子系统，所述总线包括高速总线和低速总线；高速总线与低速总线通过桥连接；所述CPU子系统与高速总线连接，高速总线分别与存储器子系统和桥连接；所述控制输出子系统与低速总线连接，低速总线与桥连接；所述输入采样子系统与低速总线连接；所述外设子系统与低速总线连接；所述时钟复位子系统与低速总线连接；所述控制输出子系统包括DAC模块和同步输出模块；所述DAC模块和同步输出模块均与低速总线连接。
  2. 根据权利要求1所述的一种应用于陀螺控制系统的SoC芯片结构，其特征在于，所述控制输出子系统包括两个总线接口，用于接收CPU子系统通过总线传递过来的控制信息，并进行控制信息的分解并传递数据给三路DAC模块和同步输出模块。
  3. 根据权利要求1或2任一所述的一种应用于陀螺控制系统的SoC芯片结构，其特征在于，所述输入采样子系统包括三路ADC模块和三路滤波器；所述三路ADC和三路滤波器均与低速总线连接，并且所述三路ADC的输入端与三路滤波器的输出端相连。
  4. 根据权利要求3所述的一种应用于陀螺控制系统的SoC芯片结构，其特征在于，所述CPU子系统包括中央处理器、唤醒中断控制器和调试接口；所述唤醒中断控制器与中央处理器连接，用于完成唤醒和中断控制功能；所述调试接口与中央处理器连接，用于实现芯片调试功能；所述CPU子系统以高速总线上主设备的方式工作，通过高速总线与其他子系统连接与通信。
  5. 根据权利要求3所述的一种应用于陀螺控制系统的SoC芯片结构，其特征在于，所述存储器子系统包括DMA模块、SRAM模块和eflash模块；所述DMA模块、SRAM模块和eflash模块均与高速总线连接。
  6. 根据权利要求1所述的一种应用于陀螺控制系统的SoC芯片结构，其特征在于，所述外设子系统包括UART模块、SPI模块、GPIO模块和TIMERS模块；所述UART模块、SPI模块、GPIO模块和TIMERS模块均为通用模块，所述UART模块、SPI模块、GPIO模块和TIMERS模块均与低速总线连接。
  7. 根据权利要求3所述的一种应用于陀螺控制系统的SoC芯片结构，其特征在于，所述时钟复位子系统包括PLL模块、POR模块和CLK/RST模块；所述PLL模块、POR模块为通用片上锁相环和上电复位电路模块，所述PLL模块用于实现3、4等倍频功能；所述CLK/RST模块用于实现对时钟和复位信号的整形滤波处理功能。
  8. 根据权利要求3所述的一种应用于陀螺控制系统的SoC芯片结构，其特征在于，片外三路信号依次通过片内三路滤波器和三路ADC模块。
  9. 根据权利要求3所述的一种应用于陀螺控制系统的SoC芯片结构，其特征在于，所述DAC模块包括三路DAC模块。
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