WO2022027847A1 - 一种应用于引信控制系统的SoC芯片结构 - Google Patents

一种应用于引信控制系统的SoC芯片结构 Download PDF

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Publication number
WO2022027847A1
WO2022027847A1 PCT/CN2020/126685 CN2020126685W WO2022027847A1 WO 2022027847 A1 WO2022027847 A1 WO 2022027847A1 CN 2020126685 W CN2020126685 W CN 2020126685W WO 2022027847 A1 WO2022027847 A1 WO 2022027847A1
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module
subsystem
speed bus
control system
bus
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PCT/CN2020/126685
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French (fr)
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武春风
刘林涛
秦勇
白明顺
莫尚军
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航天科工微电子系统研究院有限公司
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Publication of WO2022027847A1 publication Critical patent/WO2022027847A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0426—Programming the control sequence
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21137—Analog to digital conversion, ADC, DAC
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/23—Pc programming
    • G05B2219/23067—Control, human or man machine interface, interactive, HMI, MMI

Definitions

  • the invention relates to the technical field of SOC chips, and more particularly, to a SoC chip structure applied to a fuze control system.
  • the fuze control system includes linear frequency modulation output, microwave signal acquisition and processing, and three-way programmable switch pulse output control.
  • the linear frequency modulation signal is output first, then the signal is collected by the ADC, and then the data collected and converted by the ADC is analyzed and processed by the processor, and finally output through the three-way programmable switch pulse.
  • the control system of fuze is mainly realized by discrete devices such as single-chip microcomputer + ADC/DAC.
  • discrete devices such as single-chip microcomputer + ADC/DAC.
  • domestic and foreign companies and related units use a low-power single-chip microcomputer + ADC and DAC chip and other discrete device integration solutions when developing and designing the fuze control system.
  • This is mainly because there is no dedicated control SoC chip developed for the application requirements of the fuze control system, so the secondary integration scheme of discrete devices based on low-power microcontrollers can only be used, which increases the complexity of the research and development of the fuze system, and
  • the volume of the control system realized by the integration of discrete devices is large, which makes the miniaturization of the fuze encounter a bottleneck.
  • the purpose of the present invention is to overcome the deficiencies of the prior art and provide a SoC chip structure applied to a fuze control system, which effectively solves the problems of high system development complexity and large volume of a fuze control system integrated implementation scheme of discrete devices.
  • a SoC chip structure applied to a fuze control system including a bus, a bridge, a CPU subsystem, a memory subsystem, a control output subsystem, an input sampling subsystem, a peripheral subsystem and a clock reset subsystem
  • the bus includes a high-speed bus and low-speed bus; high-speed bus and low-speed bus are connected by bridge; described CPU subsystem is connected with high-speed bus, and high-speed bus is connected with memory subsystem and bridge respectively; described control output subsystem is connected with low-speed bus, and low-speed bus is connected with bridge
  • the input sampling subsystem is connected with the low-speed bus; the peripheral subsystem is connected with the low-speed bus; the clock reset subsystem is connected with the low-speed bus.
  • the CPU subsystem includes a central processing unit, a wake-up interrupt controller and a debug interface; the wake-up interrupt controller is connected to the central processing unit for completing wake-up and interrupt control functions; the debug interface is connected to the central processing unit. Connection is used to realize the function of chip debugging; the CPU subsystem works as a master device on the high-speed bus, and connects and communicates with other subsystems through the high-speed bus.
  • the memory subsystem includes a DMA module, an SRAM module and an eflash module; the DMA module, the SRAM module and the eflash module are all connected to a high-speed bus.
  • control output subsystem includes a linear frequency modulation output module and a three-way programmable switch pulse output module; the frequency of the output signal of the linear frequency modulation output module is programmable, and the upper limit frequency and the lower limit frequency can be set independently; The start/stop of the programmable switch pulse output module can be controlled independently; the linear frequency modulation output module and the three-way programmable switch pulse output module are all connected with the low-speed bus.
  • the input sampling subsystem includes an ADC module and a multi-channel optional band-pass filter; both the ADC module and the multi-channel optional band-pass filter are connected to a low-speed bus, and the input end of the ADC module is connected to the low-speed bus. Output connections for multiple selectable bandpass filters.
  • the peripheral subsystem includes a UART module, a SPI module, a GPIO module, and a TIMERS module; the UART module, the SPI module, the GPIO module, and the TIMERS module are all general-purpose modules, and the UART module, the SPI module, and the GPIO module are all general-purpose modules. and TIMERS modules are connected to the low speed bus.
  • the clock reset subsystem includes a PLL module, a POR module and a CLK/RST module; the PLL module and the POR module are a general-purpose on-chip phase-locked loop and a power-on reset circuit module, and the PLL module is used to realize 3, 4, etc. frequency multiplication function; the CLK/RST module is used to realize the shaping and filtering processing function of the clock and reset signals.
  • the three-way programmable switch pulse group includes two bus interfaces for receiving the control information transmitted by the CPU through the bus, and decomposes the control information and transmits the data to the linear frequency modulation output module and the three-way programmable switch. Pulse output module.
  • the invention effectively solves the problems of high system development complexity and large volume of the integrated realization scheme of discrete components of the fuze control system. Specifically, the linear frequency modulation signal is output first, and the fuze signal acquisition is realized through the on-chip integrated 14-bit ADC module; then the data is analyzed and processed by the 32-bit RISC CPU, and finally the fuze control system is realized through the output of three programmable switch pulses.
  • the monolithic and low power consumption of the fuze control system solves the problems of high system development complexity, large volume, and unfavorable miniaturization of the fuze control system. Therefore, the SoC chip based on the present invention can not only meet the application requirements of the fuze control system, but also meet the application requirements in the similar precision control field.
  • FIG. 1 is a schematic structural diagram of the present invention.
  • a SoC chip structure applied to a fuze control system includes a bus, a bridge, a CPU subsystem, a memory subsystem, a control output subsystem, an input sampling subsystem, a peripheral subsystem and a clock reset subsystem
  • the bus includes a high-speed bus and a low-speed bus; the high-speed bus and the low-speed bus are connected through a bridge; the CPU subsystem is connected with the high-speed bus, and the high-speed bus is respectively connected with the memory subsystem and the bridge; the control output subsystem is connected with the low-speed bus
  • the low-speed bus is connected with the bridge; the input sampling subsystem is connected with the low-speed bus; the peripheral subsystem is connected with the low-speed bus; the clock reset subsystem is connected with the low-speed bus.
  • the CPU subsystem includes a central processing unit, a wake-up interrupt controller and a debug interface; the wake-up interrupt controller is connected to the central processing unit for completing wake-up and interrupt control functions; the debug interface is connected to the central processing unit. Connection is used to realize the function of chip debugging; the CPU subsystem works as a master device on the high-speed bus, and connects and communicates with other subsystems through the high-speed bus.
  • the memory subsystem includes a DMA module, an SRAM module and an eflash module; the DMA module, the SRAM module and the eflash module are all connected to a high-speed bus.
  • control output subsystem includes a linear frequency modulation output module and a three-way programmable switch pulse output module; the frequency of the output signal of the linear frequency modulation output module is programmable, and the upper limit frequency and the lower limit frequency can be set independently; The start/stop of the programmable switch pulse output module can be controlled independently; the linear frequency modulation output module and the three-way programmable switch pulse output module are all connected with the low-speed bus.
  • the input sampling subsystem includes an ADC module and a multi-channel optional band-pass filter; both the ADC module and the multi-channel optional band-pass filter are connected to a low-speed bus, and the input end of the ADC module is connected to the low-speed bus. Output connections for multiple selectable bandpass filters.
  • the peripheral subsystem includes a UART module, a SPI module, a GPIO module, and a TIMERS module; the UART module, the SPI module, the GPIO module, and the TIMERS module are all general-purpose modules, and the UART module, the SPI module, and the GPIO module are all general-purpose modules. and TIMERS modules are connected to the low speed bus.
  • the clock reset subsystem includes a PLL module, a POR module and a CLK/RST module; the PLL module and the POR module are a general-purpose on-chip phase-locked loop and a power-on reset circuit module, and the PLL module is used to realize 3, 4, etc. frequency multiplication function; the CLK/RST module is used to realize the shaping and filtering processing function of the clock and reset signals.
  • the three-way programmable switch pulse group includes two bus interfaces for receiving the control information transmitted by the CPU through the bus, and decomposes the control information and transmits the data to the linear frequency modulation output module and the three-way programmable switch. Pulse output module.
  • the specific scheme of the present invention is divided into two parts: one is the SoC chip structure implementation scheme applied to the fuze control system, and the other is the SoC applied to the fuze control system.
  • the chip's self-working implementation scheme The main features of the SoC chip structure implementation scheme applied to the fuze control system are the chip structure:
  • the present invention as a preferred embodiment of the SoC chip structure applied to a fuze control system, includes a CPU subsystem (CPU Subsystem), a memory subsystem (Memory Subsystem), a bus (AHB Bus and APB Bus) ), bridge (Bridge), control output subsystem (Output Subsystem), input sampling subsystem (Sample Subsystem), general peripheral subsystem (Peripheral Subsystem) and clock reset subsystem (CLK/RST Subsystem).
  • CPU Subsystem CPU Subsystem
  • Memory Subsystem memory subsystem
  • APB Bus and APB Bus bus
  • bridge Bridge
  • control output subsystem Output Subsystem
  • input sampling subsystem Sample Subsystem
  • Peripheral Subsystem general peripheral subsystem
  • CLK/RST Subsystem clock reset subsystem
  • the CPU subsystem As the master device on the bus AHB Bus, the CPU subsystem (CPU Subsystem) is connected to the memory subsystem (Memory Subsystem) and bridge (Bridge) through the AHB Bus.
  • AHB Bus via Bridge and APB Bus connection.
  • Control the output subsystem Output Subsystem
  • input sampling subsystem Sample Subsystem
  • general peripheral subsystem Peripheral Subsystem
  • clock reset subsystem CLK/RST Subsystem
  • CPU Subsystem includes central processing unit (CPU), wake-up interrupt controller (WIC) and debug interface (SWD), central processing unit (CPU) 32-bit RISC CPU.
  • the WIC is connected to the CPU to complete wake-up and interrupt control functions.
  • the SWD is connected with the CPU to realize the chip debugging function.
  • the CPU Subsystem works as a master device on the AHB Bus, and connects and communicates with other subsystems through the AHB Bus.
  • DMA dynamic random access memory
  • SRAM static random access memory
  • eflash dynamic random access memory
  • Output Subsystem including linear frequency modulation output and three-way programmable switch pulse output.
  • the output signal frequency is programmable, and the upper limit frequency and lower limit frequency can be set independently.
  • the start/stop of the three-way switching pulses can be controlled individually.
  • Each block in the Output Subsystem is connected to the APB Bus.
  • the input sampling subsystem contains the ADC and multiple selectable bandpass filters. Each module in the Sample Subsystem is connected with the APB Bus, and the ADC input is connected with a multi-channel optional band-pass filter, which has good expansibility and can meet the application requirements of different servo control systems.
  • the general peripheral subsystem includes UART, SPI, GPIO and TIMERS.
  • UART, SPI, GPIO, and TIMERS are all general-purpose modules, and each module in the Peripheral Subsystem is connected to the APB Bus.
  • the general peripheral subsystem can realize the control and information exchange of the chip to other fuze systems, as well as the information exchange with the host computer.
  • the clock reset subsystem includes PLL (Phase Locked Loop), POR (Power On Reset) and CLK/RST, PLL and POR are general-purpose on-chip phase-locked loop and power-on reset circuit modules, and PLL realizes frequency multiplication functions such as 3 and 4.
  • CLK/RST implements functions such as shaping and filtering of clock and reset signals, thereby providing a clean and reliable clock and reset signal for the system.
  • the invention is applied to the self-working implementation scheme of the SoC chip of the fuze control system: first output the linear frequency modulation signal, then the ADC collects the signal, then the processor analyzes and processes the data collected and converted by the ADC, and finally outputs the three-way programmable switch pulse , the general peripheral subsystem can realize the control of the chip to other systems of the fuze and the information exchange and the information exchange with the host computer.
  • the present invention can be a SoC chip structure applied to a fuze control system, and can be applied to a fuze control system. Optionally, it can be manufactured by a 0.18um CMOS process, and the overall power consumption of the chip is less than 100mW.
  • the invention realizes the low power consumption and monolithicization of the fuze control system by implementing low-power consumption design and monolithic integration of high-performance analog circuit units such as high-precision ADCs required by the fuze control system, and solves the problem of the integration of discrete components in the fuze control system.
  • the system development of the realization scheme is complex and bulky, which is not conducive to the miniaturization of the fuze. Therefore, the SoC chip based on the present invention can not only meet the application requirements of the fuze control system, but also meet the application requirements in the similar precision control field.
  • the functions of the present invention are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present invention in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium.
  • a computer device which may be a personal computer, a server, or a network device, etc.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

Abstract

一种应用于引信控制系统的SoC芯片结构，包括CPU子系统、存储器子系统、总线、桥、控制输出子系统、输入采样子系统、通用外设子系统和时钟复位子系统；先通过线性调频输出，再由片内集成ADC实现引信控制系统中的信号转换，再由32位RISC CPU进行数据的分析处理；最后三路可编程开关脉冲输出给引信控制分系统，从而实现引信控制系统的环路控制等，有效解决了引信控制系统分立器件集成实现方案的系统开发复杂度高、体积大的问题。

Description

一种应用于引信控制系统的SoC芯片结构 技术领域
本发明涉及SOC芯片技术领域，更为具体的，涉及一种应用于引信控制系统的SoC芯片结构。
 背景技术
引信控制系统包括线性调频输出、微波信号采集和处理、三路可编程开关脉冲输出控制组成。要实现引信的控制系统，先输出线性调频信号，再由ADC采集信号，然后由处理器来分析处理ADC采集转换的数据，最后通过三路可编程开关脉冲输出。
目前，引信的控制系统主要采用单片机+ADC/DAC等分立器件实现的方式。如国内外公司和相关单位在进行引信控制系统研发设计时，采用的是低功耗单片机+ADC和DAC芯片等分立器件集成的方案。这主要是因为目前还没有针对引信控制系统的应用需求而开发的专用控制SoC芯片，所以只能采用基于低功耗单片机的分立器件二次集成方案，这增加了引信系统研发的复杂度，并且分立器件集成实现的控制系统体积大，使得引信的微型化遭遇瓶颈。
 技术问题
本发明的目的在于克服现有技术的不足，提供一种应用于引信控制系统的SoC芯片结构，有效解决了引信控制系统分立器件集成实现方案的系统开发复杂度高、体积大的问题。
 技术解决方案
本发明的目的是通过以下方案实现的：
一种应用于引信控制系统的SoC芯片结构，包括总线、桥、CPU子系统、存储器子系统、控制输出子系统、输入采样子系统、外设子系统和时钟复位子系统，所述总线包括高速总线和低速总线；高速总线与低速总线通过桥连接；所述CPU子系统与高速总线连接，高速总线分别与存储器子系统和桥连接；所述控制输出子系统与低速总线连接，低速总线与桥连接；所述输入采样子系统与低速总线连接；所述外设子系统与低速总线连接；所述时钟复位子系统与低速总线连接。
进一步地，所述CPU子系统包括中央处理器、唤醒中断控制器和调试接口；所述唤醒中断控制器与中央处理器连接，用于完成唤醒和中断控制功能；所述调试接口与中央处理器连接，用于实现芯片调试功能；所述CPU子系统以高速总线上主设备的方式工作，通过高速总线与其他子系统连接与通信。
进一步地，所述存储器子系统包括DMA模块、SRAM模块和eflash模块；所述DMA模块、SRAM模块和eflash模块均与高速总线连接。
进一步地，所述控制输出子系统包括线性调频输出模块和三路可编程开关脉冲输出模块；所述线性调频输出模块的输出信号频率可编程，上限频率和下限频率能独立设置；所述三路可编程开关脉冲输出模块的启动/停止能单独控制；所述线性调频输出模块、三路可编程开关脉冲输出模块均与低速总线连接。
进一步地，所述输入采样子系统包含ADC模块和多路可选带通滤波器；所述ADC模块和多路可选带通滤波器均与低速总线连接，并且所述ADC模块的输入端与多路可选带通滤波器的输出端连接。
进一步地，所述外设子系统包括UART模块、SPI模块、GPIO模块和TIMERS模块；所述UART模块、SPI模块、GPIO模块和TIMERS模块均为通用模块，所述UART模块、SPI模块、GPIO模块和TIMERS模块均与低速总线连接。
进一步地，所述时钟复位子系统包括PLL模块、POR模块和CLK/RST模块；所述PLL模块、POR模块为通用片上锁相环和上电复位电路模块，所述PLL模块用于实现3、4等倍频功能；所述CLK/RST模块用于实现对时钟和复位信号的整形滤波处理功能。
进一步地，所述三路可编程开关脉冲组包括两个总线接口，用于接收CPU通过总线传递过来的控制信息，并进行控制信息的分解并传递数据给线性调频输出模块和三路可编程开关脉冲输出模块。
 有益效果
本发明有效解决了引信控制系统分立器件集成实现方案的系统开发复杂度高、体积大的问题。具体的，先输出线性调频信号，通过片内集成14位ADC模块实现引信信号采集；再由32位RISC CPU进行数据的分析处理，最后通过三路可编程开关脉冲输出，从而实现了引信控制系统的单片化和低功耗，解决了引信控制系统分立器件集成实现方案的系统开发复杂度高、体积大、不利于引信微型化的问题。使得基于本发明的SoC芯片不但可以满足引信控制系统的应用需求，还能满足类似精密控制领域的应用需求。
 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明的结构示意图。
 本发明的最佳实施方式
下面结合附图进一步详细描述本发明的技术方案，但本发明的保护范围不局限于以下所述。本说明书中公开的所有特征，或隐含公开的所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以以任何方式组合。
本说明书（包括任何附加权利要求、摘要和附图）中公开的任一特征，除非特别叙述，均可被其他等效或具有类似目的的替代特征加以替换。即，除非特别叙述，每个特征只是一系列等效或类似特征中的一个例子而已。
如图1所示，一种应用于引信控制系统的SoC芯片结构，包括总线、桥、CPU子系统、存储器子系统、控制输出子系统、输入采样子系统、外设子系统和时钟复位子系统，所述总线包括高速总线和低速总线；高速总线与低速总线通过桥连接；所述CPU子系统与高速总线连接，高速总线分别与存储器子系统和桥连接；所述控制输出子系统与低速总线连接，低速总线与桥连接；所述输入采样子系统与低速总线连接；所述外设子系统与低速总线连接；所述时钟复位子系统与低速总线连接。
 本发明的实施方式
进一步地，所述CPU子系统包括中央处理器、唤醒中断控制器和调试接口；所述唤醒中断控制器与中央处理器连接，用于完成唤醒和中断控制功能；所述调试接口与中央处理器连接，用于实现芯片调试功能；所述CPU子系统以高速总线上主设备的方式工作，通过高速总线与其他子系统连接与通信。
进一步地，所述存储器子系统包括DMA模块、SRAM模块和eflash模块；所述DMA模块、SRAM模块和eflash模块均与高速总线连接。
进一步地，所述控制输出子系统包括线性调频输出模块和三路可编程开关脉冲输出模块；所述线性调频输出模块的输出信号频率可编程，上限频率和下限频率能独立设置；所述三路可编程开关脉冲输出模块的启动/停止能单独控制；所述线性调频输出模块、三路可编程开关脉冲输出模块均与低速总线连接。
进一步地，所述输入采样子系统包含ADC模块和多路可选带通滤波器；所述ADC模块和多路可选带通滤波器均与低速总线连接，并且所述ADC模块的输入端与多路可选带通滤波器的输出端连接。
进一步地，所述外设子系统包括UART模块、SPI模块、GPIO模块和TIMERS模块；所述UART模块、SPI模块、GPIO模块和TIMERS模块均为通用模块，所述UART模块、SPI模块、GPIO模块和TIMERS模块均与低速总线连接。
进一步地，所述时钟复位子系统包括PLL模块、POR模块和CLK/RST模块；所述PLL模块、POR模块为通用片上锁相环和上电复位电路模块，所述PLL模块用于实现3、4等倍频功能；所述CLK/RST模块用于实现对时钟和复位信号的整形滤波处理功能。
进一步地，所述三路可编程开关脉冲组包括两个总线接口，用于接收CPU通过总线传递过来的控制信息，并进行控制信息的分解并传递数据给线性调频输出模块和三路可编程开关脉冲输出模块。
更进一步的描述本发明的方案，如图1所示，本发明的具体方案分为两个部分：一个为应用于引信控制系统的SoC芯片结构实现方案，另外一个为应用于引信控制系统的SoC芯片的自行工作实现方案。应用于引信控制系统SoC芯片结构实现方案的特征主要是芯片结构：
如图1所示，本发明作为一种应用于引信控制系统的SoC芯片结构的较佳实施方式，包括CPU子系统（CPU Subsystem）、存储器子系统（Memory Subsystem）、总线（AHB Bus和APB Bus）、桥（Bridge）、控制输出子系统(Output Subsystem)、输入采样子系统（Sample Subsystem）、通用外设子系统（Peripheral Subsystem）和时钟复位子系统（CLK/RST Subsystem）。
CPU子系统（CPU Subsystem）作为总线AHB Bus上的主设备，通过AHB Bus和存储器子系统（Memory Subsystem）、桥（Bridge）连接。AHB Bus通过桥（Bridge）和APB Bus连接。控制输出子系统(Output Subsystem)、输入采样子系统（Sample Subsystem）、通用外设子系统（Peripheral Subsystem）和时钟复位子系统（CLK/RST Subsystem）通过总线APB Bus连接。
CPU子系统（CPU Subsystem）包括中央处理器（CPU）、唤醒中断控制器（WIC）和调试接口（SWD），中央处理器（CPU）32位RISC CPU。WIC与CPU相连，完成唤醒和中断控制功能。SWD与CPU相连，实现芯片调试功能。CPU Subsystem以AHB Bus总线上主设备的方式工作，通过AHB Bus与其他子系统连接与通信。
存储器子系统（Memory Subsystem）包括DMA、SRAM和eflash。DMA、SRAM和eflash为通用模块，Memory Subsystem中的每个模块都与AHB Bus连接。
控制输出子系统(Output Subsystem)包括线性调频输出和三路可编程开关脉冲输出。输出信号频率可编程，上限频率和下限频率可独立设置。三路开关脉冲的启动/停止可单独控制。Output Subsystem中的每个模块都与APB Bus连接。
输入采样子系统（Sample Subsystem）包含ADC和多路可选带通滤波器。Sample Subsystem中的每个模块都与APB Bus连接，并且ADC的输入和多路可选带通滤波器相连，具有较好的扩展性，可满足不同的伺服控制系统的应用需求。
通用外设子系统（Peripheral Subsystem）包括UART、SPI、GPIO和TIMERS。UART、SPI、GPIO和TIMERS都为通用模块，Peripheral Subsystem中的每个模块都与APB Bus连接。通用外设子系统可实现本芯片对引信其他系统的控制和信息交互，以及和上位机的信息交互等操作。
时钟复位子系统（CLK/RST Subsystem）包括PLL(Phase Locked Loop)、POR（Power On Reset）和CLK/RST，PLL、POR为通用片上锁相环和上电复位电路模块，PLL实现3、4等倍频功能。CLK/RST实现对时钟和复位信号的整形滤波处理等功能，从而为系统提供一个干净、可靠的时钟和复位信号。
本发明应用于引信控制系统的SoC芯片的自行工作实现方案：先输出线性调频信号，再由ADC采集信号，然后由处理器来分析处理ADC采集转换的数据，最后通过三路可编程开关脉冲输出，通用外设子系统可实现本芯片对引信其他系统的控制和信息交互以及和上位机的信息交互等操作。本发明可为一种应用于引信控制系统的SoC芯片结构，应用于引信的控制系统中，可选的，可以采用0.18umCMOS工艺制造，芯片总体功耗＜100mW。
本发明通过将引信控制系统需求的高精度ADC等高性能模拟电路单元进行低功耗设计及单片集成，实现了引信控制系统的低功耗和单片化，解决了引信控制系统分立器件集成实现方案的系统开发复杂度高、体积大、不利于引信微型化的问题。使得基于本发明的SoC芯片不但可以满足引信控制系统的应用需求，还能满足类似精密控制领域的应用需求。
本发明功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分，可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备（可以是个人计算机，服务器，或者网络设备等）执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器（Read-Only Memory，ROM）、随机存取存储器（Random Access Memory，RAM）、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (8)

  1. 一种应用于引信控制系统的SoC芯片结构，其特征在于，包括总线、桥、CPU子系统、存储器子系统、控制输出子系统、输入采样子系统、外设子系统和时钟复位子系统，所述总线包括高速总线和低速总线；高速总线与低速总线通过桥连接；所述CPU子系统与高速总线连接，高速总线分别与存储器子系统和桥连接；所述控制输出子系统与低速总线连接，低速总线与桥连接；所述输入采样子系统与低速总线连接；所述外设子系统与低速总线连接；所述时钟复位子系统与低速总线连接。
  2. 根据权利要求1所述的应用于引信控制系统的SoC芯片结构，其特征在于，所述CPU子系统包括中央处理器、唤醒中断控制器和调试接口；所述唤醒中断控制器与中央处理器连接，用于完成唤醒和中断控制功能；所述调试接口与中央处理器连接，用于实现芯片调试功能；所述CPU子系统以高速总线上主设备的方式工作，通过高速总线与其他子系统连接与通信。
  3. 根据权利要求1所述的应用于引信控制系统的SoC芯片结构，其特征在于，所述存储器子系统包括DMA模块、SRAM模块和eflash模块；所述DMA模块、SRAM模块和eflash模块均与高速总线连接。
  4. 根据权利要求1所述的应用于引信控制系统的SoC芯片结构，其特征在于，所述控制输出子系统包括线性调频输出模块和三路可编程开关脉冲输出模块；所述线性调频输出模块的输出信号频率可编程，上限频率和下限频率能独立设置；所述三路可编程开关脉冲输出模块的启动/停止能单独控制；所述线性调频输出模块、三路可编程开关脉冲输出模块均与低速总线连接。
  5. 根据权利要求1所述的应用于引信控制系统的SoC芯片结构，其特征在于，所述输入采样子系统包含ADC模块和多路可选带通滤波器；所述ADC模块和多路可选带通滤波器均与低速总线连接，并且所述ADC模块的输入端与多路可选带通滤波器的输出端连接。
  6. 根据权利要求1所述的应用于引信控制系统的SoC芯片结构，其特征在于，所述外设子系统包括UART模块、SPI模块、GPIO模块和TIMERS模块；所述UART模块、SPI模块、GPIO模块和TIMERS模块均为通用模块，所述UART模块、SPI模块、GPIO模块和TIMERS模块均与低速总线连接。
  7. 根据权利要求1所述的应用于引信控制系统的SoC芯片结构，其特征在于，所述时钟复位子系统包括PLL模块、POR模块和CLK/RST模块；所述PLL模块、POR模块为通用片上锁相环和上电复位电路模块，所述PLL模块用于实现3、4等倍频功能；所述CLK/RST模块用于实现对时钟和复位信号的整形滤波处理功能。
  8. 根据权利要求4所述的应用于引信控制系统的SoC芯片结构，其特征在于，所述三路可编程开关脉冲组包括两个总线接口，用于接收CPU通过总线传递过来的控制信息，并进行控制信息的分解并传递数据给线性调频输出模块和三路可编程开关脉冲输出模块。
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