WO2022160164A1 - 有机发光显示基板及其制作方法、显示装置 - Google Patents

有机发光显示基板及其制作方法、显示装置 Download PDF

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WO2022160164A1
WO2022160164A1 PCT/CN2021/074098 CN2021074098W WO2022160164A1 WO 2022160164 A1 WO2022160164 A1 WO 2022160164A1 CN 2021074098 W CN2021074098 W CN 2021074098W WO 2022160164 A1 WO2022160164 A1 WO 2022160164A1
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sub
anode
substrate
pixel
layer
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PCT/CN2021/074098
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English (en)
French (fr)
Inventor
何伟
李翔
邹浩伟
徐胜
张立震
李士佩
吴慧利
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京东方科技集团股份有限公司
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Priority to CN202180000085.1A priority Critical patent/CN115885594A/zh
Priority to US17/625,712 priority patent/US20230157132A1/en
Priority to DE112021001137.5T priority patent/DE112021001137T5/de
Priority to PCT/CN2021/074098 priority patent/WO2022160164A1/zh
Publication of WO2022160164A1 publication Critical patent/WO2022160164A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B30/00—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images
    • G02B30/20—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes
    • G02B30/26—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes of the autostereoscopic type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/856—Arrangements for extracting light from the devices comprising reflective means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H10K50/858—Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/875—Arrangements for extracting light from the devices
    • H10K59/878—Arrangements for extracting light from the devices comprising reflective means
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B30/00—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images
    • G02B30/20—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes
    • G02B30/26—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes of the autostereoscopic type
    • G02B30/27—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes of the autostereoscopic type involving lenticular arrays

Definitions

  • Embodiments of the present disclosure relate to the field of display technology, and in particular, to an organic light-emitting display substrate, a method for fabricating the same, and a display device.
  • the light-emitting layer of the light-emitting device needs to be placed on the focal plane of the lens .
  • the light emitting device includes a plurality of pixels (eg, R, G, B), and each pixel includes a plurality of sub-anodes.
  • the size of the space between adjacent sub-anodes is relatively large, resulting in that when the light-emitting layer is placed on the focal plane of the lens to realize 3D display, due to the magnification of the lens, the adjacent sub-anodes are separated from each other. The gap between them is enlarged, so that there will be moiré patterns between light and dark, which will affect the display effect.
  • Embodiments of the present disclosure provide an organic light-emitting display substrate, a method for fabricating the same, and a display device, which are used to solve the problem of poor moiré caused by a large gap between adjacent sub-anodes in a 3D display device.
  • embodiments of the present disclosure provide an organic light-emitting display substrate, including a substrate and a plurality of pixels disposed on the substrate, a plurality of the pixels are arranged along a first direction to form a pixel row, and a plurality of rows of pixels The rows are arranged along a second direction, the included angle between the first direction and the second direction is 80-100 degrees, and each of the pixels includes a plurality of sub-anode electrodes;
  • the organic light-emitting display substrate further includes a metal reflection layer, the metal reflection layer is located between the substrate and the layer where the plurality of sub-anodes are located, and the metal reflection layer is insulated from the layer where the plurality of sub-anodes are located, so that the
  • the metal reflection layer includes a plurality of mutually separated metal reflection patterns, each of the metal reflection patterns corresponds to one of the pixels; the orthographic projection of each of the metal reflection patterns on the substrate corresponds to the corresponding pixel.
  • the orthographic projections of the plurality of sub-anodes on the substrate overlap;
  • the plurality of sub-anode electrodes of each pixel are arranged at intervals, and the distance between the orthographic projections of two adjacent sub-anode electrodes on the substrate is less than or equal to a first preset threshold; the first preset threshold is 3.5 ⁇ m or 2 ⁇ m .
  • the distance between the orthographic projections of two adjacent sub-anodes on the substrate is greater than or equal to a second preset threshold, and the second preset threshold is 0.5 ⁇ m.
  • each of the pixels includes a row of sub-anode electrodes, and the row of sub-anode electrodes includes a plurality of sub-anode electrodes arranged along the second direction.
  • each of the pixels includes two columns of sub-anodes, each column of sub-anodes includes a plurality of sub-anodes arranged along the second direction, one of the two columns of sub-anodes is left-eye sub-anode, and the other is right-eye sub-anode, and the The light emitted by the sub-pixels corresponding to the left-eye sub-anode is used to form a left-eye image, and the light emitted by the sub-pixels corresponding to the right-eye sub-anode is used to form a right-eye image.
  • the size of the left-eye sub-anode in the first direction is larger than the size of the left-eye sub-anode in the second direction, and the size of the right-eye sub-anode in the first direction is larger than where it is located. size in the second direction.
  • the left-eye sub-anode column and the right-eye sub-anode column in the same pixel are arranged staggered in the second direction.
  • the orthographic projections of the left-eye sub-anode and the right-eye sub-anode on a straight line extending along the second direction overlap.
  • the minimum distance between the left-eye sub-anode and the right-eye sub-anode is smaller than the minimum distance between the left-eye sub-anode, and the minimum distance between the left-eye sub-anode and the right-eye sub-anode is smaller than that of the right eye.
  • Minimum distance between sub-anodes is smaller than the minimum distance between the left-eye sub-anode, and the minimum distance between the left-eye sub-anode and the right-eye sub-anode is smaller than that of the right eye.
  • the size of the two sub-anodes at the edge in the second direction in the second direction is larger than the size of the other sub-anodes in the second direction.
  • the organic light emitting display substrate further includes a plurality of sub-pixel circuits located between the substrate and the metal reflective layer, and an insulating layer between the metal reflective layer and the layer where the sub-anode is located.
  • the insulating layer has a plurality of anode holes, and each sub-anode is connected to the corresponding sub-pixel circuit through one anode hole.
  • each row of sub-anode corresponds to a plurality of anode holes, and the positions of the plurality of anode holes in the first direction are different.
  • the orthographic projection of each sub-anode on the substrate includes a first edge portion, a middle portion and a second edge portion arranged along the first direction, and the orthographic projection of some anode holes on the substrate is located in the corresponding sub-anode.
  • the first edge portion of the orthographic projection of the anode on the substrate, part of the orthographic projection of the anode hole on the substrate is located in the middle part of the orthographic projection of the corresponding sub-anode on the substrate, and part of the anode hole is in the orthographic projection of the substrate.
  • the projection is located at a second edge portion corresponding to the orthographic projection of the sub-anode on the substrate.
  • the orthographic projection on the substrate is located at the anode hole corresponding to the middle portion of the orthographic projection of the sub-anode on the substrate, and the corresponding sub-anode is located at the edge portion of the corresponding pixel in the second direction.
  • the organic light-emitting display substrate further includes a source-drain metal layer, the source-drain metal layer includes a plurality of wires, each of the sub-anode corresponds to one of the wires, and the sub-anode is connected through an anode hole.
  • the traces corresponding to different sub-anodes are not in contact, and the anode hole of each sub-anode does not overlap with the orthographic projections of the traces of other sub-anodes on the substrate .
  • each of the metal reflection patterns and the orthographic projections of the anode holes corresponding to the plurality of sub-anode electrodes of the corresponding pixel on the substrate do not overlap.
  • the organic light-emitting display substrate further includes a pixel definition layer, and the pixel definition layer includes a plurality of openings corresponding to the pixels one-to-one, and each of the openings and the plurality of sub-anodes of the corresponding pixels are located in the The orthographic projections on the substrate are all overlapping, and the orthographic projection of each opening on the substrate is located inside the orthographic projection of the corresponding metal reflection pattern on the substrate.
  • each of the pixels has a light-emitting layer
  • the orthographic projection of the light-emitting layer on the substrate overlaps with the orthographic projections of a plurality of sub-anode electrodes of the corresponding pixel on the substrate, and the light-emitting layer
  • the orthographic projection on the substrate covers the orthographic projection of the corresponding opening of the pixel definition layer on the substrate.
  • each column of sub-anode includes a first sub-anode, a second sub-anode, a third sub-anode and a fourth sub-anode arranged along the second direction, and each of the pixels includes two sub-pixel circuits, one of which is a sub-pixel circuit. Two of the first sub-anode, the second sub-anode, the third sub-anode and the fourth sub-anode are connected, and the other sub-pixel circuit is connected to the other two sub-anodes.
  • one sub-pixel circuit is connected to the first sub-anode and the third sub-anode
  • the other sub-pixel circuit is connected to the second sub-anode and the fourth sub-anode
  • the first sub-anode is connected to the third sub-anode.
  • the light emitted by the sub-pixels corresponding to the three sub-anodes is used to form the left-eye image
  • the light emitted by the sub-pixels corresponding to the second sub-anode and the fourth sub-anode is used to form the right-eye image
  • the first sub-anode and the third sub-anode The light emitted by the sub-pixels corresponding to the anode is used to form a right-eye image
  • the light emitted by the sub-pixels corresponding to the second sub-anode and the fourth sub-anode is used to form a left-eye image.
  • the sub-pixel circuit includes: thin film transistor T1, thin film transistor T2, thin film transistor T3, thin film transistor T4, thin film transistor T5, thin film transistor T6, thin film transistor T7 and capacitor C1;
  • the gate electrode of the thin film transistor T1 is connected to the n-1th gate line, the first electrode is connected to the reset voltage signal line, and the second electrode is connected to the node A;
  • the gate electrode of the thin film transistor T2 is connected to the nth gate line, the first electrode is connected to the data line, and the second electrode is connected to the node B;
  • the gate electrode of the thin film transistor T3 is connected to node A, the first electrode is connected to node B, and the second electrode is connected to node C;
  • the gate electrode of the thin film transistor T4 is connected to the nth gate line, the first electrode is connected to the node C, and the second electrode is connected to the node A;
  • the gate electrode of the thin film transistor T5 is connected to the first light-emitting control line, the first electrode is connected to the node B, and the second electrode is connected to the node D;
  • the gate electrode of the thin film transistor T6 is connected to the second light-emitting control line, the first electrode is connected to the node C, and the second electrode is connected to the first sub-anode or the second sub-anode;
  • the gate electrode of the thin film transistor T7 is connected to the third light-emitting control line, the first electrode is connected to the node C, and the second electrode is connected to the third sub-anode or the fourth sub-anode;
  • the first electrode of the capacitor C1 is connected to node A, and the second electrode is connected to node D;
  • Node D is connected to the power line, and n is a positive integer greater than 1.
  • an embodiment of the present disclosure provides a display device including the organic light-emitting display substrate of the first aspect.
  • embodiments of the present disclosure provide a method for fabricating an organic light-emitting display substrate, including:
  • a metal reflective layer is formed on the substrate, the metal reflective layer includes a plurality of mutually separated metal reflective patterns,
  • a plurality of pixels are formed on the side of the insulating layer away from the substrate, a plurality of the pixels are arranged along a first direction to form a pixel row, and a plurality of pixel rows are arranged along a second direction, the first direction and the The included angle of the second direction is 80-100 degrees, and each of the pixels includes a plurality of sub-anode electrodes;
  • each of the metal reflection patterns corresponds to one of the pixels; the orthographic projection of each of the metal reflection patterns on the substrate corresponds to the orthographic projection of the corresponding plurality of sub-anode electrodes of the pixel on the substrate. Projection overlap;
  • the plurality of sub-anode electrodes of each pixel are arranged at intervals, and the distance between the orthographic projections of two adjacent sub-anode electrodes on the substrate is less than or equal to a first preset threshold, and the first preset threshold is 3.5 ⁇ m or 2 ⁇ m .
  • the anode is a single-layer transparent anode, which does not include a metal reflective layer, so it will not be limited by the exposure and etching processes of the metal reflective layer during fabrication, resulting in adjacent sub-anodes in the same sub-pixel. If the spacing is too large, the spacing between adjacent sub-anodes in the same sub-pixel can be controlled to be less than or equal to the first preset threshold, so that when the organic light-emitting display substrate is applied to 3D display, the influence of moiré can be reduced or eliminated, Improve the display effect.
  • FIG. 1 is a schematic diagram of an anode in a 3D display substrate in the related art
  • FIG. 2 is a schematic structural diagram of an organic light-emitting display substrate according to an embodiment of the disclosure
  • FIG. 3 is a schematic structural diagram of one pixel of the organic light-emitting display substrate shown in FIG. 2;
  • FIG. 4 is a schematic structural diagram of an organic light-emitting display substrate according to another embodiment of the disclosure.
  • FIG. 5 is a schematic structural diagram of an organic light-emitting display substrate according to another embodiment of the disclosure.
  • FIG. 6 is a schematic structural diagram of an organic light-emitting display substrate according to an embodiment of the disclosure.
  • FIG. 7 is a schematic cross-sectional view of the organic light-emitting display substrate shown in FIG. 2 at X;
  • FIG. 8 is a schematic cross-sectional view of the organic light-emitting display substrate shown in FIG. 4 at the Y position;
  • FIG. 9 is a schematic structural diagram of a 3D display device according to an embodiment of the disclosure.
  • FIGS. 10-22 are schematic diagrams of a method for fabricating a 3D display substrate according to an embodiment of the disclosure.
  • FIG. 23 is a schematic cross-sectional view of an organic light emitting display substrate according to another embodiment of the disclosure.
  • a pixel on a 3D display substrate includes a plurality of sub-anodes, and the sub-anode is usually an ITO/Ag/ITO (indium tin oxide/silver/indium tin oxide) three-layer structure.
  • ITO/Ag/ITO indium tin oxide/silver/indium tin oxide
  • the Ag film layer is etched. Due to the limitation of exposure and etching process levels, the Ag pattern formed after etching has a large bias, resulting in a gap (Space) between adjacent sub-anodes in the same pixel. ) is larger, usually larger than 3.5 ⁇ m, please refer to Figure 1.
  • the light-emitting layer of the pixel needs to be placed on the focal plane of the lens to realize 3D display. Due to the magnification of the lens, the lens will magnify the gap between adjacent sub-anodes, so that the Moiré patterns alternate between light and dark, which affects the display effect.
  • an embodiment of the present disclosure provides an organic light-emitting display substrate, including: a substrate 101 and a plurality of pixels P disposed on the substrate 101 , a plurality of the Pixels P are arranged along the first direction to form pixel rows, and multiple rows of pixel rows are arranged along the second direction.
  • the included angle between the first direction and the second direction is 80-100 degrees, optionally 90 degrees, and each each of the pixels includes a plurality of sub-anode electrodes S;
  • the organic light emitting display substrate further includes a metal reflective layer, the metal reflective layer is located between the substrate 101 and the layer where the plurality of sub-anode S are located, and the metal reflective layer is insulated from the layer where the plurality of sub-anode S are located setting, the metal reflection layer includes a plurality of metal reflection patterns 104 separated from each other, and each of the metal reflection patterns 104 corresponds to one of the pixels P; projection, overlapping with the orthographic projection of the corresponding plurality of sub-anode S of the pixel P on the substrate 101;
  • the plurality of sub-anode S of each pixel P are arranged at intervals, and the distance between the orthographic projections of two adjacent sub-anodes on the substrate is less than or equal to a first preset threshold; the first preset threshold is 3.5 ⁇ m or 2 ⁇ m.
  • the sub-anode adopts a metal oxide material.
  • the metal reflective layer adopts a metal or metal alloy material, for example, Ag, nano-Ag, Ag alloy, ITO/Ag/ITO, Al, Al/ITO or Al alloy material.
  • the anode is a single-layer transparent anode, which does not include a metal reflective layer, so it will not be limited by the exposure and etching processes of the metal reflective layer during fabrication, resulting in adjacent sub-anodes in the same sub-pixel. If the spacing is too large, the spacing between adjacent sub-anodes in the same sub-pixel can be controlled to be less than or equal to the first preset threshold, so that when the organic light-emitting display substrate is applied to 3D display, the influence of moiré can be reduced or eliminated, Improve the display effect.
  • the bias of the sub-anode made of ITO is 0.5 ⁇ m, therefore, optionally, two adjacent sub-anodes on the substrate
  • the spacing of the orthographic projections is greater than or equal to a second preset threshold, and the second preset threshold is 0.5 ⁇ m.
  • each of the pixels P includes a row of sub-anode electrodes, and the row of sub-anode electrodes includes a plurality of sub-anode electrodes S arranged along the second direction.
  • part of the plurality of sub-anode S arranged along the second direction is a left-eye sub-anode, and part is a right-eye sub-anode, and the light emitted by the sub-pixels corresponding to the left-eye sub-anode is used to form a left-eye image.
  • the light emitted by the sub-pixels corresponding to the right-eye sub-anode is used to form a right-eye image.
  • a pixel in FIG. 2 and FIG. 3 includes a first sub-anode, a second sub-anode, a Three sub-anode and fourth sub-anode, the first sub-anode and the third sub-anode are the left-eye sub-anode, the second sub-anode and the fourth sub-anode are the right-eye sub-anode, or, the first sub-anode and the third sub-anode For the right eye sub-anode, the second sub-anode and the fourth sub-anode are for the left eye sub-anode.
  • the size of the left-eye sub-anode in the first direction is larger than the size in the second direction, and the right-eye sub-anode is in the The dimension in the first direction is greater than its dimension in the second direction.
  • the size of the two sub-anode S at the edge in the second direction in the second direction is larger than the size of the other sub-anode S in the second direction .
  • This design considers the crosstalk between the CD bias from the sub-anode and the pixel, and the sub-anode at the edge is larger, but in fact, the effect is the same after the light-emitting layer is lit.
  • one pixel includes one column of sub-anode, and in some other embodiments of the present disclosure, one pixel may also include two rows of sub-anode.
  • the arrangement structure of the pixels may be in the form of a row-column matrix, or may be other structures, such as a diamond structure.
  • each pixel P includes two columns of sub-anode electrodes, each column of sub-anode electrodes includes a plurality of sub-anode electrodes S arranged along the second direction, and the two columns of sub-anode electrodes One column is left-eye sub-anode, the other is right-eye sub-anode, the light emitted by the sub-pixel corresponding to the left-eye sub-anode is used to form the left-eye image, and the light emitted by the sub-pixel corresponding to the right-eye sub-anode is used to form Right eye image.
  • the orthographic projections of the left-eye sub-anode column and the right-eye sub-anode column of the same pixel on a straight line extending along the second direction overlap.
  • the orthographic projections of the left-eye sub-anode column and the right-eye sub-anode column of the same pixel on a straight line extending along the second direction are aligned.
  • the left-eye sub-anode column and the right-eye sub-anode column in the same pixel may also be arranged in a staggered arrangement in the second direction.
  • the minimum distance between the left-eye sub-anode and the right-eye sub-anode is smaller than the minimum distance between the left-eye sub-anode, the left-eye sub-anode and the right-eye sub-anode
  • the minimum distance between anodes was smaller than the minimum distance between the sub-anodes of the right eye.
  • each pixel P includes two columns of sub-anode electrodes, and each column of sub-anode electrodes includes a plurality of sub-anode electrodes S arranged along the second direction, wherein one column of sub-anode electrodes It includes both the left-eye sub-anode and the right-eye sub-anode, and in the second direction, the left-eye sub-anode and the right-eye sub-anode are spaced apart, and in the first direction, it includes both the left-eye sub-anode and the right-eye sub-anode .
  • the size of the left-eye sub-anode in the first direction is larger than the size in the second direction, and the right-eye sub-anode is in the The dimension in the first direction is greater than its dimension in the second direction.
  • the organic display panel further includes: a plurality of sub-pixel circuits located between the substrate and the metal reflective layer, and between the metal reflective layer and the layer where the sub-anode is located
  • the insulating layer has a plurality of anode holes (please refer to the anode hole H in FIG. 3 ), and each sub-anode is connected to the corresponding sub-pixel circuit through an anode hole.
  • each column of sub-anode corresponds to a plurality of anode holes, and the positions of the plurality of anode holes in the first direction are different.
  • each pixel in FIG. 3 includes: a first sub-anode, a second sub-anode, a third sub-anode and a fourth sub-anode arranged along the second direction, each sub-anode corresponds to one anode hole H, four The positions of the anode holes in the first direction are different.
  • the orthographic projection of each sub-anode on the substrate includes a first edge portion, a middle portion and a second edge portion, and some anode holes arranged along the first direction
  • the orthographic projection of the substrate is located at the first edge portion of the orthographic projection of the corresponding sub-anode on the substrate, and the orthographic projection of some anode holes on the substrate is located in the middle portion of the orthographic projection of the corresponding sub-anode on the substrate , the orthographic projection of part of the anode holes on the substrate is located at the second edge portion corresponding to the orthographic projection of the sub-anode on the substrate, so as to avoid crossing the traces connected to each sub-anode.
  • the orthographic projection of the substrate is located at the anode hole in the middle part of the orthographic projection of the corresponding sub-anode on the substrate, and the corresponding sub-anode is located in the second direction of the corresponding pixel. the edge part. For example, the lowermost sub-anode in FIG. 3 .
  • the organic light emitting display substrate further includes a source-drain metal layer, and the source-drain metal layer includes a plurality of wirings L, one for each of the sub-anode S
  • the wiring L and the sub-anode S are connected to the corresponding wiring L through the anode hole H, the wiring L corresponding to the different sub-anode S are not in contact, and the anode hole H of each sub-anode S is connected to the The orthographic projections of the traces L of the other sub-anode S on the substrate do not overlap.
  • each of the metal reflection patterns 104 and the orthographic projections of the anode holes H corresponding to the plurality of sub-anode electrodes S of the corresponding pixel on the substrate do not overlap.
  • each column of sub-anode includes a first sub-anode, a second sub-anode, a third sub-anode and a fourth sub-anode arranged along the second direction, each of the pixel It includes two sub-pixel circuits, one of which is connected to two of the first sub-anode, the second sub-anode, the third sub-anode and the fourth sub-anode, and the other sub-pixel circuit is connected to the other two sub-anodes.
  • one sub-pixel circuit is connected to the first sub-anode and the third sub-anode
  • the other sub-pixel circuit is connected to the second sub-anode and the fourth sub-anode
  • the first sub-anode is connected to the third sub-anode.
  • the light emitted by the sub-pixels corresponding to the three sub-anodes is used to form the left-eye image
  • the light emitted by the sub-pixels corresponding to the second sub-anode and the fourth sub-anode is used to form the right-eye image
  • the first sub-anode and the third sub-anode The light emitted by the sub-pixels corresponding to the anode is used to form a right-eye image
  • the light emitted by the sub-pixels corresponding to the second sub-anode and the fourth sub-anode is used to form a left-eye image.
  • the sub-pixel circuit includes: thin film transistor T1, thin film transistor T2, thin film transistor T3, thin film transistor T4, thin film transistor T5, thin film transistor T6, thin film transistor T7 and capacitor C1;
  • the gate electrode of the thin film transistor T1 is connected to the n-1th gate line (that is, connected to the Gn-1 signal in FIG. 6 ), the first electrode is connected to the reset voltage signal line, and the second electrode is connected to the node A; the first electrode and the One of the second electrodes is a source electrode, and the other is a drain electrode; the reset voltage signal line may be a Vint signal line;
  • the gate electrode of the thin film transistor T2 is connected to the nth gate line (that is, connected to the Gn signal in FIG. 6 ), the first electrode is connected to the data line, and the second electrode is connected to the node B; one of the first electrode and the second electrode is the source electrode, and the other is the drain electrode;
  • the gate electrode of the thin film transistor T3 is connected to node A, the first electrode is connected to node B, and the second electrode is connected to node C; one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode;
  • the gate electrode of the thin film transistor T4 is connected to the nth gate line, the first electrode is connected to the node C, and the second electrode is connected to the node A; one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode;
  • the gate electrode of the thin film transistor T5 is connected to the first light-emitting control line, the first electrode is connected to the node B, and the second electrode is connected to the node D; one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode; the first light-emitting
  • the control line is, for example, the EMCn control line;
  • the gate electrode of the thin film transistor T6 is connected to the second light-emitting control line, the first electrode is connected to the node C, and the second electrode is connected to the first sub-anode or the second sub-anode; one of the first electrode and the second electrode is a source electrode, and the other is a source electrode. is the drain electrode; the second light-emitting control line is, for example, the EM2-n control line;
  • the gate electrode of the thin film transistor T7 is connected to the third light-emitting control line, the first electrode is connected to the node C, and the second electrode is connected to the third sub-anode or the fourth sub-anode; one of the first electrode and the second electrode is a source electrode, and the other is a source electrode. is the drain electrode; the third light-emitting control line is, for example, the EM1-n control line;
  • the first electrode of the capacitor C1 is connected to node A, and the second electrode is connected to node D;
  • Node D is connected to the power line, and n is a positive integer greater than 1.
  • the organic light emitting display substrate further includes a pixel definition layer, and the pixel definition layer includes a plurality of openings corresponding to the pixels P one-to-one, and each of the openings corresponds to a corresponding pixel
  • the orthographic projections of the plurality of sub-anodes on the substrate overlap, and the orthographic projection of each opening on the substrate is located inside the orthographic projection of the corresponding metal reflection pattern on the substrate .
  • each of the pixels has a light-emitting layer
  • the orthographic projection of the light-emitting layer on the substrate intersects with the orthographic projections of the plurality of sub-anode electrodes of the corresponding pixel on the substrate. stack, the orthographic projection of the light-emitting layer on the substrate covers the orthographic projection of the corresponding opening of the pixel definition layer on the substrate.
  • FIG. 7 is a schematic cross-sectional view of the organic light-emitting display substrate shown in FIG. 2 at the position X according to an embodiment of the disclosure.
  • the organic light-emitting display substrate includes:
  • a thin film transistor array layer 102 disposed on one side of the substrate 101;
  • planarization layer 103 disposed on the side of the thin film transistor array layer 102 away from the substrate 101;
  • a first passivation layer 105 disposed on the side of the metal reflective layer away from the substrate 101;
  • the plurality of sub-anode electrodes of each pixel are arranged at intervals, and the distance between the orthographic projections of two adjacent sub-anode electrodes on the substrate is less than or equal to a first preset threshold; the first preset threshold is 3.5 ⁇ m or 2 ⁇ m ;
  • a pixel definition layer 107 disposed on the side of the sub-anode 106 away from the substrate 101;
  • the light-emitting layer 108 disposed on the side of the sub-anode 106 away from the substrate 101;
  • a cathode (not shown) disposed on the side of the light-emitting layer 108 away from the substrate 101;
  • the sub-anode 106 is a single-layer transparent anode and does not include a metal reflective layer, so it is not limited by the exposure and etching processes of the metal reflective layer during fabrication, resulting in adjacent sub-anodes in the same sub-pixel If the spacing is too large, the spacing of adjacent sub-anode electrodes in the same pixel can be controlled to be less than or equal to the first preset threshold, so that when the organic light-emitting display substrate is applied to 3D display, the influence of moiré can be reduced or eliminated, and the display effect.
  • FIG. 8 is a schematic cross-sectional view of the organic light-emitting display substrate shown in FIG. 4 at the Y position according to an embodiment of the disclosure.
  • the organic light-emitting display substrate includes:
  • a thin film transistor array layer 102 disposed on one side of the substrate 101;
  • planarization layer 103 disposed on the side of the thin film transistor array layer 102 away from the substrate 101;
  • a first passivation layer 105 disposed on the side of the metal reflective layer away from the substrate 101;
  • the plurality of sub-anode electrodes of each pixel are arranged at intervals, and the distance between the orthographic projections of two adjacent sub-anode electrodes on the substrate is less than or equal to a first preset threshold; the first preset threshold is 3.5 ⁇ m or 2 ⁇ m ;
  • a pixel definition layer 107 disposed on the side of the sub-anode 106 away from the substrate 101;
  • the light-emitting layer 108 disposed on the side of the sub-anode 106 away from the substrate 101;
  • a cathode (not shown) disposed on the side of the light-emitting layer 108 away from the substrate 101;
  • the sub-anode 106 is a single-layer transparent anode and does not include a metal reflective layer, so it is not limited by the exposure and etching processes of the metal reflective layer during fabrication, resulting in adjacent sub-anodes in the same sub-pixel If the spacing is too large, the spacing of adjacent sub-anode electrodes in the same pixel can be controlled to be less than or equal to the first preset threshold, so that when the organic light-emitting display substrate is applied to 3D display, the influence of moiré can be reduced or eliminated, and the display effect.
  • the thin film transistor array layer 102 includes:
  • a first gate insulating layer 1023 disposed on the active layer 1022;
  • a first gate metal layer 1024 disposed on the side of the first gate insulating layer 1023 away from the substrate;
  • a second gate insulating layer 1025 disposed on the side of the first gate metal layer 1024 away from the substrate;
  • a second gate metal layer 1026 disposed on the side of the second gate insulating layer 1025 away from the substrate;
  • an interlayer dielectric layer 1027 disposed on the side of the second gate metal layer 1026 away from the substrate;
  • a first source-drain metal layer 1028 disposed on the side of the interlayer dielectric layer 1027 away from the substrate;
  • a second passivation layer 1029 disposed on the side of the first source-drain metal layer 1028 away from the substrate;
  • the second source-drain metal layer 1030 is disposed on the side of the second passivation layer 1029 away from the substrate, and the traces of the source-drain metal layer connected to the sub-anode are located on the second source-drain metal layer 1030 .
  • the film layer sequence is the first source-drain metal layer 1028 - the second passivation layer 1029 - the second source-drain layer Metal layer 1030-planarization layer 103.
  • the film layer sequence is the first source-drain metal layer Layer 1028 - second passivation layer 1029 - planarization layer 103' - second source/drain metal layer 1030 - planarization layer 103.
  • the organic light emitting display substrate in the embodiment of the present disclosure has two layers of gate metal layers and two layers of source-drain metal layers, which can meet the requirements of wiring and capacitance.
  • only one gate metal layer, and/or one source/drain metal layer may also be included.
  • the thin film transistors in the above embodiments are top-gate thin film transistors, and in other embodiments of the present disclosure, they may also be bottom-gate thin film transistors.
  • the organic light emitting display substrate in the embodiment of the present disclosure may be an OLED display substrate, a miniLED display substrate, a microLED display substrate, a QLED display substrate, or other types of display substrates.
  • the present disclosure also provides a display device including the organic light-emitting display substrate and the lens in any of the above embodiments, wherein the light-emitting layer of the organic light-emitting display substrate is disposed on the focal plane of the lens, please refer to FIG. 9 .
  • the present disclosure also provides a method for fabricating an organic light-emitting display substrate, including:
  • Step S1 providing a substrate
  • Step S2 forming a metal reflection layer on the substrate, the metal reflection layer includes a plurality of mutually separated metal reflection patterns,
  • Step S3 forming an insulating layer on the side of the metal reflective layer away from the substrate;
  • Step S4 forming a plurality of pixels on the side of the insulating layer away from the substrate, a plurality of the pixels are arranged along a first direction to form a pixel row, a plurality of pixel rows are arranged along a second direction, the first direction
  • the included angle with the second direction is 80-100 degrees, and each of the pixels includes a plurality of sub-anode;
  • each of the metal reflection patterns corresponds to one of the pixels; the orthographic projection of each of the metal reflection patterns on the substrate corresponds to the orthographic projection of the corresponding plurality of sub-anode electrodes of the pixel on the substrate. Projection overlap;
  • the plurality of sub-anode electrodes of each pixel are arranged at intervals, and the distance between the orthographic projections of two adjacent sub-anode electrodes on the substrate is less than or equal to a first preset threshold, and the first preset threshold is 3.5 ⁇ m or 2 ⁇ m .
  • the distance between the orthographic projections of two adjacent sub-anodes on the substrate is greater than or equal to a second preset threshold, and the second preset threshold is 0.5 ⁇ m.
  • each of the pixels includes a row of sub-anode electrodes, and the row of sub-anode electrodes includes a plurality of sub-anode electrodes arranged along the second direction.
  • each of the pixels includes two columns of sub-anodes, each column of sub-anodes includes a plurality of sub-anodes arranged along the second direction, one of the two columns of sub-anodes is left-eye sub-anode, and the other is right-eye sub-anode, and the The light emitted by the sub-pixels corresponding to the left-eye sub-anode is used to form a left-eye image, and the light emitted by the sub-pixels corresponding to the right-eye sub-anode is used to form a right-eye image.
  • the size of the left-eye sub-anode in the first direction is larger than the size of the left-eye sub-anode in the second direction, and the size of the right-eye sub-anode in the first direction is larger than where it is located. size in the second direction.
  • the left-eye sub-anode column and the right-eye sub-anode column in the same pixel are arranged staggered in the second direction.
  • the orthographic projections of the left-eye sub-anode and the right-eye sub-anode on a straight line extending along the second direction overlap.
  • the minimum distance between the left-eye sub-anode and the right-eye sub-anode is smaller than the minimum distance between the left-eye sub-anode, and the minimum distance between the left-eye sub-anode and the right-eye sub-anode is smaller than that of the right eye.
  • Minimum distance between sub-anodes is smaller than the minimum distance between the left-eye sub-anode, and the minimum distance between the left-eye sub-anode and the right-eye sub-anode is smaller than that of the right eye.
  • the size of the two sub-anodes at the edge in the second direction in the second direction is larger than the size of the other sub-anodes in the second direction.
  • the method further includes:
  • each sub-anode is connected to the corresponding sub-pixel circuit through an anode hole.
  • each row of sub-anode corresponds to a plurality of anode holes, and the positions of the plurality of anode holes in the first direction are different.
  • the orthographic projection of each sub-anode on the substrate includes a first edge portion, a middle portion and a second edge portion arranged along the first direction, and the orthographic projection of some anode holes on the substrate is located in the corresponding sub-anode.
  • the first edge portion of the orthographic projection of the anode on the substrate, part of the orthographic projection of the anode hole on the substrate is located in the middle part of the orthographic projection of the corresponding sub-anode on the substrate, and part of the anode hole is in the orthographic projection of the substrate.
  • the projection is located at a second edge portion corresponding to the orthographic projection of the sub-anode on the substrate.
  • the orthographic projection on the substrate is located at the anode hole corresponding to the middle portion of the orthographic projection of the sub-anode on the substrate, and the corresponding sub-anode is located at the edge portion of the corresponding pixel in the second direction.
  • the method further includes: forming a source-drain metal layer, the source-drain metal layer includes a plurality of wires, each of the sub-anode corresponds to one of the wires, and the sub-anode is connected to the corresponding wire through an anode hole
  • the traces corresponding to different sub-anodes do not touch, and the anode holes of each sub-anode do not overlap with the orthographic projections of the traces of other sub-anodes on the substrate.
  • each of the metal reflection patterns and the orthographic projections of the anode holes corresponding to the plurality of sub-anode electrodes of the corresponding pixel on the substrate do not overlap.
  • the method further includes: forming a pixel definition layer, the pixel definition layer includes a plurality of openings corresponding to the pixels one-to-one, and each of the openings and the plurality of sub-anode electrodes of the corresponding pixel are located on the substrate.
  • the orthographic projections on the bottom overlap, and the orthographic projection of each opening on the substrate is located inside the orthographic projection of the corresponding metal reflection pattern on the substrate.
  • each of the pixels has a light-emitting layer
  • the orthographic projection of the light-emitting layer on the substrate overlaps with the orthographic projections of a plurality of sub-anode electrodes of the corresponding pixel on the substrate, and the light-emitting layer
  • the orthographic projection on the substrate covers the orthographic projection of the corresponding opening of the pixel definition layer on the substrate.
  • each column of sub-anode includes a first sub-anode, a second sub-anode, a third sub-anode and a fourth sub-anode arranged along the second direction, and each of the pixels includes two sub-pixel circuits, one of which is a sub-pixel circuit. Two of the first sub-anode, the second sub-anode, the third sub-anode and the fourth sub-anode are connected, and the other sub-pixel circuit is connected to the other two sub-anodes.
  • one sub-pixel circuit is connected to the first sub-anode and the third sub-anode
  • the other sub-pixel circuit is connected to the second sub-anode and the fourth sub-anode
  • the first sub-anode is connected to the third sub-anode.
  • the light emitted by the sub-pixels corresponding to the three sub-anodes is used to form the left-eye image
  • the light emitted by the sub-pixels corresponding to the second sub-anode and the fourth sub-anode is used to form the right-eye image
  • the first sub-anode and the third sub-anode The light emitted by the sub-pixels corresponding to the anode is used to form a right-eye image
  • the light emitted by the sub-pixels corresponding to the second sub-anode and the fourth sub-anode is used to form a left-eye image.
  • the sub-pixel circuit includes: thin film transistor T1, thin film transistor T2, thin film transistor T3, thin film transistor T4, thin film transistor T5, thin film transistor T6, thin film transistor T7 and capacitor C1;
  • the gate electrode of the thin film transistor T1 is connected to the n-1th gate line, the first electrode is connected to the reset voltage signal line, and the second electrode is connected to the node A;
  • the gate electrode of the thin film transistor T2 is connected to the nth gate line, the first electrode is connected to the data line, and the second electrode is connected to the node B;
  • the gate electrode of the thin film transistor T3 is connected to node A, the first electrode is connected to node B, and the second electrode is connected to node C;
  • the gate electrode of the thin film transistor T4 is connected to the nth gate line, the first electrode is connected to the node C, and the second electrode is connected to the node A;
  • the gate electrode of the thin film transistor T5 is connected to the first light-emitting control line, the first electrode is connected to the node B, and the second electrode is connected to the node D;
  • the gate electrode of the thin film transistor T6 is connected to the second light-emitting control line, the first electrode is connected to the node C, and the second electrode is connected to the first sub-anode or the second sub-anode;
  • the gate electrode of the thin film transistor T7 is connected to the third light-emitting control line, the first electrode is connected to the node C, and the second electrode is connected to the third sub-anode or the fourth sub-anode;
  • the first electrode of the capacitor C1 is connected to node A, and the second electrode is connected to node D;
  • Node D is connected to the power line, and n is a positive integer greater than 1.
  • a method for fabricating a 3D display substrate according to an embodiment of the present disclosure includes:
  • Step 501 providing the substrate 101
  • Step 502 forming a buffer layer 1021 on one side of the substrate 101 ;
  • the buffer layer 1021 can be a stacked structure of SiN or SiON or SiNx or SiO2 or any two or more of them.
  • the buffer layer 1021 is a stacked structure of SiNx and SiO2, wherein the thickness of SiNx is about 200- 400nm, the thickness of SiO2 is about 400-600nm.
  • Step 503 forming an active layer 1022 on the side of the buffer layer 1021 away from the substrate 101 and patterning;
  • the active layer may be a polysilicon active layer, or an oxide active layer.
  • the active layer 1022 is polysilicon, with a thickness of about 400-500 nm.
  • Step 504 forming a first gate insulating layer 1023 on the side of the active layer 1022 away from the substrate 101 ;
  • the first gate insulating layer 1023 can be a stacked structure of SiN or SiON or SiNx or SiO2 or any two or more of the above.
  • the first gate insulating layer 1023 is a stacked structure of SiO2 and SiNx, wherein , the thickness of SiO2 is about 700-900nm, and the thickness of SiNx is about 300-500nm;
  • Step 505 forming a first gate metal layer 1024 on the side of the first gate insulating layer 1023 away from the substrate 101 and patterning;
  • the first gate metal layer 1024 may be Mo, Ti or Al or an alloy of any two or more of the above. In one embodiment, the first gate metal layer 1024 is Mo, with a thickness of about 2500-3500 nm.
  • Step 506 forming a second gate insulating layer 1025 on the side of the first gate metal layer 1024 away from the substrate 101 and patterning;
  • the second gate insulating layer 1025 may be SiN or SiON or SiNx or SiO2 or a stacked structure of any two or more of the above.
  • the second gate insulating layer 1025 is SiNx, with a thickness of about 1000-2000 nm;
  • Step 507 forming a second gate metal layer 1026 on the side of the second gate insulating layer 1025 away from the substrate 101 and patterning;
  • the second gate metal layer 1026 may be Mo, Ti or Al or an alloy of any two or more of the above. In one embodiment, the second gate metal layer 1026 is Mo, with a thickness of about 2500-3500 nm.
  • Step 508 forming an interlayer dielectric layer 1027 on the side of the second gate metal layer 1026 away from the substrate 101 ;
  • the interlayer dielectric layer 1027 can be a stacked structure of SiN or SiON or SiNx or SiO2 or any two or more of the above.
  • the interlayer dielectric layer 1027 is a stacked structure of SiO2 and SiNx, and the thickness of SiO2 About 1000-3000nm, if it is SiNx, the thickness is about 2000-4000nm;
  • Step 509 forming a first source-drain metal layer 1028 on the side of the interlayer dielectric layer 1027 away from the substrate 101 and patterning;
  • the first source-drain metal layer 1028 may be a metal such as Mo, Ti or Al, or a stacked structure of any two or more of the above.
  • the first source-drain metal layer 1028 is a Ti/Al/Ti stack Structure, the thickness is about 400-600nm/3000-5000nm/400-600nm.
  • Step 510 Form a second passivation layer 1029 on the side of the first source-drain metal layer 1028 away from the substrate 101, and perform patterning;
  • the second passivation layer 1029 may be SiN or SiON or SiNx or SiO2 or a stacked structure of any two or more of the above; in one embodiment, the second passivation layer 1029 is SiNx with a thickness of about 3000-4000 nm.
  • Step 511 Form a second source-drain metal layer 1030 on the side of the second passivation layer 1029 away from the substrate 101, and perform patterning.
  • the second source-drain metal layer 1030 includes a source-drain metal layer. Wire;
  • the second source-drain metal layer 1030 may be a metal such as Mo, Ti or Al, or a stacked structure of any two or more of the above.
  • the second source-drain metal layer 1030 is a Ti/Al/Ti stack structure with a thickness of about 400-600nm/3000-5000nm/400-600nm.
  • Step 512 forming the planarization layer 103 and patterning.
  • the planarization layer 103 can be made of photoresist, and the thickness is about 15000-25000 nm.
  • Step 513 forming a metal reflection layer and patterning to form a plurality of mutually separated metal reflection patterns 104 , each of which corresponds to one of the pixels;
  • the metal reflective layer may be a metal with high reflectivity such as Ag or Al or other materials with high reflectivity in the visible light region.
  • the metal reflective layer is Ag.
  • Step 514 forming the first passivation layer 105 and patterning
  • the first passivation layer 105 may be SiN or SiON or SiNx or SiO 2 or a stacked structure of any two or more of the above; in one embodiment, the first passivation layer 105 is SiNx.
  • the reflective layer 104 is covered by the first passivation layer 105, it will not be oxidized. At the same time, no etching damage will be caused to the planarization layer.
  • Step 515 forming a plurality of sub-anode electrodes 106 of each pixel, the plurality of sub-anode electrodes of each pixel are arranged at intervals, and the distance between the orthographic projections of two adjacent sub-anode electrodes on the substrate is less than or equal to a first preset threshold ; the first preset threshold is 3.5 ⁇ m or 2 ⁇ m.
  • the sub-anode 106 may be a low resistance, high work function metal such as Au or Pt, or a metal oxide such as ITO, IZO, or the like. In one embodiment, the sub-anode 106 is ITO.
  • Step 516 The pixel definition layer 107 is formed and patterned.
  • the pixel definition layer 107 can use photoresist, and the thickness is about 10000-15000 nm.
  • Step 517 Form the pattern of the light emitting layer and the cathode.
  • the spacing between the anodes of the left-eye sub-pixel and the right-eye sub-pixel can be adjusted from greater than 3.5 to a range of greater than or equal to 0.5 and less than or equal to 1.5 ⁇ m, and the molar The grain level is less than 10%, which improves the display effect.

Abstract

一种有机发光显示基板及其制作方法、显示装置，显示基板包括衬底（101）、金属反射层和多个像素，每个像素包括多个子阳极（106）；金属反射层位于衬底（101）和多个子阳极（106）所在层之间，金属反射层与多个子阳极（106）所在层绝缘设置，金属反射层包括多个相互分离的金属反射图形（104），每个金属反射图形（104）对应一个像素；每个金属反射图形（104）在衬底（101）上的正投影，与对应的像素的多个子阳极（106）在衬底（101）上的正投影交叠；每个像素的多个子阳极（106）间隔设置，相邻的两个子阳极（106）在衬底（101）上的正投影的间距小于或等于第一预设阈值；第一预设阈值为3.5μm或2μm。将同一像素中的相邻子阳极（106）的间距控制在小于或等于第一预设阈值，可以减轻或消除摩尔纹的影响，提高显示效果。

Description

有机发光显示基板及其制作方法、显示装置 技术领域
本公开实施例涉及显示技术领域，尤其涉及一种有机发光显示基板及其制作方法、显示装置。
背景技术
OLED(有机发光二极管)、miniLED(迷你发光二极管)、microLED(微发光二极管)、QLED(量子点有机发光二极管)等类型的3D显示装置中，需要将发光器件的发光层置于透镜焦面上。发光器件包括多个像素(如R、G、B)，每个像素包括多个子阳极。受限于工艺水平，相邻的子阳极之间的间隙(space)尺寸较大，导致将发光层置于透镜焦面上实现3D显示时，由于透镜的放大作用，使得相邻的子阳极之间的间隙被放大，从而会出现明暗相间的摩尔纹，影响显示效果。
发明内容
本公开实施例提供一种有机发光显示基板及其制作方法、显示装置，用于解决3D显示装置因为相邻的子阳极之间的间隙较大导致的摩尔纹不良问题。
为了解决上述技术问题，本公开是这样实现的：
第一方面，本公开实施例提供了一种有机发光显示基板，包括衬底以及设置于所述衬底上的多个像素，多个所述像素沿第一方向排列构成像素行，多行像素行沿第二方向排列，所述第一方向和所述第二方向的夹角为80-100度，每个所述像素包括多个子阳极；
所述有机发光显示基板还包括金属反射层，所述金属反射层位于所述衬底和所述多个子阳极所在层之间，所述金属反射层与所述多个子阳极所在层绝缘设置，所述金属反射层包括多个相互分离的金属反射图形，每个所述金属反射图形对应一个所述像素；每个所述金属反射图形在所述衬底上的正投影，与对应的所述像素的多个子阳极在所述衬底上的正投影交叠；
每个所述像素的多个子阳极间隔设置，相邻的两个子阳极在所述衬底上的正投影的间距小于或等于第一预设阈值；所述第一预设阈值为3.5μm或者2μm。
可选的，相邻的两个子阳极在所述衬底上的正投影的间距大于或等于第二预设阈值，所述第二预设阈值为0.5μm。
可选的，每个所述像素包括一列子阳极，所述一列子阳极包括多个沿第二方向排列的子阳极。
可选的，每个所述像素包括两列子阳极，每列子阳极包括多个沿第二方向排列的子阳极，所述两列子阳极一列为左眼子阳极，一列为右眼子阳极，所述左眼子阳极对应的子像素发出的光用于形成左眼图像，所述右眼子阳极对应的子像素发出的光用于形成右眼图像。
可选的，所述左眼子阳极在所述第一方向上的尺寸大于其在所述第二方向上的尺寸，所述右眼子阳极在所述第一方向上的尺寸大于其在所述第二方向上的尺寸。
可选的，在同一像素中的左眼子阳极列和右眼子阳极列在第二方向上错位排列。
可选的，同一像素中，左眼子阳极和右眼子阳极在沿第二方向延伸的直线上的正投影具有交叠。
可选的，同一像素中，左眼子阳极和右眼子阳极之间的最小距离小于左眼子阳极之间的最小距离，左眼子阳极和右眼子阳极之间的最小距离小于右眼子阳极之间的最小距离。
可选的，每列子阳极中，在第二方向上的边缘的2个子阳极在第二方向的尺寸大于其他子阳极在第二方向的尺寸。
可选的，所述有机发光显示基板还包括位于所述衬底和所述金属反射层之间的多个子像素电路，以及，位于所述金属反射层和所述子阳极所在层之间的绝缘层，所述绝缘层具有多个阳极孔，每个所述子阳极通过一个阳极孔连接对应的子像素电路。
可选的，每列子阳极对应多个阳极孔，所述多个阳极孔在第一方向上的位置不同。
可选的，每个子阳极在所述衬底上的正投影包括沿第一方向排列的第一边缘部分，中间部分和第二边缘部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的第一边缘部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的中间部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的第二边缘部分。
可选的，在所述衬底的正投影位于对应子阳极在所述衬底上的正投影的中间部分的阳极孔，其对应的子阳极位于对应像素在第二方向的边缘部分。
可选的，所述有机发光显示基板还包括源漏金属层，所述源漏金属层包括多条走线，每个所述子阳极对应一条所述走线，所述子阳极通过阳极孔连接对应的所述走线，不同的所述子阳极对应的所述走线不接触，每个子阳极的阳极孔与其他子阳极的所述走线在所述衬底上的正投影均不交叠。
可选的，每个所述金属反射图形与对应的像素的多个子阳极对应的阳极孔在所述衬底上的正投影不交叠。
可选的，所述有机发光显示基板还包括像素定义层，所述像素定义层包括与所述像素一一对应的多个开口，每个所述开口与对应的像素的多个子阳极在所述衬底上的正投影均交叠，每个所述开口的在所述衬底上的正投影位于对应的所述金属反射图形在所述衬底上的正投影内部。
可选的，每个所述像素具有一个发光层，发光层在所述衬底上的正投影与对应的像素的多个子阳极在所述衬底上的正投影均交叠，所述发光层在所述衬底上的正投影覆盖像素定义层的对应开口在所述衬底上的正投影。
可选的，每列子阳极包括沿第二方向排列的第一子阳极、第二子阳极、第三子阳极和第四子阳极，每个所述像素包括2个子像素电路，其中一个子像素电路连接第一子阳极、第二子阳极、第三子阳极和第四子阳极中的其中两个子阳极，另一个子像素电路连接另外两个子阳极。
可选的，所述2个子像素电路中，一个子像素电路连接第一个子阳极和第三个子阳极，另一个子像素电路连接第二个子阳极和第四个子阳极，第一子阳极和第三子阳极对应的子像素发出的光用于形成左眼图像，第二子阳极和第四子阳极对应的子像素发出的光用于形成右眼图像，或者，第一子阳极和第三子阳极对应的子像素发出的光用于形成右眼图像，第二子阳极和第四 子阳极对应的子像素发出的光用于形成左眼图像。
可选的，所述子像素电路包括：薄膜晶体管T1、薄膜晶体管T2、薄膜晶体管T3、薄膜晶体管T4、薄膜晶体管T5、薄膜晶体管T6、薄膜晶体管T7和电容C1；
其中，薄膜晶体管T1的栅电极连接第n-1条栅线，第一电极连接复位电压信号线，第二电极连接节点A；
薄膜晶体管T2的栅电极连接第n条栅线，第一电极连接数据线，第二电极连接节点B；
薄膜晶体管T3的栅电极连接节点A，第一电极连接节点B，第二电极连接节点C；
薄膜晶体管T4的栅电极连接第n条栅线，第一电极连接节点C，第二电极连接节点A；
薄膜晶体管T5的栅电极连接第一发光控制线，第一电极连接节点B，第二电极连接节点D；
薄膜晶体管T6的栅电极连接第二发光控制线，第一电极连接节点C，第二电极连接第一子阳极或第二子阳极；
薄膜晶体管T7的栅电极连接第三发光控制线，第一电极连接节点C，第二电极连接第三子阳极或第四子阳极；
电容C1的第一电极连接节点A，第二电极连接节点D；
节点D连接电源线，n为大于1的正整数。
第二方面，本公开实施例提供了一种显示装置，包括上述第一方面的有机发光显示基板。
第三方面，本公开实施例提供了一种有机发光显示基板的制作方法，包括：
提供衬底；
在所述衬底上形成金属反射层，所述金属反射层包括多个相互分离的金属反射图形，
在所述金属反射层远离所述衬底的一侧形成绝缘层；
在所述绝缘层远离所述衬底的一侧形成多个像素，多个所述像素沿第一 方向排列构成像素行，多行像素行沿第二方向排列，所述第一方向和所述第二方向的夹角为80-100度，每个所述像素包括多个子阳极；
其中，每个所述金属反射图形对应一个所述像素；每个所述金属反射图形在所述衬底上的正投影，与对应的所述像素的多个子阳极在所述衬底上的正投影交叠；
每个所述像素的多个子阳极间隔设置，相邻的两个子阳极在所述衬底上的正投影的间距小于或等于第一预设阈值，所述第一预设阈值为3.5μm或者2μm。
本公开实施例中，阳极为单层透明阳极，不包括金属反射层，因而在制作时不会被金属反射层的曝光和刻蚀工艺所限，导致同一子像素中的相邻的子阳极的间距过大，可以将同一子像素中的相邻的子阳极的间距控制在小于或等于第一预设阈值，从而将该有机发光显示基板应用3D显示时，可以减轻或消除摩尔纹的影响，提高显示效果。
附图说明
图1为相关技术中的3D显示基板中的阳极的示意图；
图2为本公开一实施例的有机发光显示基板的结构示意图；
图3为图2所示的有机发光显示基板的一个像素的结构示意图；
图4为本公开另一实施例的有机发光显示基板的结构示意图；
图5为本公开又一实施例的有机发光显示基板的结构示意图；
图6为本公开一实施例的有机发光显示基板的结构示意图；
图7为图2所示的有机发光显示基板的X处的剖面示意图；
图8为图4所示的有机发光显示基板的Y处的剖面示意图；
图9为本公开实施例的3D显示装置的结构示意图；
图10-图22为本公开实施例的3D显示基板的制作方法示意图；
图23为本公开另一实施例的有机发光显示基板的剖面示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行 清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
相关技术中，3D显示基板上的像素包括多个子阳极，子阳极通常为ITO/Ag/ITO(氧化铟锡/银/氧化铟锡)三层结构，在形成子阳极的工艺中，需要对沉积的Ag膜层进行刻蚀，由于曝光和刻蚀工艺水平所限，刻蚀后形成的Ag图形偏差(bias)较大，从而导致同一个像素中的相邻的子阳极之间的间隙(Space)较大，通常大于3.5μm，请参考图1。
在3D显示装置中，需要将像素的发光层置于透镜的焦面上，以实现3D显示，由于透镜的放大作用，透镜会将相邻的子阳极之间的间隙放大，从而在显示时会出现明暗相间的摩尔纹，影响显示效果。
为解决上述问题，请参考图2和图3，本公开实施例提供了一种有机发光显示基板，包括：衬底101以及设置于所述衬底101上的多个像素P，多个所述像素P沿第一方向排列构成像素行，多行像素行沿第二方向排列，所述第一方向和所述第二方向的夹角为80-100度，可选的，为90度，每个所述像素包括多个子阳极S；
所述有机发光显示基板还包括金属反射层，所述金属反射层位于所述衬底101和所述多个子阳极S所在层之间，所述金属反射层与所述多个子阳极S所在层绝缘设置，所述金属反射层包括多个相互分离的金属反射图形104，每个所述金属反射图形104对应一个所述像素P；每个所述金属反射图形104在所述衬底101上的正投影，与对应的所述像素P的多个子阳极S在所述衬底101上的正投影交叠；
每个所述像素P的多个子阳极S间隔设置，相邻的两个子阳极在所述衬底上的正投影的间距小于或等于第一预设阈值；所述第一预设阈值为3.5μm或者2μm。
本公开实施例中，可选的，所述子阳极采用金属氧化物材料。
本公开实施例中，可选的，所述金属反射层采用金属或金属合金材料，例如，Ag、纳米Ag、Ag合金、ITO/Ag/ITO、Al、Al/ITO或Al合金材料。
本公开实施例中，阳极为单层透明阳极，不包括金属反射层，因而在制 作时不会被金属反射层的曝光和刻蚀工艺所限，导致同一子像素中的相邻的子阳极的间距过大，可以将同一子像素中的相邻的子阳极的间距控制在小于或等于第一预设阈值，从而将该有机发光显示基板应用3D显示时，可以减轻或消除摩尔纹的影响，提高显示效果。
在本公开的一些实施例中，由于子阳极也会存在少许bias，例如ITO制成的子阳极的bias为0.5μm，因而，可选的，相邻的两个子阳极在所述衬底上的正投影的间距大于或等于第二预设阈值，所述第二预设阈值为0.5μm。
图2和图3所示的实施例中，每个所述像素P包括一列子阳极，所述一列子阳极包括多个沿第二方向排列的子阳极S。
可选的，所述多个沿第二方向排列的子阳极S部分为左眼子阳极，部分为右眼子阳极，所述左眼子阳极对应的子像素发出的光用于形成左眼图像，所述右眼子阳极对应的子像素发出的光用于形成右眼图像。
可选的，左眼子阳极与右眼子阳极交替设置，以提高显示效果，例如，图2和图3中的一个像素包括沿第二方向排列的第一子阳极、第二子阳极、第三子阳极和第四子阳极，第一子阳极和第三子阳极为左眼子阳极，第二子阳极和第四子阳极为右眼子阳极，或者，第一子阳极和第三子阳极为右眼子阳极，第二子阳极和第四子阳极为左眼子阳极。
图2和图3所示的实施例中，可选的，所述左眼子阳极在所述第一方向上的尺寸大于其在所述第二方向上的尺寸，所述右眼子阳极在所述第一方向上的尺寸大于其在所述第二方向上的尺寸。
图2和图3所示的实施例中，可选的，每列子阳极中，在第二方向上的边缘的2个子阳极S在第二方向的尺寸大于其他子阳极S在第二方向的尺寸。该种设计考虑从到子阳极的CD bias和像素之间的串扰，边缘的子阳极偏大，但是实际上发光层点亮之后效果是一致的。
上述实施例中，一个像素包含一列子阳极，在本公开的其他一些实施例中，一个像素也可以包含两行子阳极。
图2和图3所示的实施例中，像素的排列结构可以是呈行列矩阵方式，也可以是其他结构，例如钻石结构等。
请参考图4，在本公开的其他实施例中，可选的，每个所述像素P包括 两列子阳极，每列子阳极包括多个沿第二方向排列的子阳极S，所述两列子阳极一列为左眼子阳极，一列为右眼子阳极，所述左眼子阳极对应的子像素发出的光用于形成左眼图像，所述右眼子阳极对应的子像素发出的光用于形成右眼图像。
图4所示的实施例中，可选的，同一像素的左眼子阳极列和右眼子阳极列在沿第二方向延伸的直线上的正投影具有交叠。可选的，同一像素的左眼子阳极列和右眼子阳极列在沿第二方向延伸的直线上的正投影对齐。当然，在本公开的另外一些实施例中，可选的，在同一像素中的左眼子阳极列和右眼子阳极列在第二方向上也可以错位排列。
图4所示的实施例中，可选的，同一像素中，左眼子阳极和右眼子阳极之间的最小距离小于左眼子阳极之间的最小距离，左眼子阳极和右眼子阳极之间的最小距离小于右眼子阳极之间的最小距离。
请参考图5，在本公开的其他实施例中，可选的，每个所述像素P包括两列子阳极，每列子阳极包括多个沿第二方向排列的子阳极S，其中，一列子阳极中既包括左眼子阳极，又包括右眼子阳极，在第二方向上，左眼子阳极和右眼子阳极间隔设置，在第一方向上，同时包括左眼子阳极和右眼子阳极。
图4和图5所示的实施例中，可选的，所述左眼子阳极在所述第一方向上的尺寸大于其在所述第二方向上的尺寸，所述右眼子阳极在所述第一方向上的尺寸大于其在所述第二方向上的尺寸。
上述各实施例中，所述有机显示面板还包括：位于所述衬底和所述金属反射层之间的多个子像素电路，以及，位于所述金属反射层和所述子阳极所在层之间的绝缘层，所述绝缘层具有多个阳极孔(请参考图3中的阳极孔H)，每个所述子阳极通过一个阳极孔连接对应的子像素电路。
本公开实施例中，可选的，每列子阳极对应多个阳极孔，所述多个阳极孔在第一方向上的位置不同。请参考图3，图3中每个像素包括：沿第二方向排列的第一子阳极、第二子阳极、第三子阳极和第四子阳极，每个子阳极对应一个阳极孔H，4个阳极孔在第一方向上的位置不同。
本公开实施例中，可选的，请参考图3，每个子阳极在所述衬底上的正 投影包括沿第一方向排列的第一边缘部分，中间部分和第二边缘部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的第一边缘部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的中间部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的第二边缘部分，从而避免与各子阳极连接的走线交叉。
本公开实施例中，可选的，在所述衬底的正投影位于对应子阳极在所述衬底上的正投影的中间部分的阳极孔，其对应的子阳极位于对应像素在第二方向的边缘部分。例如图3中的最下方的一个子阳极。
本公开实施例中，可选的，请参考图3，所述有机发光显示基板还包括源漏金属层，所述源漏金属层包括多条走线L，每个所述子阳极S对应一条所述走线L，所述子阳极S通过阳极孔H连接对应的所述走线L，不同的所述子阳极S对应的所述走线L不接触，每个子阳极S的阳极孔H与其他子阳极S的所述走线L在所述衬底上的正投影均不交叠。
本公开实施例中，可选的，请参考图3，每个所述金属反射图形104与对应的像素的多个子阳极S对应的阳极孔H在所述衬底上的正投影不交叠。
本公开实施例中，可选的，请参考图3，每列子阳极包括沿第二方向排列的第一子阳极、第二子阳极、第三子阳极和第四子阳极，每个所述像素包括2个子像素电路，其中一个子像素电路连接第一子阳极、第二子阳极、第三子阳极和第四子阳极中的其中两个子阳极，另一个子像素电路连接另外两个子阳极。
可选的，所述2个子像素电路中，一个子像素电路连接第一个子阳极和第三个子阳极，另一个子像素电路连接第二个子阳极和第四个子阳极，第一子阳极和第三子阳极对应的子像素发出的光用于形成左眼图像，第二子阳极和第四子阳极对应的子像素发出的光用于形成右眼图像，或者，第一子阳极和第三子阳极对应的子像素发出的光用于形成右眼图像，第二子阳极和第四子阳极对应的子像素发出的光用于形成左眼图像。
请参考图6，可选的，所述子像素电路包括：薄膜晶体管T1、薄膜晶体管T2、薄膜晶体管T3、薄膜晶体管T4、薄膜晶体管T5、薄膜晶体管T6、薄膜晶体管T7和电容C1；
其中，薄膜晶体管T1的栅电极连接第n-1条栅线(即接入图6中的Gn-1信号)，第一电极连接复位电压信号线，第二电极连接节点A；第一电极和第二电极其中之一为源电极，另一为漏电极；该复位电压信号线可以是Vint信号线；
薄膜晶体管T2的栅电极连接第n条栅线(即接入图6中的Gn信号)，第一电极连接数据线，第二电极连接节点B；第一电极和第二电极其中之一为源电极，另一为漏电极；
薄膜晶体管T3的栅电极连接节点A，第一电极连接节点B，第二电极连接节点C；第一电极和第二电极其中之一为源电极，另一为漏电极；
薄膜晶体管T4的栅电极连接第n条栅线，第一电极连接节点C，第二电极连接节点A；第一电极和第二电极其中之一为源电极，另一为漏电极；
薄膜晶体管T5的栅电极连接第一发光控制线，第一电极连接节点B，第二电极连接节点D；第一电极和第二电极其中之一为源电极，另一为漏电极；第一发光控制线例如为EMCn控制线；
薄膜晶体管T6的栅电极连接第二发光控制线，第一电极连接节点C，第二电极连接第一子阳极或第二子阳极；第一电极和第二电极其中之一为源电极，另一为漏电极；第二发光控制线例如为EM2-n控制线；
薄膜晶体管T7的栅电极连接第三发光控制线，第一电极连接节点C，第二电极连接第三子阳极或第四子阳极；第一电极和第二电极其中之一为源电极，另一为漏电极；第三发光控制线例如为EM1-n控制线；
电容C1的第一电极连接节点A，第二电极连接节点D；
节点D连接电源线，n为大于1的正整数。
本公开实施例中，可选的，所述有机发光显示基板还包括像素定义层，所述像素定义层包括与所述像素P一一对应的多个开口，每个所述开口与对应的像素的多个子阳极在所述衬底上的正投影均交叠，每个所述开口的在所述衬底上的正投影位于对应的所述金属反射图形在所述衬底上的正投影内部。
本公开实施例中，可选的，每个所述像素具有一个发光层，发光层在所述衬底上的正投影与对应的像素的多个子阳极在所述衬底上的正投影均交叠，所述发光层在所述衬底上的正投影覆盖像素定义层的对应开口在所述衬底上 的正投影。
请参考图7，图7为本公开实施例的图2所示的有机发光显示基板的X处的剖面示意图，该有机发光显示基板包括：
衬底101；
设置于所述衬底101上的多个像素，多个所述像素沿第一方向排列构成像素行，多行像素行沿第二方向排列，所述第一方向和所述第二方向的夹角为80-100度，其中，每个所述像素包括：
设置于所述衬底101一侧的薄膜晶体管阵列层102；
设置于所述薄膜晶体管阵列层102远离所述衬底101一侧的平坦化层103；
设置于所述平坦化层103远离所述衬底101一侧的金属反射层；所述金属反射层包括多个相互分离的金属反射图形104，每个所述金属反射图形104对应一个所述像素；
设置于所述金属反射层远离所述衬底101一侧的第一钝化层105；
设置于所述第一钝化层105远离所述衬底101一侧的多个子阳极106，所述子阳极106为单层透明阳极，所述子阳极106通过贯通所述第一钝化层105和所述平坦化层103的阳极孔与薄膜晶体管阵列层102的源漏金属层走线连接；每个所述像素包括一列子阳极，所述一列子阳极包括多个沿第二方向排列的子阳极。每个所述像素的多个子阳极间隔设置，相邻的两个子阳极在所述衬底上的正投影的间距小于或等于第一预设阈值；所述第一预设阈值为3.5μm或者2μm；
设置于所述子阳极106远离所述衬底101一侧的像素定义层107；
设置于所述子阳极106远离所述衬底101一侧的发光层108；
设置于所述发光层108远离所述衬底101一侧的阴极(图未示出)；
本公开实施例中，子阳极106为单层透明阳极，不包括金属反射层，因而在制作时不会被金属反射层的曝光和刻蚀工艺所限，导致同一子像素中的相邻子阳极的间距过大，可以将同一像素中的相邻子阳极的间距控制在小于或等于第一预设阈值，从而将该有机发光显示基板应用3D显示时，可以减轻或消除摩尔纹的影响，提高显示效果。
请参考图8，图8为本公开实施例的图4所示的有机发光显示基板的Y 处的剖面示意图，该有机发光显示基板包括：
衬底101；
设置于所述衬底101上的多个像素，多个所述像素沿第一方向排列构成像素行，多行像素行沿第二方向排列，所述第一方向和所述第二方向的夹角为80-100度，其中，每个所述像素包括：
设置于所述衬底101一侧的薄膜晶体管阵列层102；
设置于所述薄膜晶体管阵列层102远离所述衬底101一侧的平坦化层103；
设置于所述平坦化层103远离所述衬底101一侧的金属反射层；所述金属反射层包括多个相互分离的金属反射图形104，每个所述金属反射图形104对应一个所述像素；
设置于所述金属反射层远离所述衬底101一侧的第一钝化层105；
设置于所述第一钝化层105远离所述衬底101一侧的多个子阳极106，所述子阳极106为单层透明阳极，所述子阳极106通过贯通所述第一钝化层105和所述平坦化层103的阳极孔与薄膜晶体管阵列层102的源漏金属层走线连接；每个所述像素包括两列子阳极，每列子阳极包括多个沿第二方向排列的子阳极，所述两列子阳极一列为左眼子阳极，一列为右眼子阳极，所述左眼子阳极对应的子像素发出的光用于形成左眼图像，所述右眼子阳极对应的子像素发出的光用于形成右眼图像。每个所述像素的多个子阳极间隔设置，相邻的两个子阳极在所述衬底上的正投影的间距小于或等于第一预设阈值；所述第一预设阈值为3.5μm或者2μm；
设置于所述子阳极106远离所述衬底101一侧的像素定义层107；
设置于所述子阳极106远离所述衬底101一侧的发光层108；
设置于所述发光层108远离所述衬底101一侧的阴极(图未示出)；
本公开实施例中，子阳极106为单层透明阳极，不包括金属反射层，因而在制作时不会被金属反射层的曝光和刻蚀工艺所限，导致同一子像素中的相邻子阳极的间距过大，可以将同一像素中的相邻子阳极的间距控制在小于或等于第一预设阈值，从而将该有机发光显示基板应用3D显示时，可以减轻或消除摩尔纹的影响，提高显示效果。
图7和图8所示的实施例中，可选的，所述薄膜晶体管阵列层102包括：
缓冲层1021；
设置于所述缓冲层1021远离所述衬底一侧的有源层1022；
设置于所述有源层1022上的第一栅绝缘层1023；
设置于所述第一栅绝缘层1023远离所述衬底一侧的第一栅金属层1024；
设置于所述第一栅金属层1024远离所述衬底一侧的第二栅绝缘层1025；
设置于所述第二栅绝缘层1025远离所述衬底一侧的第二栅金属层1026；
设置于所述第二栅金属层1026远离所述衬底一侧的层间介质层1027；
设置于所述层间介质层1027远离所述衬底一侧的第一源漏金属层1028；
设置于所述第一源漏金属层1028远离所述衬底一侧的第二钝化层1029；
设置于所述第二钝化层1029远离所述衬底一侧的第二源漏金属层1030，与子阳极连接的源漏金属层走线位于所述第二源漏金属层1030。
本公开实施例中，第一源漏金属层1028上方具有第二钝化层1029和平坦化层103，膜层顺序为第一源漏金属层1028-第二钝化层1029-第二源漏金属层1030-平坦化层103，在本公开的其他一些实施例中，第一源漏金属层1028上方也可以具有两层平坦化层，请参考图23，膜层顺序为第一源漏金属层1028-第二钝化层1029-平坦化层103’-第二源漏金属层1030-平坦化层103。
本公开实施例中的有机发光显示基板，具有两层栅金属层和两层源漏金属层，可以满足走线和电容需求。当然，在本公开的其他一些实施例中，也可以仅包括一层栅金属层，和/或，一层源漏金属层。
上述实施例中的薄膜晶体管为顶栅型薄膜晶体管，在本公开的其他一些实施例中，也可以为底栅型薄膜晶体管。
本公开实施例中的有机发光显示基板可以是OLED显示基板、miniLED显示基板或microLED显示基板、QLED显示基板等类型的显示基板。
本公开还提供一种显示装置，包括上述任一实施例中的有机发光显示基板和透镜，所述有机发光显示基板的发光层设置于所述透镜的焦面上，请参考图9。
本公开还提供一种有机发光显示基板的制作方法，包括：
步骤S1：提供衬底；
步骤S2：在所述衬底上形成金属反射层，所述金属反射层包括多个相互 分离的金属反射图形，
步骤S3：在所述金属反射层远离所述衬底的一侧形成绝缘层；
步骤S4：在所述绝缘层远离所述衬底的一侧形成多个像素，多个所述像素沿第一方向排列构成像素行，多行像素行沿第二方向排列，所述第一方向和所述第二方向的夹角为80-100度，每个所述像素包括多个子阳极；
其中，每个所述金属反射图形对应一个所述像素；每个所述金属反射图形在所述衬底上的正投影，与对应的所述像素的多个子阳极在所述衬底上的正投影交叠；
每个所述像素的多个子阳极间隔设置，相邻的两个子阳极在所述衬底上的正投影的间距小于或等于第一预设阈值，所述第一预设阈值为3.5μm或者2μm。
可选的，相邻的两个子阳极在所述衬底上的正投影的间距大于或等于第二预设阈值，所述第二预设阈值为0.5μm。
可选的，每个所述像素包括一列子阳极，所述一列子阳极包括多个沿第二方向排列的子阳极。
可选的，每个所述像素包括两列子阳极，每列子阳极包括多个沿第二方向排列的子阳极，所述两列子阳极一列为左眼子阳极，一列为右眼子阳极，所述左眼子阳极对应的子像素发出的光用于形成左眼图像，所述右眼子阳极对应的子像素发出的光用于形成右眼图像。
可选的，所述左眼子阳极在所述第一方向上的尺寸大于其在所述第二方向上的尺寸，所述右眼子阳极在所述第一方向上的尺寸大于其在所述第二方向上的尺寸。
可选的，在同一像素中的左眼子阳极列和右眼子阳极列在第二方向上错位排列。
可选的，同一像素中，左眼子阳极和右眼子阳极在沿第二方向延伸的直线上的正投影具有交叠。
可选的，同一像素中，左眼子阳极和右眼子阳极之间的最小距离小于左眼子阳极之间的最小距离，左眼子阳极和右眼子阳极之间的最小距离小于右眼子阳极之间的最小距离。
可选的，每列子阳极中，在第二方向上的边缘的2个子阳极在第二方向的尺寸大于其他子阳极在第二方向的尺寸。
可选的，所述方法还包括：
形成位于所述衬底和所述金属反射层之间的多个子像素电路，以及，位于所述金属反射层和所述子阳极所在层之间的绝缘层，所述绝缘层具有多个阳极孔，每个所述子阳极通过一个阳极孔连接对应的子像素电路。
可选的，每列子阳极对应多个阳极孔，所述多个阳极孔在第一方向上的位置不同。
可选的，每个子阳极在所述衬底上的正投影包括沿第一方向排列的第一边缘部分，中间部分和第二边缘部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的第一边缘部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的中间部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的第二边缘部分。
可选的，在所述衬底的正投影位于对应子阳极在所述衬底上的正投影的中间部分的阳极孔，其对应的子阳极位于对应像素在第二方向的边缘部分。
可选的，所述方法还包括：形成源漏金属层，所述源漏金属层包括多条走线，每个所述子阳极对应一条所述走线，所述子阳极通过阳极孔连接对应的所述走线，不同的所述子阳极对应的所述走线不接触，每个子阳极的阳极孔与其他子阳极的所述走线在所述衬底上的正投影均不交叠。
可选的，每个所述金属反射图形与对应的像素的多个子阳极对应的阳极孔在所述衬底上的正投影不交叠。
可选的，所述方法还包括：形成像素定义层，所述像素定义层包括与所述像素一一对应的多个开口，每个所述开口与对应的像素的多个子阳极在所述衬底上的正投影均交叠，每个所述开口的在所述衬底上的正投影位于对应的所述金属反射图形在所述衬底上的正投影内部。
可选的，每个所述像素具有一个发光层，发光层在所述衬底上的正投影与对应的像素的多个子阳极在所述衬底上的正投影均交叠，所述发光层在所述衬底上的正投影覆盖像素定义层的对应开口在所述衬底上的正投影。
可选的，每列子阳极包括沿第二方向排列的第一子阳极、第二子阳极、 第三子阳极和第四子阳极，每个所述像素包括2个子像素电路，其中一个子像素电路连接第一子阳极、第二子阳极、第三子阳极和第四子阳极中的其中两个子阳极，另一个子像素电路连接另外两个子阳极。
可选的，所述2个子像素电路中，一个子像素电路连接第一个子阳极和第三个子阳极，另一个子像素电路连接第二个子阳极和第四个子阳极，第一子阳极和第三子阳极对应的子像素发出的光用于形成左眼图像，第二子阳极和第四子阳极对应的子像素发出的光用于形成右眼图像，或者，第一子阳极和第三子阳极对应的子像素发出的光用于形成右眼图像，第二子阳极和第四子阳极对应的子像素发出的光用于形成左眼图像。
可选的，所述子像素电路包括：薄膜晶体管T1、薄膜晶体管T2、薄膜晶体管T3、薄膜晶体管T4、薄膜晶体管T5、薄膜晶体管T6、薄膜晶体管T7和电容C1；
其中，薄膜晶体管T1的栅电极连接第n-1条栅线，第一电极连接复位电压信号线，第二电极连接节点A；
薄膜晶体管T2的栅电极连接第n条栅线，第一电极连接数据线，第二电极连接节点B；
薄膜晶体管T3的栅电极连接节点A，第一电极连接节点B，第二电极连接节点C；
薄膜晶体管T4的栅电极连接第n条栅线，第一电极连接节点C，第二电极连接节点A；
薄膜晶体管T5的栅电极连接第一发光控制线，第一电极连接节点B，第二电极连接节点D；
薄膜晶体管T6的栅电极连接第二发光控制线，第一电极连接节点C，第二电极连接第一子阳极或第二子阳极；
薄膜晶体管T7的栅电极连接第三发光控制线，第一电极连接节点C，第二电极连接第三子阳极或第四子阳极；
电容C1的第一电极连接节点A，第二电极连接节点D；
节点D连接电源线，n为大于1的正整数。
请参考图10-图22，本公开一实施例的3D显示基板的制作方法包括：
步骤501：提供衬底101；
步骤502：在所述衬底101的一侧形成缓冲层1021；
缓冲层1021可为SiN或SiON或SiNx或SiO2或者任意两者或多者的叠层结构，在一实施例中，缓冲层1021为SiNx和SiO2的叠层结构，其中，SiNx厚度约为200-400nm，SiO2厚度约为400-600nm。
步骤503：在所述缓冲层1021远离所述衬底101的一侧形成有源层1022，并进行图形化；
有源层可以为多晶硅有源层，也可以为氧化物有源层，在一实施例中，有源层1022为多晶硅，厚度约为400-500nm。
步骤504：在所述有源层1022远离所述衬底101的一侧形成第一栅绝缘层1023；
第一栅绝缘层1023可为SiN或SiON或SiNx或SiO2或上述任意两者或多者的叠层结构，在一实施例中，第一栅绝缘层1023为SiO2和SiNx的叠层结构，其中，SiO2的厚度约为700-900nm，SiNx的厚度约为300-500nm；
步骤505：在所述第一栅绝缘层1023远离所述衬底101的一侧形成第一栅金属层1024，并进行图形化；
第一栅金属层1024可为Mo，Ti或Al等金属或上述任意两者或多者的合金，在一实施例中，第一栅金属层1024为Mo，厚度约为2500-3500nm。
步骤506：在所述第一栅金属层1024远离所述衬底101的一侧形成第二栅绝缘层1025，并进行图形化；
第二栅绝缘层1025可为SiN或SiON或SiNx或SiO2或上述任意两者或多者的叠层结构，在一实施例中，第二栅绝缘层1025为SiNx，厚度约为1000-2000nm；
步骤507：在所述第二栅绝缘层1025远离所述衬底101的一侧形成第二栅金属层1026，并进行图形化；
第二栅金属层1026可为Mo，Ti或Al等金属或上述任意两者或多者的合金，在一实施例中，第二栅金属层1026为Mo，厚度约为2500-3500nm。
步骤508：在所述第二栅金属层1026远离所述衬底101的一侧形成层间介质层1027；
层间介质层1027可为SiN或SiON或SiNx或SiO2或上述任意两者或多者的叠层结构，在一实施例中，层间介质层1027为SiO2和SiNx的叠层结构，SiO2的厚度约为1000-3000nm，若为SiNx厚度约为2000-4000nm；
步骤509：在所述层间介质层1027远离所述衬底101的一侧形成第一源漏金属层1028，并进行图形化；
第一源漏金属层1028可为Mo，Ti或Al等金属或上述任意两者或多者的叠层结构，在一实施例中，第一源漏金属层1028为Ti/Al/Ti叠层结构，厚度约为400-600nm/3000-5000nm/400-600nm。
步骤510：在所述第一源漏金属层1028远离所述衬底101的一侧形成第二钝化层1029，并进行图形化；
第二钝化层1029可为SiN或SiON或SiNx或SiO2或上述任意两者或多者的叠层结构；在一实施例中，第二钝化层1029为SiNx，厚度约为3000-4000nm。
步骤511：在所述第二钝化层1029远离所述衬底101的一侧形成第二源漏金属层1030，并进行图形化，所述第二源漏金属层1030包括源漏金属层走线；
第二源漏金属层1030可为Mo，Ti或Al等金属或上述任意两者或多者的叠层结构。在一实施例中，第二源漏金属层1030为Ti/Al/Ti叠层结构，厚度约为400-600nm/3000-5000nm/400-600nm。
步骤512：形成平坦化层103，并进行图形化。
所述平坦化层103可以采用光刻胶，厚度约为15000-25000nm。
步骤513：形成金属反射层，并进行图形化，形成多个相互分离的金属反射图形104，每个所述金属反射图形对应一个所述像素；
所述金属反射层可为Ag或Al等高反射率金属或其他在可见光区域具有高反射特性的材料。在一实施例中，金属反射层为Ag。
步骤514：形成第一钝化层105，并进行图形化；
第一钝化层105可为SiN或SiON或SiNx或SiO2或上述任意两者或多者的叠层结构；在一实施例中，第一钝化层105为SiNx。
在对第一钝化层105进行图形化的过程中，由于反射层104被第一钝化 层105覆盖，因而不会被氧化。同时，也不会对平坦化层造成刻蚀损伤。
步骤515：形成每个像素的多个子阳极106，每个所述像素的多个子阳极间隔设置，相邻的两个子阳极在所述衬底上的正投影的间距小于或等于第一预设阈值；所述第一预设阈值为3.5μm或者2μm。
子阳极106可以采用为低电阻、高功函数金属，例如Au或Pt，或金属氧化物，例如ITO、IZO等。在一实施例中，子阳极106为ITO。
步骤516：形成像素定义层107，并进行图形化。
像素定义层107可以采用光刻胶，厚度约为10000-15000nm。
步骤517：形成发光层和阴极的图形。
本公开实施例中，通过摩尔纹模拟实验，得到的显示装置的相邻的次像素的阳极的间距与摩尔纹水平的对应关系，见表1。
表1
Figure PCTCN2021074098-appb-000001
Figure PCTCN2021074098-appb-000002
从表1中可以看出，本公开实施例中，可以将左眼次像素和右眼次像素的阳极的间距从大于3.5调整到大于或等于0.5且小于或等于1.5μm的范围，可以实现摩尔纹水平小于10％，从而提高了显示效果。
上面结合附图对本公开的实施例进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本公开的保护之内。

Claims (22)

  1. 一种有机发光显示基板，其特征在于，包括衬底以及设置于所述衬底上的多个像素，多个所述像素沿第一方向排列构成像素行，多行像素行沿第二方向排列，所述第一方向和所述第二方向的夹角为80-100度，每个所述像素包括多个子阳极；
    所述有机发光显示基板还包括金属反射层，所述金属反射层位于所述衬底和所述多个子阳极所在层之间，所述金属反射层与所述多个子阳极所在层绝缘设置，所述金属反射层包括多个相互分离的金属反射图形，每个所述金属反射图形对应一个所述像素；每个所述金属反射图形在所述衬底上的正投影，与对应的所述像素的多个子阳极在所述衬底上的正投影交叠；
    每个所述像素的多个子阳极间隔设置，相邻的两个子阳极在所述衬底上的正投影的间距小于或等于第一预设阈值；所述第一预设阈值为3.5μm或者2μm。
  2. 如权利要求1所述的有机发光显示基板，其特征在于，相邻的两个子阳极在所述衬底上的正投影的间距大于或等于第二预设阈值，所述第二预设阈值为0.5μm。
  3. 如权利要求1所述的有机发光显示基板，其特征在于，每个所述像素包括一列子阳极，所述一列子阳极包括多个沿第二方向排列的子阳极。
  4. 如权利要求1所述的有机发光显示基板，其特征在于，每个所述像素包括两列子阳极，每列子阳极包括多个沿第二方向排列的子阳极，所述两列子阳极一列为左眼子阳极，一列为右眼子阳极，所述左眼子阳极对应的子像素发出的光用于形成左眼图像，所述右眼子阳极对应的子像素发出的光用于形成右眼图像。
  5. 如权利要求4所述的有机发光显示基板，其特征在于，所述左眼子阳极在所述第一方向上的尺寸大于其在所述第二方向上的尺寸，所述右眼子阳极在所述第一方向上的尺寸大于其在所述第二方向上的尺寸。
  6. 如权利要求4所述的有机发光显示基板，其特征在于，在同一像素中的左眼子阳极列和右眼子阳极列在第二方向上错位排列。
  7. 如权利要求4所述的有机发光显示基板，其特征在于，同一像素中，左眼子阳极和右眼子阳极在沿第二方向延伸的直线上的正投影具有交叠。
  8. 如权利要求4所述的有机发光显示基板，其特征在于，同一像素中，左眼子阳极和右眼子阳极之间的最小距离小于左眼子阳极之间的最小距离，左眼子阳极和右眼子阳极之间的最小距离小于右眼子阳极之间的最小距离。
  9. 如权利要求3或4所述的有机发光显示基板，其特征在于，每列子阳极中，在第二方向上的边缘的2个子阳极在第二方向的尺寸大于其他子阳极在第二方向的尺寸。
  10. 如权利要求3或4所述的有机发光显示基板，其特征在于，还包括位于所述衬底和所述金属反射层之间的多个子像素电路，以及，位于所述金属反射层和所述子阳极所在层之间的绝缘层，所述绝缘层具有多个阳极孔，每个所述子阳极通过一个阳极孔连接对应的子像素电路。
  11. 如权利要求10所述的有机发光显示基板，其特征在于，每列子阳极对应多个阳极孔，所述多个阳极孔在第一方向上的位置不同。
  12. 如权利要求11所述的有机发光显示基板，其特征在于，每个子阳极在所述衬底上的正投影包括沿第一方向排列的第一边缘部分，中间部分和第二边缘部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的第一边缘部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的中间部分，部分阳极孔在所述衬底的正投影位于对应子阳极在衬底上的正投影的第二边缘部分。
  13. 如权利要求12所述的有机发光显示基板，其特征在于，在所述衬底的正投影位于对应子阳极在所述衬底上的正投影的中间部分的阳极孔，其对应的子阳极位于对应像素在第二方向的边缘部分。
  14. 如权利要求10所述的有机发光显示基板，其特征在于，所述有机发光显示基板还包括源漏金属层，所述源漏金属层包括多条走线，每个所述子阳极对应一条所述走线，所述子阳极通过阳极孔连接对应的所述走线，不同的所述子阳极对应的所述走线不接触，每个子阳极的阳极孔与其他子阳极的所述走线在所述衬底上的正投影均不交叠。
  15. 如权利要求10所述的有机发光显示基板，其特征在于，每个所述金 属反射图形与对应的像素的多个子阳极对应的阳极孔在所述衬底上的正投影不交叠。
  16. 如权利要求1所述的有机发光显示基板，其特征在于，还包括像素定义层，所述像素定义层包括与所述像素一一对应的多个开口，每个所述开口与对应的像素的多个子阳极在所述衬底上的正投影均交叠，每个所述开口的在所述衬底上的正投影位于对应的所述金属反射图形在所述衬底上的正投影内部。
  17. 如权利要求16所述的有机发光显示基板，其特征在于，每个所述像素具有一个发光层，发光层在所述衬底上的正投影与对应的像素的多个子阳极在所述衬底上的正投影均交叠，所述发光层在所述衬底上的正投影覆盖像素定义层的对应开口在所述衬底上的正投影。
  18. 如权利要求10所述的有机发光显示基板，其特征在于，每列子阳极包括沿第二方向排列的第一子阳极、第二子阳极、第三子阳极和第四子阳极，每个所述像素包括2个子像素电路，其中一个子像素电路连接第一子阳极、第二子阳极、第三子阳极和第四子阳极中的其中两个子阳极，另一个子像素电路连接另外两个子阳极。
  19. 如权利要求18所述的有机发光显示基板，其特征在于，
    所述2个子像素电路中，一个子像素电路连接第一个子阳极和第三个子阳极，另一个子像素电路连接第二个子阳极和第四个子阳极，第一子阳极和第三子阳极对应的子像素发出的光用于形成左眼图像，第二子阳极和第四子阳极对应的子像素发出的光用于形成右眼图像，或者，第一子阳极和第三子阳极对应的子像素发出的光用于形成右眼图像，第二子阳极和第四子阳极对应的子像素发出的光用于形成左眼图像。
  20. 如权利要求18所述的有机发光显示基板，其特征在于，所述子像素电路包括：薄膜晶体管T1、薄膜晶体管T2、薄膜晶体管T3、薄膜晶体管T4、薄膜晶体管T5、薄膜晶体管T6、薄膜晶体管T7和电容C1；
    其中，薄膜晶体管T1的栅电极连接第n-1条栅线，第一电极连接复位电压信号线，第二电极连接节点A；
    薄膜晶体管T2的栅电极连接第n条栅线，第一电极连接数据线，第二电 极连接节点B；
    薄膜晶体管T3的栅电极连接节点A，第一电极连接节点B，第二电极连接节点C；
    薄膜晶体管T4的栅电极连接第n条栅线，第一电极连接节点C，第二电极连接节点A；
    薄膜晶体管T5的栅电极连接第一发光控制线，第一电极连接节点B，第二电极连接节点D；
    薄膜晶体管T6的栅电极连接第二发光控制线，第一电极连接节点C，第二电极连接第一子阳极或第二子阳极；
    薄膜晶体管T7的栅电极连接第三发光控制线，第一电极连接节点C，第二电极连接第三子阳极或第四子阳极；
    电容C1的第一电极连接节点A，第二电极连接节点D；
    节点D连接电源线，n为大于1的正整数。
  21. 一种显示装置，其特征在于，包括如权利要求1-20任一项所述的有机发光显示基板。
  22. 一种有机发光显示基板的制作方法，其特征在于，包括：
    提供衬底；
    在所述衬底上形成金属反射层，所述金属反射层包括多个相互分离的金属反射图形，
    在所述金属反射层远离所述衬底的一侧形成绝缘层；
    在所述绝缘层远离所述衬底的一侧形成多个像素，多个所述像素沿第一方向排列构成像素行，多行像素行沿第二方向排列，所述第一方向和所述第二方向的夹角为80-100度，每个所述像素包括多个子阳极；
    其中，每个所述金属反射图形对应一个所述像素；每个所述金属反射图形在所述衬底上的正投影，与对应的所述像素的多个子阳极在所述衬底上的正投影交叠；
    每个所述像素的多个子阳极间隔设置，相邻的两个子阳极在所述衬底上的正投影的间距小于或等于第一预设阈值，所述第一预设阈值为3.5μm或者2μm。
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