WO2022158122A1 - Procédé de liaison et procédé d'utilisation de dispositif de liaison - Google Patents

Procédé de liaison et procédé d'utilisation de dispositif de liaison Download PDF

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Publication number
WO2022158122A1
WO2022158122A1 PCT/JP2021/043808 JP2021043808W WO2022158122A1 WO 2022158122 A1 WO2022158122 A1 WO 2022158122A1 JP 2021043808 W JP2021043808 W JP 2021043808W WO 2022158122 A1 WO2022158122 A1 WO 2022158122A1
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Prior art keywords
bonding
chip
substrate
recognition
collet
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PCT/JP2021/043808
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English (en)
Japanese (ja)
Inventor
信裕 永元
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キヤノンマシナリー株式会社
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Publication of WO2022158122A1 publication Critical patent/WO2022158122A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation

Definitions

  • the present invention relates to a bonding method and a method of using a bonding apparatus, and more particularly to a method of manufacturing a board-on-chip (BOC) type electronic component (semiconductor device) and a method of using a bonding apparatus.
  • BOC board-on-chip
  • Some electronic components are of the BOC (Board on Chip) type. That is, there is a semiconductor package shown in FIG. 9 as a BOC type electronic component.
  • the semiconductor package includes a substrate 1 having one surface serving as a pattern forming surface 1a and the other surface serving as a chip bonding surface 1b.
  • a wire 5 connects a substrate-side electrode on the surface 1a and a chip-side electrode of the chip 4 bonded to the chip bonding surface 1b.
  • 6 is a solder ball formed on the pattern forming surface 1a
  • 7 is an adhesive layer for bonding the chip bonding surface 1b of the substrate 1 and the chip 4 together.
  • the chip 4 and the wire 5 are sealed with the sealing body 8 .
  • the chip 4 with the electrodes on the chip 4 side (chip-side electrodes) facing upward. is placed on the upper surface of the moving stage 10, the moving stage 10 is moved below the substrate 1, and the chip 4 is brought into contact with the chip bonding surface 1b (here, the lower surface) on the opposite side of the pattern forming surface 1a of the substrate 1 from below. (Arrow A shown in the figure), then the substrate 1 is pressed against the chip 4 on the moving stage 10 by a thermocompression bonding tool 11 from above the substrate 1 (Arrow B shown in the figure), and the chip 4 is bonded to the substrate 1.
  • a thermocompression bonding tool 11 from above the substrate 1
  • the pattern formation surface 1a on the substrate 1 side and the electrode formation surface 4a on the chip 4 side are respectively viewed from above by a camera (the substrate side recognition camera 12 for recognizing the pattern formation surface 1a on the substrate 1 side and the chip 4). Since it can be recognized by a chip-side recognition camera 13) that recognizes the side electrode forming surface 4a, the chip 4 is aligned with the substrate 1.
  • FIG. Reference numeral 14 in FIG. 8 denotes a substrate-side pattern (substrate-side electrode portion) on the pattern forming surface 1a.
  • Patent Document 1 a die bonding apparatus and a die bonding method that can perform a die bonding process for BOC type electronic components by using a conventional die bonding apparatus.
  • the die bonding apparatus (method) described in Patent Document 1 is for bonding the chip with the chip bonding surface (surface opposite to the pattern forming surface) of the substrate facing upward.
  • the chips are picked up from the wafer by an inversion tool, and the picked up chips are inverted by the inversion tool.
  • the electrode formation surface of the chip faces downward.
  • a transfer tool is used to suck the opposite electrode forming surface of the chip from above. In this state, the electrode formation surface of the chip faces downward. Therefore, the electrode forming surface of the chip can be bonded from above to the chip bonding surface (surface opposite to the pattern forming surface) of the substrate facing upward.
  • Patent Document 1 the pattern formation surface of the substrate (the surface facing downward) is observed with a camera placed above. That is, a mirror member is provided through a transparent member on a substrate mounting table on which a substrate is mounted, and a reflected image reflected on the mirror surface of this mirror member is viewed. In this case, the reflected image is projected on the mirror surface through the wire insertion hole provided in the substrate and the transparent member.
  • the substrate and the chip are aligned based on the position of the pattern on the substrate side of the reflected image, and the electrode forming surface of the chip is bonded to the chip bonding surface of the substrate.
  • Patent Document 1 uses a reflected image.
  • a reflected image When a reflected image is used, the observation range is limited because the wire insertion hole and the transparent member are interposed, and if the mirror surface is of poor precision, an accurate reflected image cannot be obtained. be.
  • the acquisition of the reflected image is the part where the substrate is heated, the gas generated when the adhesive melts accumulates on the mirror, causing the mirror to become cloudy, and the image acquisition is unstable.
  • the apparatus of Patent Document 1 requires a substrate mounting table provided with a transparent member and a mirror member, and the members (the substrate mounting table provided with the transparent member and the mirror member) that must be formed with high precision as the entire apparatus are required.
  • the substrate mounting table provided with the transparent member and the mirror member must be replaced, resulting in poor productivity.
  • the present invention provides a bonding method and a method of using a bonding apparatus that enable stable alignment and that can use an existing bonding apparatus as the apparatus to be used.
  • a substrate having a wire insertion hole penetrating in the thickness direction and having a positioning reference mark formed on the pattern forming surface side is transported from the upstream side to the downstream side along the substrate transport path. and bonding the electrode forming surface of the chip to the chip bonding portion of the chip bonding surface on the opposite side of the substrate-side electrode portion of the pattern forming surface of the substrate at a bonding position on the downstream side of the substrate transport path, comprising: A substrate recognizing step of recognizing the positional relationship between the positioning reference mark and the wire insertion hole seen from below on the upstream side of the substrate conveying path, with the pattern forming surface of the substrate facing downward, and a pick-up collet.
  • a pick-up process for picking up the chip a reversing process for reversing the chip picked up by the pick-up side collet and directing the electrode forming surface downward, and a bonding side collet with the electrode forming surface facing downward for the chip reversed in the reversing process.
  • the chip received in the receiving step is attached to the chip bonding portion of the substrate aligned in the alignment step. and a bonding step of bonding to the bonding portion.
  • the positional relationship between the positioning reference marks and the wire insertion holes can be recognized based on the direct image of the pattern forming surface viewed from below in the substrate recognition process.
  • a chip can be picked up in the pick-up process, and the picked-up chip can be brought into a state in which the chip electrode forming surface faces downward in the reversing process.
  • the chip In the receiving process, the chip can be received by the bonding-side collet with the electrode-formed surface facing downward.
  • alignment process alignment can be performed based on the positional relationship between the positioning reference marks and the wire insertion holes, and recognition of the position of the wire insertion holes from above the bonding position.
  • the chip received in the receiving step can be bonded to the chip bonding portion of the substrate aligned in the alignment step.
  • the pattern formation surface of the substrate facing downward can be observed from below the substrate. Therefore, since the observation surface is not an indirect image, the observation field is not restricted, and the positional relationship between the positioning reference mark and the wire insertion hole can be observed stably and with high accuracy. Moreover, since this image observation is performed on the upstream side of the substrate transport path, which is a portion that is not heated, heating means (for example, an electric heater provided on the backup plate) is used in the substrate recognition process on the downstream side of the substrate transport path. It can be placed without being obstructed by a camera or the like.
  • heating means for example, an electric heater provided on the backup plate
  • the substrate recognition part and the substrate heating part can be arranged at separate positions, and the influence of the substrate heating on the substrate recognition part (the influence of the gas generated when the adhesive melts, etc. on the optical system, etc.)
  • the substrate heating portion the wire insertion hole of the substrate is recognized from above, but the substrate is not recognized at a close position, so that the substrate can be continuously heated.
  • the bonding process for bonding the chip can be performed from above the substrate, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used.
  • alignment is performed based on recognition of the positional relationship between the positioning reference mark and the wire insertion hole at a position on the upstream side away from the bonding position and recognition of the position of the wire insertion hole from above the bonding position.
  • high-precision alignment is possible. That is, since the positional relationship between the reference marks and the electrodes on the pattern formation surface is set with high accuracy, the positions of the wire insertion holes can be confirmed by confirming the positions of the wire insertion holes from the bonding surface side of the chip (the side opposite to the pattern formation surface).
  • the position of the electrode (substrate-side electrode portion) on the pattern forming surface can be detected, thereby enabling accurate bonding and bonding to the chip bonding portion on the chip bonding surface side of the substrate.
  • the chip joint portion is a portion corresponding to the substrate-side electrode portion.
  • a chip recognition process for recognizing the chip position before bonding may be provided. In this way, the alignment accuracy can be improved with the chip recognition process.
  • the substrate may be received by a backup plate from below.
  • the chip can be sandwiched between the bonding-side collet and the backup plate when the chip is bonded to the chip bonding surface of the substrate. A stable bond can be obtained.
  • this backup plate can be configured to be heated by a heating means to heat the adhesive on the substrate. This configuration eliminates the need to provide the heating means as a separate member, which contributes to downsizing of the entire apparatus.
  • the board recognition process acquire position information for one board.
  • the bonding process can be performed to continuously bond chips to all the chip bonding portions of one substrate, thereby improving productivity.
  • a chip is picked up by a pickup-side collet at a pickup position, the chip picked up at the pickup position is reversed, and the reversed chip is bonded at a bonding position by a bonding-side collet.
  • a method of using a bonding apparatus, wherein the bonding method can be performed.
  • the method of using the bonding apparatus of the present invention can use an existing general-purpose bonding apparatus, and can reduce costs.
  • the patterned surface since the observation of the patterned surface is not an indirect image, the field of view for observation is not restricted, the patterned surface can be observed stably and with high precision, and the chip is stably bonded to the substrate with high precision. be able to. In addition, the chip can be bonded to the substrate at low cost without complicating the device configuration. Furthermore, the bonding process for bonding the chip can be performed from above the substrate, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used.
  • FIG. 1 is a simplified perspective view of a bonding apparatus used in the bonding method of the present invention
  • FIG. 2 is an enlarged schematic view of a main part of a pattern formation surface of a substrate
  • FIG. 4 is a simplified diagram of a chip bonding portion of a chip bonding surface
  • FIG. 4 is a simplified diagram showing a substrate and a state in which an adhesive is applied to a chip bonding portion of a chip bonding surface
  • FIG. 3 is a simplified plan view showing a transport mechanism for substrates
  • 1 is a block diagram of the bonding method of the present invention
  • FIG. It is a block diagram which shows the process of the first half of the bonding method of this invention.
  • FIG. 1 is a cross-sectional view of a semiconductor device (BOC type semiconductor package); FIG.
  • FIG. 1 An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.
  • FIG. 1 An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.
  • FIG. 1 shows a bonding apparatus used for the bonding method according to the present invention.
  • This bonding apparatus can perform a bonding method of bonding the electrode forming surface 32a of the chip 32 to the chip bonding portion 34 of the chip bonding surface 31b on the opposite side of the substrate-side electrode portion 38 of the pattern forming surface 31a of the substrate 31. .
  • the substrate 31 is provided with a plurality of wire insertion holes 33 which are elongated holes extending in the width direction of the substrate.
  • a plurality of wire insertion holes 33 are arranged along the substrate width direction to constitute a wire insertion hole group 35, and the plurality of wire insertion hole groups 35 are arranged at a predetermined pitch along the substrate longitudinal direction. ing.
  • a substrate-side pattern (substrate-side electrode portion) 38 having substrate-side electrodes 36 and pads 37 provided on both sides of the wire insertion hole 33 is formed on the side of the pattern forming surface 31a of the substrate 31, a substrate-side pattern (substrate-side electrode portion) 38 having substrate-side electrodes 36 and pads 37 provided on both sides of the wire insertion hole 33 is formed.
  • an adhesive S is applied (applied) to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31 (the surface opposite to the pattern forming surface 31a).
  • a pair of adhesives S, S are applied to one wire insertion hole 33 with the wire insertion hole 33 interposed therebetween.
  • the adhesive S may be a paste adhesive or a die attach film (DAF).
  • a positioning reference mark 40 (see FIG. 3A) is formed on the pattern formation surface 31a of the substrate 31.
  • the positioning reference marks 40 (hereinafter sometimes simply referred to as reference marks 40) are formed at corners of a metal film formed on the pattern forming surface 31a of the substrate 31.
  • the reference mark 40 is not limited to this, and may be a mark such as a specially provided colored mark or an uneven portion.
  • the substrate 31 is transported along the direction of the arrow X in FIG. 1 by substrate transport means 41 as shown in FIG.
  • the substrate conveying means 41 has a pair of conveying rails 42, 42, and the substrate 31 placed on the conveying rails 42, 42 has a grasping mechanism (for example, a chuck mechanism, etc.) (not shown).
  • the sheet is conveyed from the upstream side to the downstream side along the arrow X direction by the feeding mechanism.
  • a backup plate (adapter plate) 43 is arranged between the transport rails 42, 42 below the bonding position (bonding position) on the downstream side of the transport path of the substrate 31.
  • the backup plate 43 can be heated by heating means (not shown). That is, by heating the backup plate 43, the adhesive S on the chip bonding surface 31b corresponding to the bonding position on the substrate 31 can be heated.
  • Various electric heating methods can be used as heating means (not shown).
  • the central portion in the substrate conveying direction can heat the substrate 31 to a temperature at which the adhesive S during bonding can be melted and effective bonding force can be exhibited.
  • the bonding temperature zone can correspond to the bonding position, and when the chip bonding portion 34 of the substrate 31 is positioned at the bonding position, the chip bonding portion 34 of the substrate 31 can be S can be heated to a temperature at which effective bonding strength can be exhibited.
  • the chip bonding portion 34 of the substrate 31 passes through the low-temperature heating zone before being positioned at the bonding position, the chip bonding portion 34 of the substrate 31 can be preheated, thereby improving working efficiency. be able to.
  • This bonding apparatus also includes a pickup mechanism 50 for picking up a chip 32 as a workpiece, and a bonding mechanism for bonding the chip 32 picked up by the pickup mechanism 50 to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31.
  • a mechanism 51 and observation means 53 for observing the pattern formation surface 31a on the back side of the substrate 31 from below are provided on the upstream side of the substrate transport path.
  • the chip 32 is made from a wafer material, and cut into a rectangular shape to form the final product. For this reason, the chip 32 may be square, strip-shaped, or the like. That is, the wafer is generally circular and is divided into individual chips 32 by dicing.
  • the pickup mechanism 50 has a pickup head 56 with a pickup arm 55 attached to the tip side, and a collet 57 is attached to the tip of the pickup arm 55 .
  • a plurality of suction holes (not shown) that open to the tip surface of the collet 57 are provided on the tip surface of the collet 57 , and the tip 32 is vacuum-sucked through the suction holes, and the tip 32 is attached to the tip surface of the collet 57 .
  • the chip 32 is removed from the collet 57 when the vacuum suction (vacuum drawing) is released.
  • vacuum suction vacuum drawing
  • a vacuum mechanism As the vacuum mechanism, a vacuum pump, a vacuum ejector, or the like is used.
  • the pickup head 56 has a reversing mechanism 58 that can reverse the collet 57 at the tip of the pickup arm 55 .
  • the reversing mechanism 58 has a drive mechanism (for example, a motor, etc.) that rotates the pickup head 56 around its axis. It is possible to change the attitude between the posture and the posture in which the tip end surface, which is the suction surface of the collet 57, faces upward.
  • the pickup head 56 of the pickup mechanism 50 can be vertically moved as indicated by arrows Z1 and Z2 by a vertical movement mechanism (not shown).
  • the vertical movement mechanism can be composed of various reciprocating mechanisms such as a cylinder mechanism, a ball screw mechanism, and a linear motor mechanism.
  • the bonding mechanism 51 has a bonding head 60 and a collet 62 attached to the tip of a bonding arm 61 .
  • a plurality of suction holes (not shown) that open to the tip surface are provided on the lower surface (tip surface) of the collet 62 , and the tip 32 is vacuum-sucked through the suction holes. be done.
  • the chip 32 is removed from the collet 62 when the vacuum suction (vacuum drawing) is released. Further, vacuum suction (vacuum drawing) is performed by a vacuum mechanism (not shown).
  • a vacuum pump, a vacuum ejector, or the like is used as the vacuum mechanism.
  • the bonding head 60 can be moved in the longitudinal direction of the substrate 31 in the directions of arrows X1 and X2, in the direction of arrows A and B in the width direction, and in the direction of arrows C and D in the vertical direction through a moving mechanism (not shown).
  • a moving mechanism various reciprocating mechanisms such as a cylinder mechanism, a ball screw mechanism, and a linear motor mechanism can be used.
  • the observation means 53 includes a camera mechanism 65 arranged below the upstream side of the substrate transport path. That is, the camera mechanism 65 includes a camera body 66 composed of an image recognition camera (for example, a CCD camera, a CMOS camera, etc.) and an optical system 67 that forms the image field of the camera body 66 .
  • the optical system 67 includes a mirror member 68 for allowing the image of the pattern forming surface 31 a of the substrate in a predetermined field of view to enter the camera body 66 .
  • the observation field of view of the observation means 53 is a range indicated by a two-dot chain line.
  • an insertion hole recognizing means 71 for recognizing the wire insertion holes 33 of the substrate 31 is provided above the bonding position of the chip 32 .
  • a first chip recognizing means 72 for confirming the chip 32 in an inverted state after being picked up by the pickup mechanism 50 is arranged, and on the bonding mechanism 51 side, A second chip recognition means 73 is provided for recognizing the chip 32 sucked and held by the bonding collet 62 .
  • the insertion hole recognizing means 71 and the first chip recognizing means 72 can be configured with a CCD camera, a CMOS camera, or the like.
  • the second chip recognition means 73 also includes a camera body 74 consisting of an image recognition camera (for example, a CCD camera, a CMOS camera, etc.) and an optical system 75 that forms the image field of the camera body 74 .
  • the optical system 75 in this case includes a mirror member 76 for making the image of the chip 32 enter the camera body 74 .
  • position recognition of the chip 32 before bonding is performed, that is, chip recognition steps 87 and 88, which will be described later, are performed. can be done. That is, the first chip recognition means 72 recognizes the position of the chip 32 sucked by the pick-up collet 57, and the second chip recognition means 73 recognizes the position of the chip 32 sucked by the bonding collet 62. will do. These positional recognitions are used for alignment when bonding the chip 32 .
  • the substrate transport means 41, the pick-up mechanism 50, and the bonding mechanism 51 are controlled by a computer (not shown).
  • the computer basically comprises input means with an input function, output means with an output function, storage means with a storage function, and arithmetic means with an arithmetic function. It is composed of control means having a control function.
  • the input function is for reading information from the outside into the computer, and the read data and programs are converted into signals in a format suitable for the computer system.
  • the output function is to display the calculation results, stored data, etc. to the outside.
  • the storage means stores and saves programs, data, processing results, and the like. Arithmetic functions process data by performing calculations and comparisons according to program instructions.
  • the control function interprets the instructions of the program and issues instructions to each means, and this control function controls all the means of the computer.
  • Input means include keyboards, mice, tablets, microphones, joysticks, scanners, capture boards, and the like.
  • Output means include a monitor, a speaker, a printer, and the like.
  • Storage means include memory, hard disk, CD/CD-R, PD/MO, and the like.
  • the calculation means includes a CPU and the like, and the control means includes a CPU, a motherboard, and the like.
  • the electrode forming surface 32a of the chip 32 is attached to the chip bonding portion 34 of the chip bonding surface 31b on the opposite side of the substrate-side electrode portion 38 of the pattern forming surface 31a of the substrate 31.
  • a bonding method for joining will be described.
  • the chip joint portion 34 corresponds to the opposite surface of the board-side electrode portion 38 .
  • This bonding method includes a substrate recognition process 81, a pick-up process 82, an inversion process 83, a receiving process 84, an alignment process 85, and a bonding process 86, as shown in FIG.
  • a first chip recognition process 87 is provided between the reversing process 83 and the receiving process 84
  • a second chip recognition process 88 is provided between the receiving process 84 and the alignment process 85. be done.
  • the position of the substrate-side pattern on the pattern forming surface 31a is recognized based on a direct image of the pattern forming surface 31a from below, with the pattern forming surface 31a of the substrate 31 facing downward. It is a process of performing
  • a pick-up step 82 is a step of picking up the chip 32 via the pick-up collet 57 .
  • the reversing step 83 is a step of reversing the chip 32 picked up by the pickup-side collet 57 so that the electrode forming surface 32a faces downward.
  • the receiving step 84 is a step of receiving the chip 32 reversed in the reversing step 83 with the bonding side collet 62 with the electrode forming surface 32a facing downward.
  • the alignment step 85 aligns the substrate 31 with the chip 32 received in the receiving step 84 based on the position of the substrate-side pattern (substrate-side electrode portion 38 ) on the pattern forming surface 31 a recognized in the recognition step 81 . It is a process of performing
  • the bonding step 86 is a step of bonding the chip 32 aligned with the substrate 31 in the alignment step to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31 with the bonding-side collet.
  • the first chip recognizing step 87 is a step of observing from above the chip 32 attracted to the pick-up side collet 57 by the first chip recognizing means 72 with the counter-chip side electrode facing upward.
  • the bonding side collet 62 is detected by the second chip recognition means 73 . This is a step of observing from below the chip 32 sucked with the electrode forming surface 32a facing downward.
  • the substrate is placed on the upstream side of the substrate transport path with the pattern forming surface 31a facing downward.
  • the substrate recognition step 81 that is, substrate recognition is performed (step S1).
  • the position of the wire insertion hole 33 is recognized based on the reference mark provided on the pattern forming surface 31a.
  • the positional information of the chip joint portion 34 on one substrate 31 is acquired. That is, the positions of all wire insertion holes 33 are confirmed. This position information is stored in the storage means of the computer.
  • step S2 the pick-up process by the pick-up mechanism 50, that is, the chip 32 is picked up at the pick-up position (step S2). That is, the pickup-side collet 57 located above the pickup position is lowered as indicated by arrow Z1 in FIG. Raise 57. Thereby, the chip 32 can be picked up.
  • the reversing process 83 is performed. That is, in the pickup mechanism 50, the tip 32 is inverted by inverting the pickup head 56 by 180° (step S3). In this case, it may be clockwise or counterclockwise. In this case, the electrode formation surface 32a of the chip 32 faces downward.
  • step S4 determines whether or not to recognize the position of the tip 32. If it is determined in step S4 that the position is not recognized, the process proceeds to step S5 to perform a receiving process for receiving the inverted chip 32. FIG. If it is determined in step S4 that the position should be recognized, the process proceeds to step S6 to recognize the position of the tip 32. FIG. That is, the chip 32 is imaged by the first chip recognition means 72 and the position of the chip 32 is confirmed.
  • step S5 the inverted chip 32 is received by the bonding mechanism 51. That is, the bonding-side collet 62 is positioned above the inverted chip 32 and the chip 32 is sucked to this collet 62 . At this time, the suction of the pickup-side collet 57 is released. As a result, the chip 32 is attracted to the attraction surface, which is the lower surface of the bonding-side collet 62 . In this case, the electrode forming surface 32a of the chip 32 faces downward.
  • step S7 it is determined whether the position of the chip 32 should be confirmed. If the position is not to be confirmed in step S7, the process proceeds to step S8. If the position is to be confirmed in step S7, the process proceeds to step S9, the position is confirmed, and then the process proceeds to step S8.
  • step S7 the chip 32 is imaged by the second chip recognition means 73 and the position of the chip 32 is confirmed.
  • step S8 the substrate 31 and the chip 32 are aligned.
  • the substrate 31 is transported from the upstream side to the downstream side of the substrate transport path by the substrate transport means 41 so that the chip bonding portion 34 of the substrate 31 to which the chip 34 is to be bonded is positioned above the bonding position. .
  • step S8 based on the relationship between the reference marks 40 on the pattern forming surface 31a of the substrate 31 and the wire insertion holes 33 and the position recognition of the wire insertion holes 33 confirmed by the insertion hole recognition means 71, the chip 32 and the wire insertion hole 33 are detected. Alignment with the chip joint portion 34 is performed. In this case, the wire insertion hole 33 of the chip bonding portion to which the chip 32 is to be bonded is recognized by the insertion hole recognizing means 71 . Then, the positional relationship between the recorded reference mark 40 and the wire insertion hole 33 is compared with the wire insertion hole 33 of the chip joint 34 recognized by the insertion hole recognition means 71 .
  • the positional deviation (by the recognition means 71)
  • the positional deviation between the recognized wire insertion hole 33 and the reference mark 40 occurs, and the wire insertion hole 33 recognized by the recognition means 71 is detected by the board based on the amount of positional deviation recognized by the recognition means 71 . It is necessary to align the reference mark 40 of 31 with the electrode position of the tip 32 (or the outer shape position of the tip 32). It should be noted that there may be a case where the position is not shifted. If there is no misalignment, there is no need to perform alignment.
  • the position of the chip 32 can be recognized before bonding in the first and second chip recognition processes 87 and 88, the position of the chip 32 before bonding detected in the chip recognition processes 87 and 88 can be detected. can be used for this alignment.
  • This enables more precise alignment. That is, the positional information of the chip 32 obtained in the first and second chip recognition steps 87 and 88 is inputted to the computer, and positional alignment is performed by calculating the positional deviation including this information.
  • the positional deviation there are cases of positional deviation in the longitudinal direction of the substrate 31, cases of positional deviation in the width direction of the substrate 31, and cases of positional deviation in the longitudinal direction and the width direction. If the position is shifted in the longitudinal direction, the position of the bonding side collet 62 is displaced in the directions of arrows X1 and X2; if the position is shifted in the width direction, the position of the bonding side collet 62 is displaced in the directions of arrows A and B; If the position is shifted in the longitudinal direction and the width direction, the position of the bonding side collet 62 may be displaced in the directions of arrows X1, X2, A and B.
  • step S10 the chips 32 are bonded in the aligned state.
  • the bonding-side collet 62 receiving the chip 32 from the pickup-side collet 57 is lifted as indicated by arrow C, and then moved to above the chip bonding portion as indicated by arrow A. , and then the bonding side collet 62 is lowered for bonding.
  • the alignment can be performed while the bonding-side collet 62 is operating. However, the alignment is performed after the position of the chip 34, which is being sucked by the collet 57 and inverted, has been confirmed. Alternatively, alignment may be performed after confirming the position of the tip 34 sucked by the collet 62 .
  • the backup plate 43 is heated to a temperature at which the adhesive can be bonded. Therefore, the collet 62 is lowered, and the substrate 31 is sandwiched between the collet 62 and the backup plate 43, and the chip 32 is joined with the adhesive S. FIG.
  • the electrode forming surface 32a of the chip 32 is accurately bonded to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31 by the alignment process. can be done.
  • step S11 determines whether or not to end this process (work). If it is determined to end, the process ends, and if it is determined not to end in step S10, the process returns to step S2.
  • chips can be bonded to all the chip bonding portions of one substrate 31 by performing the steps from step S2 to step S10.
  • the pattern formation surface 31a of the substrate 31 facing downward can be observed from below the substrate 31. Therefore, since the observation of the pattern-formed surface 31a is not an indirect image, the observation field of view is not restricted, and the pattern-formed surface 31a can be observed stably and with high accuracy. Moreover, since this image observation is performed on the upstream side of the substrate transport path, which is a portion that is not heated, the heating means (for example, the heating means provided on the backup plate) is placed downstream of the substrate transport path in the substrate recognition process. It can be arranged without being obstructed by the camera or the like used.
  • the board recognition part and the board heating part can be arranged at separate positions, and the positional relationship between the positioning reference mark 40 and the wire insertion hole 33 can be recognized in a place where the board 31 is not heated. Therefore, the substrate recognition portion is not affected by the heating of the substrate (such as the influence of the gas generated when the adhesive melts on the optical system, etc.).
  • recognition is performed (recognition by the insertion hole recognition means 71 as the recognition portion in FIG. 1), since board recognition is not performed at a close position, continuous heating of the board 31 is possible.
  • the bonding process 86 for bonding the chip 32 can be performed from above the substrate 31, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used.
  • the adhesive S for bonding the chip 32 and the chip bonding surface 31b of the substrate 31 is disposed on the chip bonding surface 31b facing upward, it is relatively fluid. There is no danger of it falling down even if you have it. Therefore, the application work of the adhesive S is easy, and various kinds of adhesives can be used as the adhesive S, which contributes to cost reduction.
  • the pattern-formed surface 31a since the observation of the pattern-formed surface 31a is not an indirect image, the observation field of view is not restricted, the pattern-formed surface 31a can be observed stably and accurately, and the bonding of the chip 32 to the substrate 31 can be performed with high accuracy. can be done stably.
  • the chip 32 can be bonded to the substrate 31 at low cost without complicating the device configuration.
  • the bonding process 86 for bonding the chip 32 can be performed from above the substrate 31, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used. Moreover, continuous heating of the substrate 31 is possible, and the productivity is excellent.
  • the positioning process can be performed stably. That is, since the positional relationship between the position of the positioning reference mark 40 and the position of the electrode on the pattern forming surface 31a of the substrate 31 is highly accurate, the positioning step 85 can be stably performed.
  • chip recognition processes 87 and 88 for recognizing the position of the chip 32 before bonding. As described above, the chip recognition processes 87 and 88 can improve the alignment accuracy.
  • the substrate 31 is received by the backup plate 43 from below, so when the chip 32 is bonded to the chip bonding surface 31b of the substrate 31, the chip 32 can be sandwiched between the collet 62 and the backup plate 43.
  • stable bonding can be obtained without bending the substrate 31 or the like.
  • An existing general-purpose bonding apparatus can be used as each component of the bonding apparatus used in the bonding method of the present invention, and cost reduction can be achieved.
  • the present invention is not limited to the above embodiments, and various modifications are possible.
  • the bonding side collet 62 may be heated.
  • the heating means may be provided only on the side, the heating means may be provided only on the backup plate 43 side, or the heating means may be provided on the collet 62 side and the backup plate 43 side.
  • the backup plate 43 may not be provided, and in such a case, a separate heating means is provided below the bonding position.
  • Various electric heating can be used as each heating means in this case.
  • the first chip recognition means 72 and the second chip recognition means 73 are used to confirm the positions of the chips before bonding, but either one of the chip recognition means may be used. .
  • the camera body 66 is arranged along the horizontal direction, but the camera body 66 may face the vertical direction.
  • the process of performing board recognition of step S1 is followed by the process of picking up the chip 32 of step S2.
  • the substrate and the chip may be aligned in step S8 after transporting. That is, the chip and the chip bonding portion are aligned based on the positional relationship between the positioning reference mark and the wire insertion hole and the recognition of the position of the wire insertion hole from above the bonding position.
  • This bonding method and this bonding apparatus usage method are for manufacturing a board-on-chip (BOC) type electronic component (semiconductor device).
  • BOC board-on-chip

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

Dans ce procédé de liaison selon la présente invention, un substrat, qui a un trou d'insertion de fil qui pénètre à travers celui-ci dans la direction de l'épaisseur et dans lequel une marque de référence de positionnement est formée sur un côté de surface de formation de motif, est transporté du côté amont vers le côté aval le long d'un trajet de transport de substrat, et au niveau d'une position de liaison côté aval sur le trajet de transport de substrat, une surface de formation d'électrode d'une puce est liée à une section de liaison de puce d'une surface de liaison de puce qui est sur le côté opposé à la surface de formation de motif de ce substrat.
PCT/JP2021/043808 2021-01-21 2021-11-30 Procédé de liaison et procédé d'utilisation de dispositif de liaison WO2022158122A1 (fr)

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JP2021007920A JP6999841B1 (ja) 2021-01-21 2021-01-21 ボンディング方法およびボンディング装置使用方法
JP2021-007920 2021-01-21

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WO2022158122A1 true WO2022158122A1 (fr) 2022-07-28

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030000738A1 (en) * 2001-06-25 2003-01-02 Rumsey Brad D. Solder resist opening to define a combination pin one indicator and fiducial
JP2006041006A (ja) * 2004-07-23 2006-02-09 Matsushita Electric Ind Co Ltd 半導体チップのボンディング方法及び装置
JP2007287834A (ja) * 2006-04-14 2007-11-01 Renesas Technology Corp 電子部品の実装方法および装置
JP2009200203A (ja) * 2008-02-21 2009-09-03 Panasonic Corp ダイボンディング装置及びダイボンディング方法
JP2018074090A (ja) * 2016-11-04 2018-05-10 パナソニックＩｐマネジメント株式会社 部品搭載装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030000738A1 (en) * 2001-06-25 2003-01-02 Rumsey Brad D. Solder resist opening to define a combination pin one indicator and fiducial
JP2006041006A (ja) * 2004-07-23 2006-02-09 Matsushita Electric Ind Co Ltd 半導体チップのボンディング方法及び装置
JP2007287834A (ja) * 2006-04-14 2007-11-01 Renesas Technology Corp 電子部品の実装方法および装置
JP2009200203A (ja) * 2008-02-21 2009-09-03 Panasonic Corp ダイボンディング装置及びダイボンディング方法
JP2018074090A (ja) * 2016-11-04 2018-05-10 パナソニックＩｐマネジメント株式会社 部品搭載装置

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