WO2022158122A1 - Bonding method and bonding device use method - Google Patents

Bonding method and bonding device use method Download PDF

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Publication number
WO2022158122A1
WO2022158122A1 PCT/JP2021/043808 JP2021043808W WO2022158122A1 WO 2022158122 A1 WO2022158122 A1 WO 2022158122A1 JP 2021043808 W JP2021043808 W JP 2021043808W WO 2022158122 A1 WO2022158122 A1 WO 2022158122A1
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Prior art keywords
bonding
chip
substrate
recognition
collet
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PCT/JP2021/043808
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French (fr)
Japanese (ja)
Inventor
信裕 永元
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キヤノンマシナリー株式会社
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Publication of WO2022158122A1 publication Critical patent/WO2022158122A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation

Definitions

  • the present invention relates to a bonding method and a method of using a bonding apparatus, and more particularly to a method of manufacturing a board-on-chip (BOC) type electronic component (semiconductor device) and a method of using a bonding apparatus.
  • BOC board-on-chip
  • Some electronic components are of the BOC (Board on Chip) type. That is, there is a semiconductor package shown in FIG. 9 as a BOC type electronic component.
  • the semiconductor package includes a substrate 1 having one surface serving as a pattern forming surface 1a and the other surface serving as a chip bonding surface 1b.
  • a wire 5 connects a substrate-side electrode on the surface 1a and a chip-side electrode of the chip 4 bonded to the chip bonding surface 1b.
  • 6 is a solder ball formed on the pattern forming surface 1a
  • 7 is an adhesive layer for bonding the chip bonding surface 1b of the substrate 1 and the chip 4 together.
  • the chip 4 and the wire 5 are sealed with the sealing body 8 .
  • the chip 4 with the electrodes on the chip 4 side (chip-side electrodes) facing upward. is placed on the upper surface of the moving stage 10, the moving stage 10 is moved below the substrate 1, and the chip 4 is brought into contact with the chip bonding surface 1b (here, the lower surface) on the opposite side of the pattern forming surface 1a of the substrate 1 from below. (Arrow A shown in the figure), then the substrate 1 is pressed against the chip 4 on the moving stage 10 by a thermocompression bonding tool 11 from above the substrate 1 (Arrow B shown in the figure), and the chip 4 is bonded to the substrate 1.
  • a thermocompression bonding tool 11 from above the substrate 1
  • the pattern formation surface 1a on the substrate 1 side and the electrode formation surface 4a on the chip 4 side are respectively viewed from above by a camera (the substrate side recognition camera 12 for recognizing the pattern formation surface 1a on the substrate 1 side and the chip 4). Since it can be recognized by a chip-side recognition camera 13) that recognizes the side electrode forming surface 4a, the chip 4 is aligned with the substrate 1.
  • FIG. Reference numeral 14 in FIG. 8 denotes a substrate-side pattern (substrate-side electrode portion) on the pattern forming surface 1a.
  • Patent Document 1 a die bonding apparatus and a die bonding method that can perform a die bonding process for BOC type electronic components by using a conventional die bonding apparatus.
  • the die bonding apparatus (method) described in Patent Document 1 is for bonding the chip with the chip bonding surface (surface opposite to the pattern forming surface) of the substrate facing upward.
  • the chips are picked up from the wafer by an inversion tool, and the picked up chips are inverted by the inversion tool.
  • the electrode formation surface of the chip faces downward.
  • a transfer tool is used to suck the opposite electrode forming surface of the chip from above. In this state, the electrode formation surface of the chip faces downward. Therefore, the electrode forming surface of the chip can be bonded from above to the chip bonding surface (surface opposite to the pattern forming surface) of the substrate facing upward.
  • Patent Document 1 the pattern formation surface of the substrate (the surface facing downward) is observed with a camera placed above. That is, a mirror member is provided through a transparent member on a substrate mounting table on which a substrate is mounted, and a reflected image reflected on the mirror surface of this mirror member is viewed. In this case, the reflected image is projected on the mirror surface through the wire insertion hole provided in the substrate and the transparent member.
  • the substrate and the chip are aligned based on the position of the pattern on the substrate side of the reflected image, and the electrode forming surface of the chip is bonded to the chip bonding surface of the substrate.
  • Patent Document 1 uses a reflected image.
  • a reflected image When a reflected image is used, the observation range is limited because the wire insertion hole and the transparent member are interposed, and if the mirror surface is of poor precision, an accurate reflected image cannot be obtained. be.
  • the acquisition of the reflected image is the part where the substrate is heated, the gas generated when the adhesive melts accumulates on the mirror, causing the mirror to become cloudy, and the image acquisition is unstable.
  • the apparatus of Patent Document 1 requires a substrate mounting table provided with a transparent member and a mirror member, and the members (the substrate mounting table provided with the transparent member and the mirror member) that must be formed with high precision as the entire apparatus are required.
  • the substrate mounting table provided with the transparent member and the mirror member must be replaced, resulting in poor productivity.
  • the present invention provides a bonding method and a method of using a bonding apparatus that enable stable alignment and that can use an existing bonding apparatus as the apparatus to be used.
  • a substrate having a wire insertion hole penetrating in the thickness direction and having a positioning reference mark formed on the pattern forming surface side is transported from the upstream side to the downstream side along the substrate transport path. and bonding the electrode forming surface of the chip to the chip bonding portion of the chip bonding surface on the opposite side of the substrate-side electrode portion of the pattern forming surface of the substrate at a bonding position on the downstream side of the substrate transport path, comprising: A substrate recognizing step of recognizing the positional relationship between the positioning reference mark and the wire insertion hole seen from below on the upstream side of the substrate conveying path, with the pattern forming surface of the substrate facing downward, and a pick-up collet.
  • a pick-up process for picking up the chip a reversing process for reversing the chip picked up by the pick-up side collet and directing the electrode forming surface downward, and a bonding side collet with the electrode forming surface facing downward for the chip reversed in the reversing process.
  • the chip received in the receiving step is attached to the chip bonding portion of the substrate aligned in the alignment step. and a bonding step of bonding to the bonding portion.
  • the positional relationship between the positioning reference marks and the wire insertion holes can be recognized based on the direct image of the pattern forming surface viewed from below in the substrate recognition process.
  • a chip can be picked up in the pick-up process, and the picked-up chip can be brought into a state in which the chip electrode forming surface faces downward in the reversing process.
  • the chip In the receiving process, the chip can be received by the bonding-side collet with the electrode-formed surface facing downward.
  • alignment process alignment can be performed based on the positional relationship between the positioning reference marks and the wire insertion holes, and recognition of the position of the wire insertion holes from above the bonding position.
  • the chip received in the receiving step can be bonded to the chip bonding portion of the substrate aligned in the alignment step.
  • the pattern formation surface of the substrate facing downward can be observed from below the substrate. Therefore, since the observation surface is not an indirect image, the observation field is not restricted, and the positional relationship between the positioning reference mark and the wire insertion hole can be observed stably and with high accuracy. Moreover, since this image observation is performed on the upstream side of the substrate transport path, which is a portion that is not heated, heating means (for example, an electric heater provided on the backup plate) is used in the substrate recognition process on the downstream side of the substrate transport path. It can be placed without being obstructed by a camera or the like.
  • heating means for example, an electric heater provided on the backup plate
  • the substrate recognition part and the substrate heating part can be arranged at separate positions, and the influence of the substrate heating on the substrate recognition part (the influence of the gas generated when the adhesive melts, etc. on the optical system, etc.)
  • the substrate heating portion the wire insertion hole of the substrate is recognized from above, but the substrate is not recognized at a close position, so that the substrate can be continuously heated.
  • the bonding process for bonding the chip can be performed from above the substrate, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used.
  • alignment is performed based on recognition of the positional relationship between the positioning reference mark and the wire insertion hole at a position on the upstream side away from the bonding position and recognition of the position of the wire insertion hole from above the bonding position.
  • high-precision alignment is possible. That is, since the positional relationship between the reference marks and the electrodes on the pattern formation surface is set with high accuracy, the positions of the wire insertion holes can be confirmed by confirming the positions of the wire insertion holes from the bonding surface side of the chip (the side opposite to the pattern formation surface).
  • the position of the electrode (substrate-side electrode portion) on the pattern forming surface can be detected, thereby enabling accurate bonding and bonding to the chip bonding portion on the chip bonding surface side of the substrate.
  • the chip joint portion is a portion corresponding to the substrate-side electrode portion.
  • a chip recognition process for recognizing the chip position before bonding may be provided. In this way, the alignment accuracy can be improved with the chip recognition process.
  • the substrate may be received by a backup plate from below.
  • the chip can be sandwiched between the bonding-side collet and the backup plate when the chip is bonded to the chip bonding surface of the substrate. A stable bond can be obtained.
  • this backup plate can be configured to be heated by a heating means to heat the adhesive on the substrate. This configuration eliminates the need to provide the heating means as a separate member, which contributes to downsizing of the entire apparatus.
  • the board recognition process acquire position information for one board.
  • the bonding process can be performed to continuously bond chips to all the chip bonding portions of one substrate, thereby improving productivity.
  • a chip is picked up by a pickup-side collet at a pickup position, the chip picked up at the pickup position is reversed, and the reversed chip is bonded at a bonding position by a bonding-side collet.
  • a method of using a bonding apparatus, wherein the bonding method can be performed.
  • the method of using the bonding apparatus of the present invention can use an existing general-purpose bonding apparatus, and can reduce costs.
  • the patterned surface since the observation of the patterned surface is not an indirect image, the field of view for observation is not restricted, the patterned surface can be observed stably and with high precision, and the chip is stably bonded to the substrate with high precision. be able to. In addition, the chip can be bonded to the substrate at low cost without complicating the device configuration. Furthermore, the bonding process for bonding the chip can be performed from above the substrate, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used.
  • FIG. 1 is a simplified perspective view of a bonding apparatus used in the bonding method of the present invention
  • FIG. 2 is an enlarged schematic view of a main part of a pattern formation surface of a substrate
  • FIG. 4 is a simplified diagram of a chip bonding portion of a chip bonding surface
  • FIG. 4 is a simplified diagram showing a substrate and a state in which an adhesive is applied to a chip bonding portion of a chip bonding surface
  • FIG. 3 is a simplified plan view showing a transport mechanism for substrates
  • 1 is a block diagram of the bonding method of the present invention
  • FIG. It is a block diagram which shows the process of the first half of the bonding method of this invention.
  • FIG. 1 is a cross-sectional view of a semiconductor device (BOC type semiconductor package); FIG.
  • FIG. 1 An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.
  • FIG. 1 An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.
  • FIG. 1 shows a bonding apparatus used for the bonding method according to the present invention.
  • This bonding apparatus can perform a bonding method of bonding the electrode forming surface 32a of the chip 32 to the chip bonding portion 34 of the chip bonding surface 31b on the opposite side of the substrate-side electrode portion 38 of the pattern forming surface 31a of the substrate 31. .
  • the substrate 31 is provided with a plurality of wire insertion holes 33 which are elongated holes extending in the width direction of the substrate.
  • a plurality of wire insertion holes 33 are arranged along the substrate width direction to constitute a wire insertion hole group 35, and the plurality of wire insertion hole groups 35 are arranged at a predetermined pitch along the substrate longitudinal direction. ing.
  • a substrate-side pattern (substrate-side electrode portion) 38 having substrate-side electrodes 36 and pads 37 provided on both sides of the wire insertion hole 33 is formed on the side of the pattern forming surface 31a of the substrate 31, a substrate-side pattern (substrate-side electrode portion) 38 having substrate-side electrodes 36 and pads 37 provided on both sides of the wire insertion hole 33 is formed.
  • an adhesive S is applied (applied) to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31 (the surface opposite to the pattern forming surface 31a).
  • a pair of adhesives S, S are applied to one wire insertion hole 33 with the wire insertion hole 33 interposed therebetween.
  • the adhesive S may be a paste adhesive or a die attach film (DAF).
  • a positioning reference mark 40 (see FIG. 3A) is formed on the pattern formation surface 31a of the substrate 31.
  • the positioning reference marks 40 (hereinafter sometimes simply referred to as reference marks 40) are formed at corners of a metal film formed on the pattern forming surface 31a of the substrate 31.
  • the reference mark 40 is not limited to this, and may be a mark such as a specially provided colored mark or an uneven portion.
  • the substrate 31 is transported along the direction of the arrow X in FIG. 1 by substrate transport means 41 as shown in FIG.
  • the substrate conveying means 41 has a pair of conveying rails 42, 42, and the substrate 31 placed on the conveying rails 42, 42 has a grasping mechanism (for example, a chuck mechanism, etc.) (not shown).
  • the sheet is conveyed from the upstream side to the downstream side along the arrow X direction by the feeding mechanism.
  • a backup plate (adapter plate) 43 is arranged between the transport rails 42, 42 below the bonding position (bonding position) on the downstream side of the transport path of the substrate 31.
  • the backup plate 43 can be heated by heating means (not shown). That is, by heating the backup plate 43, the adhesive S on the chip bonding surface 31b corresponding to the bonding position on the substrate 31 can be heated.
  • Various electric heating methods can be used as heating means (not shown).
  • the central portion in the substrate conveying direction can heat the substrate 31 to a temperature at which the adhesive S during bonding can be melted and effective bonding force can be exhibited.
  • the bonding temperature zone can correspond to the bonding position, and when the chip bonding portion 34 of the substrate 31 is positioned at the bonding position, the chip bonding portion 34 of the substrate 31 can be S can be heated to a temperature at which effective bonding strength can be exhibited.
  • the chip bonding portion 34 of the substrate 31 passes through the low-temperature heating zone before being positioned at the bonding position, the chip bonding portion 34 of the substrate 31 can be preheated, thereby improving working efficiency. be able to.
  • This bonding apparatus also includes a pickup mechanism 50 for picking up a chip 32 as a workpiece, and a bonding mechanism for bonding the chip 32 picked up by the pickup mechanism 50 to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31.
  • a mechanism 51 and observation means 53 for observing the pattern formation surface 31a on the back side of the substrate 31 from below are provided on the upstream side of the substrate transport path.
  • the chip 32 is made from a wafer material, and cut into a rectangular shape to form the final product. For this reason, the chip 32 may be square, strip-shaped, or the like. That is, the wafer is generally circular and is divided into individual chips 32 by dicing.
  • the pickup mechanism 50 has a pickup head 56 with a pickup arm 55 attached to the tip side, and a collet 57 is attached to the tip of the pickup arm 55 .
  • a plurality of suction holes (not shown) that open to the tip surface of the collet 57 are provided on the tip surface of the collet 57 , and the tip 32 is vacuum-sucked through the suction holes, and the tip 32 is attached to the tip surface of the collet 57 .
  • the chip 32 is removed from the collet 57 when the vacuum suction (vacuum drawing) is released.
  • vacuum suction vacuum drawing
  • a vacuum mechanism As the vacuum mechanism, a vacuum pump, a vacuum ejector, or the like is used.
  • the pickup head 56 has a reversing mechanism 58 that can reverse the collet 57 at the tip of the pickup arm 55 .
  • the reversing mechanism 58 has a drive mechanism (for example, a motor, etc.) that rotates the pickup head 56 around its axis. It is possible to change the attitude between the posture and the posture in which the tip end surface, which is the suction surface of the collet 57, faces upward.
  • the pickup head 56 of the pickup mechanism 50 can be vertically moved as indicated by arrows Z1 and Z2 by a vertical movement mechanism (not shown).
  • the vertical movement mechanism can be composed of various reciprocating mechanisms such as a cylinder mechanism, a ball screw mechanism, and a linear motor mechanism.
  • the bonding mechanism 51 has a bonding head 60 and a collet 62 attached to the tip of a bonding arm 61 .
  • a plurality of suction holes (not shown) that open to the tip surface are provided on the lower surface (tip surface) of the collet 62 , and the tip 32 is vacuum-sucked through the suction holes. be done.
  • the chip 32 is removed from the collet 62 when the vacuum suction (vacuum drawing) is released. Further, vacuum suction (vacuum drawing) is performed by a vacuum mechanism (not shown).
  • a vacuum pump, a vacuum ejector, or the like is used as the vacuum mechanism.
  • the bonding head 60 can be moved in the longitudinal direction of the substrate 31 in the directions of arrows X1 and X2, in the direction of arrows A and B in the width direction, and in the direction of arrows C and D in the vertical direction through a moving mechanism (not shown).
  • a moving mechanism various reciprocating mechanisms such as a cylinder mechanism, a ball screw mechanism, and a linear motor mechanism can be used.
  • the observation means 53 includes a camera mechanism 65 arranged below the upstream side of the substrate transport path. That is, the camera mechanism 65 includes a camera body 66 composed of an image recognition camera (for example, a CCD camera, a CMOS camera, etc.) and an optical system 67 that forms the image field of the camera body 66 .
  • the optical system 67 includes a mirror member 68 for allowing the image of the pattern forming surface 31 a of the substrate in a predetermined field of view to enter the camera body 66 .
  • the observation field of view of the observation means 53 is a range indicated by a two-dot chain line.
  • an insertion hole recognizing means 71 for recognizing the wire insertion holes 33 of the substrate 31 is provided above the bonding position of the chip 32 .
  • a first chip recognizing means 72 for confirming the chip 32 in an inverted state after being picked up by the pickup mechanism 50 is arranged, and on the bonding mechanism 51 side, A second chip recognition means 73 is provided for recognizing the chip 32 sucked and held by the bonding collet 62 .
  • the insertion hole recognizing means 71 and the first chip recognizing means 72 can be configured with a CCD camera, a CMOS camera, or the like.
  • the second chip recognition means 73 also includes a camera body 74 consisting of an image recognition camera (for example, a CCD camera, a CMOS camera, etc.) and an optical system 75 that forms the image field of the camera body 74 .
  • the optical system 75 in this case includes a mirror member 76 for making the image of the chip 32 enter the camera body 74 .
  • position recognition of the chip 32 before bonding is performed, that is, chip recognition steps 87 and 88, which will be described later, are performed. can be done. That is, the first chip recognition means 72 recognizes the position of the chip 32 sucked by the pick-up collet 57, and the second chip recognition means 73 recognizes the position of the chip 32 sucked by the bonding collet 62. will do. These positional recognitions are used for alignment when bonding the chip 32 .
  • the substrate transport means 41, the pick-up mechanism 50, and the bonding mechanism 51 are controlled by a computer (not shown).
  • the computer basically comprises input means with an input function, output means with an output function, storage means with a storage function, and arithmetic means with an arithmetic function. It is composed of control means having a control function.
  • the input function is for reading information from the outside into the computer, and the read data and programs are converted into signals in a format suitable for the computer system.
  • the output function is to display the calculation results, stored data, etc. to the outside.
  • the storage means stores and saves programs, data, processing results, and the like. Arithmetic functions process data by performing calculations and comparisons according to program instructions.
  • the control function interprets the instructions of the program and issues instructions to each means, and this control function controls all the means of the computer.
  • Input means include keyboards, mice, tablets, microphones, joysticks, scanners, capture boards, and the like.
  • Output means include a monitor, a speaker, a printer, and the like.
  • Storage means include memory, hard disk, CD/CD-R, PD/MO, and the like.
  • the calculation means includes a CPU and the like, and the control means includes a CPU, a motherboard, and the like.
  • the electrode forming surface 32a of the chip 32 is attached to the chip bonding portion 34 of the chip bonding surface 31b on the opposite side of the substrate-side electrode portion 38 of the pattern forming surface 31a of the substrate 31.
  • a bonding method for joining will be described.
  • the chip joint portion 34 corresponds to the opposite surface of the board-side electrode portion 38 .
  • This bonding method includes a substrate recognition process 81, a pick-up process 82, an inversion process 83, a receiving process 84, an alignment process 85, and a bonding process 86, as shown in FIG.
  • a first chip recognition process 87 is provided between the reversing process 83 and the receiving process 84
  • a second chip recognition process 88 is provided between the receiving process 84 and the alignment process 85. be done.
  • the position of the substrate-side pattern on the pattern forming surface 31a is recognized based on a direct image of the pattern forming surface 31a from below, with the pattern forming surface 31a of the substrate 31 facing downward. It is a process of performing
  • a pick-up step 82 is a step of picking up the chip 32 via the pick-up collet 57 .
  • the reversing step 83 is a step of reversing the chip 32 picked up by the pickup-side collet 57 so that the electrode forming surface 32a faces downward.
  • the receiving step 84 is a step of receiving the chip 32 reversed in the reversing step 83 with the bonding side collet 62 with the electrode forming surface 32a facing downward.
  • the alignment step 85 aligns the substrate 31 with the chip 32 received in the receiving step 84 based on the position of the substrate-side pattern (substrate-side electrode portion 38 ) on the pattern forming surface 31 a recognized in the recognition step 81 . It is a process of performing
  • the bonding step 86 is a step of bonding the chip 32 aligned with the substrate 31 in the alignment step to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31 with the bonding-side collet.
  • the first chip recognizing step 87 is a step of observing from above the chip 32 attracted to the pick-up side collet 57 by the first chip recognizing means 72 with the counter-chip side electrode facing upward.
  • the bonding side collet 62 is detected by the second chip recognition means 73 . This is a step of observing from below the chip 32 sucked with the electrode forming surface 32a facing downward.
  • the substrate is placed on the upstream side of the substrate transport path with the pattern forming surface 31a facing downward.
  • the substrate recognition step 81 that is, substrate recognition is performed (step S1).
  • the position of the wire insertion hole 33 is recognized based on the reference mark provided on the pattern forming surface 31a.
  • the positional information of the chip joint portion 34 on one substrate 31 is acquired. That is, the positions of all wire insertion holes 33 are confirmed. This position information is stored in the storage means of the computer.
  • step S2 the pick-up process by the pick-up mechanism 50, that is, the chip 32 is picked up at the pick-up position (step S2). That is, the pickup-side collet 57 located above the pickup position is lowered as indicated by arrow Z1 in FIG. Raise 57. Thereby, the chip 32 can be picked up.
  • the reversing process 83 is performed. That is, in the pickup mechanism 50, the tip 32 is inverted by inverting the pickup head 56 by 180° (step S3). In this case, it may be clockwise or counterclockwise. In this case, the electrode formation surface 32a of the chip 32 faces downward.
  • step S4 determines whether or not to recognize the position of the tip 32. If it is determined in step S4 that the position is not recognized, the process proceeds to step S5 to perform a receiving process for receiving the inverted chip 32. FIG. If it is determined in step S4 that the position should be recognized, the process proceeds to step S6 to recognize the position of the tip 32. FIG. That is, the chip 32 is imaged by the first chip recognition means 72 and the position of the chip 32 is confirmed.
  • step S5 the inverted chip 32 is received by the bonding mechanism 51. That is, the bonding-side collet 62 is positioned above the inverted chip 32 and the chip 32 is sucked to this collet 62 . At this time, the suction of the pickup-side collet 57 is released. As a result, the chip 32 is attracted to the attraction surface, which is the lower surface of the bonding-side collet 62 . In this case, the electrode forming surface 32a of the chip 32 faces downward.
  • step S7 it is determined whether the position of the chip 32 should be confirmed. If the position is not to be confirmed in step S7, the process proceeds to step S8. If the position is to be confirmed in step S7, the process proceeds to step S9, the position is confirmed, and then the process proceeds to step S8.
  • step S7 the chip 32 is imaged by the second chip recognition means 73 and the position of the chip 32 is confirmed.
  • step S8 the substrate 31 and the chip 32 are aligned.
  • the substrate 31 is transported from the upstream side to the downstream side of the substrate transport path by the substrate transport means 41 so that the chip bonding portion 34 of the substrate 31 to which the chip 34 is to be bonded is positioned above the bonding position. .
  • step S8 based on the relationship between the reference marks 40 on the pattern forming surface 31a of the substrate 31 and the wire insertion holes 33 and the position recognition of the wire insertion holes 33 confirmed by the insertion hole recognition means 71, the chip 32 and the wire insertion hole 33 are detected. Alignment with the chip joint portion 34 is performed. In this case, the wire insertion hole 33 of the chip bonding portion to which the chip 32 is to be bonded is recognized by the insertion hole recognizing means 71 . Then, the positional relationship between the recorded reference mark 40 and the wire insertion hole 33 is compared with the wire insertion hole 33 of the chip joint 34 recognized by the insertion hole recognition means 71 .
  • the positional deviation (by the recognition means 71)
  • the positional deviation between the recognized wire insertion hole 33 and the reference mark 40 occurs, and the wire insertion hole 33 recognized by the recognition means 71 is detected by the board based on the amount of positional deviation recognized by the recognition means 71 . It is necessary to align the reference mark 40 of 31 with the electrode position of the tip 32 (or the outer shape position of the tip 32). It should be noted that there may be a case where the position is not shifted. If there is no misalignment, there is no need to perform alignment.
  • the position of the chip 32 can be recognized before bonding in the first and second chip recognition processes 87 and 88, the position of the chip 32 before bonding detected in the chip recognition processes 87 and 88 can be detected. can be used for this alignment.
  • This enables more precise alignment. That is, the positional information of the chip 32 obtained in the first and second chip recognition steps 87 and 88 is inputted to the computer, and positional alignment is performed by calculating the positional deviation including this information.
  • the positional deviation there are cases of positional deviation in the longitudinal direction of the substrate 31, cases of positional deviation in the width direction of the substrate 31, and cases of positional deviation in the longitudinal direction and the width direction. If the position is shifted in the longitudinal direction, the position of the bonding side collet 62 is displaced in the directions of arrows X1 and X2; if the position is shifted in the width direction, the position of the bonding side collet 62 is displaced in the directions of arrows A and B; If the position is shifted in the longitudinal direction and the width direction, the position of the bonding side collet 62 may be displaced in the directions of arrows X1, X2, A and B.
  • step S10 the chips 32 are bonded in the aligned state.
  • the bonding-side collet 62 receiving the chip 32 from the pickup-side collet 57 is lifted as indicated by arrow C, and then moved to above the chip bonding portion as indicated by arrow A. , and then the bonding side collet 62 is lowered for bonding.
  • the alignment can be performed while the bonding-side collet 62 is operating. However, the alignment is performed after the position of the chip 34, which is being sucked by the collet 57 and inverted, has been confirmed. Alternatively, alignment may be performed after confirming the position of the tip 34 sucked by the collet 62 .
  • the backup plate 43 is heated to a temperature at which the adhesive can be bonded. Therefore, the collet 62 is lowered, and the substrate 31 is sandwiched between the collet 62 and the backup plate 43, and the chip 32 is joined with the adhesive S. FIG.
  • the electrode forming surface 32a of the chip 32 is accurately bonded to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31 by the alignment process. can be done.
  • step S11 determines whether or not to end this process (work). If it is determined to end, the process ends, and if it is determined not to end in step S10, the process returns to step S2.
  • chips can be bonded to all the chip bonding portions of one substrate 31 by performing the steps from step S2 to step S10.
  • the pattern formation surface 31a of the substrate 31 facing downward can be observed from below the substrate 31. Therefore, since the observation of the pattern-formed surface 31a is not an indirect image, the observation field of view is not restricted, and the pattern-formed surface 31a can be observed stably and with high accuracy. Moreover, since this image observation is performed on the upstream side of the substrate transport path, which is a portion that is not heated, the heating means (for example, the heating means provided on the backup plate) is placed downstream of the substrate transport path in the substrate recognition process. It can be arranged without being obstructed by the camera or the like used.
  • the board recognition part and the board heating part can be arranged at separate positions, and the positional relationship between the positioning reference mark 40 and the wire insertion hole 33 can be recognized in a place where the board 31 is not heated. Therefore, the substrate recognition portion is not affected by the heating of the substrate (such as the influence of the gas generated when the adhesive melts on the optical system, etc.).
  • recognition is performed (recognition by the insertion hole recognition means 71 as the recognition portion in FIG. 1), since board recognition is not performed at a close position, continuous heating of the board 31 is possible.
  • the bonding process 86 for bonding the chip 32 can be performed from above the substrate 31, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used.
  • the adhesive S for bonding the chip 32 and the chip bonding surface 31b of the substrate 31 is disposed on the chip bonding surface 31b facing upward, it is relatively fluid. There is no danger of it falling down even if you have it. Therefore, the application work of the adhesive S is easy, and various kinds of adhesives can be used as the adhesive S, which contributes to cost reduction.
  • the pattern-formed surface 31a since the observation of the pattern-formed surface 31a is not an indirect image, the observation field of view is not restricted, the pattern-formed surface 31a can be observed stably and accurately, and the bonding of the chip 32 to the substrate 31 can be performed with high accuracy. can be done stably.
  • the chip 32 can be bonded to the substrate 31 at low cost without complicating the device configuration.
  • the bonding process 86 for bonding the chip 32 can be performed from above the substrate 31, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used. Moreover, continuous heating of the substrate 31 is possible, and the productivity is excellent.
  • the positioning process can be performed stably. That is, since the positional relationship between the position of the positioning reference mark 40 and the position of the electrode on the pattern forming surface 31a of the substrate 31 is highly accurate, the positioning step 85 can be stably performed.
  • chip recognition processes 87 and 88 for recognizing the position of the chip 32 before bonding. As described above, the chip recognition processes 87 and 88 can improve the alignment accuracy.
  • the substrate 31 is received by the backup plate 43 from below, so when the chip 32 is bonded to the chip bonding surface 31b of the substrate 31, the chip 32 can be sandwiched between the collet 62 and the backup plate 43.
  • stable bonding can be obtained without bending the substrate 31 or the like.
  • An existing general-purpose bonding apparatus can be used as each component of the bonding apparatus used in the bonding method of the present invention, and cost reduction can be achieved.
  • the present invention is not limited to the above embodiments, and various modifications are possible.
  • the bonding side collet 62 may be heated.
  • the heating means may be provided only on the side, the heating means may be provided only on the backup plate 43 side, or the heating means may be provided on the collet 62 side and the backup plate 43 side.
  • the backup plate 43 may not be provided, and in such a case, a separate heating means is provided below the bonding position.
  • Various electric heating can be used as each heating means in this case.
  • the first chip recognition means 72 and the second chip recognition means 73 are used to confirm the positions of the chips before bonding, but either one of the chip recognition means may be used. .
  • the camera body 66 is arranged along the horizontal direction, but the camera body 66 may face the vertical direction.
  • the process of performing board recognition of step S1 is followed by the process of picking up the chip 32 of step S2.
  • the substrate and the chip may be aligned in step S8 after transporting. That is, the chip and the chip bonding portion are aligned based on the positional relationship between the positioning reference mark and the wire insertion hole and the recognition of the position of the wire insertion hole from above the bonding position.
  • This bonding method and this bonding apparatus usage method are for manufacturing a board-on-chip (BOC) type electronic component (semiconductor device).
  • BOC board-on-chip

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Abstract

In this bonding method, a substrate, which has a wire insertion hole that penetrates therethrough in the thickness direction and in which a positioning reference mark is formed on a pattern formation surface side, is conveyed from the upstream side to the downstream side along a substrate conveyance path, and at a downstream-side bonding position on the substrate conveyance path, an electrode formation surface of a chip is bonded to a chip bonding section of a chip bonding surface which is on the side opposite the pattern formation surface of this substrate.

Description

ボンディング方法およびボンディング装置使用方法Bonding method and bonding equipment usage method
 ボンディング方法およびボンディング装置使用方法に関し、特に、ボードオンチップ(BOC)タイプの電子部品(半導体装置)を製造するためのボンディング方法およびボンディング装置使用方法に関する。 The present invention relates to a bonding method and a method of using a bonding apparatus, and more particularly to a method of manufacturing a board-on-chip (BOC) type electronic component (semiconductor device) and a method of using a bonding apparatus.
 電子部品には、BOC(ボードオンチップ)タイプのものがある。すなわち、BOCタイプの電子部品として、図9に示す半導体パッケージがある。半導体パッケージは、一方の面がパターン形成面1aとされるとともに他方の面がチップ接合面1bとされる基板1を備え、基板1に設けられたスリット孔(貫通孔)3を介してパターン形成面1aにおける基板側電極と、チップ接合面1bに接合されるチップ4のチップ側電極とがワイヤ5にて接続される。 Some electronic components are of the BOC (Board on Chip) type. That is, there is a semiconductor package shown in FIG. 9 as a BOC type electronic component. The semiconductor package includes a substrate 1 having one surface serving as a pattern forming surface 1a and the other surface serving as a chip bonding surface 1b. A wire 5 connects a substrate-side electrode on the surface 1a and a chip-side electrode of the chip 4 bonded to the chip bonding surface 1b.
 図9において、6はパターン形成面1aに形成されたはんだボールであり、7は基板1のチップ接合面1bとチップ4とが接合されるための接着層である。また、チップ4とワイヤ5とを封止体8にて封止している。 In FIG. 9, 6 is a solder ball formed on the pattern forming surface 1a, and 7 is an adhesive layer for bonding the chip bonding surface 1b of the substrate 1 and the chip 4 together. Also, the chip 4 and the wire 5 are sealed with the sealing body 8 .
 このため、このような電子部品においては、基板1のチップ接合面1bにチップ4を接合する工程(ボンディング工程)を必要としていた。この場合の従来の一般的なボンディング方法を図8を用いて説明する。 Therefore, in such an electronic component, a process (bonding process) of bonding the chip 4 to the chip bonding surface 1b of the substrate 1 is required. A conventional general bonding method in this case will be described with reference to FIG.
 基板1側の電極(基板側電極)を含むパターン形成面1aを上に向けた状態で基板1を所定位置に保持した後、チップ4側の電極(チップ側電極)を上に向けたチップ4を移動ステージ10の上面に載置し、移動ステージ10を基板1の下方に移動させて基板1のパターン形成面1aと反対側のチップ接合面1b(ここでは下面)にチップ4を下方から当接させ(図中に示す矢印A)、次いで基板1の上方から熱圧着ツール11により移動ステージ10上のチップ4に基板1を押し付けて(図中に示す矢印B)基板1にチップ4を接合していた。このような方法では、基板1側のパターン形成面1aとチップ4側の電極形成面4aのそれぞれを上方からカメラ(基板1側のパターン形成面1aの認識を行う基板側認識カメラ12及びチップ4側の電極形成面4aの認識を行うチップ側認識カメラ13)で認識することができるので、基板1に対するチップ4の位置合わせ(アライメント)を行っていた。なお、図8の14は、パターン形成面1aの基板側パターン(基板側電極部)を示している。 After holding the substrate 1 at a predetermined position with the pattern formation surface 1a including the electrodes on the substrate 1 (substrate-side electrodes) facing upward, the chip 4 with the electrodes on the chip 4 side (chip-side electrodes) facing upward. is placed on the upper surface of the moving stage 10, the moving stage 10 is moved below the substrate 1, and the chip 4 is brought into contact with the chip bonding surface 1b (here, the lower surface) on the opposite side of the pattern forming surface 1a of the substrate 1 from below. (Arrow A shown in the figure), then the substrate 1 is pressed against the chip 4 on the moving stage 10 by a thermocompression bonding tool 11 from above the substrate 1 (Arrow B shown in the figure), and the chip 4 is bonded to the substrate 1. Was. In such a method, the pattern formation surface 1a on the substrate 1 side and the electrode formation surface 4a on the chip 4 side are respectively viewed from above by a camera (the substrate side recognition camera 12 for recognizing the pattern formation surface 1a on the substrate 1 side and the chip 4). Since it can be recognized by a chip-side recognition camera 13) that recognizes the side electrode forming surface 4a, the chip 4 is aligned with the substrate 1. FIG. Reference numeral 14 in FIG. 8 denotes a substrate-side pattern (substrate-side electrode portion) on the pattern forming surface 1a.
 このようなボンディング方法では、ピックアップアームを介してチップをピックアップした後、吸着面が上向きのボンディングアームに移載する必要があり、この状態で、チップ4側の電極形成面4aの認識を行って、基板の下方を向いたチップ接合面にチップを接合する必要があった。この場合、基板裏面側の接着剤を加熱して、下方に配置されるボンディングアームと基板のパターン形成面から荷重を掛けることによって、チップを挟んで接合することになる。 In such a bonding method, after picking up the chip via the pickup arm, it is necessary to transfer it to the bonding arm with the suction surface facing upward. , it was necessary to bond the chip to the chip bonding surface facing downward of the substrate. In this case, the chip is sandwiched and bonded by heating the adhesive on the back side of the substrate and applying a load from the bonding arm arranged below and the pattern formation surface of the substrate.
 しかしながら、このように、基板の下方からボンディングする方法で、一般的に使用されている汎用のボンディング装置(基板の上方からボンディングする装置)を用いることができなかった。 However, in such a method of bonding from below the substrate, it was not possible to use a generally used general-purpose bonding device (device for bonding from above the substrate).
 そこで、従来には、従来型のダイボンディング装置を流用してBOCタイプの電子部品のダイボンディング工程を行うことができるダイボンディング装置およびダイボンディング方法が提案されている(特許文献1)。 Therefore, conventionally, there has been proposed a die bonding apparatus and a die bonding method that can perform a die bonding process for BOC type electronic components by using a conventional die bonding apparatus (Patent Document 1).
 特許文献1に記載のダイボンディング装置(方法)は、基板のチップ接合面(パターン形成面と反対の面)を、上方に向けてこのチップを接合するものである。この場合、チップをウエハから反転ツールでピックアップし、ピックアップしたチップを反転ツールで反転させる。これによって、チップの電極形成面を下方に向かせる。その後、移載ツールで上方からチップの反電極形成面を吸着する。この状態では、チップの電極形成面が下方を向いている。このため、上を向いている基板のチップ接合面(パターン形成面と反対側の面)に上方からチップの電極形成面を接合させることができる。 The die bonding apparatus (method) described in Patent Document 1 is for bonding the chip with the chip bonding surface (surface opposite to the pattern forming surface) of the substrate facing upward. In this case, the chips are picked up from the wafer by an inversion tool, and the picked up chips are inverted by the inversion tool. As a result, the electrode formation surface of the chip faces downward. Thereafter, a transfer tool is used to suck the opposite electrode forming surface of the chip from above. In this state, the electrode formation surface of the chip faces downward. Therefore, the electrode forming surface of the chip can be bonded from above to the chip bonding surface (surface opposite to the pattern forming surface) of the substrate facing upward.
 この特許文献1では、基板のパターン形成面(下方を向いている面)を、上方に配置したカメラで観察するものである。すなわち、基板が載置される基板載置台に透明部材を介してミラー部材を設け、このミラー部材のミラー面に映った反射画像を見るものである。この場合、反射画像は、基板に設けられたワイヤ挿通孔及び透明部材を通して、ミラー面に映った反射画像を映し出すというものである。 In Patent Document 1, the pattern formation surface of the substrate (the surface facing downward) is observed with a camera placed above. That is, a mirror member is provided through a transparent member on a substrate mounting table on which a substrate is mounted, and a reflected image reflected on the mirror surface of this mirror member is viewed. In this case, the reflected image is projected on the mirror surface through the wire insertion hole provided in the substrate and the transparent member.
 そして、この反射画像の基板側パターンの位置に基づいて基板とチップの位置合わせを行って、チップの電極形成面を基板のチップ接合面に接合する。 Then, the substrate and the chip are aligned based on the position of the pattern on the substrate side of the reflected image, and the electrode forming surface of the chip is bonded to the chip bonding surface of the substrate.
特開2009-200203号公報Japanese Patent Application Laid-Open No. 2009-200203
 しかしながら、特許文献1に記載のものでは、反射画像を用いることになる。反射画像を用いる場合、ワイヤ挿通孔及び透明部材を介するものであるので、観察範囲が限られ、また、ミラー面が精度の悪いものでは、正確な反射画像を得ることができない等の問題点がある。しかも、この反射画像の取得が、基板が加熱される部位であるため、接着剤が解ける際に発生するガスがミラーに堆積してミラーが曇る等の影響を受け、画像取得が安定しない。 However, the one described in Patent Document 1 uses a reflected image. When a reflected image is used, the observation range is limited because the wire insertion hole and the transparent member are interposed, and if the mirror surface is of poor precision, an accurate reflected image cannot be obtained. be. Moreover, since the acquisition of the reflected image is the part where the substrate is heated, the gas generated when the adhesive melts accumulates on the mirror, causing the mirror to become cloudy, and the image acquisition is unstable.
 また、特許文献1の装置では、透明部材及びミラー部材を設けた基板載置台を必要とし、装置全体として高精度に形成する必要がある部材(透明部材及びミラー部材を設けた基板載置台)を用いたり、基板に設けられたワイヤ挿通孔のサイズや基板の幅が変わると透明部材及びミラー部材を設けた基板載置台を交換する必要があるため、生産性に劣る。 In addition, the apparatus of Patent Document 1 requires a substrate mounting table provided with a transparent member and a mirror member, and the members (the substrate mounting table provided with the transparent member and the mirror member) that must be formed with high precision as the entire apparatus are required. When the size of the wire insertion hole provided in the substrate or the width of the substrate changes, the substrate mounting table provided with the transparent member and the mirror member must be replaced, resulting in poor productivity.
 そこで、本発明は、上記課題に鑑みて、安定した位置合わせができて、用いる装置として、既存のボンディング装置を用いることができるボンディング方法およびボンディング装置使用方法を提供する。 Therefore, in view of the above problems, the present invention provides a bonding method and a method of using a bonding apparatus that enable stable alignment and that can use an existing bonding apparatus as the apparatus to be used.
 本発明のボンディング方法は、厚さ方向に貫通したワイヤ挿通孔を有しかつパターン形成面側に位置決め用基準マークが形成された基板が、基板搬送路に沿って上流側から下流側へ搬送され、基板搬送路の下流側のボンディングポジションで、この基板におけるパターン形成面の基板側電極部の反対側のチップ接合面のチップ接合部に、チップの電極形成面を接合するボンディング方法であって、基板のパターン形成面を下方に向けて配設した状態で、基板搬送路の上流側における下方からの位置決め用基準マークとワイヤ挿通孔との位置関係を認識する基板認識工程と、ピックアップ側コレットでチップをピックアップするピックアップ工程と、ピックアップ側コレットでピックアップしたチップを反転させて電極形成面を下方に向ける反転工程と、反転工程で反転されたチップを電極形成面が下方に向けたままボンディング側コレットで受け取る受け取り工程と、認識工程にて認識された位置決め用基準マークとワイヤ挿通孔との位置関係と、ボンディングポジション上方からのワイヤ挿通孔の位置の認識とに基づいて、チップと基板側のチップ接合部との位置合わせを行う位置合わせ工程と、基板搬送路の下流側のボンディングポジションにおいて、位置合わせ工程にて位置合わせされた基板のチップ接合部に、受け取り工程で受け取ったチップを基板のチップ接合部に接合する接合工程とを備えたものである。 In the bonding method of the present invention, a substrate having a wire insertion hole penetrating in the thickness direction and having a positioning reference mark formed on the pattern forming surface side is transported from the upstream side to the downstream side along the substrate transport path. and bonding the electrode forming surface of the chip to the chip bonding portion of the chip bonding surface on the opposite side of the substrate-side electrode portion of the pattern forming surface of the substrate at a bonding position on the downstream side of the substrate transport path, comprising: A substrate recognizing step of recognizing the positional relationship between the positioning reference mark and the wire insertion hole seen from below on the upstream side of the substrate conveying path, with the pattern forming surface of the substrate facing downward, and a pick-up collet. A pick-up process for picking up the chip, a reversing process for reversing the chip picked up by the pick-up side collet and directing the electrode forming surface downward, and a bonding side collet with the electrode forming surface facing downward for the chip reversed in the reversing process. , the positional relationship between the positioning reference mark and the wire insertion hole recognized in the recognition step, and the recognition of the position of the wire insertion hole from above the bonding position, the chip and the chip on the substrate side. In an alignment step of aligning with the bonding portion, and at a bonding position on the downstream side of the substrate transport path, the chip received in the receiving step is attached to the chip bonding portion of the substrate aligned in the alignment step. and a bonding step of bonding to the bonding portion.
 本発明のボンディング方法によれば、基板認識工程にて、下方からのパターン形成面の直接画像に基づいて、位置決め用基準マークとワイヤ挿通孔との位置関係の認識を行うことができる。ピックアップ工程にて、チップをピックアップでき、このピックアップしたチップを反転工程にて、チップをチップ電極形成面が下方に向けた状態とすることができる。受け取り工程にて、電極形成面を下方に向けたままチップをボンディング側コレットで受け取ることができる。位置合わせ工程にて、位置決め用基準マークとワイヤ挿通孔との位置関係と、ボンディングポジション上方からのワイヤ挿通孔の位置の認識とに基づいて位置合わせを行うことができる。接合工程にて、位置合わせ工程にて位置合わせされた基板のチップ接合部に、受け取り工程で受け取ったチップを基板のチップ接合部に接合することができる。 According to the bonding method of the present invention, the positional relationship between the positioning reference marks and the wire insertion holes can be recognized based on the direct image of the pattern forming surface viewed from below in the substrate recognition process. A chip can be picked up in the pick-up process, and the picked-up chip can be brought into a state in which the chip electrode forming surface faces downward in the reversing process. In the receiving process, the chip can be received by the bonding-side collet with the electrode-formed surface facing downward. In the alignment process, alignment can be performed based on the positional relationship between the positioning reference marks and the wire insertion holes, and recognition of the position of the wire insertion holes from above the bonding position. In the bonding step, the chip received in the receiving step can be bonded to the chip bonding portion of the substrate aligned in the alignment step.
 基板認識工程では、下方を向いた基板のパターン形成面を基板の下方から観察できる。このため、観察面が間接画像ではないので、観察視野が規制されず、位置決め用基準マークとワイヤ挿通孔との位置関係を安定して高精度に観察できる。しかも、この画像観察を、加熱されない部位である基板搬送路の上流側で行うので、加熱手段(例えば、バックアッププレートに設けられる電気ヒータ等)を基板搬送路の下流側において、基板認識工程に用いるカメラ等に邪魔されずに配置することができる。すなわち、基板認識部位と基板加熱部位とを離れた位置に配設することができ、基板認識部位では、基板加熱の影響(接着剤が解ける際に発生するガス等による光学系への影響等)が生じず、基板加熱部位では、上方から基板のワイヤ挿通孔を認識しているが、接近した位置で基板認識を行わないので、基板の連続加熱が可能となる。また、チップを接合させる接合工程では、基板の上方から行うことができ、このボンディング方法としては、通常のフェースアップボンディング(チップの電極面を接着する場合)に用いることができる。 In the substrate recognition process, the pattern formation surface of the substrate facing downward can be observed from below the substrate. Therefore, since the observation surface is not an indirect image, the observation field is not restricted, and the positional relationship between the positioning reference mark and the wire insertion hole can be observed stably and with high accuracy. Moreover, since this image observation is performed on the upstream side of the substrate transport path, which is a portion that is not heated, heating means (for example, an electric heater provided on the backup plate) is used in the substrate recognition process on the downstream side of the substrate transport path. It can be placed without being obstructed by a camera or the like. That is, the substrate recognition part and the substrate heating part can be arranged at separate positions, and the influence of the substrate heating on the substrate recognition part (the influence of the gas generated when the adhesive melts, etc. on the optical system, etc.) In the substrate heating portion, the wire insertion hole of the substrate is recognized from above, but the substrate is not recognized at a close position, so that the substrate can be continuously heated. In addition, the bonding process for bonding the chip can be performed from above the substrate, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used.
 また、本ボンディング方法では、チップと基板のチップ接合面と接合するための接着剤として、上方を向いた状態のチップ接合面に配設されているので、比較的流動性を有するものでも下方へたれるおそれがない。このため、接着剤の塗布作業が容易で、しかも、接着剤として種々のものを用いることができ、低コスト化に寄与する。 In addition, in this bonding method, since the adhesive for bonding the chip and the chip bonding surface of the substrate is disposed on the chip bonding surface facing upward, even a relatively fluid material can be applied downward. There is no danger of dripping. Therefore, the adhesive application work is easy, and various kinds of adhesives can be used, which contributes to cost reduction.
 特に、位置合わせは、ボンディングポジションから離間した上流側の位置での位置決め用基準マークとワイヤ挿通孔との位置関係の認識と、ボンディングポジション上方からのワイヤ貫通孔の位置の認識に基づいて行うので、高精度の位置合わせが可能となる。すなわち、基準マークとパターン形成面の電極の位置関係は高精度に設定されているので、チップの接合面側(反パターン形成面側)からワイヤ挿通孔の位置を確認することによって、基準マークとワイヤ挿通孔との位置関係から、パターン形成面の電極(基板側電極部)の位置を検知することができ、これによって、基板のチップ接合面側のチップ接合部に正確にボンディングできて接合できる。ここで、チップ接合部とは、基板側電極部に相対応する部位である。 In particular, alignment is performed based on recognition of the positional relationship between the positioning reference mark and the wire insertion hole at a position on the upstream side away from the bonding position and recognition of the position of the wire insertion hole from above the bonding position. , high-precision alignment is possible. That is, since the positional relationship between the reference marks and the electrodes on the pattern formation surface is set with high accuracy, the positions of the wire insertion holes can be confirmed by confirming the positions of the wire insertion holes from the bonding surface side of the chip (the side opposite to the pattern formation surface). From the positional relationship with the wire insertion hole, the position of the electrode (substrate-side electrode portion) on the pattern forming surface can be detected, thereby enabling accurate bonding and bonding to the chip bonding portion on the chip bonding surface side of the substrate. . Here, the chip joint portion is a portion corresponding to the substrate-side electrode portion.
 ボンディング前にチップの位置認識を行うチップ認識工程を備えたものであってもよい。このように、チップ認識工程を備えたものでは、位置合わせ精度の向上を図ることができる。 A chip recognition process for recognizing the chip position before bonding may be provided. In this way, the alignment accuracy can be improved with the chip recognition process.
 接合工程において、基板を下方からバックアッププレートで受けるものであってもよい。このように、基板を下方からバックアッププレートで受けるものでは、チップを基板のチップ接合面に接合する際、ボンディング側コレットとバックアッププレートとでチップを挟むことができ、基板を湾曲等させることなく、安定した接合を得ることができる。 In the bonding process, the substrate may be received by a backup plate from below. In this way, when the substrate is supported by the backup plate from below, the chip can be sandwiched between the bonding-side collet and the backup plate when the chip is bonded to the chip bonding surface of the substrate. A stable bond can be obtained.
 また、このバックアッププレートは加熱手段に加熱されて、基板上の接着剤を加熱するように構成できる。このように構成することによって、加熱手段を別部材として設ける必要がなく、装置全体のコンパクト化に寄与する。 Also, this backup plate can be configured to be heated by a heating means to heat the adhesive on the substrate. This configuration eliminates the need to provide the heating means as a separate member, which contributes to downsizing of the entire apparatus.
 基板認識工程は、基板1枚分の位置情報を取得するものが好ましい。このように構成することによって、ボンディング工程を、1枚の基板の全てのチップ接合部に対して連続してチップを接合していくことができ、生産性の向上を図ることができる。 It is preferable that the board recognition process acquire position information for one board. With this configuration, the bonding process can be performed to continuously bond chips to all the chip bonding portions of one substrate, thereby improving productivity.
 本発明のボンディング装置使用方法は、ピックアップポジションにてピックアップ側コレットにてチップをピックアップし、ピックアップポジションでピックアップしたチップを反転させ、その反転させたチップをボンディングポジションにてボンディング側コレットにてボンディングするボンディング装置を用いた使用方法であって、前記ボンディング方法を行うことができる。 According to the method of using the bonding apparatus of the present invention, a chip is picked up by a pickup-side collet at a pickup position, the chip picked up at the pickup position is reversed, and the reversed chip is bonded at a bonding position by a bonding-side collet. A method of using a bonding apparatus, wherein the bonding method can be performed.
 本発明のボンディング装置使用方法は、既存の汎用のボンディング装置を用いることができ、コスト低減を図ることができる。 The method of using the bonding apparatus of the present invention can use an existing general-purpose bonding apparatus, and can reduce costs.
 本発明は、パターン形成面の観察が間接画像ではないので、観察視野が規制されず、パターン形成面を安定して高精度に観察でき、チップの基板への接合を高精度に安定して行うことができる。また、装置構成として、複雑化せず低コストにてチップを基板に接合できる。さらには、チップを接合させる接合工程では、基板の上方から行うことができ、このボンディング方法としては、通常のフェースアップボンディング(チップの電極面を接着する場合)に用いることができる。 In the present invention, since the observation of the patterned surface is not an indirect image, the field of view for observation is not restricted, the patterned surface can be observed stably and with high precision, and the chip is stably bonded to the substrate with high precision. be able to. In addition, the chip can be bonded to the substrate at low cost without complicating the device configuration. Furthermore, the bonding process for bonding the chip can be performed from above the substrate, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used.
本発明のボンディング方法に用いるボンディング装置の簡略斜視図である。1 is a simplified perspective view of a bonding apparatus used in the bonding method of the present invention; FIG. 基板のパターン形成面の要部拡大簡略図である。FIG. 2 is an enlarged schematic view of a main part of a pattern formation surface of a substrate; チップ接合面のチップ接合部の簡略図である。FIG. 4 is a simplified diagram of a chip bonding portion of a chip bonding surface; 基板を示し、チップ接合面のチップ接合部に接着剤を塗布した状態の簡略図である。FIG. 4 is a simplified diagram showing a substrate and a state in which an adhesive is applied to a chip bonding portion of a chip bonding surface; 基板の搬送機構を示す簡略平面図である。FIG. 3 is a simplified plan view showing a transport mechanism for substrates; 本発明のボンディング方法のブロック図である。1 is a block diagram of the bonding method of the present invention; FIG. 本発明のボンディング方法の前半の工程を示すブロック図である。It is a block diagram which shows the process of the first half of the bonding method of this invention. 本発明のボンディング方法の後半の工程を示すブロック図である。It is a block diagram showing the latter half of the process of the bonding method of the present invention. 従来のボンディング方法のボンディング方法を示す斜視図である。It is a perspective view which shows the bonding method of the conventional bonding method. 半導体装置(BOCタイプの半導体パッケージ)の断面図である。1 is a cross-sectional view of a semiconductor device (BOC type semiconductor package); FIG.
以下本発明の実施の形態を図1~図7に基づいて説明する。 An embodiment of the present invention will be described below with reference to FIGS. 1 to 7. FIG.
 図1に本発明に係るボンディング方法に用いるボンディング装置を示す。このボンディング装置は、基板31におけるパターン形成面31aの基板側電極部38の反対側のチップ接合面31bのチップ接合部34に、チップ32の電極形成面32aを接合するボンディング方法を行うことができる。 FIG. 1 shows a bonding apparatus used for the bonding method according to the present invention. This bonding apparatus can perform a bonding method of bonding the electrode forming surface 32a of the chip 32 to the chip bonding portion 34 of the chip bonding surface 31b on the opposite side of the substrate-side electrode portion 38 of the pattern forming surface 31a of the substrate 31. .
 基板31には、基板幅方向に延びる細長孔からなる複数個のワイヤ挿通孔33が設けられている。この場合、基板幅方向に沿って複数のワイヤ挿通孔33が配設されてワイヤ挿通孔群35を構成し、複数のワイヤ挿通孔群35は、基板長手方向に沿って所定ピッチで配設されている。 The substrate 31 is provided with a plurality of wire insertion holes 33 which are elongated holes extending in the width direction of the substrate. In this case, a plurality of wire insertion holes 33 are arranged along the substrate width direction to constitute a wire insertion hole group 35, and the plurality of wire insertion hole groups 35 are arranged at a predetermined pitch along the substrate longitudinal direction. ing.
 基板31のパターン形成面31a側には、図2に示すように、ワイヤ挿通孔33の両側に基板側電極36及びパッド37が設けられる基板側パターン(基板側電極部)38が形成され、また、基板31のチップ接合面31b(パターン形成面31aの反対側の面)のチップ接合部34は、図3Bに示すように、接着剤Sが配設(塗布)されている。この場合、一つのワイヤ挿通孔33に対して、ワイヤ挿通孔33を挟んで、一対の接着剤S,Sが塗布されている。接着剤Sとして、ペースト状の接着剤であっても、ダイアタッチフィルム(DAF)であってもよい。 As shown in FIG. 2, on the side of the pattern forming surface 31a of the substrate 31, a substrate-side pattern (substrate-side electrode portion) 38 having substrate-side electrodes 36 and pads 37 provided on both sides of the wire insertion hole 33 is formed. 3B, an adhesive S is applied (applied) to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31 (the surface opposite to the pattern forming surface 31a). In this case, a pair of adhesives S, S are applied to one wire insertion hole 33 with the wire insertion hole 33 interposed therebetween. The adhesive S may be a paste adhesive or a die attach film (DAF).
 ところで、基板31のパターン形成面31aには位置決め用基準マーク40(図3A参照)が形成されている。位置決め用基準マーク40(以下、単に基準マーク40と呼ぶ場合がある。)として、この実施形態では、基板31のパターン形成面31aに形成された金属膜の角部にて形成している。しかしながら、基準マーク40としては、これに限らず、特別に付与された着色マークや凹凸部などの目印であってもよい。 By the way, on the pattern formation surface 31a of the substrate 31, a positioning reference mark 40 (see FIG. 3A) is formed. In this embodiment, the positioning reference marks 40 (hereinafter sometimes simply referred to as reference marks 40) are formed at corners of a metal film formed on the pattern forming surface 31a of the substrate 31. FIG. However, the reference mark 40 is not limited to this, and may be a mark such as a specially provided colored mark or an uneven portion.
 この基板31は、図4に示すような、基板搬送手段41にて図1の矢印X方向に沿って搬送される。基板搬送手段41は、一対の搬送レール42,42を備えたものであり、この搬送レール42、42上に載置された基板31は、図示省略の把持機構(例えば、チャック機構等)を有する送り機構にて矢印X方向に沿って上流側から下流側へと搬送される。 The substrate 31 is transported along the direction of the arrow X in FIG. 1 by substrate transport means 41 as shown in FIG. The substrate conveying means 41 has a pair of conveying rails 42, 42, and the substrate 31 placed on the conveying rails 42, 42 has a grasping mechanism (for example, a chuck mechanism, etc.) (not shown). The sheet is conveyed from the upstream side to the downstream side along the arrow X direction by the feeding mechanism.
 また、基板31の搬送路の下流側のポンデング位置(ボンディングポジション)の下方には、搬送レール42,42間にバックアッププレート(アダプタプレート)43が配設される。このバックアッププレート43は、図示省略の加熱手段にて、加熱することができる。すなわち、バックアッププレート43を加熱することによって、基板31上のボンディングポジションに対応するチップ接合面31bの接着剤Sを加熱することができる。図示省略の加熱手段として、各種の電気加熱方式を用いることができる。 A backup plate (adapter plate) 43 is arranged between the transport rails 42, 42 below the bonding position (bonding position) on the downstream side of the transport path of the substrate 31. The backup plate 43 can be heated by heating means (not shown). That is, by heating the backup plate 43, the adhesive S on the chip bonding surface 31b corresponding to the bonding position on the substrate 31 can be heated. Various electric heating methods can be used as heating means (not shown).
 ところで、加熱手段にて、加熱されるバックアッププレート43として、基板搬送方向中央部が、ボンディング中における接着剤Sが解けて有効な接合力を発揮できる温度に基板31を加熱することができる接合温度ゾーンとなり、この基板搬送方向中央部の上流側及び下流側を接合温度ゾーンの加熱温度よりも低い温度に加熱でき低温加熱ゾーンを構成するのが好ましい。このように設定することによって、接合温度ゾーンがボンディングポジションに対応でき、また、基板31のチップ接合部34を、ボンディングポジションに位置させた際には、基板31のチップ接合部34を、接着剤Sを有効な接合力を発揮できる温度に加熱できる。しかも、基板31のチップ接合部34を、ボンディングポジションに位置させる前には、低温加熱ゾーンを通過するので、基板31のチップ接合部34を予備加熱することができて、作業効率の向上を図ることができる。 By the way, as the backup plate 43 heated by the heating means, the central portion in the substrate conveying direction can heat the substrate 31 to a temperature at which the adhesive S during bonding can be melted and effective bonding force can be exhibited. It is preferable to constitute a low-temperature heating zone that can be heated to a temperature lower than the heating temperature of the bonding temperature zone on the upstream side and the downstream side of the central portion in the substrate transfer direction. By setting in this way, the bonding temperature zone can correspond to the bonding position, and when the chip bonding portion 34 of the substrate 31 is positioned at the bonding position, the chip bonding portion 34 of the substrate 31 can be S can be heated to a temperature at which effective bonding strength can be exhibited. Moreover, since the chip bonding portion 34 of the substrate 31 passes through the low-temperature heating zone before being positioned at the bonding position, the chip bonding portion 34 of the substrate 31 can be preheated, thereby improving working efficiency. be able to.
 また、このボンディング装置は、ワークであるチップ32をピックアップするピックアップ機構50と、このピックアップ機構50にてピップアップしたチップ32を基板31のチップ接合面31bのチップ接合部34に接合するためのボンディング機構51と、基板搬送路の上流側において、基板31の裏面側のパターン形成面31aを下方から観察する観察手段53等を備える。 This bonding apparatus also includes a pickup mechanism 50 for picking up a chip 32 as a workpiece, and a bonding mechanism for bonding the chip 32 picked up by the pickup mechanism 50 to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31. A mechanism 51 and observation means 53 for observing the pattern formation surface 31a on the back side of the substrate 31 from below are provided on the upstream side of the substrate transport path.
 チップ32は、ウエハ素材とし、この素材を矩形状に切断することによって最終製品となる。このため、チップ32には正方形や短冊状のもの等がある。すなわち、ウエハは全体として円形であり、ダイシングにより個々のチップ32に分割される。 The chip 32 is made from a wafer material, and cut into a rectangular shape to form the final product. For this reason, the chip 32 may be square, strip-shaped, or the like. That is, the wafer is generally circular and is divided into individual chips 32 by dicing.
 ピックアップ機構50は、先端側にピックアップアーム55が付設されたピックアップヘッド56を備え、このピックアップアーム55の先端にコレット57が取付られている。コレット57の先端面には先端面に開口する複数個の図示省略の吸着孔が設けられ、吸着孔を介してチップ32が真空吸引され、このコレット57の先端面にチップ32が吸着される。なお、真空吸引(真空引き)が解除されれば、コレット57からチップ32が外れる。また、真空吸引(真空引き)は図示省略の真空機構で行われる、真空機構としては、真空ポンプや真空エジェクタ等が使用される。 The pickup mechanism 50 has a pickup head 56 with a pickup arm 55 attached to the tip side, and a collet 57 is attached to the tip of the pickup arm 55 . A plurality of suction holes (not shown) that open to the tip surface of the collet 57 are provided on the tip surface of the collet 57 , and the tip 32 is vacuum-sucked through the suction holes, and the tip 32 is attached to the tip surface of the collet 57 . Note that the chip 32 is removed from the collet 57 when the vacuum suction (vacuum drawing) is released. Further, vacuum suction (vacuum drawing) is performed by a vacuum mechanism (not shown). As the vacuum mechanism, a vacuum pump, a vacuum ejector, or the like is used.
 また、ピックアップヘッド56は反転機構58を有し、ピックアップアーム55の先端のコレット57を反転させることができる。反転機構58は、ピックアップヘッド56をその軸心回りに回動させる駆動機構(例えば、モータ等)を備えたものであり、ピックアップアーム55を、コレット57の吸着面である先端面が下方を向く姿勢と、コレット57の吸着面である先端面が上方を向く姿勢とに変更可能とする。また、このピックアップ機構50は、そのピックアップヘッド56は、図示省略の上下動機構で矢印Z1,Z2で示すように上下動が可能とされる。なお、この上下動機構としては、シリンダ機構、ボールねじ機構、リニアモータ機構等の種々の往復動機構で構成できる。ウエハ上方にあるチップ32を認識する図示省略の認識部(認識手段)に基づいてコレット57の位置を補正するために矢印X3,X4及び矢印Y1、Y2方向の移動が可能となっている。なお、矢印X3,X4は、基板31の長手方向(基板の搬送方向)と平行な方向に沿った往復動を示し、矢印Y1,Y2は、矢印X3,X4と直交する方向の往復動である。 In addition, the pickup head 56 has a reversing mechanism 58 that can reverse the collet 57 at the tip of the pickup arm 55 . The reversing mechanism 58 has a drive mechanism (for example, a motor, etc.) that rotates the pickup head 56 around its axis. It is possible to change the attitude between the posture and the posture in which the tip end surface, which is the suction surface of the collet 57, faces upward. The pickup head 56 of the pickup mechanism 50 can be vertically moved as indicated by arrows Z1 and Z2 by a vertical movement mechanism (not shown). The vertical movement mechanism can be composed of various reciprocating mechanisms such as a cylinder mechanism, a ball screw mechanism, and a linear motor mechanism. In order to correct the position of the collet 57 based on a recognition unit (recognition means) not shown that recognizes the chip 32 above the wafer, it is possible to move in the directions of arrows X3, X4 and arrows Y1, Y2. Arrows X3 and X4 indicate reciprocating motion in a direction parallel to the longitudinal direction of the substrate 31 (transporting direction of the substrate), and arrows Y1 and Y2 indicate reciprocating motion in a direction perpendicular to the arrows X3 and X4. .
 ボンディング機構51は、ボンディングヘッド60を備え、ボンディングアーム61の先端にコレット62が取付られている.コレット62の下面(先端面)には先端面に開口する複数個の図示省略の吸着孔が設けられ、吸着孔を介してチップ32が真空吸引され、このコレット62の先端面にチップ32が吸着される。なお、真空吸引(真空引き)が解除されれば、コレット62からチップ32が外れる。また、真空吸引(真空引き)は図示省略の真空機構で行われる、真空機構としては、真空ポンプや真空エジェクタ等が使用される。 The bonding mechanism 51 has a bonding head 60 and a collet 62 attached to the tip of a bonding arm 61 . A plurality of suction holes (not shown) that open to the tip surface are provided on the lower surface (tip surface) of the collet 62 , and the tip 32 is vacuum-sucked through the suction holes. be done. Note that the chip 32 is removed from the collet 62 when the vacuum suction (vacuum drawing) is released. Further, vacuum suction (vacuum drawing) is performed by a vacuum mechanism (not shown). As the vacuum mechanism, a vacuum pump, a vacuum ejector, or the like is used.
 また、ボンディングヘッド60は、図示省略の移動機構を介して、基板31の長手方向の矢印X1,X2方向、幅方向の矢印A、B方向、及び上下方向の矢印C、D方向の移動が可能とされる。移動機構としては、シリンダ機構、ボールねじ機構、リニアモータ機構等の種々の往復動機構で構成できる。 In addition, the bonding head 60 can be moved in the longitudinal direction of the substrate 31 in the directions of arrows X1 and X2, in the direction of arrows A and B in the width direction, and in the direction of arrows C and D in the vertical direction through a moving mechanism (not shown). It is said that As the moving mechanism, various reciprocating mechanisms such as a cylinder mechanism, a ball screw mechanism, and a linear motor mechanism can be used.
 観察手段53は、基板搬送路の上流側の下方に配置されるカメラ機構65を備える。すなわち、カメラ機構65は、画像認識カメラ(例えば、CCDカメラやCOMSカメラ等)からなるカメラ本体66と、このカメラ本体66の画像視野を形成する光学系67とを備える。この場合の光学系67は、所定視野の基板のパターン形成面31aの画像を、カメラ本体66に入光させるためのミラー部材68を備える。なお、この観察手段53の観察視野は、2点鎖線で示す範囲である。 The observation means 53 includes a camera mechanism 65 arranged below the upstream side of the substrate transport path. That is, the camera mechanism 65 includes a camera body 66 composed of an image recognition camera (for example, a CCD camera, a CMOS camera, etc.) and an optical system 67 that forms the image field of the camera body 66 . In this case, the optical system 67 includes a mirror member 68 for allowing the image of the pattern forming surface 31 a of the substrate in a predetermined field of view to enter the camera body 66 . Note that the observation field of view of the observation means 53 is a range indicated by a two-dot chain line.
 また、このボンディング装置では、チップ32のボンディング位置上方に、基板31のワイヤ挿通孔33を認識する挿通孔認識手段71が設けられている。さらに、ピックアップ機構50の上方には、ピックアップ機構50にてピックアップして、反転させた状態で、チップ32を確認する第1チップ認識手段72が配置されているとともに、ボンディング機構51側には、ボンディング側コレット62に吸着保持されたチップ32を認識する第2チップ認識手段73が設けられている。 Further, in this bonding apparatus, an insertion hole recognizing means 71 for recognizing the wire insertion holes 33 of the substrate 31 is provided above the bonding position of the chip 32 . Further, above the pickup mechanism 50, a first chip recognizing means 72 for confirming the chip 32 in an inverted state after being picked up by the pickup mechanism 50 is arranged, and on the bonding mechanism 51 side, A second chip recognition means 73 is provided for recognizing the chip 32 sucked and held by the bonding collet 62 .
 挿通孔認識手段71及び第1チップ認識手段72としては、CCDカメラやCOMSカメラ等で構成できる。また、第2チップ認識手段73は、画像認識カメラ(例えば、CCDカメラやCOMSカメラ等)からなるカメラ本体74と、このカメラ本体74の画像視野を形成する光学系75とを備える。この場合の光学系75は、チップ32の画像を、カメラ本体74に入光させるためのミラー部材76を備える。 The insertion hole recognizing means 71 and the first chip recognizing means 72 can be configured with a CCD camera, a CMOS camera, or the like. The second chip recognition means 73 also includes a camera body 74 consisting of an image recognition camera (for example, a CCD camera, a CMOS camera, etc.) and an optical system 75 that forms the image field of the camera body 74 . The optical system 75 in this case includes a mirror member 76 for making the image of the chip 32 enter the camera body 74 .
 第1チップ認識手段72のチップ32の観察と第2チップ認識手段73のチップ32の観察とで、ボンディング前のチップ32の位置認識を行う、つまり、後述するチップ認識工程87,88を行うことができる。すなわち、第1チップ認識手段72が、ピックアップ側コレット57で吸着されているチップ32の位置認識を行い、第2チップ認識手段73が、ボンディング側コレット62で吸着されているチップ32の位置認識を行うことになる。これらの位置認識が、チップ32をボンディングする際の位置合わせに用いられる。 By observing the chip 32 by the first chip recognizing means 72 and observing the chip 32 by the second chip recognizing means 73, position recognition of the chip 32 before bonding is performed, that is, chip recognition steps 87 and 88, which will be described later, are performed. can be done. That is, the first chip recognition means 72 recognizes the position of the chip 32 sucked by the pick-up collet 57, and the second chip recognition means 73 recognizes the position of the chip 32 sucked by the bonding collet 62. will do. These positional recognitions are used for alignment when bonding the chip 32 .
 ところで、基板搬送手段41、ピックアップ機構50、及びボンディング機構51とは、図示省略のコンピュータで制御される。ここで、コンピュータは、コンピュータは、基本的には、入力機能を備えた入力手段と、出力機能を備えた出力手段と、記憶機能を備えた記憶手段と、演算機能を備えた演算手段と、制御機能を備えた制御手段にて構成される。 By the way, the substrate transport means 41, the pick-up mechanism 50, and the bonding mechanism 51 are controlled by a computer (not shown). Here, the computer basically comprises input means with an input function, output means with an output function, storage means with a storage function, and arithmetic means with an arithmetic function. It is composed of control means having a control function.
 入力機能は、外部からの情報を、コンピュータに読み取るためのものであって、読み込まれたデータやプログラムは、コンピュータシステムに適した形式の信号に変換される。出力機能は、演算結果や保存されているデータなどを外部に表示するものである。記憶手段は、プログラムやデータ、処理結果などを記憶して保存するものである。演算機能は、データをプログラムの命令に随って、計算や比較して処理するものである。制御機能は、プログラムの命令を解読し、各手段に指示を出すものであり、この制御機能はコンピュータの全手段の統括をする。入力手段には、キーボード、マウス、タブレット、マイク、ジョイスティック、スキャナ、キャプチャーボード等がある。また、出力手段には、モニタ、スピーカー、プリンタ等がある。記憶手段には、メモリ、ハードディスク、CD・CD-R,PD・MO等がある。演算手段には、CPU等があり、制御手段には、CPUやマザーボード等がある。 The input function is for reading information from the outside into the computer, and the read data and programs are converted into signals in a format suitable for the computer system. The output function is to display the calculation results, stored data, etc. to the outside. The storage means stores and saves programs, data, processing results, and the like. Arithmetic functions process data by performing calculations and comparisons according to program instructions. The control function interprets the instructions of the program and issues instructions to each means, and this control function controls all the means of the computer. Input means include keyboards, mice, tablets, microphones, joysticks, scanners, capture boards, and the like. Output means include a monitor, a speaker, a printer, and the like. Storage means include memory, hard disk, CD/CD-R, PD/MO, and the like. The calculation means includes a CPU and the like, and the control means includes a CPU, a motherboard, and the like.
 次に、上述のように構成されたボンディング装置で、基板31におけるパターン形成面31aの基板側電極部38の反対側のチップ接合面31bのチップ接合部34に、チップ32の電極形成面32aを接合するボンディング方法を説明する。この場合、チップ接合部34は、基板側電極部38の反対面に相対応している。このボンディング方法は、図5に示すように、基板認識工程81と、ピックアップ工程82と、反転工程83と、受け取り工程84と、位置合わせ工程85と、接合工程86とを備える。また、この実施形態では、反転工程83と受け取り工程84との間に、第1チップ認識工程87が設けられ、受け取り工程84と位置合わせ工程85との間に、第2チップ認識工程88が設けられる。 Next, using the bonding apparatus configured as described above, the electrode forming surface 32a of the chip 32 is attached to the chip bonding portion 34 of the chip bonding surface 31b on the opposite side of the substrate-side electrode portion 38 of the pattern forming surface 31a of the substrate 31. A bonding method for joining will be described. In this case, the chip joint portion 34 corresponds to the opposite surface of the board-side electrode portion 38 . This bonding method includes a substrate recognition process 81, a pick-up process 82, an inversion process 83, a receiving process 84, an alignment process 85, and a bonding process 86, as shown in FIG. In this embodiment, a first chip recognition process 87 is provided between the reversing process 83 and the receiving process 84, and a second chip recognition process 88 is provided between the receiving process 84 and the alignment process 85. be done.
 基板認識工程81は、基板31のパターン形成面31aを下方に向けて配設した状態で、下方からのパターン形成面31aの直接画像に基づいて、パターン形成面31aの基板側パターンの位置の認識を行う工程である。ピックアップ工程82は、ピックアップ側コレット57を介してチップ32をピックアップする工程である。反転工程83は、ピックアップ側コレット57でピックアップしたチップ32を反転させて電極形成面32aを下方に向ける工程である。受け取り工程84は、反転工程83で反転されたチップ32を電極形成面32aを下方に向けたままボンディング側コレット62で受け取る工程である。位置合わせ工程85は、認識工程81にて認識されたパターン形成面31aの基板側パターン(基板側電極部38)の位置に基づいて基板31と受け取り工程84にて受け取ったチップ32との位置合わせを行う工程である。接合工程86は、位置合わせ工程にて基板31と位置合わせされたチップ32をボンディング側コレットで基板31のチップ接合面31bのチップ接合部34に接合する工程である。 In the substrate recognizing step 81, the position of the substrate-side pattern on the pattern forming surface 31a is recognized based on a direct image of the pattern forming surface 31a from below, with the pattern forming surface 31a of the substrate 31 facing downward. It is a process of performing A pick-up step 82 is a step of picking up the chip 32 via the pick-up collet 57 . The reversing step 83 is a step of reversing the chip 32 picked up by the pickup-side collet 57 so that the electrode forming surface 32a faces downward. The receiving step 84 is a step of receiving the chip 32 reversed in the reversing step 83 with the bonding side collet 62 with the electrode forming surface 32a facing downward. The alignment step 85 aligns the substrate 31 with the chip 32 received in the receiving step 84 based on the position of the substrate-side pattern (substrate-side electrode portion 38 ) on the pattern forming surface 31 a recognized in the recognition step 81 . It is a process of performing The bonding step 86 is a step of bonding the chip 32 aligned with the substrate 31 in the alignment step to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31 with the bonding-side collet.
 第1チップ認識工程87は、第1チップ認識手段72にて、ピックアップ側コレット57に、反チップ側電極が上を向いた状態で吸着されているチップ32を上方から観察する工程である。第2チップ認識工程88は、第2チップ認識手段73にて、ボンディング側コレット62に。電極形成面32aが下を向いた状態で吸着されているチップ32を下方から観察する工程である。 The first chip recognizing step 87 is a step of observing from above the chip 32 attracted to the pick-up side collet 57 by the first chip recognizing means 72 with the counter-chip side electrode facing upward. In the second chip recognition process 88 , the bonding side collet 62 is detected by the second chip recognition means 73 . This is a step of observing from below the chip 32 sucked with the electrode forming surface 32a facing downward.
 次に、前記各工程81,82,83、87,84,88,85,86を備えたボンディング方法を図6及び図7のフローチャート図を用いて説明する。まず、基板搬送路の上流側にパターン形成面31aが下方を向いた状態で配置する。この状態で、基板認識工程81、つまり基板認識を行う(ステップS1)。この場合、ワイヤ挿通孔33は、一般的には精度よく形成されていないので、パターン形成面31aに設けられた基準マークを基準に、ワイヤ挿通孔33の位置を認識することになる。この場合、一枚の基板31におけるチップ接合部34の位置情報を取得する。すなわち、全てのワイヤ挿通孔33の位置の確認を行う。この位置情報は、コンピュータの記憶手段に記憶する。 Next, the bonding method including the steps 81, 82, 83, 87, 84, 88, 85, and 86 will be described with reference to the flow charts of FIGS. 6 and 7. FIG. First, the substrate is placed on the upstream side of the substrate transport path with the pattern forming surface 31a facing downward. In this state, the substrate recognition step 81, that is, substrate recognition is performed (step S1). In this case, since the wire insertion hole 33 is generally not formed with high accuracy, the position of the wire insertion hole 33 is recognized based on the reference mark provided on the pattern forming surface 31a. In this case, the positional information of the chip joint portion 34 on one substrate 31 is acquired. That is, the positions of all wire insertion holes 33 are confirmed. This position information is stored in the storage means of the computer.
 次に、ピックアップ機構50によるピックアップ工程、つまりチップ32をピックアップポジションでチップ32をピックアップする(ステップS2)。すなわち、ピックアップポジションの上方に位置したピックアップ側コレット57を図1の矢印Z1のように下降させて、一枚のチップ32をこのコレット57に吸着させて、図1の矢印Z2のように、コレット57を上昇させる。これによって、チップ32をピックアップすることができる。 Next, the pick-up process by the pick-up mechanism 50, that is, the chip 32 is picked up at the pick-up position (step S2). That is, the pickup-side collet 57 located above the pickup position is lowered as indicated by arrow Z1 in FIG. Raise 57. Thereby, the chip 32 can be picked up.
 その後は、反転工程83を行う。すなわち、ピックアップ機構50において、ピックアップヘッド56を180°反転させることによって、チップ32を反転させる(ステップS3)。この場合、時計廻りであっても反時計廻りであってもよい。この場合、チップ32の電極形成面32aは下方を向くことになる。 After that, the reversing process 83 is performed. That is, in the pickup mechanism 50, the tip 32 is inverted by inverting the pickup head 56 by 180° (step S3). In this case, it may be clockwise or counterclockwise. In this case, the electrode formation surface 32a of the chip 32 faces downward.
 次に、ステップS4へ移行して、チップ32の位置認識をするか否かの判断を行う。ステップS4で位置認識しないと判断すれば、ステップS5へ移行して反転させたチップ32を受け取る受け取り工程を行う。ステップS4で、位置認識すると判断すれば、ステップS6へ移行してチップ32の位置認識をする。すなわち、第1チップ認識手段72で、チップ32を撮像して、チップ32の位置を確認する。 Next, the process proceeds to step S4 to determine whether or not to recognize the position of the tip 32. If it is determined in step S4 that the position is not recognized, the process proceeds to step S5 to perform a receiving process for receiving the inverted chip 32. FIG. If it is determined in step S4 that the position should be recognized, the process proceeds to step S6 to recognize the position of the tip 32. FIG. That is, the chip 32 is imaged by the first chip recognition means 72 and the position of the chip 32 is confirmed.
 ステップS5では、反転させたチップ32をボンディング機構51にて受け取る。すなわち、反転しているチップ32の上方に、ボンディング側コレット62を位置させて、このコレット62にチップ32を吸引する。この際、ピックアップ側コレット57の吸引を解除する。これによって、チップ32がボンディング側コレット62の下面である吸着面にチップ32が吸着する。この場合、チップ32はその電極形成面32aが下方を向いている状態である。 In step S5, the inverted chip 32 is received by the bonding mechanism 51. That is, the bonding-side collet 62 is positioned above the inverted chip 32 and the chip 32 is sucked to this collet 62 . At this time, the suction of the pickup-side collet 57 is released. As a result, the chip 32 is attracted to the attraction surface, which is the lower surface of the bonding-side collet 62 . In this case, the electrode forming surface 32a of the chip 32 faces downward.
 その後は、図7のステップS7に移行する。ステップS7では、チップ32の位置確認を行うかを判断する。ステップS7で、位置確認を行わない場合、ステップS8へ移行し、ステップS7で、位置確認を行う場合、ステップS9へ移行して位置確認を行った後、ステップS8へ移行する。ステップS7で位置確認を行う場合、第2チップ認識手段73で、チップ32を撮像して、チップ32の位置を確認する。 After that, the process moves to step S7 in FIG. In step S7, it is determined whether the position of the chip 32 should be confirmed. If the position is not to be confirmed in step S7, the process proceeds to step S8. If the position is to be confirmed in step S7, the process proceeds to step S9, the position is confirmed, and then the process proceeds to step S8. When the position is confirmed in step S7, the chip 32 is imaged by the second chip recognition means 73 and the position of the chip 32 is confirmed.
 ステップS8では、基板31とチップ32との位置合わせ行う。この場合、チップ34が接合すべき基板31のチップ接合部34がボンディングポジション上に位置するように、基板31は基板搬送手段41にて、基板搬送路の上流側から下流側へ搬送されている。 In step S8, the substrate 31 and the chip 32 are aligned. In this case, the substrate 31 is transported from the upstream side to the downstream side of the substrate transport path by the substrate transport means 41 so that the chip bonding portion 34 of the substrate 31 to which the chip 34 is to be bonded is positioned above the bonding position. .
 ステップS8では、基板31の、パターン形成面31aの基準マーク40とワイヤ挿通孔33との関係と、挿通孔認識手段71にて確認したワイヤ挿通孔33の位置認識とに基づいて、チップ32とチップ接合部34との位置合わせを行うものである。この場合、挿通孔認識手段71で、チップ32を接合すべきチップ接合部のワイヤ挿通孔33を認識する。そして、記録されている基準マーク40とワイヤ挿通孔33との位置関係と、挿通孔認識手段71で認識したチップ接合部34のワイヤ挿通孔33とを比較する。この場合、アイランド(チップ接合部34)間ピッチに合わせて精度よく形成された基準マーク40に対して、ワイヤ挿通孔33の位置がチップ接合部34毎に異なるので、位置ずれ(認識手段71で認識したワイヤ挿通孔33と、基準マーク40との位置ずれ)が生じることになり、認識手段71にて確認されたワイヤ挿入孔33から、認識手段71で認識した位置ずれ量に基づいて、基板31の基準マーク40とチップ32の電極位置(あるいはチップ32の外形位置)の位置合わせを行う必要がある。なお、位置ずれしていない場合もありうる。位置ずれしていない場合は位置合わせを行う必要がない。 In step S8, based on the relationship between the reference marks 40 on the pattern forming surface 31a of the substrate 31 and the wire insertion holes 33 and the position recognition of the wire insertion holes 33 confirmed by the insertion hole recognition means 71, the chip 32 and the wire insertion hole 33 are detected. Alignment with the chip joint portion 34 is performed. In this case, the wire insertion hole 33 of the chip bonding portion to which the chip 32 is to be bonded is recognized by the insertion hole recognizing means 71 . Then, the positional relationship between the recorded reference mark 40 and the wire insertion hole 33 is compared with the wire insertion hole 33 of the chip joint 34 recognized by the insertion hole recognition means 71 . In this case, since the positions of the wire insertion holes 33 are different for each chip bonding portion 34 with respect to the reference marks 40 that are accurately formed in accordance with the pitch between the islands (chip bonding portions 34), the positional deviation (by the recognition means 71) The positional deviation between the recognized wire insertion hole 33 and the reference mark 40 occurs, and the wire insertion hole 33 recognized by the recognition means 71 is detected by the board based on the amount of positional deviation recognized by the recognition means 71 . It is necessary to align the reference mark 40 of 31 with the electrode position of the tip 32 (or the outer shape position of the tip 32). It should be noted that there may be a case where the position is not shifted. If there is no misalignment, there is no need to perform alignment.
 ところで、この実施形態では、第1・第2チップ認識工程87,88で、ボンディング前にチップ32の位置認識を行うことができるので、このチップ認識工程87,88で検出したボンディング前のチップ32の位置情報を本位置合わせの際に利用することができる。これによって、より高精度の位置合わせが可能となる。すなわち、第1・第2チップ認識工程87,88で得たチップ32の位置情報は、前記コンピュータに入力され、この情報を含めて位置ずれを演算して、位置合わせを行うことになる。 By the way, in this embodiment, since the position of the chip 32 can be recognized before bonding in the first and second chip recognition processes 87 and 88, the position of the chip 32 before bonding detected in the chip recognition processes 87 and 88 can be detected. can be used for this alignment. This enables more precise alignment. That is, the positional information of the chip 32 obtained in the first and second chip recognition steps 87 and 88 is inputted to the computer, and positional alignment is performed by calculating the positional deviation including this information.
 ところで、位置ずれとしては、基板31の長手方向に位置ずれている場合と、基板31の幅方向に位置ずれとている場合と、長手方向及び幅方向に位置ずれている場合がある。長手方向に位置ずれている場合、ボンディング側コレット62の位置を矢印X1,X2方向に変位させ、幅方向に位置ずれていれば、ボンディング側コレット62の位置を矢印A,B方向に変位させ、長手方向及び幅方向に位置ずれている場合、ボンディング側コレット62の位置を矢印X1,X2、A,B方向に変位させればよい。 By the way, as the positional deviation, there are cases of positional deviation in the longitudinal direction of the substrate 31, cases of positional deviation in the width direction of the substrate 31, and cases of positional deviation in the longitudinal direction and the width direction. If the position is shifted in the longitudinal direction, the position of the bonding side collet 62 is displaced in the directions of arrows X1 and X2; if the position is shifted in the width direction, the position of the bonding side collet 62 is displaced in the directions of arrows A and B; If the position is shifted in the longitudinal direction and the width direction, the position of the bonding side collet 62 may be displaced in the directions of arrows X1, X2, A and B.
 ステップS10では、位置合わせされた状態で、チップ32をボンディングすることになる。この場合、ピックアップ側コレット57から、チップ32を受け取ったボンディング側コレット62を矢印Cのように、上昇させた後、矢印Aのように、チップ接合部の上方まで移動させた状態となっており、その後、ボンディング側コレット62を下降させて接合する。なお、位置合わせは、ボンディング側コレット62の動作中に行うことができるが、チップ34がコレット57による吸着されて反転さえている状態のチップ34の位置確認を終わった状態で、位置合わせを行っても、チップ34がコレット62による吸着されている状態のチップ34の位置確認を終わった状態で、位置合わせを行ってもよい。 In step S10, the chips 32 are bonded in the aligned state. In this case, the bonding-side collet 62 receiving the chip 32 from the pickup-side collet 57 is lifted as indicated by arrow C, and then moved to above the chip bonding portion as indicated by arrow A. , and then the bonding side collet 62 is lowered for bonding. The alignment can be performed while the bonding-side collet 62 is operating. However, the alignment is performed after the position of the chip 34, which is being sucked by the collet 57 and inverted, has been confirmed. Alternatively, alignment may be performed after confirming the position of the tip 34 sucked by the collet 62 .
 また、このボンディング工程中においては、バックアッププレート43が加熱されており、接着剤が接合可能の温度に上昇している。このため、コレット62を下降させて、このコレット62とバックアッププレート43で基板31を挟むことになって、チップ32を接着剤Sを介して接合することになる。このように、チップ32をチップ接合部34にボンディングする際には、位置合わせ工程によって、チップ32の電極形成面32aを、基板31のチップ接合面31bのチップ接合部34に正確に接合させることができる。 Also, during this bonding process, the backup plate 43 is heated to a temperature at which the adhesive can be bonded. Therefore, the collet 62 is lowered, and the substrate 31 is sandwiched between the collet 62 and the backup plate 43, and the chip 32 is joined with the adhesive S. FIG. Thus, when bonding the chip 32 to the chip bonding portion 34, the electrode forming surface 32a of the chip 32 is accurately bonded to the chip bonding portion 34 of the chip bonding surface 31b of the substrate 31 by the alignment process. can be done.
 その後は、ステップS11へ移行して、この工程(作業)を終了するか否かを判断する。終了するとの判断であれば、終了し、ステップS10で終了しないと判断すれば、ステップS2へ戻る。このように、このステップS2からステップS10までの工程を行うことによって、1枚の基板31の全部のチップ接合部にチップを接合することができる。 After that, move to step S11 to determine whether or not to end this process (work). If it is determined to end, the process ends, and if it is determined not to end in step S10, the process returns to step S2. Thus, chips can be bonded to all the chip bonding portions of one substrate 31 by performing the steps from step S2 to step S10.
 基板認識工程81では、下方を向いた基板31のパターン形成面31aを基板31の下方から観察できる。このため、パターン形成面31aの観察が間接画像ではないので、観察視野が規制されず、パターン形成面31aを安定して高精度に観察できる。しかも、この画像観察を、加熱されない部位である基板搬送路の上流側で行うので、加熱手段(例えば、バックアッププレートに設けられる加熱手段等)を基板搬送路の下流側において、この基板認識工程に用いるカメラ等に邪魔されずに配置することができる。すなわち、基板認識部位と基板加熱部位とを離れた位置に配設することができ、位置決め用基準マーク40とワイヤ挿通孔33との位置関係を、基板31が加熱されないところで認識することができる。このため、基板認識部位では、基板加熱の影響(接着剤が解ける際に発生するガス等による光学系への影響等)が生じず、基板加熱部位では、上方から基板31のワイヤ挿通孔33を認識(図1の認識部としての挿通孔認識手段71による認識)しているが、接近した位置で基板認識を行わないので、基板認識を行わないので、基板31の連続加熱が可能となる。また、チップ32を接合させる接合工程86では、基板31の上方から行うことができ、このボンディング方法としては、通常のフェースアップボンディング(チップの電極面を接着する場合)に用いることができる。 In the substrate recognition step 81, the pattern formation surface 31a of the substrate 31 facing downward can be observed from below the substrate 31. Therefore, since the observation of the pattern-formed surface 31a is not an indirect image, the observation field of view is not restricted, and the pattern-formed surface 31a can be observed stably and with high accuracy. Moreover, since this image observation is performed on the upstream side of the substrate transport path, which is a portion that is not heated, the heating means (for example, the heating means provided on the backup plate) is placed downstream of the substrate transport path in the substrate recognition process. It can be arranged without being obstructed by the camera or the like used. That is, the board recognition part and the board heating part can be arranged at separate positions, and the positional relationship between the positioning reference mark 40 and the wire insertion hole 33 can be recognized in a place where the board 31 is not heated. Therefore, the substrate recognition portion is not affected by the heating of the substrate (such as the influence of the gas generated when the adhesive melts on the optical system, etc.). Although recognition is performed (recognition by the insertion hole recognition means 71 as the recognition portion in FIG. 1), since board recognition is not performed at a close position, continuous heating of the board 31 is possible. Also, the bonding process 86 for bonding the chip 32 can be performed from above the substrate 31, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used.
 また、本ボンディング方法では、チップ32と基板31のチップ接合面31bとを接合するための接着剤Sとして、上方を向いた状態のチップ接合面31bに配設さてれるので、比較的流動性を有するものでも下方へたれるおそれがない。このため、接着剤Sの塗布作業が容易で、しかも、接着剤Sとして種々のものを用いることができ、低コスト化に寄与する。 In addition, in this bonding method, since the adhesive S for bonding the chip 32 and the chip bonding surface 31b of the substrate 31 is disposed on the chip bonding surface 31b facing upward, it is relatively fluid. There is no danger of it falling down even if you have it. Therefore, the application work of the adhesive S is easy, and various kinds of adhesives can be used as the adhesive S, which contributes to cost reduction.
 本発明は、パターン形成面31aの観察が間接画像ではないので、観察視野が規制されず、パターン形成面31aを安定して高精度に観察でき、チップ32の基板31への接合を高精度に安定して行うことができる。また、装置構成として、複雑化せず低コストにてチップ32を基板31に接合できる。さらには、チップ32を接合させる接合工程86では、基板31の上方から行うことができ、このボンディング方法としては、通常のフェースアップボンディング(チップの電極面を接着する場合)に用いることができる。しかも、基板31の連続加熱が可能となり、生産性に優れる。 In the present invention, since the observation of the pattern-formed surface 31a is not an indirect image, the observation field of view is not restricted, the pattern-formed surface 31a can be observed stably and accurately, and the bonding of the chip 32 to the substrate 31 can be performed with high accuracy. can be done stably. In addition, the chip 32 can be bonded to the substrate 31 at low cost without complicating the device configuration. Furthermore, the bonding process 86 for bonding the chip 32 can be performed from above the substrate 31, and as this bonding method, normal face-up bonding (when bonding the electrode surface of the chip) can be used. Moreover, continuous heating of the substrate 31 is possible, and the productivity is excellent.
 基板31のパターン形成面31aが形成される面に、位置決め用基準マーク40が形成されているので、位置決め工程を安定して行うことができる。すなわち、位置決め用基準マーク40の位置と、基板31のパターン形成面31aの電極の位置との位置関係は、高精度の関係になるので、位置決め工程85を安定して行うことができる。 Since the positioning reference marks 40 are formed on the surface of the substrate 31 on which the pattern forming surface 31a is formed, the positioning process can be performed stably. That is, since the positional relationship between the position of the positioning reference mark 40 and the position of the electrode on the pattern forming surface 31a of the substrate 31 is highly accurate, the positioning step 85 can be stably performed.
 ボンディング前にチップ32の位置認識を行うチップ認識工程87,88を備えたものであってもよい。このように、チップ認識工程87,88を備えたものでは、位置合わせ精度の向上を図ることができる。 It may be provided with chip recognition processes 87 and 88 for recognizing the position of the chip 32 before bonding. As described above, the chip recognition processes 87 and 88 can improve the alignment accuracy.
 接合工程86においては、基板31を下方からバックアッププレート43で受けるものであるので、チップ32を基板31のチップ接合面31bに接合する際、コレット62とバックアッププレート43とでチップ32を挟むことができ、基板31を湾曲等させることなく、安定した接合を得ることができる。 In the bonding step 86, the substrate 31 is received by the backup plate 43 from below, so when the chip 32 is bonded to the chip bonding surface 31b of the substrate 31, the chip 32 can be sandwiched between the collet 62 and the backup plate 43. Thus, stable bonding can be obtained without bending the substrate 31 or the like.
 本発明のボンディング方法に用いるボンディング装置の各構成要素として、既存の汎用のボンディング装置を用いることができ、コスト低減を図ることができる。 An existing general-purpose bonding apparatus can be used as each component of the bonding apparatus used in the bonding method of the present invention, and cost reduction can be achieved.
 本発明は前記実施形態に限定されることなく種々の変形が可能であって、例えば、接着剤Sを加熱する場合、ボンディング側コレット62を加熱するものであってもよく、この場合、コレット62側にのみ加熱手段を設けたり、バックアッププレート43側のみ加熱手段を設けたり、コレット62側およびバックアッププレート43側に設けものであってもよい。また、バックアッププレート43を有さないものであってもよく、このような場合には、ボンディングポジションの下方に、別途加熱手段を設けることになる。この場合の各加熱手段として、種々の電気加熱を用いることができる。 The present invention is not limited to the above embodiments, and various modifications are possible. For example, when heating the adhesive S, the bonding side collet 62 may be heated. The heating means may be provided only on the side, the heating means may be provided only on the backup plate 43 side, or the heating means may be provided on the collet 62 side and the backup plate 43 side. Alternatively, the backup plate 43 may not be provided, and in such a case, a separate heating means is provided below the bonding position. Various electric heating can be used as each heating means in this case.
 また、前記実施形態では、ボンディング前のチップの位置確認として、第1チップ認識手段72及び第2チップ認識手段73を用いていたが、いずれか1つのチップ認識手段を用いるものであってもよい。ところで、観察手段53として、実施形態では、カメラ本体66は水平方向に沿って配設されたものであったが、カメラ本体66が鉛直方向を向くものであってもよい。 Further, in the above embodiment, the first chip recognition means 72 and the second chip recognition means 73 are used to confirm the positions of the chips before bonding, but either one of the chip recognition means may be used. . By the way, as the observation means 53, in the embodiment, the camera body 66 is arranged along the horizontal direction, but the camera body 66 may face the vertical direction.
 ところで、実施形態では、図6に示すように、ステップS1の基板認識を行い工程から、ステップS2のチップ32をピックアップする工程を行うようにしていたが、ステップS1の工程の後、基板31を搬送して、ステップS8の基板とチップの位置合わせを行うようにしてもよい。すなわち、位置決め用基準マークとワイヤ挿通孔との位置関係と、ボンディングポジション上方からのワイヤ貫通孔の位置の認識とに基づいて、チップとチップ接合部との位置合わせを行う。この場合、第1チップ認識工程88及び第2チップ認識工程でのチップの位置認識を用いた位置合わせを行うことができないか、又は、位置決め用基準マークとワイヤ挿通孔との位置関係と、ボンディングポジション上方からのワイヤ貫通孔の位置の認識とに基づいて、チップとチップ接合部との位置合わせを行った後、チップ自体の位置に基づく位置合わせを行うことになる。 By the way, in the embodiment, as shown in FIG. 6, the process of performing board recognition of step S1 is followed by the process of picking up the chip 32 of step S2. The substrate and the chip may be aligned in step S8 after transporting. That is, the chip and the chip bonding portion are aligned based on the positional relationship between the positioning reference mark and the wire insertion hole and the recognition of the position of the wire insertion hole from above the bonding position. In this case, it may not be possible to perform alignment using chip position recognition in the first chip recognition process 88 and the second chip recognition process, or the positional relationship between the positioning reference marks and the wire insertion holes and the bonding After aligning the chip and the chip bonding portion based on recognition of the position of the wire through-hole from above the position, alignment based on the position of the chip itself is performed.
 本ボンディング方法および本ボンディング装置使用方法は、ボードオンチップ(BOC)タイプの電子部品(半導体装置)を製造するためのものである。 This bonding method and this bonding apparatus usage method are for manufacturing a board-on-chip (BOC) type electronic component (semiconductor device).
31   基板
31a パターン形成面
31b チップ接合面
32   チップ
32a 電極形成面
33   ワイヤ挿通孔
34   チップ接合部
40   基準マーク
43   バックアッププレート
57   ピックアップ側コレット
58   反転機構
62   ボンディング側コレット
81   基板認識工程
82   ピックアップ工程
83   反転工程
84   受け取り工程
85   位置合わせ工程
86   接合工程
S     接着剤
31 substrate 31a pattern forming surface 31b chip bonding surface 32 chip 32a electrode forming surface 33 wire insertion hole 34 chip bonding portion 40 reference mark 43 backup plate 57 pickup side collet 58 reversing mechanism 62 bonding side collet 81 substrate recognition process 82 pickup process 83 reversing Step 84 Receiving step 85 Positioning step 86 Joining step S Adhesive

Claims (7)

  1.  厚さ方向に貫通したワイヤ挿通孔を有しかつパターン形成面側に位置決め用基準マークが形成された基板が、基板搬送路に沿って上流側から下流側へ搬送され、基板搬送路の下流側のボンディングポジションで、この基板におけるパターン形成面の基板側電極部の反対側のチップ接合面のチップ接合部に、チップの電極形成面を接合するボンディング方法であって、
     基板のパターン形成面を下方に向けて配設した状態で、基板搬送路の上流側における下方からの位置決め用基準マークとワイヤ挿通孔との位置関係を認識する基板認識工程と、
     ピックアップ側コレットでチップをピックアップするピックアップ工程と、
     ピックアップ側コレットでピックアップしたチップを反転させてチップの電極形成面を下方に向ける反転工程と、
     反転工程で反転されたチップを電極形成面を下方に向けたままボンディング側コレットで受け取る受け取り工程と、
     認識工程にて認識された位置決め用基準マークとワイヤ挿通孔との位置関係と、ボンディングポジション上方からのワイヤ貫通孔の位置の認識とに基づいて、チップとチップ接合部との位置合わせを行う位置合わせ工程と、
     基板搬送路の下流側のボンディングポジションにおいて、位置合わせ工程にて位置合わせされた基板のチップ接合部に、受け取り工程で受け取ったチップを接合する接合工程とを備えたことを特徴とするボンディング方法。
    A substrate having a wire insertion hole penetrating in the thickness direction and having a positioning reference mark formed on the pattern forming surface side is conveyed from the upstream side to the downstream side along the substrate conveying path, and the downstream side of the substrate conveying path is conveyed. A bonding method for bonding an electrode forming surface of a chip to a chip bonding portion on a chip bonding surface on the opposite side of the substrate-side electrode portion on the pattern forming surface of the substrate at the bonding position of
    a substrate recognizing step of recognizing the positional relationship between the positioning reference mark and the wire insertion hole seen from below on the upstream side of the substrate transport path, with the pattern forming surface of the substrate facing downward;
    a pick-up process of picking up the tip with the pick-up side collet;
    a reversing step of reversing the chip picked up by the pickup-side collet so that the electrode-formed surface of the chip faces downward;
    a receiving step of receiving the chip flipped in the flipping step with the bonding side collet with the electrode forming surface facing downward;
    A position for aligning the chip and the chip bonding portion based on the positional relationship between the positioning reference mark and the wire insertion hole recognized in the recognition step and the recognition of the position of the wire insertion hole from above the bonding position. a matching process;
    and a bonding step of bonding a chip received in a receiving step to a chip bonding portion of a substrate aligned in the alignment step at a bonding position on the downstream side of a substrate transport path.
  2.  基板認識工程は、基板が加熱されないところで行うことを特徴とする請求項1に記載のボンディング方法。 The bonding method according to claim 1, wherein the substrate recognition process is performed where the substrate is not heated.
  3.  基板認識工程は、基板1枚分の位置情報を取得することを特徴とする請求項1又は請求項2に記載のボンディング方法。 The bonding method according to claim 1 or claim 2, wherein the substrate recognition step acquires position information for one substrate.
  4.  ボンディング前にチップの位置認識を行うチップ認識工程を備えたことを特徴とする請求項1~請求項3のいずれか1項に記載のボンディング方法。 The bonding method according to any one of claims 1 to 3, further comprising a chip recognition step of recognizing the position of the chip before bonding.
  5.  接合工程において、基板を下方からバックアッププレートで受けることを特徴とする請求項1~請求項4のいずれか1項に記載のボンディング方法。 The bonding method according to any one of claims 1 to 4, characterized in that in the bonding process, the substrate is received by a backup plate from below.
  6.  バックアッププレートは加熱手段に加熱されて、基板上の接着剤を加熱することを特徴とする請求項5に記載のボンディング方法。 The bonding method according to claim 5, wherein the backup plate is heated by the heating means to heat the adhesive on the substrate.
  7.  ピックアップポジションにてピックアップ側コレットにてチップをピックアップし、ピックアップポジションでピックアップしたチップを反転させ、その反転させたチップをボボンディングポジションにてボンディング側コレットにてボンディングするボンディング装置を用いた使用方法であって、
     前記請求項1~請求項6のいずれか1項に記載のボンディング方法を行うことを特徴とするボンディング装置使用方法。
    A method using a bonding device that picks up a chip with a pick-up side collet at a pick-up position, reverses the picked-up chip at the pickup position, and bonds the reversed chip with a bonding side collet at a bonding position. There is
    A method of using a bonding apparatus, characterized by performing the bonding method according to any one of claims 1 to 6.
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