WO2022157954A1 - 半導体素子メモリ装置 - Google Patents
半導体素子メモリ装置 Download PDFInfo
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- WO2022157954A1 WO2022157954A1 PCT/JP2021/002368 JP2021002368W WO2022157954A1 WO 2022157954 A1 WO2022157954 A1 WO 2022157954A1 JP 2021002368 W JP2021002368 W JP 2021002368W WO 2022157954 A1 WO2022157954 A1 WO 2022157954A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 239000004020 conductor Substances 0.000 claims abstract description 101
- 239000012535 impurity Substances 0.000 claims abstract description 56
- 230000008878 coupling Effects 0.000 claims abstract description 49
- 238000010168 coupling process Methods 0.000 claims abstract description 49
- 238000005859 coupling reaction Methods 0.000 claims abstract description 49
- 230000015654 memory Effects 0.000 claims description 100
- 239000000758 substrate Substances 0.000 claims description 20
- 230000014759 maintenance of location Effects 0.000 claims description 18
- 238000006243 chemical reaction Methods 0.000 claims description 17
- 239000011159 matrix material Substances 0.000 claims description 9
- 238000007667 floating Methods 0.000 description 36
- 238000010586 diagram Methods 0.000 description 22
- 230000007246 mechanism Effects 0.000 description 14
- 239000003990 capacitor Substances 0.000 description 12
- 238000003860 storage Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002135 nanosheet Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 101710114762 50S ribosomal protein L11, chloroplastic Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
Definitions
- the present invention relates to a columnar semiconductor memory device using semiconductor elements.
- the channel In a normal planar MOS transistor, the channel extends horizontally along the upper surface of the semiconductor substrate. In contrast, the SGT channel extends in a direction perpendicular to the upper surface of the semiconductor substrate (see Patent Document 1 and Non-Patent Document 1, for example). For this reason, the SGT enables a higher density semiconductor device compared to a planar MOS transistor.
- a DRAM Dynamic Random Access Memory
- PCM Phase Change Memory
- RRAM Resistive Random Access Memory
- MRAM Magnetic-resistive Random Access Memory
- Non-Patent Document 5 Magnetic-resistive Random Access Memory
- the present application relates to a dynamic flash memory that does not have resistance change elements or capacitors and can be configured only with MOS transistors.
- FIGS. 8(a) to 8(d) show the write operation of a DRAM memory cell composed of a single MOS transistor without the aforementioned capacitor
- FIGS. 9(a) and 9(b) show the operation. Problems and the read operation are shown in FIGS. FIG. 8(a) shows a "1" write state.
- the memory cell is formed on the SOI substrate 100, the source N + layer 103 is connected to the source line SL, the drain N + layer 104 is connected to the bit line BL, and the gate conductive layer 105 is connected to the word line SL.
- WL is connected, it is composed of a floating body 102 of a MOS transistor 110, does not have a capacitor, and one MOS transistor 110 constitutes a DRAM memory cell.
- the SiO 2 layer 101 of the SOI substrate is in contact directly below the floating body 102 .
- the MOS transistor 110 is operated in the saturation region. That is, the electron channel 107 extending from the source N + layer 103 has a pinch-off point 108 and does not reach the drain N + layer 104 connected to the bit line.
- both the bit line BL connected to the drain N + layer and the word line WL connected to the gate conductive layer 105 are set at a high voltage, and the MOS transistor 110 is turned on by setting the gate voltage to about half the drain voltage. In operation, the electric field strength is maximum at the pinch-off point 108 near the drain N + layer 104 .
- a small portion of the very hot electrons jump over the gate oxide film 109 and reach the gate conductive layer 105 .
- the holes 106 generated at the same time charge the floating body 102 . In this case, the generated holes contribute as increments of majority carriers because the floating body 102 is P-type Si.
- the floating body 102 is filled with the generated holes 106, and when the voltage of the floating body 102 becomes higher than that of the source N + layer 103 by Vb or more, the generated holes are discharged to the source N + layer 103.
- Vb is the built-in voltage of the PN junction between the source N + layer 103 and the floating body 102 of the P layer, which is approximately 0.7V.
- FIG. 8B shows the floating body 102 saturated with the generated holes 106 .
- FIG. 8(c) shows how the "1" write state is rewritten to the "0" write state.
- the voltage of the bit line BL is negatively biased, and the PN junction between the drain N + layer 104 and the floating body 102 of the P layer is forward biased.
- the holes 106 previously generated in the floating body 102 in the previous cycle flow to the drain N + layer 104 connected to the bit line BL.
- two memory cells 110 FIG.
- FIGS. 10(a) to (c) The read operation is shown in FIGS. 10(a) to (c), where FIG. 10(a) shows a "1" write state and FIG. 10(b) shows a "0" write state.
- FIGS. 10(a) to (c) show a "1" write state
- FIG. 10(b) shows a "0" write state.
- Vb the floating body 102
- the floating body 102 is pulled down to a negative bias when the word line returns to 0 V at the end of writing.
- the negative bias becomes even deeper. Therefore, as shown in FIG. Therefore, it has been difficult to commercialize a DRAM memory cell that does not actually have a capacitor.
- Critoloveanu “A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration,” Electron Device Letters, Vol. 35, No.2, pp. 179-181 (2012) T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory design using a one-transistor gain cell on SOI,” IEEE JSSC, vol.37, No.11, pp1510-1522 (2002). T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F.
- a columnar semiconductor memory cell includes: a semiconductor body on a substrate, standing vertically or extending horizontally with respect to the substrate; a first impurity layer and a second impurity layer at both ends of the semiconductor matrix; a first gate insulating layer surrounding part or all of a side surface of the semiconductor base body between the first impurity layer and the second impurity layer and in contact with or adjacent to the first impurity layer; , a second gate insulating layer surrounding part or all of a side surface of the semiconductor base, connected to the first gate insulating layer, and in contact with or close to the second impurity layer; a first gate conductor layer covering the first gate insulating layer; a second gate conductor layer covering the second gate insulating layer; the semiconductor matrix has a channel semiconductor layer covered with the first gate insulating layer and the second gate insulating layer; By controlling the voltage applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second
- the first capacitive coupling and the second capacitive coupling set the voltage of the channel semiconductor layer to a second data retention voltage lower than the first data retention voltage
- the voltage of the first gate conductor layer is changed from a first voltage to a second voltage higher than the first voltage, and the voltage of the second gate conductor layer is changed from a third voltage to the third voltage. a fourth voltage higher than the voltage of 3,
- the voltage of the channel semiconductor layer is controlled to be higher than the first data retention voltage by the first capacitive coupling and the second capacitive coupling;
- the voltage of the channel semiconductor layer is increased by a built-in voltage higher than the voltage of one or both of the first impurity layer and the second impurity layer, and the holes remaining in the group of holes extracting a group of holes from the inside of the channel semiconductor layer through one or both of the first impurity layer and the second impurity layer;
- the first capacitive coupling and the second capacitive coupling cause the voltage of the channel semiconductor layer to be a second data retention voltage lower than the first data retention voltage; It is characterized by (Second invention
- the channel semiconductor is controlled by using one or both of the first capacitive coupling and the second capacitive coupling depending on the voltage applied to the first impurity region and the second impurity region. preventing the formation of an inversion layer in the channel semiconductor layer during the first period during which the voltage of the layer is changed and part or all of the second period; It is characterized by (Third Invention)
- the first gate capacitance between the first gate conductor layer and the channel semiconductor layer is the first gate capacitance between the second gate conductor layer and the channel semiconductor layer. formed to be larger than the gate capacitance of 2, It is characterized by (Fourth invention)
- a columnar semiconductor memory device In a columnar semiconductor memory device according to the present invention, a plurality of columnar semiconductor memory cells according to any one of the first to fourth aspects of the present invention are arranged in a matrix to form a block, and all the cells in the block are erased during the memory erase operation. simultaneously performing the memory erase operation on the semiconductor base; It is characterized by (Fifth invention)
- a columnar semiconductor memory device includes a block group in which a plurality of columnar semiconductor memory devices according to the fifth aspect of the present invention are arranged,
- the first impurity layer is connected to a source line
- the second impurity layer is connected to a bit line
- one of the first gate conductor layer and the second gate conductor layer is a word line.
- the other is connected to the first drive control line
- the source line is connected between the semiconductor base bodies in the block;
- any one of the above fifth and sixth inventions comprising a logical-physical conversion table that associates physical addresses and logical addresses of the blocks, and a controller circuit that manages the logical-physical conversion table,
- a logical-physical conversion table that associates physical addresses and logical addresses of the blocks
- a controller circuit that manages the logical-physical conversion table
- One or both of the logical-to-physical conversion table and the controller circuit are outside the columnar semiconductor memory cell, It is characterized by (Seventh invention)
- FIG. 1 is a structural diagram of a memory device having SGTs according to the first embodiment;
- FIG. The gate capacitance of the first gate conductor layer 5a connected to the plate line PL of the memory device having the SGT according to the first embodiment is greater than the gate capacitance of the second gate conductor layer 5b connected to the word line WL.
- FIG. 10 is a diagram for explaining the effect of increasing the .
- FIG. 4 is a diagram for explaining a write operation mechanism of a memory device having SGTs according to the first embodiment;
- FIG. 3 is a diagram for explaining an erase operation mechanism of a memory device having SGTs according to the first embodiment;
- FIG. 3 is a diagram for explaining an erase operation mechanism of a memory device having SGTs according to the first embodiment;
- FIG. 3 is a diagram for explaining an erase operation mechanism of a memory device having SGTs according to the first embodiment;
- FIG. 10A is a circuit block diagram for explaining a block erase operation of a memory device having an SGT according to the second embodiment, and an application voltage diagram for performing block erase
- FIG. 10A is a circuit block diagram for explaining a block erase operation of a memory device having an SGT according to the second embodiment, and an application voltage diagram for performing block erase
- FIG. 12 is a circuit block diagram for explaining block rewrite operation and block erase operation of a memory device having SGTs according to the third embodiment
- FIG. 12 is a circuit block diagram for explaining block rewrite operation and block erase operation of a memory device having SGTs according to the third embodiment
- FIG. 12 is a circuit block diagram for explaining block rewrite operation and block erase operation of a memory device having SGTs according to the third embodiment
- FIG. 10A is a circuit block diagram for explaining a block erase operation of a memory device having an SGT according to the second embodiment, and an application voltage diagram for performing block erase
- FIG. 12 is a circuit block diagram for explaining block rewrite operation and
- FIG. 12 is a circuit block diagram for explaining block rewrite operation and block erase operation of a memory device having SGTs according to the third embodiment
- FIG. 12 is a circuit block diagram for explaining block rewrite operation and block erase operation of a memory device having SGTs according to the third embodiment
- FIG. 10 is a diagram for explaining a write operation of a conventional DRAM memory cell that does not have a capacitor
- FIG. 4 is a diagram for explaining operational problems of a conventional DRAM memory cell that does not have a capacitor
- FIG. 2 illustrates a read operation of a DRAM memory cell without a conventional capacitor
- dynamic flash memory a memory device using semiconductor elements (hereinafter referred to as dynamic flash memory) according to the present invention will be described with reference to the drawings.
- FIG. 1 The structure and operation mechanism of the dynamic flash memory cell according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 5.
- FIG. 2 The structure of a dynamic flash memory cell will be described with reference to FIG.
- the gate capacitance of the first gate conductor layer 5a connected to the plate line PL becomes larger than the gate capacitance of the second gate conductor layer 5b connected to the word line WL.
- a data write operation mechanism will be described with reference to FIG. 3
- a data erase operation mechanism will be described with reference to FIG. 4
- a data read operation mechanism will be described with reference to FIG.
- FIG. 1 shows the structure of a dynamic flash memory cell according to a first embodiment of the invention.
- a first gate insulating layer 4a (which is an example of the "first gate insulating layer” in the claims) and a second gate insulating layer 4b (the “first gate insulating layer” in the claims) surround the channel region 7. 2) is formed.
- the first gate insulating layer 4a and the second gate insulating layer 4b are in contact with or close to the N.sup .+ layers 3a and 3b serving as the source and drain, respectively.
- a first gate conductor layer 5a (which is an example of the "first gate conductor layer” in the scope of claims) and a second gate conductor layer 5a surround the first gate insulation layer 4a and the second gate insulation layer 4b.
- a gate conductor layer 5b (which is an example of the "second gate conductor layer” in the claims) is formed respectively.
- the first gate conductor layer 5a and the second gate conductor layer 5b are separated by an insulating layer 6 (which is an example of the "first insulating layer” in the claims).
- a channel region 7 between the N + layers 3a and 3b is a first channel Si layer 7a (an example of a "first channel semiconductor layer” in the scope of claims) surrounded by a first gate insulating layer 4a.
- a dynamic flash memory cell 10 is formed.
- the N + layer 3a serving as the source is connected to the source line SL (an example of the "source line” in the scope of claims), and the N + layer 3b serving as the drain is connected to the bit line BL ("bit line" in the scope of claims).
- the first gate conductor layer 5a is connected to the plate line PL which is the first drive control line (which is an example of the “first drive control line” in the scope of claims), the second are connected to word lines WL (one example of "word lines” in the claims).
- the gate capacitance of the first gate conductor layer 5a to which the plate line PL is connected may be larger than the gate capacitance of the second gate conductor layer 5b to which the word line WL is connected. desirable.
- the gate capacitance of the first gate conductor layer 5a connected to the plate line PL is made larger than the gate capacitance of the second gate conductor layer 5b connected to the word line WL.
- the gate length of the first gate conductor layer 5a is made longer than the gate length of the second gate conductor layer 5b.
- the gate length of the first gate conductor layer 5a is not made longer than the gate length of the second gate conductor layer 5b.
- the thickness of the gate insulating film of the gate insulating layer 4a may be thinner than the thickness of the gate insulating film of the second gate insulating layer 4b.
- the dielectric constant of the gate insulating film of the first gate insulating layer 4a is made higher than that of the gate insulating film of the second gate insulating layer 4b.
- the gate capacitance of the first gate conductor layer 5a connected to the plate line PL is It may be larger than the gate capacitance of the second gate conductor layer 5b to which the word line WL is connected.
- FIG. 2(a) shows a structural diagram of the dynamic flash memory cell according to the first embodiment of the present invention with only the main parts simplified.
- a bit line BL, a word line WL, a plate line PL, and a source line SL are connected to the dynamic flash memory cell, and the potential state of the channel region 7 is determined by the voltage state thereof.
- FIG.2(b) is a figure for demonstrating each capacity
- the capacitance CFB of the channel region 7 is composed of the capacitance CWL between the gate conductor layer 5b connected to the word line WL and the channel region 7, and the capacitance CWL between the gate conductor layer 5a connected to the plate line PL and the channel region 7.
- C PL >C WL ⁇ PL > ⁇ WL .
- FIG. 2(c) is a diagram for explaining changes in the voltage VFB of the channel region 7 when the voltage VWL of the word line WL rises and then falls during read and write operations.
- the voltage VFB of the channel region 7 and the potential difference ⁇ VFB between the low voltage state VFBL and the high voltage state VFBH is , below.
- FIG. 3(a)-(d) show the write operation of the dynamic flash memory cell according to the first embodiment of the present invention.
- FIG. 3(a) shows the mechanism of the write operation
- FIG. 3(b) shows operation waveforms of the bit line BL, the source line SL, the plate line PL, the word line WL, and the channel region 7 which is the floating body FB.
- Vss is applied to the bit line BL, source line SL and word line WL
- V PLL is applied to the plate line PL.
- Vss is 0V and V PLL is 2V.
- word line WL rises from Vss to V WLH .
- the threshold voltage for erasing "0" of the second N-channel MOS transistor is VtWL "0".
- the voltage of the line WL rises, from Vss to Vt WL "0", the second capacitive coupling between the word line WL and the channel region 7 (an example of the "second capacitive coupling" in the scope of claims).
- the voltage of the channel region 7 becomes V FB "0"+ ⁇ BL ⁇ V BLH + ⁇ WL ⁇ Vt WL "0".
- an annular inversion layer 12b is formed in the channel region 7 on the inner circumference of the second gate conductor layer 5b, and the word line WL and the channel region 7 are separated from each other. block the capacitive coupling of 2.
- FIG. 3A an annular inversion layer 12a is formed in the inner peripheral channel region 7 of the first gate conductor layer 5a connected to the plate line PL.
- a pinch-off point 13 exists.
- the first N-channel MOS transistor having the first gate conductor layer 5a operates in the linear region.
- the second N-channel MOS transistor having the second gate conductor layer 12b connected to the word line WL operates in the saturation region.
- there is no pinch-off point in channel region 7 on the inner periphery of second gate conductor layer 5b connected to word line WL and inversion layer 12b is formed on the entire inner periphery of gate conductor layer 5b.
- the inversion layer 12b formed entirely on the inner periphery of the second gate conductor layer 5b connected to the word line WL is the substantial drain of the second N-channel MOS transistor having the second gate conductor layer 5b.
- the channel region 7 between the first N-channel MOS transistor having the first gate conductor layer 5a and the second N-channel MOS transistor having the second gate conductor layer 5b, which are connected in series, has a second The electric field is maximum at the boundary region of 1 and the impact ionization phenomenon occurs in this region. Since this region is the region on the source side viewed from the second N-channel MOS transistor having the second gate conductor layer 5b connected to the word line WL, this phenomenon is called the source-side impact ionization phenomenon. Due to this source-side impact ionization phenomenon, electrons flow from the N + layer 3a connected to the source line SL toward the N + layer 3b connected to the bit line.
- the generated hole group 9 (an example of the "hole group” in the claims) is the majority carrier in the channel region 7, and the channel region 7 is Charge to positive bias. Since the N + layer 3a connected to the source line SL is at 0V, the channel region 7 is at the built-in voltage Vb (approximately 0 V) of the PN junction between the N + layer 3a connected to the source line SL and the channel region 7. .7V). When channel region 7 is positively biased, the threshold voltages of the first N-channel MOS transistor and the second N-channel MOS transistor are lowered due to the substrate bias effect.
- bit line BL drops from V BLH to Vss. Since the bit line BL and the channel region 7 are capacitively coupled, the final "1" write voltage V FB "1" of the channel region 7 is as follows.
- VFB "1" Vb - ⁇ WL x VtWL "1" - ⁇ BL x VBLH (7)
- the coupling ratio ⁇ BL between the bit line BL and the channel region 7 is also small.
- FIG. 3(d) the threshold voltage of the second N-channel MOS transistor in the second channel region 7b connected to the word line WL is lowered.
- a memory write operation (“memory (which is an example of a write operation), and is assigned to the logical storage data "1".
- Electron-hole pairs may be generated by the impact ionization phenomenon in the third boundary region between the channel semiconductor layer 7b and the channel region 7 may be charged with the generated hole groups 9 .
- FIG. 4A(a) shows the timing operation waveform diagram of the main nodes of the erase operation.
- T0 to T12 represent times from the start to the end of the erasing operation.
- FIG. 4A(b) shows a state in which the hole groups 9 generated by impact ionization in the previous cycle are stored in the channel region 7 at time T0 before the erasing operation.
- the bit line BL and the source line SL go from Vss to high voltage states of V BLH and V SLH , respectively.
- Vss is 0V, for example.
- the plate line PL and the word line WL are set to the first voltage ( From V PLL (which is an example of the "first voltage” in the scope of claims) to V PLH (which is an example of the "second voltage” in the scope of claims), a third voltage ( From Vss (an example of a “third voltage” in the claims) to a fourth voltage (an example of a "fourth voltage” in the claims) VWLH , the high voltage state is reached, and the channel region 7 Inversion layer 12a (which is an example of the "inversion layer” in the scope of claims) on the inner periphery of the first gate conductor layer 5a to which the plate line PL is connected, and the second gate to which the word line WL is connected The inversion layer 12b on the inner circumference of the conductor layer 5b is not formed.
- V BLH and V SLH correspond to the threshold voltages of the second N-channel MOS transistor on the word line WL side and the first N-channel MOS transistor on the plate line PL side as V tWL and V tPL respectively. Then, it is desirable that V BLH >V WLH +V tWL and V SLH >V PLH +V tPL . For example, if V tWL and V tPL are 0.5 V, V WLH and V PLH should be set to 3 V, and V BLH and V SLH should be set to 3.5 V or higher.
- the plate line PL and the word line WL are set to the high voltage state of the second voltage V PLH and the fourth voltage V WLH , so that the floating channel region 7 is applied to the first capacitive coupling between the plate line PL and the channel region 7 (which is an example of the “first capacitive coupling” in the scope of claims) and the second capacitive coupling between the word line WL and the channel region 7 . It is pushed up by capacitive coupling. The voltage of the channel region 7 becomes a high voltage from V FB "1" in the "1" write state.
- the voltages of the bit line BL and the source line SL are high voltages V BLH and V SLH , this is because the PN junction between the source N + layer 3a and the channel region 7, the drain N + layer 3b and the channel Since the PN junction with region 7 is in a reverse-biased state, boosting is possible.
- the erase operation mechanism of FIG. 4A(a) will be described.
- the voltages of the bit line BL and the source line SL change from the high voltages V BLH and V SLH to to Vss.
- the PN junction between the source N + layer 3a and the channel region 7 and the PN junction between the drain N + layer 3b and the channel region 7 are forward biased as shown in FIG.
- the remaining hole groups (an example of the "residual hole group" in the scope of claims) of the hole groups 9 in the channel region 7 are located in the source N + layer 3a and the drain N + layer 3b. ,Discharge.
- the voltage V FB of the channel region 7 becomes the PN junction formed between the source N + layer 3 a and the P layer channel region 7 and the PN junction formed between the drain N + layer 3 b and the P layer channel region 7 . is the built-in voltage Vb.
- the erase operation mechanism of FIG. 4A(a) will be described.
- the voltages of the bit line BL and the source line SL rise from Vss to high voltages V BLH and V SLH .
- the plate line PL and the word line WL are connected at times T11 to T12 in the third period (an example of the "third period" in the scope of claims).
- the inversion layer 12 a on the plate line PL side and the word line side inversion layer 12 a on the word line side are formed in the channel region 7 .
- the voltage V FB of the channel region 7 is effectively controlled by the first capacitive coupling between the plate line PL and the channel region 7 and the second capacitance between the word line WL and the channel region 7. Coupling goes from Vb to V FB "0". Therefore, the voltage difference ⁇ V FB between the "1" written state and the "0" erased state of the channel region 7 is expressed by the following equation.
- VFB “1” Vb - ⁇ WL x VtWL “1” - ⁇ BL x VBLH (7)
- V FB “0” Vb - ⁇ WL ⁇ V WLH - ⁇ PL ⁇ (V PLH - V PLL )
- the sum of ⁇ WL and ⁇ PL is 0.8 or more, ⁇ V FB becomes large, and a sufficient margin can be obtained.
- a large margin can be obtained between the "1" write state and the "0" erase state.
- the erase operation mechanism of FIG. 4A(a) will be described.
- the voltages of the bit line BL and the source line SL drop from V BLH to Vss and from V SLH to Vss respectively, and the erase operation ends.
- the bit line BL and the source line SL slightly lower the voltage of the channel region 7 by capacitive coupling. Since it is equal to the increased amount, the increase and decrease of the voltages of the bit line BL and the source line SL are canceled out, and as a result, the voltage of the channel region 7 is not affected.
- a memory erase operation (which is an example of a "second data retention voltage” in the scope of claims) using the voltage VFB “0" in the “0" erased state of the channel region 7 as a second data retention voltage (an example of a “second data retention voltage” in the scope of claims) (which is an example of the “memory erasing operation" in the scope of claims) is performed and assigned to the logical storage data "0".
- FIG. 5A to 5C are diagrams for explaining the read operation of the dynamic flash memory cell according to the first embodiment of the present invention.
- FIG. 5(a) when the channel region 7 is charged to the built-in voltage Vb (approximately 0.7V), a second N-channel having a second gate conductor layer 5b connected to the word line WL is formed.
- the threshold voltage of the MOS transistor is lowered due to the substrate bias effect. This state is assigned to logical storage data "1".
- FIG. 5(b) the memory block selected before writing is in the erased state "0" in advance, and the voltage VFB of the channel region 7 is VFB "0".
- a write operation randomly stores a write state of "1".
- logical storage data of logical "0" and “1” are created for the word line WL.
- reading is performed by the sense amplifier using the level difference between the two threshold voltages for the word line WL.
- the vertical length of the first gate conductor layer 5a connected to the plate line PL is made longer than the vertical length of the second gate conductor layer 5b connected to the word line WL, It is desirable that C PL >C WL .
- simply adding the plate line PL reduces the capacitive coupling ratio (C WL /(C PL +C WL +C BL +C SL )) of the word line WL to the channel region 7 .
- the potential variation ⁇ V FB of the channel region 7 of the floating body becomes small.
- the voltage V PLL of the plate line PL may be a fixed voltage of 2 V, for example, in each operation mode other than selective erasing in the block erasing operation.
- the dynamic flash memory operation described in this embodiment can be performed.
- Circular, elliptical, and rectangular dynamic flash memory cells may also be mixed on the same chip.
- a first gate insulating layer 4a and a second gate insulating layer 4b surrounding the entire side surface of the Si pillar 2 standing vertically on the substrate 1 are provided.
- the dynamic flash memory device has been described by taking the SGT having the first gate conductor layer 5a and the second gate conductor layer 5b surrounding the entire second gate insulating layer 4b as an example.
- the dynamic flash memory device may have any structure as long as it satisfies the condition that the hole groups 9 generated by the impact ionization phenomenon are retained in the channel region 7 .
- the channel region 7 may have a floating body structure separated from the substrate 1 .
- Non-Patent Document 10 GAA (Gate All Around: see, for example, Non-Patent Document 10 10) technology and Nanosheet technology (see, for example, Non-Patent Document 11), which is one of SGTs, the semiconductor matrix in the channel region is formed into the substrate 1
- the dynamic flash memory operation described above is possible even if it is formed horizontally with respect to the
- it may be a device structure using SOI (Silicon On Insulator) (for example, see Non-Patent Documents 7 to 10).
- SOI Silicon On Insulator
- the bottom of the channel region is in contact with the insulating layer of the SOI substrate, and another channel region is surrounded by a gate insulating layer and an element isolation insulating layer.
- the channel region has a floating body structure.
- the dynamic flash memory device provided by the present embodiment only needs to satisfy the condition that the channel region has a floating body structure. Also, even in a structure in which a Fin transistor (see, for example, Non-Patent Document 13) is formed on an SOI substrate, the dynamic flash operation can be performed if the channel region has a floating body structure.
- a gate insulating layer, a gate conductor layer, or the like covers a channel or the like means “to cover”. It also includes the case of surrounding a part of the transistor like a transistor, and the case of overlapping a planar object like a planar transistor.
- FIG. 4B An example of erase operation conditions is shown in FIG. 4B.
- the hole group 9 in the channel region 7 can be removed from either or both of the N + layer 3a and the N + layer 3b, the source line SL, the plate line PL, and the bit line BL , the voltage applied to the word line WL may be changed.
- the N + layer 3a serving as the source is connected to the source line SL
- the N + layer 3b serving as the drain is connected to the bit line BL
- the first gate conductor layer 5a is connected to the plate line PL
- the second gate conductor layer 5b is connected to the word line. line WL, respectively.
- the structure is characterized in that the gate capacitance of the first gate conductor layer 5a to which the plate line PL is connected is larger than the gate capacitance of the second gate conductor layer 5b to which the word line WL is connected. .
- a first gate conductor layer and a second gate conductor layer are stacked vertically. Therefore, the structure is such that the gate capacitance of the first gate conductor layer 5a to which the plate line PL is connected is larger than the gate capacitance of the second gate conductor layer 5b to which the word line WL is connected.
- it does not increase the memory cell area in plan view. As a result, high performance and high integration of dynamic flash memory cells can be realized at the same time.
- the first gate conductor layer 5a to which the plate line PL is connected and the second gate electrode 5b to which the word line WL are connected and , change from a low voltage state to a high voltage state, and by capacitive coupling with the channel region 7, the PN junction between the source N + layer 3a and the channel region 7, the drain N + layer 3b and the channel region. 7 is forward-biased, the hole group 9 in the channel region 7 is discharged to the source N + layer 3a and the drain N + layer 3b.
- FIG. 6A shows the memory block schematic selected for block erase.
- Source lines SL 1 to SL 3 bit lines BL 1 to BL 3 , plate lines PL 1 to PL 3 and word lines WL 1 to WL 3 are connected to each memory cell.
- FIG. 6B the source lines SL 1 -SL 3 , bit lines BL 1 -BL 3 , plate lines PL 1 -PL 3 , and word lines WL 1 -WL 3 of the memory block selected for block erasure.
- the pulse waveform shown in FIG. 3(b) is input. A pulse waveform is not input to blocks that are not to be erased (recorded data retention blocks).
- bit lines BL, source lines SL, plate lines PL, and word lines WL can be independently controlled for each block in order to perform block erasing independently for each block. .
- FIGS. 7A to 7D are circuit block diagrams for explaining block rewrite and block erase operations of the dynamic flash memory cell of the third embodiment.
- a controller circuit 33 (which is an example of the “controller circuit” in the scope of claims) and a logical/physical block address conversion lookup table circuit 32 (abbreviated as a logical-to-physical conversion table (in the scope of claims) )), which is an example of a "logical-to-physical conversion table”, always manages which physical block address in the dynamic flash memory corresponds to the data stored in the logical block address. This is because in dynamic flash memory, as with flash memory, block data rewriting requires constant management of the correspondence between logical block addresses and physical block addresses because blocks that have already been erased are used for rewriting. is.
- the controller circuit 33 and logical-physical conversion table 32 may be provided within the chip of the dynamic flash memory, or may be provided outside the chip as shown in FIG. 7(a). Instructions from the logical-to-physical conversion table 32 are input to the block address decoder circuit 34, and the block to be rewritten and the block to be erased are blocks BLK00 to BLK33 (an example of "block” in the claims). is selected from
- FIG. 7B An erasing operation accompanying rewriting of stored data will be specifically described with reference to FIGS. 7B to 7D.
- blocks BLK01 and BLK13 are already erased blocks, and data are stored in other blocks.
- controller circuit 33 issues an instruction to rewrite the data stored in the block BLK21.
- controller circuit 33 refers to logical-to-physical conversion table 32 to find out which blocks are erased blocks.
- the data not to be rewritten in the block BLK21 to be rewritten is copied to the erased block BLK01, and the page data related to the word line WL to be rewritten is newly written to the block BLK01.
- FIG. 7D when the data copy from block BLK21 to block BLK01 and the writing of new data in block BLK01 are completed, the old stored data in block BLK21 is block-erased. Then, the physical block BLK01 is registered in the logical-physical conversion table 32 through the controller circuit 33.
- block erasing is performed, but block erasing may be performed by simultaneously selecting at least one or more blocks.
- flash memory operations similar to block rewriting and block erasing described with reference to FIGS. 7B to 7D are performed.
- the controller circuit monitors and manages how many times each block has been rewritten.
- a high electric field is applied to transfer electrons stored in a storage node through a tunnel oxide film. For this reason, the rewriting life of the tunnel oxide film is determined in specifications.
- rewriting is performed at a much lower electric field than in flash memory. Therefore, in terms of reliability, it is not necessary to set limits on the number of rewrites for each block.
- a cache memory (not shown) for temporarily storing data stored in blocks to be rewritten may be required.
- the cache memory may be provided inside or outside the chip of the dynamic flash memory of this embodiment.
- the logical-to-physical conversion table 32 or the cache memory may be composed of a memory cell array in which dynamic flash memory cells are made accessible at high speed.
- a refresh operation may be performed for each block in order to retain the stored data in the block. In this case, since refresh is performed within the block of the physical address, block rewrite operation or block erase operation does not have to be performed.
- the dynamic flash memory cell of the third embodiment is a volatile memory, it realizes block rewrite operation and block erase operation, which are conventionally available only in non-volatile flash memories, and thus achieves higher integration. possible memory cells.
- a Si pillar is formed, but a semiconductor pillar made of a semiconductor material other than Si may be used. This also applies to other embodiments according to the present invention.
- the logical-to-physical conversion tables of FIGS. 7A to 7D are provided outside the columnar semiconductor memory device chip, but they may be provided on-chip within the columnar semiconductor memory device. This also applies to other embodiments according to the present invention.
- the memory elements of the logical-to-physical conversion tables in FIGS. 7A to 7D of the third embodiment may be configured with dynamic flash memories that can be accessed at high speed. This also applies to other embodiments according to the present invention.
- a timer circuit may be provided for each of the blocks BLK00 to BLK33 in FIGS. 7A to 7D of the third embodiment, and each block may be refreshed according to instructions from the timer circuit. This also applies to other embodiments according to the present invention.
- At least two or more blocks may be block-erased simultaneously. This also applies to other embodiments according to the present invention.
- a semiconductor pillar is used as a channel. formed in the direction
- the semiconductor pillars at both ends of these memory cells have a source line impurity layer corresponding to the source and a bit line impurity layer corresponding to the drain.
- the vertical NAND flash memory circuit is one of the SGT circuits. Therefore, the present invention can also be applied to mixed circuits with NAND flash memory circuits.
- Non-Patent Document 14 In addition, in writing “1”, electron-hole pairs are generated by impact ionization phenomenon using a GIDL (Gate Induced Drain Leakage) current referred to [Non-Patent Document 14], and the generated hole group The inside of the floating body FB may be filled. This also applies to other embodiments according to the present invention.
- a dynamic flash memory which is a memory device using high-density and high-performance SGTs, can be obtained.
- Dynamic flash memory cell 2 Si pillars 3a, 3b having conductivity type of P-type or i-type (intrinsic type): N + layer 7: Channel regions 4a, 4b: Gate insulating layers 5a, 5b: Gate conductor layer 6 : insulating layer for separating two gate conductor layers BL: bit line SL: source line PL: plate line WL: word line FB: Floating body CL11 to CL33 , CL0 to CL3: memory cells SL1 to SL3 , SL: source lines BL1 to BL3, BL0 to BL3: bit lines PL1 to PL3 , PL: plate lines WL1 to WL3 , WL: word line 35, BLK00 to BLK33: block 34: block address decoder circuit 33: controller circuit 32: logical-physical conversion table 110: DRAM memory cell without capacitor 100: SOI substrate 101: SiO 2 film of SOI substrate 102: Floating Body 103: Source N + layer 104: Drain
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Abstract
Description
CFB = CWL + CBL + CSL (10)
で表される。また、ワード線の接続されたゲートとフローティングボディ間の容量結合比βWLは、
βWL=CWL/(CWL + CBL + CSL) (11)
で表される。したがって、読出し時または書込み時にワード線電圧VWLが振幅すると、メモリセルの記憶ノード(接点)となるフローティングボディ102の電圧も、その影響を受ける。その様子を図9(b)に示している。読出し時、または、書込み時にワード線電圧VWLが0VからVWLHに上昇すると、フローティングボディ102の電圧VFBは、ワード線電圧が変化する前の初期状態の電圧VFB1からVFB2へワード線との容量結合によって上昇する。その電圧変化量ΔVFBは、
ΔVFB = VFB1 - VFB2
= βWL ×VWLH (12)
で表される。
ここで、式(11)のβWLにおいて、CWLの寄与率が大きく、例えば、CWL:CBL:CSL=8:1:1である。この場合、β=0.8となる。ワード線が、例えば、書込み時の5Vから、書込み終了後に0Vになると、ワード線WLとフローティングボディ102との容量結合によって、フローティングボディ102が、5V×βWL=4Vも振幅ノイズを受ける。このため、書込み時のフローティングボディ102の“1”電位と“0”電位との電位差マージンを十分に取れない問題点があった。
基板上に、前記基板に対して、垂直方向に立つか、または水平方向に伸延する半導体母体と、
前記半導体母体の両端にある第1の不純物層と、第2の不純物層と、
前記第1の不純物層と前記第2の不純物層の間の前記半導体母体の側面の一部または全てを囲み、前記第1の不純物層に接するか、または、近接した第1のゲート絶縁層と、
前記半導体母体の側面の一部または全てを囲み、前記第1のゲート絶縁層に繋がり、且つ前記第2の不純物層に接するか、または、近接した第2のゲート絶縁層と、
前記第1のゲート絶縁層を覆う第1のゲート導体層と、
前記第2のゲート絶縁層を覆う第2のゲート導体層と、
前記半導体母体が前記第1のゲート絶縁層と、前記第2のゲート絶縁層とで覆われたチャネル半導体層をと、有し、
前記第1のゲート導体層と、前記第2のゲート導体層と、前記第1の不純物領域と、前記第2の不純物領域と、に印加する電圧を制御して、前記チャネル半導体層の内部に、インパクトイオン化現象、またはゲート誘起ドレインリーク電流により生成した正孔群を保持し、
書込み動作時に、前記チャネル半導体層の電圧を、前記第1の不純物層及び前記第2の不純物層の一方もしくは両方の電圧より、ビルトイン電圧だけ高い、第1のデータ保持電圧とし、
前記第1のゲート導体層と前記チャネル半導体層との間の第1の容量結合と、前記第2のゲート導体層と前記チャネル半導体層との間の第2の容量結合とにより、前記チャネル半導体層の電圧を前記第1のデータ保持電圧よりも高い電圧に制御して、前記チャネル半導体層の電圧が、前記第1の不純物層及び前記第2の不純物層の一方もしくは両方の電圧より、ビルトイン電圧だけ高くなるまで、前記正孔群のうちの残存正孔群を前記チャネル半導体層の内部から、前記第1の不純物層及び前記第2の不純物層の一方もしくは両方通して除去し、
消去動作時に、前記第1の容量結合及び前記第2の容量結合により、前記チャネル半導体層の電圧を、前記第1のデータ保持電圧よりも低い、第2のデータ保持電圧とする、
ことを特徴とする。(第1発明)
前記消去動作時に、
前記第1のゲート導体層の電圧を、第1の電圧から、前記第1の電圧よりも高い第2の電圧とし、前記第2のゲート導体層の電圧を、第3の電圧から、前記第3の電圧よりも高い第4の電圧とし、
第1の期間において、前記第1の容量結合と前記第2の容量結合とにより、前記チャネル半導体層の電圧を前記第1のデータ保持電圧よりも高い電圧に制御し、
第2の期間において、前記チャネル半導体層の電圧を、前記第1の不純物層と前記第2の不純物層の一方もしくは両方の電圧より、ビルトイン電圧だけ高くなるまで、前記正孔群のうちの残存正孔群を前記チャネル半導体層の内部から、前記第1の不純物層と、前記第2の不純物層の一方もしくは両方を通して抜きとり、
第3の期間において、前記第1の容量結合と前記第2の容量結合とにより、前記チャネル半導体層の電圧を、前記第1のデータ保持電圧よりも低い、第2のデータ保持電圧とする、
ことを特徴とする。(第2発明)
ことを特徴とする。(第3発明)
ことを特徴とする。(第4発明)
ことを特徴とする。(第5発明)
前記第1の不純物層は、ソース線と接続し、前記第2の不純物層は、ビット線と接続し、前記第1のゲート導体層と前記第2のゲート導体層のうちの一方がワード線と接続すれば、他方が第1の駆動制御線と接続し、
前記ソース線は、前記ブロック内の前記半導体母体間で繋がり、
前記ソース線と、前記ビット線と、前記第1の駆動制御線と、前記ワード線とに印加する電圧により、前記ブロック群の中の選択した前記ブロックの全ての前記半導体母体にある前記残存正孔群を除去する前記消去動作を行う、
ことを特徴とする。(第6発明)
前記論物変換テーブルと、前記コントローラ回路とが、片方、もしくは、両方が前記柱状半導体メモリセルの外部にある、
ことを特徴とする。(第7発明)
図1~図5を用いて、本発明の第1実施形態に係るダイナミック フラッシュ メモリセルの構造と動作メカニズムを説明する。図1を用いて、ダイナミック フラッシュ メモリセルの構造を説明する。そして、図2を用いて、プレート線PLに接続された第1のゲート導体層5aのゲート容量が、ワード線WLが接続された、第2のゲート導体層5bのゲート容量よりも、大きくなるようにした場合の効果を説明する。そして、図3を用いてデータ書込み動作メカニズムを、図4を用いてデータ消去動作メカニズムを、図5を用いてデータ読出し動作メカニズムを説明する。
CFB = CWL + CPL + CBL + CSL (1)
で表される。
したがって、ワード線WLとチャネル領域7間のカップリング率βWL、プレート線PLとチャネル領域7間のカップリング率βPL、ビット線BLとチャネル領域7間のカップリング率βBL、ソース線SLとチャネル領域7間のカップリング率βSLは、以下でそれぞれ表される。
βWL= CWL / (CWL + CPL+ CBL + CSL) (2)
βPL= CPL / (CWL + CPL+ CBL + CSL) (3)
βBL= CBL / (CWL + CPL+ CBL + CSL) (4)
βSL= CSL / (CWL + CPL+ CBL + CSL) (5)
ここで、CPL >CWL であるため、βPL>βWLとなる。
ΔVFB=VFBH-VFBL
=βWL×VWLH (6)
ワード線WLとチャネル領域7間のカップリング率βWLが小さく、プレート線PLとチャネル領域7間のカップリング率βPLが大きいため、ΔVFBは、小さく、ワード線WLの電圧VWLが、読出し動作と書込み動作で、上下しても、チャネル領域7の電圧VFBは、殆ど変化しない。
VFB“1”=Vb-βWL×VtWL“1”-βBL×VBLH (7)
ここで、ビット線BLとチャネル領域7とのカップリング比βBLも小さい。これにより、図3(d)で示すように、ワード線WLの接続された第2のチャネル領域7bの第2のNチャネルMOSトランジスタのしきい値電圧は、低くなる。このチャネル領域7の“1”書込み状態を第1のデータ保持電圧(特許請求の範囲の「第1のデータ保持電圧」の一例である)とする、メモリ書込み動作(特許請求の範囲の「メモリ書込み動作」の一例である)を行い、論理記憶データ“1”に割り当てる。
VFB“1”=Vb-βWL×VtWL“1”-βBL×VBLH (7)
VFB“0”=Vb-βWL×VWLH-βPL×(VPLH-VPLL) (8)
ΔVFB=VFB“1”-VFB“0”
=βWL×VWLH+βPL×(VPLH-VPLL)
-βWL×VtWL“1”-βBL×VBLH (9)
ここで、βWLとβPLとの和は、0.8以上あり、ΔVFBは、大きくなり、十分にマージンが取れる。その結果、図4B(e)に示すように、“1”書込み状態と“0”消去状態とで、マージンを大きく取れる。
(特徴1)
本実施形態のダイナミック フラッシュ メモリセルでは、ソース、ドレインとなるN+層3a、3b、チャネル領域7、第1のゲート絶縁層4a、第2のゲート絶縁層4b、第1のゲート導体層5a、第2のゲート導体層5bが、全体として柱状に形成される。また、ソースとなるN+層3aはソース線SLに、ドレインとなるN+層3bはビット線BLに、第1のゲート導体層5aはプレート線PLに、第2のゲート導体層5bはワード線WLに、それぞれ接続している。プレート線PLが接続された、第1のゲート導体層5aのゲート容量は、ワード線WLが接続された、第2のゲート導体層5bのゲート容量よりも、大きくなるような構造を特徴としている。本ダイナミック フラッシュ メモリセルでは、垂直方向に第1のゲート導体層と、第2のゲート導体層が、積層されている。このため、プレート線PLが接続された、第1のゲート導体層5aのゲート容量が、ワード線WLが接続された、第2のゲート導体層5bのゲート容量よりも、大きくなるような構造にしても、平面視において、メモリセル面積を大きくさせない。これによりダイナミック フラッシュ メモリセルの高性能化と高集積化が同時に実現できる。
本発明の第1実施形態に係るダイナミック フラッシュ メモリセルの消去動作をする際に、プレート線PLが接続された第1のゲート導体層5aと、ワード線WLが接続された第2のゲート電極5bと、の両者が、低電圧状態から高電圧状態になり、チャネル領域7との容量結合によって、ソースN+層3aとチャネル領域7との間のPN接合と、ドレインN+層3bとチャネル領域7との間のPN接合を、順バイアス状態として、チャネル領域7の正孔群9は、ソースN+層3aと、ドレインN+層3bとに、排出する。
本発明の第1実施形態に係るダイナミック フラッシュ メモリセルの(特徴2)で説明した動作に続いて、プレート線PLが接続された、第1のゲート導体層5aと、ワード線WLが接続された第2のゲート導体層5bと、の両者が、高電圧状態から低電圧状態に戻り、再びチャネル領域7との容量結合によって、チャネル領域7の電圧を負バイアスにする。このように、ソースN+層3a、または、ドレインN+層3bに負バイアスを印加せずに“0”消去状態のチャネル領域7の電圧を負バイアスすることが可能である。これにより、負バイアスを印加するための二重構造ウェルや負バイアス発生回路が必要なくなり、メモリコアおよび周辺回路設計とプロセスが容易になる。
本発明の第1実施形態に係るダイナミック フラッシュ メモリセルのプレート線PLの接続する第1のゲート導体層5aの役割に注目すると、ダイナミック フラッシュ メモリセルが書込み、読出し動作をする際に、ワード線WLの電圧が上下に振幅する。この際に、プレート線PLは、ワード線WLとチャネル領域7との間の容量結合比を低減させる役目を担う。この結果、ワード線WLの電圧が上下に振幅する際の、チャネル領域7の電圧変化の影響を著しく抑えることができる。これにより、論理“0”と“1”を示すワード線WLのSGTトランジスタのしきい値電圧差を大きくすることが出来る。これは、ダイナミック フラッシュ メモリセルの動作マージンの拡大に繋がる。
図6A、図6Bを参照して、第2実施形態に係るSGTを有するメモリ装置のブロック消去動作を説明する。
第2実施形態のダイナミック フラッシュ メモリセルでは、ブロック毎で独立にブロック消去を行うために、ブロック毎で、ビット線BL、ソース線SL、プレート線PL、ワード線WLを独立に制御することができる。
第2実施形態のダイナミック フラッシュ メモリセルでは、フラッシュメモリと同様な、図6A、図6Bで説明したブロック消去動作を行うが、フラッシュメモリに比べて、遥かに低電界で書き換えを行っている。このため、信頼性上、ブロック毎の書き換え回数制限を定める必要がない。
図7(a)~(d)は、第3実施形態のダイナミック フラッシュ メモリセルのブロック書き換え動作とブロック消去動作を説明するための回路ブロック図を示している。
第3実施形態のダイナミック フラッシュ メモリセルでは、揮発性メモリでありながら、従来、不揮発性メモリのフラッシュメモリにしか無かった機能である、ブロック書き換え動作とブロック消去動作を実現し、より高集積化が可能なメモリセルを提供することが可能となる。
なお、本発明では、Si柱を形成したが、Si以外の半導体材料よりなる半導体柱であってもよい。このことは、本発明に係るその他の実施形態においても同様である。
2:P型又はi型(真性型)の導電型を有するSi柱
3a、3b:N+層
7:チャネル領域
4a、4b:ゲート絶縁層
5a、5b:ゲート導体層
6:2層のゲート導体層を分離するための絶縁層
BL:ビット線
SL:ソース線
PL:プレート線
WL:ワード線
FB:フローティングボディ
CL11~CL33、CL0~CL3:メモリセル
SL1~SL3、SL:ソース線
BL1~BL3、BL0~BL3:ビット線
PL1~PL3、PL:プレート線
WL1~WL3、WL:ワード線
35、BLK00~BLK33:ブロック
34:ブロックアドレスデコーダー回路
33:コントローラ回路
32:論物変換テーブル
110:キャパシタを有しない、DRAMメモリセル
100:SOI基板
101:SOI基板のSiO2膜
102:フローティングボディ(Floating Body)
103:ソースN+層
104:ドレインN+層
105:ゲート導電層
106:正孔
107:反転層、電子のチャネル
108:ピンチオフ点
109:ゲート酸化膜
Claims (7)
- 基板上に、前記基板に対して、垂直方向に立つか、または水平方向に伸延する半導体母体と、
前記半導体母体の両端にある第1の不純物層と、第2の不純物層と、
前記第1の不純物層と前記第2の不純物層の間の前記半導体母体の側面の一部または全てを囲み、前記第1の不純物層に接するか、または、近接した第1のゲート絶縁層と、
前記半導体母体の側面の一部または全てを囲み、前記第1のゲート絶縁層に繋がり、且つ前記第2の不純物層に接するか、または、近接した第2のゲート絶縁層と、
前記第1のゲート絶縁層を覆う第1のゲート導体層と、
前記第2のゲート絶縁層を覆う第2のゲート導体層と、
前記半導体母体が前記第1のゲート絶縁層と、前記第2のゲート絶縁層とで覆われたチャネル半導体層をと、有し、
前記第1のゲート導体層と、前記第2のゲート導体層と、前記第1の不純物領域と、前記第2の不純物領域と、に印加する電圧を制御して、前記チャネル半導体層の内部に、インパクトイオン化現象、またはゲート誘起ドレインリーク電流により生成した正孔群を保持し、
書込み動作時に、前記チャネル半導体層の電圧を、前記第1の不純物層及び前記第2の不純物層の一方もしくは両方の電圧より、ビルトイン電圧だけ高い、第1のデータ保持電圧とし、
前記第1のゲート導体層と前記チャネル半導体層との間の第1の容量結合と、前記第2のゲート導体層と前記チャネル半導体層との間の第2の容量結合とにより、前記チャネル半導体層の電圧を前記第1のデータ保持電圧よりも高い電圧に制御して、前記チャネル半導体層の電圧が、前記第1の不純物層及び前記第2の不純物層の一方もしくは両方の電圧より、ビルトイン電圧だけ高くなるまで、前記正孔群のうちの残存正孔群を前記チャネル半導体層の内部から、前記第1の不純物層及び前記第2の不純物層の一方もしくは両方通して除去し、
消去動作時に、前記第1の容量結合及び前記第2の容量結合により、前記チャネル半導体層の電圧を、前記第1のデータ保持電圧よりも低い、第2のデータ保持電圧とする、
ことを特徴とする柱状半導体メモリセル。 - 前記消去動作時に、
前記第1のゲート導体層の電圧を、第1の電圧から、前記第1の電圧よりも高い第2の電圧とし、前記第2のゲート導体層の電圧を、第3の電圧から、前記第3の電圧よりも高い第4の電圧とし、
第1の期間において、前記第1の容量結合と前記第2の容量結合とにより、前記チャネル半導体層の電圧を前記第1のデータ保持電圧よりも高い電圧に制御し、
第2の期間において、前記チャネル半導体層の電圧を、前記第1の不純物層と前記第2の不純物層の一方もしくは両方の電圧より、ビルトイン電圧だけ高くなるまで、前記正孔群のうちの残存正孔群を前記チャネル半導体層の内部から、前記第1の不純物層と、前記第2の不純物層の一方もしくは両方を通して抜きとり、
第3の期間において、前記第1の容量結合と前記第2の容量結合とにより、前記チャネル半導体層の電圧を、前記第1のデータ保持電圧よりも低い、第2のデータ保持電圧とする、
ことを特徴とする請求項1に記載の柱状半導体メモリセル。 - 前記第1の不純物領域と、前記第2の不純物領域と、に印加する電圧により前記第1の容量結合及び前記第2の容量結合の一方もしくは両方を用い、前記チャネル半導体層の電圧を変化させる前記第1の期間と、前記第2の期間の一部、又はすべての期間で、前記チャネル半導体層に反転層を形成させない、
ことを特徴とする請求項1に記載の柱状半導体メモリセル。 - 前記第1のゲート導体層と、前記チャネル半導体層との間、の第1のゲート容量が、前記第2のゲート導体層と、前記チャネル半導体層との間、の第2のゲート容量よりも大きくなるように形成する、
ことを特徴とする請求項1に記載の柱状半導体メモリセル。 - 請求項1乃至4のいずれかに記載の柱状半導体メモリセルを複数個行列状に配列してブロックとし、前記メモリ消去動作の際に前記ブロック内の全ての前記半導体母体に対して、同時に前記メモリ消去動作を行う、
ことを特徴とする柱状半導体メモリ装置。 - 請求項5に記載の柱状半導体メモリ装置を複数配置したブロック群を含み、
前記第1の不純物層は、ソース線と接続し、前記第2の不純物層は、ビット線と接続し、前記第1のゲート導体層と前記第2のゲート導体層のうちの一方がワード線と接続すれば、他方が第1の駆動制御線と接続し、
前記ソース線は、前記ブロック内の前記半導体母体間で繋がり、
前記ソース線と、前記ビット線と、前記第1の駆動制御線と、前記ワード線とに印加する電圧により、前記ブロック群の中の選択した前記ブロックの全ての前記半導体母体にある前記残存正孔群を除去する前記消去動作を行う、
ことを特徴とする柱状半導体メモリ装置。 - 前記ブロックの物理アドレスと論理アドレスを対応させる論物変換テーブルと、前記論物変換テーブルを管理するコントローラ回路を備え、
前記論物変換テーブルと、前記コントローラ回路とが、片方、もしくは、両方が前記柱状半導体メモリセルの外部にある、
ことを特徴とする請求項5又は6に記載の柱状半導体メモリ装置。
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